Auxiliary resonance commutation type DC-AC converter

Abstract

The invention discloses an auxiliary resonance commutation type DC-AC converter, belongs to the technical field of voice coil motor precision driving, and aims to solve the problems of dead zone effect, zero-crossing distortion, high switching loss and difficulty in THD suppression of a traditional DC-AC converter in voice coil motor driving. The converter is formed by interleaving N power modules in parallel, each power module comprises a switch unit A and a switch unit B which are symmetrical, and the structures, parameters and limiting conditions of the two switch units are the same; the switch unit A is composed of four SiC MOSFETs S1, S2, S3 and S4, an auxiliary inductor La1 and filter inductors Lo1 and Lo2. The switch unit B is composed of four SiC MOSFETs S5, S6, S7 and S8, an auxiliary inductor La2 and filter inductors Lo3 and Lo4. The auxiliary inductors La1 and La2, the filter inductors Lo1-Lo4 and an equivalent junction capacitor of the SiC MOSFET form a resonant circuit, and zero-voltage switching is realized through auxiliary resonant commutation; the limiting condition for realizing the zero-voltage switch is as follows: the current imx, x = 1, 2, 3, 4 is reversed before the SiC MOSFET is turned off, and charging and discharging of the SiC MOSFET junction capacitor are completed in the dead time.

Description

Technical Field

[0001] The invention relates to an auxiliary resonant commutation type DC-AC converter topology structure, belonging to the technical field of precision driving of voice coil motors. Background Art

[0002] In the integrated circuit manufacturing process, nanometer-level precision positioning requires ultra-high-precision voice coil motor actuation systems. To minimize disturbance forces, ultra-high-precision DC-AC converters must be used to drive the motors. Generally, linear or hybrid amplifiers are used for high-precision applications. However, the positioning systems of semiconductor manufacturing equipment feature high speed, high acceleration, and high jerk, and their operating environment is temperature-sensitive. Linear or hybrid amplifiers are not suitable for this scenario due to their limited output capacity, poor scalability, and significant heat generation.

[0003] Traditional DC-AC converters have problems in voice coil motor driving, such as dead zone effect, zero-crossing distortion, high switching loss, and difficulty in suppressing THD. Their accuracy is not enough to be used in voice coil motor actuation systems. Summary of the Invention

[0004] In order to solve the problems of dead zone effect, zero-crossing distortion, high switching loss and difficult to suppress THD in traditional DC-AC converters in voice coil motor driving, the present invention provides an auxiliary resonant commutation DC-AC converter, which is a DC-AC converter that achieves zero voltage switching and ultra-low THD in the full load range.

[0005] The present invention provides an auxiliary resonant commutation DC-AC converter, wherein the converter is composed of N power modules connected in parallel in an interlaced manner, where N is greater than or equal to 1. Each power module includes two symmetrical switching units, A and B, and the structures, parameters, and limiting conditions of the two switching units are the same.

[0006] Switch unit A consists of four SiC MOSFETs (S1, S2, S3, and S4), auxiliary inductor La1, and filter inductors Lo1 and Lo2. Switch unit B consists of four SiC MOSFETs (S5, S6, S7, and S8), auxiliary inductor La2, and filter inductors Lo3 and Lo4.

[0007] Auxiliary inductors La1, La2, filter inductors Lo1-Lo4 and equivalent junction capacitance of SiC MOSFET form a resonant circuit, achieving zero voltage switching through auxiliary resonant commutation;

[0008] The limiting conditions for achieving zero voltage switching are: current i mx ,x=1,2,3,4 reverses before SiC MOSFET turns off and completes the charging and discharging of SiC MOSFET junction capacitance within the dead time, i m1is the SiC MOSFET current output by the S1 and S2 bridge arms, i m2 is the SiC MOSFET current output by the S3 and S4 bridge arms, i m3 is the SiC MOSFET current output by the S5 and S6 bridge arms, i m4 The SiC MOSFET current output by the S7 and S8 bridge arms;

[0009] Filter capacitors C1 and C2 are connected to the output end to suppress high-frequency ripples. Filter capacitors C1 and C2 and filter inductors Lo1-Lo4 form a filter.

[0010] Preferably, in the switch unit A, S1 and S2 are connected in series to form a first bridge arm, and a common node is simultaneously connected to one end of the auxiliary inductor La1 and one end of the filter inductor Lo1; S3 and S4 are connected in series to form a second bridge arm, and a common node is simultaneously connected to the other end of the auxiliary inductor La1 and one end of the filter inductor Lo2; the other end of the filter inductor Lo1 and the other end of the filter inductor Lo2 are connected together and connected to one end of the load R as the output end of the switch unit A;

[0011] In switch unit B, S5 and S6 are connected in series to form a third bridge arm, and their common node is connected to one end of the auxiliary inductor La2 and one end of the filter inductor Lo3. S7 and S8 are connected in series to form a fourth bridge arm, and their common node is connected to the other end of the auxiliary inductor La2 and one end of the filter inductor Lo4. The other end of the filter inductor Lo3 and the other end of the filter inductor Lo4 are connected together and connected to the other end of the load R as the output end of switch unit B.

[0012] The parameters of auxiliary inductors La1 and La2 are consistent;

[0013] The parameters of the filter inductors Lo1-Lo4 are consistent.

[0014] Preferably, the current i mx , x=1,2,3,4 reverses before the SiC MOSFET is turned off, and the charging and discharging of the SiC MOSFET junction capacitance is completed within the dead time by meeting the following conditions:

[0015] In the full load range, the absolute value of the upper and lower envelopes of the two SiC MOSFET currents of each switching unit is greater than the soft switching current threshold I mx,ZVS :

[0016] I up ≥I mx,ZVS

[0017] I down ≤-I mx,ZVS

[0018] Iup for i mx The upper envelope of I down for i mx The lower envelope of

[0019] Soft switching current threshold

[0020] Where U dc is the DC power supply at the input of the converter, L a is the value of auxiliary inductance La1, La2, L o is the value of the filter inductor Lo1-Lo4, C oss is the equivalent junction capacitance of SiC MOSFET, L a ||L o Indicates two inductors connected in parallel.

[0021] Preferably, i mx The upper envelope I up , lower envelope I down for:

[0022]

[0023]

[0024] Where m(t) is the modulation ratio, T s is the switching cycle.

[0025] Preferably, the filter design parameters are:

[0026] The bandwidth constraints are:

[0027] Where k f is the cut-off frequency coefficient, take the empirical value 4; f out,max is the maximum frequency of the actual output of the power amplifier, L o,eff is the equivalent filter inductance, L o,eff =15μH, filter capacitor C1=C2=2C o , C o is the capacitance value, C o =220nF;

[0028] The filter parameter design takes into account the i at the maximum output frequency C and u L , satisfying the following two constraints:

[0029] 2π·f out,max ·L o,eff I out ≤k v ·U o

[0030] 2π·f out,max ·C o ·U out ≤k i I out

[0031] Where k v and k i is the maximum inductor voltage drop coefficient and the maximum capacitor shunt coefficient, which are 22% and 25% respectively; I out and U out is the output current i C and output voltage u L Valid values.

[0032] Preferably, the SiC MOSFET uses a component with a model number of C3M0060065K, which has a maximum drain current of 30A and a safety current threshold of 15A.

[0033] Preferably, the number of interleaved parallel power modules of the converter is N=2, and the auxiliary inductor La1=La2=La=60 μH.

[0034] Beneficial effects of the present invention: The present invention focuses on the design of an ultra-low THD single-phase DC-AC converter for a voice coil motor actuation system. THD (Total Harmonic Distortion) is an indicator that measures the degree to which the load current waveform deviates from the ideal sine wave, reflecting the proportion of harmonic components in the current.

[0035] When applied to a smaller voice coil motor, the converter of the present invention produces output current with no visible distortion and an amplitude consistent with the target value of 7.5A. Under resistive loads, the converter achieves a load current THD of less than 1%, which is more than 10 times the THD of a conventional interleaved parallel half-bridge current, achieving ultra-high precision to meet the requirements of voice coil motors. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a schematic structural diagram of an auxiliary resonant commutation DC-AC converter according to the present invention;

[0037] Figure 2 It is a waveform diagram of each stage in a switching cycle of the converter of the present invention;

[0038] Figure 3 Schematic diagram of the current path of the eight operating modes of the converter in one switching cycle of the present invention, wherein Figure 3 (a)~ Figure 3 (h) Schematic diagram of the current paths corresponding to the eight operating modes;

[0039] Figure 4It is the voltage-current trajectory diagram of the converter during resonance, which is used to show the conditions for achieving ZVS, where: Figure 4 (a) is the voltage u S1 -Current i m1 Trajectory map, Figure 4 (b) is the voltage u S3 -Current i m2 Trajectory map;

[0040] Figure 5 This is a schematic diagram of SPWM modulation;

[0041] Figure 6 is a schematic diagram of the relationship between the current envelope and the soft switching threshold, where Figure 6 (a) is i m1 ,i m2 ,I up and I down Schematic diagram, Figure 6 (b) is i o1 ,i o2 Schematic diagram, Figure 6 (c) is i a1 Schematic diagram, Figure 6 (d) is i o ,Schematic diagram;

[0042] Figure 7 is the phase relationship of the filter parameters and the multi-module equivalent circuit diagram, where Figure 6 (a) is the phase relationship of the filter parameters at the fundamental frequency, Figure 6 (b) is the equivalent circuit diagram of multiple modules staggered in parallel;

[0043] Figure 8 This is the LC filter design space diagram;

[0044] Figure 9 is the characteristic curve of SiC MOSFET junction capacitance and output charge, where Figure 9 (a) is the nonlinear junction capacitance C of C3M0060065K oss characteristic curve, Figure 9 (b) is the output charge Q of C3M0060065K oss The calculation results are: Figure 9 (c) is the nonlinear junction capacitance C of IDL08G65C5 D characteristic curve, Figure 9 (d) is the output charge Q of IDL08G65C5 D The calculation results of

[0045] Figure 10 This is the auxiliary inductor design space diagram;

[0046] Figure 11The load current THD comparison diagram of the traditional interleaved parallel half-bridge converter and the converter of the present invention under resistive load is shown in FIG. Figure 11 (a) is the load current waveform of the traditional interleaved parallel half-bridge under resistive load and target current of 7.5A. Figure 11 (b) is the load current waveform of the converter proposed by the present invention when the target current is 7.5A under resistive load. Figure 11 (c) is the FFT result obtained by APX500 measuring the traditional interleaved parallel half-bridge. Figure 11 (d) is the FFT result obtained by measuring the converter of the present invention by APX500. Figure 11 (e) is the THD result obtained by measuring the traditional interleaved parallel half-bridge of APX500. Figure 11 (f) THD results of the converter of the present invention measured by APX500;

[0047] Figure 12 is the waveform diagram of each component during experimental verification; Figure 12 (a) is a load resistance of 18Ω, an output of 900W, an output frequency of 20kHz, and a switching frequency of 250kHz (equivalent switching frequency of 1MHz). The load current i o , auxiliary inductor current i a1 , filter inductor current i Lo1，2 and the MOSFET current i m1,2 Waveform chart, Figure 12 (b) is the waveform details within two power frequency cycles;

[0048] Figure 13 It is the soft switching test result;

[0049] Figure 14 The input voltage is 300V, the load resistance is 18Ω, and the output frequency is f o = Current THD test results at 50Hz;

[0050] Figure 15 The input voltage is 200V, the load winding is 30mH+4.8Ω, and the output frequency is f o = Current THD test results at 50Hz;

[0051] Figure 16 The input voltage is 300V, the load winding is 4.8mH+0.9Ω, and the output frequency is f o = Current THD test results at 500Hz;

[0052] Figure 17 This is a schematic diagram of the module staggered parallel structure with N=2. DETAILED DESCRIPTION

[0053] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0054] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0055] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0056] Specific implementation method 1: Figures 1 to 17 This embodiment describes an auxiliary resonant commutation DC-AC converter, wherein the converter is composed of N power modules connected in parallel, N≥1, see Figure 17 , give a schematic diagram of the structure of N = 2, and then refer to Figure 1 ,Each power module includes two symmetrical switch units A and B, and the structures, parameters and limiting conditions of the two switch units are the same;

[0057] In one power module, S1 to S4 and L a1 、L o1 and L o2 Composed of switch unit A, S5~S8 and L a2 、L o3 and L o4 The two switch units have the same parameters. Therefore, the analysis process of switch unit B is exactly the same as that of switch unit A. In this analysis, we only focus on switch unit A.

[0058] Switch unit A consists of four SiC MOSFETs (S1, S2, S3, and S4), an auxiliary inductor La1, and filter inductors Lo1 and Lo2. In switch unit A, S1 and S2 are connected in series to form the first bridge arm, and the common node is simultaneously connected to one end of the auxiliary inductor La1 and one end of the filter inductor Lo1. S3 and S4 are connected in series to form the second bridge arm, and the common node is simultaneously connected to the other end of the auxiliary inductor La1 and one end of the filter inductor Lo2. The other end of the filter inductor Lo1 and the other end of the filter inductor Lo2 are connected together and connected to one end of the load R as the output end of switch unit A.

[0059] Switch unit B consists of four SiC MOSFETs (S5, S6, S7, and S8), an auxiliary inductor La2, and filter inductors Lo3 and Lo4. In switch unit B, S5 and S6 are connected in series to form the third bridge arm, and their common node is simultaneously connected to one end of the auxiliary inductor La2 and one end of the filter inductor Lo3. S7 and S8 are connected in series to form the fourth bridge arm, and their common node is simultaneously connected to the other end of the auxiliary inductor La2 and one end of the filter inductor Lo4. The other ends of the filter inductor Lo3 and the other ends of the filter inductor Lo4 are connected together and connected to the other end of the load R as the output end of switch unit B.

[0060] Auxiliary inductors La1, La2, filter inductors Lo1-Lo4 and equivalent junction capacitance of SiC MOSFET form a resonant circuit, achieving zero voltage switching through auxiliary resonant commutation;

[0061] Filter capacitors C1 and C2 are connected to the output end to suppress high-frequency ripples. Filter capacitors C1 and C2 and filter inductors Lo1-Lo4 form a filter.

[0062] Among them, S1~S8 are SiC MOSFETs (MOSFETs made of silicon carbide materials), L a1 and L a2 is the auxiliary inductor, and its value is equal to L a Similarly, the filter inductor L o1 、L o2 、L o3 and L o4 The values are also equal, both are L o . C o is the filter capacitor, and the equivalent junction capacitance of SiCMOSFET is C oss The input voltage is U dc , the output voltage is u o .i a1 、i a2 is the auxiliary inductor current, i Lo1 ~i Lo4 is the filter inductor current, i o is the load current, i m1 ~i m4 is the SiC MOSFET current, i m1 is the SiC MOSFET current output by the S1 and S2 bridge arms, i m2 is the SiC MOSFET current output by the S3 and S4 bridge arms, i m3 is the SiCMOSFET current output by the S5 and S6 bridge arms, i m4 is the SiC MOSFET current output by the S7 and S8 bridge arms.

[0063] Figure 2 and Figure 3 They are the typical waveforms of the proposed power amplifier and the eight specific operating modes within a switching cycle. S Represents the switching cycle, ds1~ds8 respectively represent the current stage of driving S1~S8. In these 8 modes, there are 4 auxiliary resonance stages. During the resonance process, the characteristic impedance Z r and angular frequency ω r As shown in formula (1):

[0064]

[0065] It should be emphasized here that in actual applications, SiC MOSFET is usually connected in parallel with SiC SBD (silicon carbide Schottky barrier diode), so C in the above formula is oss By default, we do not include the junction capacitance of the SiC SBD. The junction capacitance of the SiC SBD is still calculated using Equation (1), but the variable signs are different, so it will not be repeated here.

[0066] The SiC MOSFET current can be decomposed into the auxiliary inductor current i a1 、i a2 and the filter inductor current i Lo1 ~i Lo4 . With the current i of unit A m1 、i m2 、i a1 、i Lo1 and i Lo2 For example, there is the following relationship:

[0067]

[0068] Stage 1[t0,t1): Figure 2 and Figure 3 As shown in (a). At t0, S2 realizes ZVS-ON (zero voltage switching), after which S2 and S3 remain open, and the voltage at point A1 is pulled down to 0. dc Reverse addition to L a1 Both ends, so that i a1 in U dc Similarly, i Lo1 and i Lo2 Descend and ascend respectively. a1 、i Lo1 and i Lo2 The on-state voltage drop 2R generated in SiC MOSFETs ds,on ·i a1 Taking into account, R ds,on is the on-state resistance of SiC MOSFET. Combined with L a1 、L o1 and Lo2 The voltage drop across the load voltage u o , we can get the following system of equations:

[0069]

[0070] Solving equation (3) yields the following equation: a1 、i Lo1 and i Lo2 The expression is

[0071]

[0072] Among them I a1,t0 , I Lo1,t0 and I Lo2,t0 is time t0 a1 、i Lo1 and i Lo2 The initial value of .

[0073] Stage 2[t1,t2): before t1, i m1 The direction has changed. At t1, S2 is turned off, i m1 Start to discharge the equivalent junction capacitance of S1 and charge the equivalent junction capacitance of S2. oss With L a ||L o Series resonance occurs, L a ||L o Indicates two inductors connected in parallel. The initial value of the circuit at this stage is u S1 (t1) = U dc ,u S2 (t1)=0, i m1 (t1)=I m1,t1 ,u S1 (t1) represents the voltage of S1 at time t1, u S2 (t1) represents the voltage of S2 at time t1, i m1 (t1) represents the SiC MOSFET current output by the S1 and S2 bridge arms at time t1. The corresponding current path is as follows: Figure 3 (b). The circuit equations are as follows:

[0074]

[0075] Solve for i m1 、u S1 The expression of is shown in (6)

[0076]

[0077] The trajectory diagram corresponding to the resonance process described by this mode is Figure 4The radius of the arc is r1, and the expression of the radius is

[0078] r1=Z r |I m1,t2 | (7)

[0079] I m1,t2 is the value of the SiC MOSFET current output by the S1 and S2 bridge arms at time t2.

[0080] According to the geometric relationship shown in the trajectory diagram, r1≥U dc To ensure that the equivalent junction capacitance of S1 is discharged to 0V at time t2, ZVS-ON is achieved. Otherwise, the ZVS-ON part is lost. m1,t1 The following conditions should be met:

[0081]

[0082] I mx,ZVS This is the soft switching current threshold.

[0083] Stage 3[t2,t4): after t2, i m1 Flowing through the anti-parallel diode of S1, u S1 and u S2 Clamped by D1 at 0 and U dc At t3, S1 realizes ZVS-ON, after which both S1 and S3 are in the on state, and the voltages at points A1 and A2 are both U dc At this time L a1 The voltage across the terminals is -2R ds,on ·i a1 This stage Lo1 and i Lo2 Keep rising. The circuit equations are as follows:

[0084]

[0085] Solving equation (9) yields i a1 、i Lo1 and i Lo2 The expression of is shown in (10):

[0086]

[0087] Among them I a1,t2 , I Lo1,t2 and I Lo2,t2 is time t2 a1 、i Lo1 and i Lo2 The initial value of .

[0088] Stage 4[t4, t5): S3 is turned off at t4, i m2 Charge the equivalent junction capacitance of S3 and discharge the equivalent junction capacitance of S4. a ||L o With 2C oss Series resonance occurs. The initial value of the circuit at this stage is u S3 (t4) = 0, u S4 (t4) = U dc ,i m2 (t4) = I m2,t4 ,u S3 (t4) represents the voltage of S3 at time t4, u S4 (t4) represents the voltage of S4 at time t4, i m2 (t4) represents the SiC MOSFET current output by the S3 and S4 bridge arms at time t4. The current path at this stage is as follows Figure 3 (d). The circuit equations are shown in (11):

[0089]

[0090] Solve for i m2 and u S3 The expression of is shown in (12)

[0091]

[0092] The trajectory diagram corresponding to this mode is Figure 4 The radius of the arc in (b) is r4, and the expression for this radius is

[0093]

[0094] I m2,t5 is the value of the SiC MOSFET current output by the S3 and S4 bridge arms at time t5.

[0095] Stage 5[t5,t7): after t5 i d2 Flowing through the anti-parallel diode of S4, u S3 and u S4 are clamped at U dc and 0. At t6, S4 realizes ZVS-ON. At this time, S1 and S4 are both in the on state, and the voltages at A1 and A2 are U dc and 0. i a1 in U dc starts to rise under the stimulation of Lo1 Keep rising, i Lo2 Start to descend. a1 、i Lo1 and i Lo2The changing process of the three can be described by equation group (14):

[0096]

[0097] Solving equation (14) we can get i a1 、i Lo1 and i Lo2 The expression is

[0098]

[0099] Among them I a1,t5 , I Lo1,t5 and I Lo2,t5 is time t5 a1 、i Lo1 and i Lo2 The initial value of .

[0100] Stage 6[t7, t8): S4 is turned off at t7, i m2 Discharge the equivalent junction capacitance of S3 and charge the equivalent junction capacitance of S4. a ||L o With 2C oss Series resonance occurs. The initial value of the circuit is u S3 (t7) = U dc ,u S4 (t7)=0, i m2 (t7) = 1 m2,t7 ,u S3 (t7) represents the voltage of S3 at time t7, u S4 (t7) represents the voltage of S4 at time t7, i m2 (t7) represents the SiC MOSFET current output by the S3 and S4 bridge arms at time t7. The current path at this stage is as follows: Figure 4 (b) and 3(f). The circuit equations are shown in (16):

[0101]

[0102] Solve for i m2 and u S3 The expression of is shown in (17):

[0103]

[0104] The trajectory corresponding to this stage is Figure 4 The radius of the arc with radius r3 in (b) is calculated in the same way as in Stage 2.

[0105] Stage 7[t8,t 10 ):After time t8 m2Flowing through the anti-parallel diode of S3, u S3 and u S4 are clamped at 0 and U dc At t9, S3 realizes ZVS-ON, S1 and S3 are both in the on state, and the voltages at A1 and A2 are both U dc . Similar to Stage3, i a1 Remain unchanged. Lo1 and i Lo2 Keep rising. The circuit equation is:

[0106]

[0107] Solving equation (18) yields i a1 、i Lo1 and i Lo2 The expression of is shown in (19)

[0108]

[0109] Among them I a1,t8 , I Lo1,t8 and I Lo2,t8 It is time t8 a1 、i Lo1 and i Lo2 The initial value of .

[0110] Stage 8[t 10 , t 11 ):t 10 At the moment S1 is turned off, L a ||L o The sum of the equivalent junction capacitance of S1 and S2 is 2C oss Series resonance occurs, i m1 The equivalent junction capacitance of S1 is charged and the equivalent junction capacitance of S2 is discharged. The initial value of the circuit at this stage is u S1 (t 10 )=0,u S2 (t 10 )=U dc ,i m1 (t 10 )=I m1,t10 The current path at this stage is as follows Figure 3 (h). The circuit equations are shown in (20):

[0111]

[0112] Solve for i m1 and u S1 The expression of is shown in (21)

[0113]

[0114] The trajectory corresponding to this stage is Figure 4 The radius of the arc with radius r2 in (a) is calculated in the same way as in Stage 5.

[0115] Parameter design.

[0116] The core point of the topology proposed in this invention to eliminate zero-crossing distortion and dead zone effect is that the current i mx , x = 1, 2, 3, 4 reverses before the SiC MOSFET turns off, and completes the charging and discharging of the SiC MOSFET junction capacitance during the dead time. Operational modal analysis shows that this process is essentially equivalent to achieving soft switching of the SiC MOSFET. Therefore, the parameter design of the proposed topology must focus on achieving soft switching across the full load range.

[0117] First, the relationship between duty cycle and modulation wave amplitude under SPWM modulation is derived. Figure 5 As shown, assuming that the carrier amplitude is constant at 2U c , the modulation wave amplitude is u m (t). Then the expression of duty cycle D is:

[0118]

[0119] Where m(t) is the modulation ratio, T s is the switching period; T on Indicates the duration of the switch on.

[0120] Because I m1 、i m2 There is no other difference except that the phase is 180°, so i m1 Take the example to design the parameters. According to formula (2), i m1 byi a1 and i Lo1 Superposition. And i Lo1 It can be decomposed into ripple current and load current. After ignoring the MOSFET on-state voltage drop, we can get i from formulas (3) and (22): a1 The amplitude is:

[0121]

[0122] For i Lo1 , the load current component contained in it is half of the load current output by switch unit A, so i Lo1 The load current component contained in can be expressed as:

[0123]

[0124] Where R is the load resistance and N is the number of power modules interleaved in parallel.

[0125] For i Lo1 The ripple current component in can still be derived from formula (3):

[0126]

[0127] Combining formulas (23), (24) and (25), i mx The upper and lower current envelopes can be expressed as (26) and (27), respectively. As long as the absolute value of the envelope is greater than the soft switching threshold (Formula (8)), the proposed topology can be guaranteed to operate in the soft switching state.

[0128]

[0129] I up ≥I mx,ZVS , I down ≤-I mx,ZVS .

[0130] According to (26) and (27), the envelope is closest to the soft switching threshold when m(t) is at its maximum, i.e., at maximum load. Therefore, as long as the designed parameters enable the proposed topology to achieve soft switching at maximum load, soft switching over the entire load range can be guaranteed.

[0131] Figure 6 Given i o ,i m1 ,i m2 ,i o1 ,i o2 ,i a1 ,I up and I down Here we take N=1 as an example. According to formula (2), i o1 ,i o2 and i a1 The superposition of i m1 and i m2 I up and I down That is i m1 and i m2 As long as the upper and lower envelopes are within the full load range, I up Are greater than or equal to I mx,ZVS , I down are less than or equal to -I mx,ZVS , then ZVS-ON can be achieved in the full load range. o It is equal to twice the common mode current output by the two bridge arms in switch unit A.

[0132] The specific design indicators are as follows: ① DC bus voltage U dc=300V;②Output current peak value I o 10A (resistive load); ③Switching frequency 250kHz; ④Target bandwidth 20kHz. Since the positive and negative half-cycles of the modulation wave are symmetrical, the following analysis will take the positive half-cycle as an example.

[0133] First, to design the filter, we need to establish a filter design space. The filter design must consider two factors: first, meeting the bandwidth requirements of the power amplifier, and second, minimizing the maximum inductor voltage drop and capacitor current shunt, thereby limiting reactive power.

[0134] First, there should be the following restrictions on bandwidth

[0135]

[0136] where k f is the cut-off frequency coefficient, which is usually taken as 4. out,max is the maximum frequency of the actual output of the power amplifier, L o,eff is the equivalent filter inductor, C o It is a filter capacitor.

[0137] If the modules connected in parallel are treated as equivalent, the equivalent input voltage of the filter is u sw,eff , the total input current is i sum . Figure 7 (a) is the load current i o , load voltage u o With filter sw,eff and i sum Schematic diagram of the phase relationship between Figure 7 (b) is the equivalent circuit after multiple modules are staggered in parallel. When the output frequency increases, the reactive power absorbed by the capacitor and inductor will increase accordingly, resulting in i C and u L Increase. Reactive power is also input from the DC side. If the parameter design is unreasonable, excessive reactive power may burn out the switching device. Therefore, the filter parameter design needs to take into account the maximum output frequency i C and u L , that is, the following two constraints need to be considered:

[0138] 2π·f out,max ·L o,eff I out ≤k v ·U o (29)

[0139] 2π·f out,max ·C o ·U out ≤k i Iout (30)

[0140] where k v and k i is the maximum inductor voltage drop coefficient and the maximum capacitor shunt coefficient, which are 22% and 25% respectively. out and U out are the effective values of output current and output voltage.

[0141] In summary, we can get Figure 8 The filter design space shown in Figure 1. The area that meets the bandwidth constraint is the lower left of the blue hyperbola, which satisfies the maximum u L The area with the constraint condition should be on the left side of the yellow straight line, satisfying the maximum i C The area of the restriction condition should be the lower side of the orange straight line, and the ideal filter parameter value point should be the point marked by the red five-pointed star (L o,eff =15μH, C o =220nF).

[0142] Secondly, auxiliary inductor design

[0143] Under the premise of given input voltage level, switching frequency and filter inductance, L a The design of the switch tube should consider the following two points: ① The peak current of the switch tube cannot be greater than the safety current threshold, otherwise the switch tube will be easily damaged; ② Soft switching can still be maintained at maximum load.

[0144] For condition ①, the SiC MOSFET model selected in the present invention is C3M0060065K, whose maximum drain current is 30A. Here, the safety current threshold is 15A, that is, the SiC MOSFET current i m All must be less than 15A to meet the C3M0060065K Safe Operating Area (SOA) limits. m is i a and i Lo The superimposed value, the peak current calculation of the switch tube should also consider i a and i Lo We can combine formulas (23) and (25) to calculate L under the constraint condition of the switch tube safety current threshold. a .

[0145] For condition ②, the soft switching current threshold can be calculated by formula (8), as long as the maximum load i m As long as the soft switching current threshold is not exceeded, the soft switching capability can be guaranteed under the maximum load. The equivalent junction capacitance of SiCMOSFET used in the calculation process of formula (8) can be obtained by Figure 9Using formula (31), we can obtain that the equivalent junction capacitance of C3M0060065K is 153.3pF and that of IDL08G65C5 is 46.7pF within 300V.

[0146]

[0147] Figure 9 (a) C3M0060065K nonlinear junction capacitance C oss (b) C3M0060065K output charge Q oss (c) IDL08G65C5 nonlinear junction capacitance C D (d) IDL08G65C5 output charge Q D The calculation results of .

[0148] Finally, combining the above conditions ① and ②, we can get Figure 10 The auxiliary inductor design space. Conditions ① and ② correspond to Figure 10 The area to the right of the purple vertical line and the area below the green curve. The three gradient blue lines represent different L values for 1 to 3 power modules. a Time mx The maximum lower envelope I downM , which can be calculated by formula (27). Obviously, at least two power modules need to be staggered in parallel to meet the soft switching current threshold and safety current threshold requirements. The final number of staggered parallel power modules is 2 [as shown in Figure (17)]. Select the auxiliary inductor L a =60μH.

[0149] The effects of the invention are illustrated by experimental verification.

[0150] Figure 11 Figures (a) and (b) show the load current THD of a conventional interleaved parallel half-bridge converter and the proposed converter, respectively, under a resistive load at a target current of 7.5A. Clearly, the current amplitude and waveform of the interleaved half-bridge converter differ significantly from the 7.5A target. In contrast, the output current of the proposed converter exhibits no visible distortion, and its amplitude matches the 7.5A target. Figure 11 (c), (d), (e) and (f) are the FFT and THD results measured by APX500. The current THD of the present invention is only 0.47%, while the current THD of the traditional interleaved parallel half-bridge is 4.97%, a difference of more than 10 times.

[0151] Figure 12 (a) shows the load current i of the present invention at 18Ω load resistance, 900W output, 20kHz output frequency, and 250kHz switching frequency (equivalent switching frequency up to 1MHz). o , auxiliary inductor current ia1 , filter inductor current i Lo1，2 and the MOSFET current i m1,2 Waveform. i a1 As m(t) changes, it presents a saddle-shaped change within the power frequency cycle. Lo1,2 and i m1,2 There are spikes in the waveform. This is because the filter capacitor absorbs a large reactive current at an output frequency of 20kHz, which, when superimposed on the filter inductor current, causes the spikes shown in the figure. Figure 12 (b) is the waveform details within two power frequency cycles, i a1 As m(t) changes, it changes between quadrilateral current and triangular current. From formula (22), we can see that when m(t)≠0, duty cycle D≠0.5, then the staggered parallel operation will definitely cause two upper tubes or two lower tubes to be turned on at the same time, resulting in L a The voltage across the terminals is 0, i a1 There will be a situation where di / dt≈0, resulting in a flat-top phase in the quadrilateral current. When m(t)=0, the duty cycle D=0.5, and the two upper tubes or the two lower tubes will not be turned on at the same time. At this time, the flat-top current disappears and the quadrilateral current degenerates into a triangular current. a1 with i Lo1,2 After superposition, we get i m1,2 , so i m1,2 It also changes between quadrilateral current and triangular current.

[0152] According to the previous analysis, as long as the maximum load i mx Lower envelope I down Still less than -I mx,ZVS , which can ensure soft switching within the full load range. Figure 13 The u under the maximum load is given ds and u gs ,u ds After the gate-source voltage u of SiCMOSFET drops to 0 gs It is important to note that since all bridge arms operate in the same state, only the soft switching of one bridge arm is shown.

[0153] The current THD under resistive load is as follows: Figure 14 As shown, I o,peak is i o The present invention can achieve a current THD of less than 1% under a resistive load.

[0154] Figure 15The current THD measured under a real voice coil motor winding (30mH + 4.8Ω) is shown. Since the ITN 12-P fluxgate sensor has a nominal value of 12.5A, the load current is generally limited to 15A to ensure measurement accuracy. To ensure that the modulation ratio m(t) is not too small, a 200V input voltage and a 50Hz output frequency are selected. In the 0-10A range, the THD reaches a minimum of 0.055%. It is important to emphasize that the rapid increase in THD above 10A is caused by L a and L o The inductor howling is caused by unreasonable parameters.

[0155] Figure 16 Another smaller voice coil motor winding (4.8mH + 0.9Ω) was selected to measure the THD at an output frequency of 500Hz. It can be seen that at a higher output frequency, a current THD of around 0.2% can still be achieved.

[0156] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the invention. It should be understood that many modifications may be made to the illustrative embodiments, and that other arrangements may be devised, without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in ways other than those described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in conjunction with other described embodiments.

Claims

1. An auxiliary resonant commutation DC-AC converter, characterized in that: The converter is composed of N power modules connected in parallel, N≥1, and each power module includes two symmetrical switch units A and B. The structures, parameters and limiting conditions of the two switch units are the same; Switch unit A consists of four SiC MOSFETs (S1, S2, S3, and S4), auxiliary inductor La1, and filter inductors Lo1 and Lo2. Switch unit B consists of four SiC MOSFETs (S5, S6, S7, and S8), auxiliary inductor La2, and filter inductors Lo3 and Lo4. Auxiliary inductors La1, La2, filter inductors Lo1-Lo4 and equivalent junction capacitance of SiC MOSFET form a resonant circuit, achieving zero voltage switching through auxiliary resonant commutation; The limiting conditions for achieving zero voltage switching are: current i mx ,x=1,2,3,4 reverses before SiC MOSFET turns off and completes the charging and discharging of SiC MOSFET junction capacitance within the dead time, i m1 is the SiC MOSFET current output by the S1 and S2 bridge arms, i m2 is the SiC MOSFET current output by the S3 and S4 bridge arms, i m3 is the SiC MOSFET current output by the S5 and S6 bridge arms, i m4 The SiC MOSFET current output by the S7 and S8 bridge arms; Filter capacitors C1 and C2 are connected to the output end to suppress high-frequency ripples. Filter capacitors C1 and C2 and filter inductors Lo1-Lo4 form a filter.

2. The auxiliary resonant commutated DC-AC converter according to claim 1, characterized in that: In switch unit A, S1 and S2 are connected in series to form a first bridge arm, and a common node is connected to one end of the auxiliary inductor La1 and one end of the filter inductor Lo1. S3 and S4 are connected in series to form a second bridge arm, and a common node is connected to the other end of the auxiliary inductor La1 and one end of the filter inductor Lo2. The other end of the filter inductor Lo1 and the other end of the filter inductor Lo2 are connected together and connected to one end of the load R as the output end of switch unit A. In switch unit B, S5 and S6 are connected in series to form a third bridge arm, and their common node is connected to one end of the auxiliary inductor La2 and one end of the filter inductor Lo3. S7 and S8 are connected in series to form a fourth bridge arm, and their common node is connected to the other end of the auxiliary inductor La2 and one end of the filter inductor Lo4. The other end of the filter inductor Lo3 and the other end of the filter inductor Lo4 are connected together and connected to the other end of the load R as the output end of switch unit B. The parameters of auxiliary inductors La1 and La2 are consistent; The parameters of the filter inductors Lo1-Lo4 are consistent.

3. The auxiliary resonant commutated DC-AC converter according to claim 2, characterized in that: Current i mx , x=1,2,3,4 reverses before the SiC MOSFET is turned off, and the charging and discharging of the SiC MOSFET junction capacitance is completed within the dead time by meeting the following conditions: In the full load range, the absolute value of the upper and lower envelopes of the two SiC MOSFET currents of each switching unit is greater than the soft switching current threshold I mx,ZVS : I up ≥I mx,ZVS I down ≤-I mx,ZVS I up for i mx The upper envelope of I down for i mx The lower envelope of Soft switching current threshold Where U dc is the DC power supply at the input of the converter, L a is the value of auxiliary inductance La1, La2, L o is the value of the filter inductor Lo1-Lo4, C oss is the equivalent junction capacitance of SiC MOSFET, L a ||L o Indicates two inductors connected in parallel.

4. The auxiliary resonant commutated DC-AC converter according to claim 3, characterized in that: i mx The upper envelope I up , lower envelope I down for: Where m(t) is the modulation ratio, T s is the switching cycle.

5. The auxiliary resonant commutation DC-AC converter according to claim 4, characterized in that: Filter design parameters: The bandwidth constraints are: Where k f is the cut-off frequency coefficient, take the empirical value 4; f out,max is the maximum frequency of the actual output of the power amplifier, L o,eff is the equivalent filter inductance, L o,eff =15μH, filter capacitor C1=C2=2C o , C o is the capacitance value, C o =220nF; The filter parameter design takes into account the i at the maximum output frequency C and u L , satisfying the following two constraints: 2π·f out,max ·L o,eff ·I out ≤k v ·U o 2π·f out,max ·C o ·U out ≤k i ·I out Where k v and k i is the maximum inductor voltage drop coefficient and the maximum capacitor shunt coefficient, which are 22% and 25% respectively; I out and U out is the output current i C and output voltage u L Valid values.

6. The auxiliary resonant commutated DC-AC converter according to claim 1, characterized in that: The SiC MOSFET uses the component model C3M0060065K, which has a maximum drain current of 30A and a safety current threshold of 15A.

7. The auxiliary resonant commutated DC-AC converter according to claim 6, characterized in that: The number of interleaved parallel power modules of the converter is N=2, and the auxiliary inductor La1=La2=La=60μH.

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