Transistor structure and amplifier circuit
By setting multiple gate bias pads in the transistor structure to control the switching state of each unit transistor, the problems of small range of transistors in the transistor are solved, the transistor output power adjustment range is small, operation difficulty is high, complexity is high and cost is high, and multi-order adjustable and simplified operation of the output power is achieved.
Patent Information
- Application Number
- CN202510562614.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2025-08-15
AI Technical Summary
Existing transistors have problems such as small output power adjustment range, high operation difficulty, high complexity and high cost.
By setting multiple gate bias pads in the transistor structure, different gate modules are connected to receive different gate bias voltages, and the switching states of each cell transistor are controlled separately, so as to achieve multi-order adjustable output power of the entire transistor.
A wide range of multi-order adjustable transistor output power is realized, which simplifies operation, reduces system complexity and cost, while improving regulation efficiency and device stability.
Smart Images
Figure CN120498392A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of radio frequency technology, and in particular to a transistor structure and an amplifier circuit. Background Art
[0002] The continuous development of 5G and millimeter wave communication systems has put forward higher requirements for RF devices, among which the transistors in RF devices need to have adjustable output power.
[0003] In related technologies, considering that the drain voltage of a transistor is usually a fixed value, most methods adjust the power characteristics of the transistor by changing the gate voltage to achieve adjustable output power. However, adjusting the gate voltage has the following disadvantages:
[0004] 1. The output power of the transistor varies little and cannot achieve wide range power adjustment;
[0005] 2. The gate Schottky barrier height fluctuates with process parameters, causing fluctuations in the channel pinch-off voltage under different gates. This results in large discreteness in transistor performance, making power regulation difficult.
[0006] 3. Adjusting the gate voltage increases the demand for system bias hardware and software, increasing system complexity and cost.
[0007] In summary, the method of adjusting the transistor output power by adjusting the gate voltage has the disadvantages of a small power adjustment range, high operational difficulty, high complexity and high cost, which is not conducive to practical application. Summary of the Invention
[0008] The embodiments of the present invention provide a transistor structure and an amplifier circuit to solve the problems of small power adjustment range, high operation difficulty coefficient, high complexity and high cost in the existing transistor output power adjustment process.
[0009] In a first aspect, an embodiment of the present invention provides a transistor structure, comprising: a plurality of drain modules, a plurality of source modules, a plurality of gate modules, a plurality of gate bias pads, a gate radio frequency pad, a drain pad, and a source pad;
[0010] The drain modules and the source modules are arranged in a staggered manner, and the source modules are located on the outside of the arrangement structure, and the gate modules are arranged between adjacent drain modules and source modules;
[0011] Each gate module is connected to a gate bias pad, and each gate bias pad is connected to at least one gate module; each gate bias pad is used to receive a different gate bias voltage;
[0012] Each gate bias pad is connected to the gate RF pad via a different DC blocking capacitor;
[0013] Each drain module is connected to the drain pad;
[0014] Each source module is connected to the source pad.
[0015] In one possible implementation, the transistor structure further includes: an inductor respectively disposed between each gate bias pad and the corresponding DC blocking capacitor;
[0016] For each gate bias pad, the gate bias pad is connected to the gate RF pad via the inductor and the DC blocking capacitor in sequence.
[0017] In a possible implementation, the transistor structure further includes: a first bypass capacitor and / or a second bypass capacitor;
[0018] The positive electrode of the first bypass capacitor is connected to the drain pad, and the negative electrode of the first bypass capacitor is grounded;
[0019] The positive electrode of the second bypass capacitor is connected to the gate RF pad, and the negative electrode of the second bypass capacitor is grounded.
[0020] In a possible implementation, the number of the gate modules is less than the number of the gate bias pads;
[0021] When the number of gate modules connected to the same gate bias pad is two or more, the gate modules connected to the gate bias pad are not directly adjacent.
[0022] In a possible implementation, the number of the gate modules is less than the number of the gate bias pads;
[0023] The gate modules are sequentially connected to the gate bias pads according to their arrangement order.
[0024] In a possible implementation, the transistor structure further includes: a plurality of gate beams, and each gate beam corresponds to each gate bias pad one by one;
[0025] The plurality of gate beams are arranged on both sides of the arrangement structure along the arrangement direction of the drain module and the source module;
[0026] The gate modules in the arrangement structure are connected to corresponding gate bias pads via the gate beams.
[0027] In a possible implementation, the transistor structure further includes: an air bridge provided between the gate module and the corresponding gate beam;
[0028] When the physical positions of the gate module and the corresponding grid beam are not directly adjacent, the gate module is connected to the corresponding grid beam via the air bridge.
[0029] In an embodiment of the present invention, each adjacent set of drain modules, source modules, and gate modules can form a unit transistor. The gate modules in the unit transistors are connected to different gate bias pads for receiving different gate bias voltages, thereby separately controlling the switching state of each unit transistor to adjust the output power of each unit transistor. By separately adjusting the output power of each unit transistor, the output power of the entire transistor structure can be adjusted in multiple stages. Compared with the traditional method of adjusting the gate voltage, this power adjustment method is not only simple and easy, but also has a wider power adjustment range. It does not increase the demand for bias hardware and software, thereby reducing system complexity and cost.
[0030] In a second aspect, an embodiment of the present invention provides an amplifier circuit, comprising: an input matching circuit, a bias circuit, the transistor structure according to any one of the first aspects above, and an output matching circuit;
[0031] The input end of the input matching circuit is used to receive an input radio frequency signal, and the output end of the input matching circuit is connected to the gate radio frequency pad of the transistor structure;
[0032] Each input terminal of the bias circuit is used to connect to a different external power supply, and each gate voltage output terminal of the bias circuit is connected to each gate bias pad of the transistor structure;
[0033] The drain pad of the transistor structure is connected to the input end of the output matching circuit;
[0034] The source pad of the transistor structure is grounded;
[0035] The output end of the output matching circuit is connected to the leakage voltage output end of the bias circuit and is used to output the radio frequency amplified signal.
[0036] In a possible implementation, the bias circuit is a T-type network based on an inductor or a quarter wavelength line.
[0037] In a possible implementation, the input matching circuit and the output matching circuit are impedance transformation lines of multiple sections of 1 / 4 wavelength lines.
[0038] The amplifier circuit provided by the embodiments of the present invention can dynamically adjust output power, overcome high-frequency signal attenuation, and ensure the stability of the communication link. Furthermore, in communication systems requiring a compact design, an amplifier with multi-level, easily adjustable output power can perform the functions of multiple amplifiers, effectively reducing the number of components in the system and facilitating high integration and miniaturization of the communication system. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1Schematic diagram of the working principle of the transistor structure provided by an embodiment of the present invention;
[0040] Figure 2 is a schematic diagram of a transistor structure in related art;
[0041] Figure 3 is a schematic structural diagram of a transistor structure provided by an embodiment of the present invention;
[0042] Figure 4 is a schematic structural diagram of a transistor structure provided by another embodiment of the present invention;
[0043] Figure 5 1 is a schematic structural diagram of an amplifier circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0044] To help those skilled in the art better understand this solution, the following will clearly describe the technical solutions in the embodiments of this solution in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of this solution, not all of it. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of this solution.
[0045] Throughout the specification, claims, and accompanying figures of this solution, the term "including" and any variations thereof mean "including, but not limited to," and are intended to cover non-exclusive inclusions and are not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish between different objects, not to describe a specific order.
[0046] First, combine Figure 1 The working principle of the transistor structure is introduced. For details, see Figure 1 , the source is grounded, bias voltages are applied to the gate and drain respectively, and the input RF signal is applied to the gate to affect the channel formation, regulate the concentration of carriers in the channel, cause the drain current to change, realize RF output, and amplify the input RF signal. In related technologies, the total width of the transistor channel is usually increased to increase its output power. For details, see Figure 2 By staggering multiple source modules, gate modules, and drain modules, the total width of the transistor channel is widened, thereby improving the output power of the transistor structure. Among them, all gate modules are interconnected by the same gate beam and ultimately connected to the gate pad. The gate bias voltage passes through the gate pad and applies the same bias voltage to all gate modules through the gate beam. The input RF signal passes through the gate pad and is evenly distributed to all gate modules in the same direction through the gate beam. The RF signal amplitude and phase on all gate modules are similar.
[0047] Refer to the above Figure 2 Based on existing transistor structures, the output power of transistors is usually adjusted by adjusting the gate bias voltage. However, this method has disadvantages such as a narrow output power adjustment range, high operational difficulty, and increased system complexity and cost.
[0048] To circumvent the aforementioned shortcomings and easily and conveniently achieve wide-range adjustment of transistor output power, embodiments of the present invention improve the transistor structure by providing multiple gate bias pads within the transistor structure for connecting different gate modules within the transistor structure. This allows the gate modules corresponding to different gate bias pads to receive different gate bias voltages, thereby individually controlling the switching state of the unit transistors within each gate module and, in turn, the output power of the unit transistors. By individually controlling the output power of each unit transistor, the output power of the overall transistor structure can ultimately be adjusted over a wide range and in multiple stages.
[0049] The following is a detailed description of the implementation of the present invention with reference to the accompanying drawings:
[0050] Figure 3 A schematic diagram of a transistor structure provided by an embodiment of the present invention. Figure 3 The transistor structure includes: a plurality of drain modules 31, a plurality of source modules 32, a plurality of gate modules 33, a plurality of gate bias pads 34, a gate RF pad 35, a drain pad 36 and a source pad 37;
[0051] The drain modules 31 and the source modules 32 are arranged in a staggered manner, and the source modules 32 are arranged on the outside of the arrangement structure. The gate modules 33 are arranged between the adjacent drain modules 31 and source modules 32.
[0052] Each gate module 33 is connected to a gate bias pad 34, and each gate bias pad 34 is connected to at least one gate module 33; each gate bias pad 34 is used to receive a different gate bias voltage;
[0053] Each gate bias pad 34 is connected to the gate RF pad 35 via a different DC blocking capacitor C;
[0054] Each drain module 31 is connected to a drain pad 36;
[0055] Each source module 32 is connected to a source pad 37 .
[0056] Here, drain modules 31 and source modules 32 are arranged in an interlaced manner to form an arrangement structure 30. The outer sides of the arrangement structure 30 are all source modules 32. Each group of adjacent source modules 32, gate modules 33, and drain modules 31 in the arrangement structure 30 forms a unit transistor. The arrangement structure 20 includes multiple unit transistors.
[0057] The gate module in each unit transistor is connected to a corresponding gate bias pad for receiving a gate bias voltage to control the operating state of the unit transistor. It can be understood that when the gate bias voltage is greater than the threshold voltage, the channel in the unit transistor is in a normal static bias state. At this time, the unit transistor is in an operating state and outputs power normally. When the gate bias voltage is less than the threshold voltage, the channel in the unit transistor is in a deeply depleted state. At this time, the unit transistor is in a "sleep" state and cannot output power.
[0058] Here, each gate bias pad can be connected to one or more gate modules to simultaneously control the output power of one or more unit transistors. It can be understood that the sum of the output power of each unit transistor structure is the output power of the entire transistor structure. The embodiment of the present invention can control the switching state of each unit transistor by adjusting the gate bias voltage received by each gate bias pad, thereby ultimately achieving multi-stage adjustable output power of the entire transistor structure.
[0059] by Figure 3 For example, Figure 3 Here, the transistor structure is divided into four parts, each of which shares a unified drain pad, source pad, and gate RF pad, and each part uses its own independent gate bias pad.
[0060] The bias states of gate modules 1 and 5 are controlled by gate bias pad 1, and together with the source and drain on either side, they form the first sub-device. The bias states of gate modules 2 and 6 are controlled by gate bias pad 2, and together with the source and drain on either side, they form the second sub-device. The bias states of gate modules 3 and 7 are controlled by gate bias pad 3, and together with the source and drain on either side, they form the third sub-device. The bias states of gate modules 4 and 8 are controlled by gate bias pad 4, and together with the source and drain on either side, they form the fourth sub-device.
[0061] The output power of this transistor structure is adjustable in four levels. When this transistor structure is applied to AlGaN / GaN HEMT devices, the power density is 5W / mm, the width of a single gate module is 100 microns, and the corresponding output power is 0.5 watts. Under this solution, the output power of each sub-device is 1 watt.
[0062] Case 1: Gate bias pad 1 is biased above the threshold voltage (Vth) (e.g., Vth + 0.5V), indicating a normal static bias state. Gate bias pads 2, 3, and 4 are biased below the threshold voltage (Vth) (e.g., Vth - 10V), indicating a deep depletion state. The output power of the entire transistor structure is 1 watt.
[0063] Case 2: Gate bias pads 1 and 2 are biased above the threshold voltage (Vth) (e.g., Vth + 0.5V), indicating a normal static bias state. Gate bias pads 3 and 4 are biased below the threshold voltage (Vth) (e.g., Vth - 10V), indicating a deep depletion state. The output power of the entire transistor structure is 2 watts.
[0064] Case 3: Gate bias pads 1, 2, and 3 are biased above the threshold voltage (Vth) (e.g., Vth + 0.5V), indicating a normal static bias state. Gate bias pad 4 is biased below the threshold voltage (Vth) (e.g., Vth - 10V), indicating a deep depletion state. The output power of the entire transistor structure is 3 watts.
[0065] Case 4: The bias voltage of gate bias pads 1, 2, 3, and 4 is above the threshold voltage (Vth) (eg, Vth+0.5V). At this time, the output power of the entire transistor structure is 4 watts.
[0066] The embodiment of the present invention provides multiple gate bias pads for receiving different gate bias voltages to control the working state of each unit transistor in the transistor structure respectively, thereby achieving multi-stage adjustable output power for the entire transistor structure. Compared with the traditional method of controlling the output power by adjusting the gate bias voltage, the transistor structure provided by the embodiment of the present invention not only has a wider adjustable output power range, but also has simple and easy power regulation operation, without the need to add complex bias hardware and software, and will not increase system complexity and cost. In addition, the embodiment of the present invention adjusts the output power by switching the switching state of each unit transistor, and its switching response time is short and the regulation efficiency is high.
[0067] Optionally, the transistor structure further includes: a plurality of gate beams 38, and each gate beam 38 corresponds to each gate bias pad 34. Figure 3 Multiple gate beams 38 are arranged on both sides of the array structure 30 along the arrangement direction of the drain modules 31 and the source modules 32. The gate modules 33 in the array structure 30 are connected to the corresponding gate bias pads 34 via the gate beams 38. To facilitate the connection of external devices, the gate bias pads can be arranged on the periphery of the entire transistor structure.
[0068] Considering that the number of grid beams located on one side of the arrangement structure is greater than 1, there will be a problem that the gate module in the arrangement structure cannot be directly connected to the corresponding grid beam. To this end, the transistor structure in the embodiment of the present invention also includes an air bridge 39 arranged between the gate module and the corresponding grid beam. When the physical positions of the gate module and the corresponding grid beam are not directly adjacent, the gate module is connected to the corresponding grid beam via the air bridge.
[0069] For example, see Figure 3The drain pad and source pad can be respectively arranged on the outside of the gate beam to connect to other external devices. Considering that the physical positions of the source module and the source pad are not directly adjacent, an air bridge can be set between each source module and the source pad to connect the source module and the source pad. Similarly, an air bridge can be set between each drain module and the drain pad to connect the drain module and the drain pad.
[0070] In addition, considering the heat dissipation problem of the transistor structure, when the number of gate modules is less than the number of gate bias pads, that is, when the number of gate modules connected to the same gate bias pad is two or more, the gate modules connected to the gate bias pad are not directly adjacent.
[0071] Still Figure 3 For example, gate module 3 and gate module 7 are both connected to gate bias pad 3. In the embodiment of the present invention, gate module 4, gate module 5, and gate module 6 are arranged between gate module 3 and gate module 7 to separate gate module 3 and gate module 7. When gate module 3 and gate module 7 are working simultaneously, the heat dissipation of the entire transistor structure can be uniform, thereby improving device stability.
[0072] Furthermore, when the number of gate modules is less than the number of gate bias pads, the gate modules are sequentially connected to the gate bias pads according to their arrangement sequence.
[0073] Still Figure 3 For example, gate modules 1-4 are connected to gate bias pads 1-4 in sequence, and gate modules 5-8 are also connected to gate bias pads 1-4 in sequence.
[0074] Each gate module is connected to each gate bias pad in sequence according to the arrangement order. When the same gate bias pad controls the operation of different unit transistors, the heat generated by each unit transistor can be evenly distributed throughout the entire transistor, thereby improving its heat dissipation performance, reducing the channel temperature within the unit transistor, and thus improving device stability.
[0075] Optional, see Figure 4 , the above transistor structure further includes: an inductor L respectively arranged between each gate bias pad and the corresponding DC blocking capacitor;
[0076] For each gate bias pad, the gate bias pad is connected to the gate RF pad via an inductor and a DC blocking capacitor in sequence.
[0077] Here, the gate RF pad can be placed on the periphery of the transistor structure to facilitate connection to external devices. The gate bias pad is connected to the gate RF pad via a gate beam, an inductor, and a DC-blocking capacitor. The inductor is used to compensate for circuit mismatch caused by the DC-blocking capacitor.
[0078] Optional, see Figure 4, the above transistor structure further includes: a first bypass capacitor C1 and / or a second bypass capacitor C2;
[0079] The positive electrode of the first bypass capacitor C1 is connected to the drain pad, and the negative electrode of the first bypass capacitor is grounded;
[0080] The positive electrode of the second bypass capacitor C2 is connected to the gate RF pad, and the negative electrode of the second bypass capacitor is grounded.
[0081] Here, the first bypass capacitor C1 and / or the second bypass capacitor C2 can bypass the surge circuit caused by the state switching state to ground.
[0082] The above transistor structure can not only be applied to Si RF MOSFET, GaN RF HEMT, GaN RF MOSFET, GaAs RF pHEMT, GaAs RF mHEMT or InP RF HBT, but can also be used in other transistors made of SiGe, silicon carbide, graphene, diamond and other materials.
[0083] Based on the above transistor structure, an embodiment of the present invention further provides an amplifier circuit with multi-stage adjustable output power.
[0084] See also Figure 5 , the amplifier circuit includes: an input matching circuit 51, a bias circuit 52, a transistor structure 53, and an output matching circuit 54;
[0085] The input end of the input matching circuit 51 is used to receive the input RF signal, and the output end of the input matching circuit 51 is connected to the gate RF pad of the transistor structure 53;
[0086] Each input terminal of the bias circuit 52 is used to connect to different external power supplies, and each gate voltage output terminal of the bias circuit 52 is correspondingly connected to each gate bias pad of the transistor structure 53;
[0087] The drain pad of the transistor structure 53 is connected to the input terminal of the output matching circuit 54;
[0088] The source pad of the transistor structure 53 is grounded;
[0089] The output end of the output matching circuit 54 is connected to the drain voltage output end of the bias circuit 52 and is used to output the radio frequency amplified signal.
[0090] For example, see Figure 5 The bias circuit's input terminals are connected to external power supplies VDS, VG1, VG2, VG3, and VG4, respectively. VG1, VG2, VG3, and VG4 provide gate bias voltages to gate bias pads 1-4, respectively, via the bias circuit. VDS is connected to the output terminal of the output matching circuit via the bias circuit to provide drain bias voltage.
[0091] Optionally, the bias circuit may be a T-type network based on an inductor or a quarter wavelength line.
[0092] Optionally, the input matching circuit and the output matching circuit may be impedance transformation lines of multiple sections of 1 / 4 wavelength lines.
[0093] Based on the characteristic that the output power of the transistor structure is adjustable in multiple stages, the amplifier circuit provided by the embodiment of the present invention also has the characteristic that the output power is adjustable in multiple stages.
[0094] To achieve adjustable amplifier output power, related technologies have mostly proposed improvements at the circuit level. Specifically, these improvements involve subcircuits such as the bias circuit and input / output matching circuits within the amplifier circuit to achieve adjustable output power. For example, a development array is used to implement a matching network with variable capacitance to achieve multiple power outputs. However, power regulation at the circuit level has the following main drawbacks:
[0095] 1. Using a switch takes a long time to switch, which also causes circuit gain loss and reduced efficiency.
[0096] 2. Adding additional design circuits results in a larger circuit scale, lower yield rate, and higher cost;
[0097] 3. The power usually only has two modes: low power and high power, and multi-level adjustment cannot be achieved between the modes.
[0098] Compared with the above-mentioned power adjustment method, the embodiment of the present invention improves the transistor structure to achieve multi-stage and wide-range adjustment of the output power of the amplifier circuit. There is no need to add additional switching devices, which will not cause circuit gain loss and efficiency reduction, and there is no need to add additional design circuits, which can effectively reduce costs and improve yield.
[0099] In current 5G and millimeter-wave communication systems, amplifiers with variable output power can dynamically adjust output power, overcoming high-frequency signal attenuation and ensuring communication link stability. In radio frequency identification and wireless sensor networks, they better meet the demands of communication systems, enabling real-time adjustment of transmit power while also ensuring both system stability and efficiency. Furthermore, in communication systems requiring compact designs, amplifiers with easily adjustable multi-level output power can perform the functions of multiple amplifiers, effectively reducing the number of components in the system and facilitating high integration and miniaturization.
[0100] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.
Claims
1. A transistor structure, characterized in that: include: Multiple drain modules, multiple source modules, multiple gate modules, multiple gate bias pads, gate RF pads, drain pads and source pads; The drain modules and the source modules are arranged in a staggered manner, and the source modules are located on the outside of the arrangement structure, and the gate modules are arranged between adjacent drain modules and source modules; Each gate module is connected to a gate bias pad, and each gate bias pad is connected to at least one gate module; each gate bias pad is used to receive a different gate bias voltage; Each gate bias pad is connected to the gate RF pad via a different DC blocking capacitor; Each drain module is connected to the drain pad; Each source module is connected to the source pad.
2. The transistor structure according to claim 1, wherein: Also includes: an inductor respectively arranged between each gate bias pad and the corresponding DC blocking capacitor; For each gate bias pad, the gate bias pad is connected to the gate RF pad via the inductor and the DC blocking capacitor in sequence.
3. The transistor structure according to claim 1 or 2, wherein: Also includes: a first bypass capacitor and / or a second bypass capacitor; The positive electrode of the first bypass capacitor is connected to the drain pad, and the negative electrode of the first bypass capacitor is grounded; The positive electrode of the second bypass capacitor is connected to the gate RF pad, and the negative electrode of the second bypass capacitor is grounded.
4. The transistor structure according to claim 1 or 2, wherein: The number of the gate modules is less than the number of the gate bias pads; When the number of gate modules connected to the same gate bias pad is two or more, the gate modules connected to the gate bias pad are not directly adjacent.
5. The transistor structure according to claim 4, wherein: The number of the gate modules is less than the number of the gate bias pads; The gate modules are sequentially connected to the gate bias pads according to their arrangement order.
6. The transistor structure according to claim 1 or 2, wherein: Also includes: A plurality of grid beams, each grid beam corresponding to each grid bias pad; The plurality of gate beams are arranged on both sides of the arrangement structure along the arrangement direction of the drain module and the source module; The gate modules in the arrangement structure are connected to corresponding gate bias pads via the gate beams.
7. The transistor structure according to claim 6, wherein: Also includes: An air bridge is provided between the grid module and the corresponding grid beam; When the physical positions of the gate module and the corresponding grid beam are not directly adjacent, the gate module is connected to the corresponding grid beam via the air bridge.
8. An amplifier circuit, characterized in that: include: An input matching circuit, a bias circuit, a transistor structure according to any one of claims 1 to 7, and an output matching circuit; The input end of the input matching circuit is used to receive an input radio frequency signal, and the output end of the input matching circuit is connected to the gate radio frequency pad of the transistor structure; Each input terminal of the bias circuit is used to connect to a different external power supply, and each gate voltage output terminal of the bias circuit is connected to each gate bias pad of the transistor structure; The drain pad of the transistor structure is connected to the input end of the output matching circuit; The source pad of the transistor structure is grounded; The output end of the output matching circuit is connected to the leakage voltage output end of the bias circuit and is used to output the radio frequency amplified signal.
9. The amplifier circuit according to claim 8, wherein: The bias circuit is a T-type network based on an inductor or a 1 / 4 wavelength line.
10. The amplifier circuit according to claim 8 or 9, characterized in that The input matching circuit and the output matching circuit are impedance transformation lines of multiple sections of 1 / 4 wavelength lines.