Common-mode rejection circuit, power amplifier circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of electronic circuits, in particular to a common-mode rejection circuit which is applied to a differential amplification circuit and comprises a common-mode disturbance rejection circuit and an output common-mode detection circuit. A first input end and a second input end of the output common-mode detection circuit are respectively connected with a first common-mode output end and a second common-mode output end of the differential amplification circuit; the output end of the output common-mode detection circuit is connected with the input end of the common-mode disturbance suppression circuit; a first output end and a second output end of the common-mode disturbance suppression circuit are respectively connected with a first common-mode input end and a second common-mode input end of the differential amplification circuit; the output common-mode detection circuit generates control information according to respective voltages of the first common-mode output end and the second common-mode output end; and the common-mode disturbance suppression circuit adjusts the common-mode voltage of the differential amplification circuit based on the control information, so that common-mode currents flowing in and out of the same common-mode input end are the same, or the common-mode voltage is one half of the voltage of the power supply. Therefore, the voltage disturbance of the common-mode input end is effectively inhibited.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a common-mode suppression circuit, a power amplifier circuit, a chip, and an electronic device. Background Art

[0002] In a fully differential amplifier circuit, the voltage at the common-mode input is typically determined by the current fed back from the common-mode output through feedback resistor RFB. Understandably, in a fully differential amplifier circuit, when the input signal is 0, the common-mode output will output a signal with a 50% duty cycle. That is, within a given period, the signal at the common-mode output remains high and low for the same amount of time.

[0003] However, due to the presence of feedback resistor RFB in the fully differential amplifier circuit, a feedback current will be fed back from the common-mode output to the common-mode input, and the feedback current will flow through the integrating capacitor in the fully differential amplifier circuit. Due to the charging and discharging characteristics of the integrating capacitor, the voltage at the common-mode input will have periodic ripples, that is, the voltage at the common-mode input will fluctuate at a certain frequency, causing voltage disturbances at the common-mode input.

[0004] In some cases, the voltage disturbance at the common-mode input can be seen as a noise signal and can mix with the input signal, affecting the overall performance of the fully differential amplifier circuit. Summary of the Invention

[0005] The illustrative embodiments of the present application provide a common-mode suppression circuit, a power amplifier circuit, a chip, and an electronic device.

[0006] In a first aspect, the present application provides a common-mode suppression circuit, which is applied to a differential amplifier circuit, including: a common-mode disturbance suppression circuit and an output common-mode detection circuit; the first input terminal of the output common-mode detection circuit is used to connect to the first common-mode output terminal of the differential amplifier circuit, and the second input terminal of the output common-mode detection circuit is used to connect to the second common-mode output terminal of the differential amplifier circuit; the output terminal of the output common-mode detection circuit is connected to the input terminal of the common-mode disturbance suppression circuit; the first output terminal of the common-mode disturbance suppression circuit is used to connect to the second common-mode input terminal of the differential amplifier circuit, and the second output terminal of the common-mode disturbance suppression circuit is used to connect to the first common-mode input terminal of the differential amplifier circuit; wherein the output common-mode detection circuit is used to generate control information according to the voltage of the first common-mode output terminal and the voltage of the second common-mode output terminal; the common-mode disturbance suppression circuit is used to adjust the common-mode voltage of the differential amplifier circuit based on the control information, so that the common-mode current flowing into and out of the same common-mode input terminal is the same, or so that the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

[0007] It can be understood that in the embodiment of the present application, the common-mode voltage of the differential amplifier circuit may refer to the voltage of the first common-mode input terminal INT_INP of the differential amplifier circuit, or the voltage of the second common-mode input terminal INT_INN of the differential amplifier circuit.

[0008] Based on the common-mode suppression circuit provided by the present application, by adding an output common-mode detection circuit and detecting the voltage (VOUTP and VOUTN) of the common-mode output terminal using the output common-mode detection circuit, control information that can adjust the common-mode disturbance suppression circuit is generated, so that the common-mode disturbance suppression circuit can adjust the common-mode voltage based on the control information. The common-mode current flowing into and out of the same common-mode input terminal (such as INT_INP or INT_INN) of the differential amplifier circuit is thereby made the same. In this way, the voltage disturbance at the common-mode input terminal can be effectively suppressed. Alternatively, by making the common-mode voltage of the differential amplifier circuit half of the power supply voltage, the symmetry of the differential amplifier circuit is ensured, thereby effectively suppressing the voltage disturbance at the common-mode input terminal of the differential amplifier circuit.

[0009] In a possible implementation of the first aspect above, the output common-mode detection circuit includes a digital logic detection module, a first input terminal of the digital logic detection module is used to connect to the first common-mode output terminal, and a second input terminal of the digital logic detection module is used to connect to the second common-mode output terminal; the digital logic detection module is used to obtain the voltage of the first common-mode output terminal and the voltage of the second common-mode output terminal, and generate control information based on the voltage of the first common-mode output terminal and the voltage of the second common-mode output terminal to control the common-mode disturbance suppression circuit, wherein the control information includes a first logic signal and a second logic signal.

[0010] It can be understood that the first logic signal may refer to the PG mentioned in the embodiment of the present application, and the second logic signal may refer to the NG mentioned in the embodiment of the present application.

[0011] In a possible implementation of the first aspect above, the common-mode disturbance suppression circuit includes a first field-effect transistor and a second field-effect transistor, a first common-mode suppression resistor and a second common-mode suppression resistor, wherein the first common-mode suppression resistor and the second common-mode suppression resistor have equal resistance values; the source of the first field-effect transistor is connected to the power supply terminal, the gate of the first field-effect transistor is connected to the first output terminal of the digital logic detection module, the drain of the first field-effect transistor is connected to the drain of the second field-effect transistor, the first end of the first common-mode suppression resistor, and the first end of the second common-mode suppression resistor; the gate of the second field-effect transistor is connected to the second output terminal of the digital logic detection module, and the source of the second field-effect transistor is connected to the ground terminal; the second end of the first common-mode suppression resistor is used to be connected to the second common-mode input terminal, and the second end of the second common-mode suppression resistor is used to be connected to the first common-mode input terminal; the first logic signal is used to control the gate voltage of the first field-effect transistor to be high or low, and the second logic signal is used to control the gate voltage of the second field-effect transistor to be high or low.

[0012] In a possible implementation of the first aspect above, based on the first feedback resistor of the differential amplifier circuit being equal to the first common-mode suppression resistor, if the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both low, then the first logic signal and the second logic signal are both low, the gate voltage of the first field-effect transistor and the gate voltage of the second field-effect transistor are both low, the first field-effect transistor is turned on, the second field-effect transistor is turned off, and the common-mode adjustment voltage of the differential amplifier circuit is high, so that the common-mode current corresponding to the first feedback resistor flows out of the first common-mode input terminal, and the common-mode current corresponding to the first common-mode suppression resistor is high. The current flows into the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor of the differential amplifier circuit; based on the first feedback resistor being equal to the first common-mode suppression resistor, if the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both high, then the first logic signal and the second logic signal are both high, the gate voltage of the first field-effect transistor and the gate voltage of the second field-effect transistor are both high, the first field-effect transistor is turned off, the second field-effect transistor is turned on, and the common-mode adjustment voltage of the differential amplifier circuit is low, so that the common-mode current corresponding to the first feedback resistor flows into the first common-mode input terminal. The common-mode current corresponding to the first common-mode suppression resistor flows out of the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor; if the voltage of the first common-mode output terminal is high and the voltage of the second common-mode output terminal is low, the first logic signal is high and the second logic signal is low, the gate voltage of the first field-effect transistor is high and the gate voltage of the second field-effect transistor is low, and the first field-effect transistor and the second field-effect transistor are both cut off, so that the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage of the first common-mode input terminal and the voltage of the second common-mode input terminal, and the differential amplifier circuit is turned off. The common-mode voltage of the differential amplifier circuit is half of the power supply voltage; if the voltage of the first common-mode output terminal is low and the voltage of the second common-mode output terminal is high, the first logic signal is high and the second logic signal is low, the gate voltage of the first field-effect transistor is high and the gate voltage of the second field-effect transistor is low, and the first field-effect transistor and the second field-effect transistor are both cut off, so that the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage of the first common-mode input terminal and the voltage of the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

[0013] In a possible implementation of the first aspect above, the common-mode disturbance suppression circuit includes a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, a first current source, a second current source, a third current source, and a fourth current source, wherein the first current source is equal to the product of the power supply voltage and twice the first feedback resistance of the differential amplifier circuit, and the second current source, the third current source, and the fourth current source are equal; the source of the third field-effect transistor is connected to the first end of the first current source, the second end of the first current source is connected to the power supply end, the gate of the third field-effect transistor is connected to the first output end of the digital logic detection module and the gate of the fifth field-effect transistor, and the drain of the third field-effect transistor is connected to the fourth field-effect transistor. The drain of the first field effect transistor is connected to the drain of the second common mode input terminal; the gate of the fourth field effect transistor is connected to the second output terminal of the digital logic detection module and the gate of the sixth field effect transistor, the source of the fourth field effect transistor is connected to the first end of the second current source, and the second end of the second current source is connected to the ground terminal; the source of the fifth field effect transistor is connected to the first end of the third current source, and the second end of the third current source is connected to the power supply terminal, the drain of the fifth field effect transistor is used to be connected to the second common mode input terminal, and the drain of the fifth field effect transistor is connected to the drain of the sixth field effect transistor; the source of the sixth field effect transistor is connected to the first end of the fourth current source, and the second end of the fourth current source is connected to the ground terminal.

[0014] In a possible implementation of the first aspect above, if the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both low, then the first logic signal and the second logic signal are both low, the gate voltage of the third field-effect transistor and the gate voltage of the fourth field-effect transistor are both low, the third field-effect transistor and the fifth field-effect transistor are turned on, the fourth field-effect transistor and the sixth field-effect transistor are turned off, the common-mode adjustment voltage of the differential amplifier circuit is high, the common-mode current corresponding to the first feedback resistor flows out of the first common-mode input terminal, and the common-mode current corresponding to the common-mode disturbance suppression circuit flows into the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor of the differential amplifier circuit; if the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both high, then the first logic signal and the second logic signal are both high, the gate voltage of the third field-effect transistor and the gate voltage of the fourth field-effect transistor are both high, the third field-effect transistor and the fifth field-effect transistor are turned off, the fourth field-effect transistor and the sixth field-effect transistor are turned on, the common-mode adjustment voltage of the differential amplifier circuit is low, and the common-mode current corresponding to the first feedback resistor flows into The common-mode current corresponding to the common-mode disturbance suppression circuit flows out of the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor; if the voltage of the first common-mode output terminal is high and the voltage of the second common-mode output terminal is low, the first logic signal is high and the second logic signal is low, and the third field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor and the sixth field-effect transistor are all cut off, so that the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage of the first common-mode input terminal and the voltage of the second common-mode input terminal , the common-mode voltage of the differential amplifier circuit is half of the power supply voltage; if the voltage of the first common-mode output terminal is low and the voltage of the second common-mode output terminal is high, the first logic signal is high and the second logic signal is low, and the third field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor and the sixth field-effect transistor are all cut off, so that the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage of the first common-mode input terminal and the voltage of the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

[0015] In a possible implementation of the first aspect above, the output common-mode detection circuit includes a NOR gate, a NAND gate, a first NAND gate, and a second NAND gate; the first input terminal of the NOR gate is used to connect to the first common-mode output terminal, the second input terminal of the NOR gate is used to connect to the second common-mode output terminal, the output terminal of the NOR gate is connected to the input terminal of the first NAND gate, and the first NAND gate is used to output a first logic signal; the first input terminal of the NAND gate is used to connect to the first common-mode output terminal, the second input terminal of the NAND gate is used to connect to the second common-mode output terminal, the output terminal of the NAND gate is connected to the input terminal of the second NAND gate, and the second NAND gate is used to output a second logic signal.

[0016] In a possible implementation of the first aspect above, the output common-mode detection circuit includes a first common-mode detection resistor and a second common-mode detection resistor, wherein the first common-mode detection resistor and the second common-mode detection resistor have equal resistance values; the common-mode disturbance suppression circuit includes a first operational amplifier, a negative feedback resistor, a third common-mode suppression resistor and a fourth common-mode suppression resistor, wherein the third common-mode suppression resistor and the fourth common-mode suppression resistor have equal resistance values; the first end of the first common-mode detection resistor is used to be connected to the first common-mode output terminal, the first end of the second common-mode detection resistor is used to be connected to the second common-mode output terminal, and the second end of the first common-mode detection resistor is connected to the second end of the second common-mode detection resistor and the inverting input terminal of the first operational amplifier. The first operational amplifier is connected to the output terminal of the first operational amplifier, wherein the input voltage of the positive input terminal of the first operational amplifier is half of the power supply voltage; the output terminal of the first operational amplifier is connected to the second terminal of the negative feedback resistor, the first terminal of the third common-mode suppression resistor, and the first terminal of the fourth common-mode suppression resistor, the second terminal of the third common-mode suppression resistor is used to be connected to the second common-mode input terminal, and the second terminal of the fourth common-mode suppression resistor is used to be connected to the first common-mode input terminal; the output common-mode detection circuit is used to generate control information according to the voltage of the first common-mode output terminal and the voltage of the second common-mode output terminal, the control information includes a divided voltage generated based on the first common-mode detection resistor and the second common-mode detection resistor, and the voltage of the negative input terminal of the first operational amplifier is the divided voltage.

[0017] In a possible implementation of the first aspect above, based on the negative feedback resistor being equal to half of the first common-mode detection resistor, if the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both low, based on the first operational amplifier and the negative feedback resistor, the common-mode adjustment voltage of the differential amplifier circuit is made to be the power supply voltage, thereby causing the common-mode current corresponding to the first feedback resistor of the differential amplifier circuit to flow out of the first common-mode input terminal, and the common-mode current corresponding to the common-mode disturbance suppression circuit to flow into the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor; based on the negative feedback resistor being equal to half of the first common-mode detection resistor, if the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both high, based on the first operational amplifier and the negative feedback resistor, the common-mode adjustment voltage of the differential amplifier circuit is made to be low, thereby causing the common-mode current corresponding to the first feedback resistor to flow into the first common-mode input terminal, and the common-mode current corresponding to the common-mode disturbance suppression circuit to flow into the first common-mode input terminal. The current flows out of the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor; based on the negative feedback resistor being equal to half of the first common-mode detection resistor, if the voltage at the first common-mode output terminal is high and the voltage at the second common-mode output terminal is low, based on the first operational amplifier and the negative feedback resistor, the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage at the first common-mode input terminal and the voltage at the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage; based on the negative feedback resistor being equal to half of the first common-mode detection resistor, if the voltage at the first common-mode output terminal is low and the voltage at the second common-mode output terminal is high, based on the first operational amplifier and the negative feedback resistor, the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage at the first common-mode input terminal and the voltage at the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

[0018] In a second aspect, the present application provides a power amplifier circuit, comprising the common-mode suppression circuit and the differential amplifier circuit provided in the first aspect above.

[0019] In a possible implementation of the second aspect above, the differential amplifier circuit includes a modulation module, a first comparison amplifier module, a second comparison amplifier module, a first integral capacitor, a second integral capacitor, a first feedback resistor, a second feedback resistor, and an output driver module, wherein the first feedback resistor and the second feedback resistor have equal resistance values, and the first integral capacitor and the second integral capacitor are equal; the first input terminal of the modulation module is connected to the first common-mode input terminal, the first end of the first integral capacitor, and the first end of the first feedback resistor, the second end of the first integral capacitor is connected to the first output terminal of the modulation module and the first input terminal of the first comparison amplifier module, the second end of the first feedback resistor is connected to the first common-mode output terminal, and the second end of the modulation module is connected to the first common-mode output terminal. The input end is connected to the second common-mode input end, the first end of the second integrating capacitor, and the first end of the second feedback resistor; the second end of the second integrating capacitor is connected to the second output end of the modulation module and the first input end of the second comparison amplification module, and the second end of the second feedback resistor is connected to the second common-mode output end; the second input end of the first comparison amplification module is connected to the second input end of the second comparison amplification module, the output end of the first comparison amplification module is connected to the first input end of the output driving module, and the output end of the second comparison amplification module is connected to the second input end of the output driving module; the first output end of the output driving module is connected to the first common-mode output end, and the second output end of the output driving module is connected to the second common-mode output end.

[0020] In a third aspect, the present application provides a chip comprising the power amplifier circuit provided in the second aspect above.

[0021] In a fourth aspect, the present application provides an electronic device comprising a chip provided in the third aspect above.

[0022] The beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions of the first aspect and various possible implementations of the first aspect, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A waveform diagram of a common-mode input voltage disturbance is shown;

[0024] Figure 2 A schematic diagram of a power amplifier circuit 001 and its common-mode suppression circuit of the present application is shown;

[0025] Figure 3 A schematic diagram of another power amplifier circuit 002 and its common-mode suppression circuit of the present application is shown;

[0026] Figure 4 A schematic diagram of another power amplifier circuit 003 and its common-mode suppression circuit of the present application is shown;

[0027] Figure 5 A schematic diagram of a digital logic detection module 201 of the present application is shown;

[0028] Figure 6 A schematic diagram of another power amplifier circuit 004 and its common-mode suppression circuit is shown in the present application;

[0029] Figure 7 A waveform diagram of a common mode input terminal in a power amplifier circuit of the present application is shown. DETAILED DESCRIPTION

[0030] The illustrative embodiments of the present application include, but are not limited to, a common-mode rejection circuit, a power amplifier circuit, a chip, and an electronic device.

[0031] It can be understood that the differential amplifier circuit in the power amplifier circuit in the embodiment of the present application can be a fully differential amplifier circuit, which is not limited here.

[0032] The specific implementation process of the technical solution provided by the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0033] As mentioned above, the voltage disturbance at the common-mode input of the differential amplifier circuit can be regarded as a noise signal and will mix with the input signal to affect the overall performance of the fully differential amplifier circuit.

[0034] For example, Figure 1 A waveform diagram of a common-mode input voltage disturbance is shown.

[0035] like Figure 1 As shown in , when the input signal is 0, the common-mode output terminal will output a signal with a 50% duty cycle. Due to the presence of the feedback resistor RFB, the common-mode output terminal will feedback a current I_RFB to the common-mode input terminal (INT_INP / N). When the voltage at the common-mode output terminal (VOUTP / N) is high, the I_RFB corresponding to the feedback resistor RFB will flow into the common-mode input terminal (INT_INP / N) and then be injected into the integrating capacitor C, charging the integrating capacitor C and increasing the voltage at the common-mode input terminal (INT_INP / N). When the voltage at the common-mode output terminal (VOUTP / N) is low, I_RFB will flow out of the common-mode input terminal (INT_INP / N), and then the current I_C corresponding to the integrating capacitor C will flow out of the integrating capacitor C, discharging the integrating capacitor C, thereby reducing the voltage at the common-mode input terminal (INT_INP / N). That is to say, when the input signal is 0 and the common-mode output terminal outputs a square wave with a 50% duty cycle, the periodic charge and discharge process of the integrating capacitor C will cause the voltage of the common-mode input terminal (INT_INP / N) to fluctuate around VDD / 2, that is, there is a periodic voltage disturbance.

[0036] It is understood that the voltage disturbance problem at the common-mode input terminal of the differential amplifier circuit mentioned above will be discussed below in conjunction with the present application. Figure 2 、 Figure 3、 Figure 4 and Figure 6 The different common-mode suppression circuits and power amplifier circuits provided in the paper elaborate on the specific process of improving the voltage disturbance at the common-mode input end.

[0037] In order to solve the above problems, an embodiment of the present application provides a common-mode suppression circuit, which is applied to a differential amplifier circuit, including: a common-mode disturbance suppression circuit and an output common-mode detection circuit; the first input terminal of the output common-mode detection circuit is used to connect to the first common-mode output terminal of the differential amplifier circuit, and the second input terminal of the output common-mode detection circuit is used to connect to the second common-mode output terminal of the differential amplifier circuit; the output terminal of the output common-mode detection circuit is connected to the input terminal of the common-mode disturbance suppression circuit; the first output terminal of the common-mode disturbance suppression circuit is used to connect to the second common-mode input terminal of the differential amplifier circuit, and the second output terminal of the common-mode disturbance suppression circuit is used to connect to the first common-mode input terminal of the differential amplifier circuit; wherein the output common-mode detection circuit is used to generate control information according to the voltage of the first common-mode output terminal and the voltage of the second common-mode output terminal; the common-mode disturbance suppression circuit is used to adjust the common-mode voltage of the differential amplifier circuit based on the control information, so that the common-mode current flowing into and out of the same common-mode input terminal is the same, or so that the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

[0038] Based on the common-mode suppression circuit provided in the embodiment of the present application, by adding an output common-mode detection circuit and using the output common-mode detection circuit to detect the voltage of the first common-mode output terminal or the second common-mode output terminal of the differential amplifier circuit, control information that can adjust the common-mode disturbance suppression circuit is generated, so that the common-mode disturbance suppression circuit can adjust the common-mode adjustment voltage of the differential amplifier circuit based on the control information. In this way, the common-mode current flowing into and out of the same common-mode input terminal (such as the first common-mode input terminal or the second common-mode input terminal) of the differential amplifier circuit is the same. In this way, no common-mode current flows through the integrating capacitor in the power amplifier circuit, and the voltage disturbance at the common-mode input terminal can be effectively suppressed. Alternatively, by making the common-mode voltage of the differential amplifier circuit half of the power supply voltage, the symmetry of the differential amplifier circuit is ensured, thereby effectively suppressing the voltage disturbance at its common-mode input terminal.

[0039] It can be understood that the embodiments of the present application are mainly explained by taking the suppression of the voltage disturbance at the first common-mode input terminal of the differential amplifier circuit as an example. Similarly, the suppression of the voltage disturbance at the second common-mode input terminal of the corresponding differential amplifier circuit can refer to the first common-mode input terminal.

[0040] For example, Figure 2 The schematic diagram of a power amplifier circuit 001 and its common-mode suppression circuit is shown. The power amplifier circuit 001 may include a differential amplifier circuit 10 and a common-mode suppression circuit, wherein the common-mode suppression circuit includes an output common-mode detection circuit 20 and a common-mode disturbance suppression circuit 30.

[0041] Specifically, the first input terminal of the output common-mode detection circuit 20 is used to connect to the first common-mode output terminal OUTP of the differential amplifier circuit 10, the second input terminal of the output common-mode detection circuit 20 is used to connect to the second common-mode output terminal OUTN of the differential amplifier circuit 10, and the output terminal of the output common-mode detection circuit 20 is connected to the input terminal of the common-mode disturbance suppression circuit 30. The first output terminal of the common-mode disturbance suppression circuit 30 is used to connect to the second common-mode input terminal INT_INN of the differential amplifier circuit 10, and the second output terminal of the common-mode disturbance suppression circuit 30 is used to connect to the first common-mode input terminal INT_INP of the differential amplifier circuit 10. It can be understood that the specific structure of the differential amplifier circuit 10 will be described in detail below.

[0042] In some embodiments of the present application, the specific structures of the output common mode detection circuit 20 and the common mode disturbance suppression circuit 30 in the common mode suppression circuit may be different. For example, Figure 3 A schematic diagram of a power amplifier circuit 002 and a common-mode suppression circuit thereof is shown.

[0043] refer to Figure 3 In the power amplifier circuit 002, the output common-mode detection circuit 20 may include a digital logic detection module 201. The common-mode disturbance suppression circuit 30 may include a first field-effect transistor MP1, a second field-effect transistor MN1, a first common-mode suppression resistor RCMI1, and a second common-mode suppression resistor RCMI2. The first common-mode suppression resistor RCMI1 and the second common-mode suppression resistor RCMI2 are equal. Specifically:

[0044] refer to Figure 3 In some embodiments of the present application, the output common-mode detection circuit 20 includes a digital logic detection module 201. A first input terminal of the digital logic detection module 201 is connected to the first common-mode output terminal OUTP of the differential amplifier circuit 10, and a second input terminal of the digital logic detection module 201 is connected to the second common-mode output terminal OUTN of the differential amplifier circuit 10. The digital logic detection module 201 can be used to obtain the voltage VOUTP of the first common-mode output terminal and the voltage VOUTN of the second common-mode output terminal, and generate control information based on the voltage VOUTP of the first common-mode output terminal and the voltage VOUTN of the second common-mode output terminal to control the common-mode disturbance suppression circuit. The control information can include a first logic signal PG and a second logic signal NG. It is understood that the first logic signal PG and the second logic signal can be used to control the common-mode disturbance suppression circuit 30.

[0045] Continue to refer Figure 3In some embodiments of the present application, the common-mode disturbance suppression circuit 30 includes a first field-effect transistor MP1 and a second field-effect transistor MN1, a first common-mode suppression resistor RCMI1 and a second common-mode suppression resistor RCMI2, wherein the first common-mode suppression resistor RCMI1 and the second common-mode suppression resistor RCMI2 have the same resistance value; the source of the first field-effect transistor MP1 is connected to the power supply terminal VDD, the gate of the first field-effect transistor MP1 is connected to the first output terminal of the digital logic detection module 201, the drain of the first field-effect transistor MP1 is connected to the drain of the second field-effect transistor MN1, the first common-mode suppression resistor RCMI1 and the second common-mode suppression resistor RCMI2. The first end of the common-mode suppression resistor RCMI1 and the first end of the second common-mode suppression resistor RCMI2 are connected; the gate of the second field-effect transistor MN1 is connected to the second output terminal of the digital logic detection module 201, and the source of the second field-effect transistor MN1 is connected to the ground terminal GND; the second end of the first common-mode suppression resistor RCMI1 is used to be connected to the second common-mode input terminal INT_INN, and the second end of the second common-mode suppression resistor is used to be connected to the first common-mode input terminal INT_INP; the first logic signal is used to control the gate voltage of the first field-effect transistor to be high or low. It can be understood that the second logic signal PG is used to control the gate voltage of the first field-effect transistor MP1 and the gate voltage of the second field-effect transistor MN1.

[0046] The following combination Figure 3 The power amplifier circuit 002 shown in FIG. 1 illustrates a process of improving the voltage disturbance problem at the common-mode input terminal based on the power amplifier circuit 002 and its common-mode suppression circuit.

[0047] In some embodiments of the present application, based on the first feedback resistor RFB1 in the differential amplifier circuit 10 being equal to the first common-mode suppression resistor RCMI1, if the voltage VOUTP at the first common-mode output terminal and the voltage VOUTN at the second common-mode output terminal are both at a low level (GND), the first logic signal PG and the second logic signal NG are both at a low level (GND), the gate voltage of the first field-effect transistor MP1 and the gate voltage of the second field-effect transistor MN1 are both at a low level (GND), the first field-effect transistor MP1 is turned on, and the second field-effect transistor MN1 is turned off, so that the common-mode adjustment voltage of the differential amplifier circuit 10 is at a high level (VDD). Based on the fact that current in a circuit generally flows from a high potential to a low potential, the common-mode current I_RFB corresponding to the first feedback resistor RFB1 flows out of the first common-mode input terminal INT_INP, and the common-mode current I_RCMI corresponding to the first common-mode suppression resistor RCMI1 flows into the first common-mode input terminal INT_INP. In this way, I_RFB and I_RCMI cancel each other out, so that no common-mode current flows through the first integrating capacitor C1 , thereby effectively suppressing the voltage disturbance of the first common-mode input terminal INT_INP.

[0048] It can be understood that the first field effect transistor MP1 is a P-type field effect transistor (P-channel MOSFET, PMOS), corresponding to a P-type field effect transistor, which is turned on when the gate voltage is less than the source voltage, and is otherwise turned off. The second field effect transistor MN1 is an N-type field effect transistor, corresponding to an N-channel MOSFET, NMOS, which is turned on when the gate voltage is greater than the source voltage, and is otherwise turned off.

[0049] Based on this, reference Figure 3 When the gate voltage of the first FET MP1 and the gate voltage of the second FET MN1 are both low (GND), since the source voltage of the first FET is the power supply voltage VDD, the gate voltage (GND) of the first FET MP1 is less than the source voltage (VDD), turning on the first FET MP1. Furthermore, since the source of the second FET MN1 is grounded GND, the gate voltage (GND) of the second FET MN1 is less than the source voltage (GND), turning off the second FET MN1. When the first FET MP1 is on and the second FET MN1 is off, the common-mode adjustment voltage (com point voltage) is pulled up to the power supply voltage VDD. The common-mode current I_RCMI corresponding to the first common-mode suppression resistor RCMI1 is equal to VDD / (2*RCMI1). Furthermore, the common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1). When the first common-mode suppression resistor RCMI1 is equal to the first feedback resistor RFB1, the common-mode current I_RCMI and the common-mode current I_RFB are equal. This allows the common-mode current I_RFB flowing out of the first common-mode input terminal INT_INP to cancel out the common-mode current I_RCMI flowing into the first common-mode input terminal INT_INP. Consequently, no resistance flows through the first integrating capacitor C1, effectively suppressing voltage disturbances at the first common-mode input terminal INT_INP.

[0050] In some embodiments of the present application, based on the first feedback resistor RFB1 being equal to the first common-mode suppression resistor RCMI1, if the voltage VOUTP at the first common-mode output terminal and the voltage VOUTN at the second common-mode output terminal are both at a high level (VDD), the first logic signal PG and the second logic signal NG are both at a high level (VDD), the gate voltage of the first field-effect transistor MP1 and the gate voltage of the second field-effect transistor MN1 are both at a high level (VDD), the first field-effect transistor MP1 is turned off, and the second field-effect transistor MN1 is turned on, so that the common-mode adjustment voltage of the differential amplifier circuit is at a low level (GND). In the circuit, current generally flows from a high potential to a low potential, so that the common-mode current I_RFB corresponding to the first feedback resistor RFB1 flows into the first common-mode input terminal, and the common-mode current I_RCMI corresponding to the first common-mode suppression resistor RCMI1 flows out of the first common-mode input terminal INT_INP, so that no common-mode current flows through the first integrating capacitor C1.

[0051] It can be understood that the first field effect transistor MP1 is a P-type field effect transistor (P-channel MOSFET, PMOS), corresponding to a P-type field effect transistor, which is turned on when the gate voltage is less than the source voltage, and is otherwise turned off. The second field effect transistor MN1 is an N-type field effect transistor, corresponding to an N-channel MOSFET, NMOS, which is turned on when the gate voltage is greater than the source voltage, and is otherwise turned off.

[0052] Based on this, reference Figure 3When the gate voltage of the first FET MP1 and the gate voltage of the second FET MN1 are both high (VDD), since the source voltage of the first FET is the power supply voltage VDD, the gate voltage (VDD) of the first FET MP1 is no less than the source voltage (VDD), and the first FET MP1 is turned off. Furthermore, since the source of the second FET MN1 is grounded GND, the gate voltage (VDD) of the second FET MN1 is greater than the source voltage (GND), and the second FET MN1 is turned on. When the first FET MP1 is turned off and the second FET MN1 is turned on, the common-mode adjustment voltage (com point voltage) is pulled down to ground GND, and the common-mode current I_RCMI corresponding to the first common-mode suppression resistor RCMI1 is equal to VDD / (2*RCMI1). Furthermore, the common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1). When the first common-mode suppression resistor RCMI1 is equal to the first feedback resistor RFB1, the common-mode current I_RCMI and the common-mode current I_RFB are equal. This allows the common-mode current I_RFB flowing into the first common-mode input terminal INT_INP to cancel out the common-mode current I_RCMI flowing out of the first common-mode input terminal INT_INP. Consequently, no resistance flows through the first integrating capacitor C1, effectively suppressing voltage disturbances at the first common-mode input terminal INT_INP.

[0053] In some embodiments of the present application, if the voltage VOUTP of the first common-mode output terminal is at a high level (VDD) and the voltage VOUTN of the second common-mode output terminal is at a low level (GND), the first logic signal PG is at a high level, the second logic signal NG is at a low level (GND), the gate voltage of the first field-effect transistor MP1 is at a high level, the gate voltage of the second field-effect transistor MN1 is at a low level, and both the first field-effect transistor MP1 and the second field-effect transistor MN1 are turned off, so that the common-mode adjustment voltage of the differential amplifier circuit is half of the voltage of the first common-mode input terminal and the voltage of the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit 10 is half of the power supply voltage.

[0054] It can be understood that the first field effect transistor MP1 is a P-type field effect transistor (P-channel MOSFET, PMOS), corresponding to a P-type field effect transistor, which is turned on when the gate voltage is less than the source voltage, and is otherwise turned off. The second field effect transistor MN1 is an N-type field effect transistor, corresponding to an N-channel MOSFET, NMOS, which is turned on when the gate voltage is greater than the source voltage, and is otherwise turned off.

[0055] Based on this, reference Figure 3When the gate voltage of the first field-effect transistor MP1 is high (VDD) and the gate voltage of the second field-effect transistor MN1 is low (GND), since the source voltage of the first field-effect transistor MP1 is the power supply voltage VDD, the gate voltage (VDD) of the first field-effect transistor MP1 is not less than the source voltage (VDD), and the first field-effect transistor MP1 is turned off. Furthermore, since the source of the second field-effect transistor MN1 is grounded GND, the gate voltage (GND) of the second field-effect transistor MN1 is not greater than the source voltage (GND), and the second field-effect transistor MN1 is also turned off. When the first field-effect transistor MP1 is turned off and the second field-effect transistor MN1 is also turned off, since both the first field-effect transistor MP1 and the second field-effect transistor MN1 are turned off, no effective current path is formed. Therefore, no current can flow through RCMI1 and RCMI2, and I_RCMI = 0. The common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1), and the common-mode current I_RFB flows into the first common-mode input terminal INT_INP. This ensures that the common-mode voltage of the power amplifier circuit 002 is half the power supply voltage, ensuring the symmetry of the differential amplifier circuit 10 and improving the ability to suppress common-mode signals, thereby effectively suppressing voltage disturbances at the first common-mode input terminal INT_INP.

[0056] In some embodiments of the present application, if the voltage VOUTP of the first common-mode output terminal is at a low level (GND) and the voltage VOUTN of the second common-mode output terminal is at a high level (VDD), the first logic signal PG is at a high level (VDD), the second logic signal NG is at a low level (GND), the gate voltage of the first field-effect transistor MP1 is at a high level (VDD), the gate voltage of the second field-effect transistor MN1 is at a low level (GND), and both the first field-effect transistor MP1 and the second field-effect transistor MN1 are turned off, so that the common-mode adjustment voltage of the differential amplifier circuit is half of the voltage of the first common-mode input terminal and the voltage of the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

[0057] It can be understood that the first field effect transistor MP1 is a P-type field effect transistor (P-channel MOSFET, PMOS), corresponding to a P-type field effect transistor, which is turned on when the gate voltage is less than the source voltage, and is otherwise turned off. The second field effect transistor MN1 is an N-type field effect transistor, corresponding to an N-channel MOSFET, NMOS, which is turned on when the gate voltage is greater than the source voltage, and is otherwise turned off.

[0058] Based on this, reference Figure 3When the gate voltage of the first FET MP1 is low (GND) and the gate voltage of the second FET MN1 is high (VDD), since the source voltage of the first FET MP1 is low (GND), the gate voltage (VDD) of the first FET MP1 is no less than the source voltage (VDD), and the first FET MP1 is turned off. Furthermore, since the source of the second FET MN1 is grounded (GND), the gate voltage (GND) of the second FET MN1 is no greater than the source voltage (GND), and the second FET MN1 is also turned off. When the first FET MP1 and the second FET MN1 are turned off, since both the first FET MP1 and the second FET MN1 are turned off, no effective current path is formed. Therefore, no current can flow through the RCMI resistor, and I_RCMI = 0. The common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1), and the common-mode current I_RFB flows out of the first common-mode input terminal INT_INP. In this way, the common-mode voltage of the power amplifier circuit 002 is half of the power supply voltage, and the symmetry of the differential amplifier circuit 10 is ensured, thereby improving the suppression capability of the common-mode signal, thereby effectively suppressing the voltage disturbance of the first common-mode input terminal INT_INP.

[0059] It is understood that the above description uses the first common-mode input terminal INT_INP of the differential amplifier circuit 10 in the power amplifier circuit 002 as an example to illustrate the process of suppressing the voltage disturbance at the first common-mode input terminal. In other embodiments of the present application, the voltage disturbance at the second common-mode input terminal INT_INN can be suppressed in a similar manner, which will not be described in detail here.

[0060] It can be understood that in the above four cases where the voltage VOUTP of the first common-mode output terminal and the voltage VOUTN of the second common-mode output terminal are respectively high level, low level, high level and low level, and low level and high level, the corresponding first logic signal, second logic signal, common-mode adjustment voltage (com point voltage), I_RFB and I_RCMI are summarized in Table 1. For Table 1, please refer to the corresponding description above and will not be repeated here.

[0061] Table 1

[0062]

[0063] In some embodiments of the present application, the specific structures of the output common-mode detection circuit 20 and the common-mode disturbance suppression circuit 30 in the common-mode disturbance suppression circuit may be different. For example, Figure 4 A schematic diagram of a power amplifier circuit 003 and a common-mode suppression circuit thereof is shown.

[0064] refer to Figure 4In the power amplifier circuit 004, the output common-mode detection circuit 20 may include a digital logic detection module 201. The common-mode disturbance suppression circuit 30 may include a third field-effect transistor MP2, a fourth field-effect transistor MN2, a fifth field-effect transistor MP3, a sixth field-effect transistor MN3, a first current source Isource1, a second current source Isink1, a third current source Isource2, and a fourth current source Isink2, wherein the first current source Isource1 is equal to the product of the power supply voltage and twice the first feedback resistor RFB1 of the differential amplifier circuit 10, that is, Isource1=VDD / (2*RFB1), and the second current source, the third current source, and the fourth current source are equal, that is, Isink1=Isource2=Isink2=Isource1=VDD / (2*RFB1).

[0065] Specifically, refer to Figure 4 , the source of the third field effect transistor MP2 is connected to the first end of the first current source Isource1, the second end of the first current source Isource1 is connected to the power supply terminal VDD, the gate of the third field effect transistor MP2 is connected to the first output end of the digital logic detection module 201 and the gate of the fifth field effect transistor MP3, the drain of the third field effect transistor MP2 is connected to the drain of the fourth field effect transistor MN2, and the drain of the third field effect transistor MP2 is used to be connected to the second common mode input terminal INT_INN; the gate of the fourth field effect transistor MN2 is connected to the second output end of the digital logic detection module 201 and the gate of the sixth field effect transistor MN3, the source of the fourth field effect transistor MN2 is connected to the first end of the second current source Isink1, and the gate of the fourth field effect transistor MN3 is connected to the second common mode input terminal INT_INN. The second end of the second current source Isink1 is connected to the ground terminal GND; the source of the fifth field effect transistor MP3 is connected to the first end of the third current source Isource2, the second end of the third current source Isource2 is connected to the power supply terminal VDD, the gate of the fifth field effect transistor MP3 is connected to the gate of the third field effect transistor MP2 and the first output end of the digital logic detection module 201, the drain of the fifth field effect transistor MP3 is used to be connected to the second common mode input terminal INT_INN, the drain of the fifth field effect transistor MP3 is connected to the drain of the sixth field effect transistor MN3; the source of the sixth field effect transistor MN3 is connected to the first end of the fourth current source Isink2, and the second end of the fourth current source Isink2 is connected to the ground terminal GND.

[0066] The following combination Figure 4 The power amplifier circuit 003 shown in FIG. 1 illustrates a process of improving the voltage disturbance problem at the common-mode input terminal based on the power amplifier circuit 003 and its common-mode suppression circuit.

[0067] In some embodiments of the present application, if the voltage VOUTP of the first common-mode output terminal and the voltage VOUTN of the second common-mode output terminal are both low (GND), the first logic signal PG and the second logic signal NG are both low (GND), the gate voltage of the third field-effect transistor MP2 and the gate voltage of the fourth field-effect transistor MN2 are both low (GND), the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are turned on, the fourth field-effect transistor MN2 and the sixth field-effect transistor MN3 are turned off, the common-mode adjustment voltage of the differential amplifier circuit is high (VDD), the common-mode current I_RFB corresponding to the first feedback resistor RFB1 flows out of the first common-mode input terminal INT_INP, and the common-mode current I_RCMI corresponding to the common-mode disturbance suppression circuit 30 flows into the first common-mode input terminal INT_INP, so that no common-mode current flows through the first integrating capacitor C1.

[0068] It can be understood that the third field effect transistor MP2 and the fifth field effect transistor MP3 are both P-type field effect transistors (P-channel MOSFET, PMOS), corresponding to P-type field effect transistors, which are turned on when the gate voltage is less than the source voltage, and are otherwise turned off. The fourth field effect transistor MN2 and the sixth field effect transistor MN3 are N-type field effect transistors, corresponding to N-channel MOSFET, NMOS, which are turned on when the gate voltage is greater than the source voltage, and are otherwise turned off.

[0069] Based on this, reference Figure 4When the voltage VOUTP at the first common-mode output terminal is low and the voltage VOUTN at the second common-mode output terminal is low (GND), the first logic signal PG and the second logic signal NG are both low (GND). This means that the gate voltages of the third field-effect transistor MP2, the fifth field-effect transistor MP3, the fourth field-effect transistor MN2, and the sixth field-effect transistor MN3 are all low (GND). Since the sources of the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are the power supply voltage VDD, the gate voltage (GND) of the third field-effect transistor MP2 is less than the source voltage (VDD), and the gate voltage (GND) of the fifth field-effect transistor MP3 is less than the source voltage (VDD), and thus the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are turned on. Because the sources of the fourth and sixth field-effect transistors MN2 and MN3 are grounded (GND), the gate voltage (GND) of the fourth field-effect transistor MN1 is no greater than the source voltage (GND), and the gate voltage (GND) of the sixth field-effect transistor MN3 is no greater than the source voltage (GND), thereby turning off the fourth and sixth field-effect transistors MN2 and MN3. When the third and fifth field-effect transistors MP2 and MP3 are turned on and the fourth and sixth field-effect transistors MN2 and MN3 are turned off, the common-mode adjustment voltage (com point voltage) is pulled up to VDD, where Isource = Isink = VDD / (2*RFB). Furthermore, the common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1). When the first common-mode rejection resistor RCMI1 is equal to the first feedback resistor RFB1, I_RCMI and I_RFB are equal. In this way, the common mode current I_RFB flowing out of the first common mode input terminal INT_INP is offset by the common mode current I_RCMI flowing into the first common mode input terminal INT_INP, and no resistance flows through the first integrating capacitor C1, thereby effectively suppressing the voltage disturbance of the first common mode input terminal INT_INP.

[0070] In some embodiments of the present application, if the voltage VOUTP of the first common-mode output terminal and the voltage VOUTN of the second common-mode output terminal are both high (VDD), the first logic signal PG and the second logic signal NG are both high, the gate voltage of the third field-effect transistor MP2 and the gate voltage of the fourth field-effect transistor MN2 are both high, the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are turned off, the fourth field-effect transistor MN2 and the sixth field-effect transistor MN3 are turned on, the common-mode adjustment voltage (com point voltage) of the differential amplifier circuit 10 is low, the common-mode current I_RFB corresponding to the first feedback resistor RFB1 flows into the first common-mode input terminal INT_INP, and the common-mode current corresponding to the common-mode disturbance suppression circuit 30 flows out of the first common-mode input terminal INT_INP, so that no common-mode current flows through the first integrating capacitor C1.

[0071] It can be understood that the third field effect transistor MP2 and the fifth field effect transistor MP3 are both P-type field effect transistors (P-channel MOSFET, PMOS), corresponding to P-type field effect transistors, which are turned on when the gate voltage is less than the source voltage, and are otherwise turned off. The fourth field effect transistor MN2 and the sixth field effect transistor MN3 are N-type field effect transistors, corresponding to N-channel MOSFET, NMOS, which are turned on when the gate voltage is greater than the source voltage, and are otherwise turned off.

[0072] Based on this, reference Figure 4 When the voltage VOUTP at the first common-mode output terminal and the voltage VOUTN at the second common-mode output terminal are both at a high level (VDD), the first logic signal PG and the second logic signal NG are both at a high level (VDD). This means that the gate voltages of the third field-effect transistor MP2, the fifth field-effect transistor MP3, the fourth field-effect transistor MN2, and the sixth field-effect transistor MN3 are all at a high level (VDD). Since the sources of the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are at the power supply voltage VDD, the gate voltage (VDD) of the third field-effect transistor MP2 is not less than the source voltage (VDD), and the gate voltage (VDD) of the fifth field-effect transistor MP3 is not less than the source voltage (VDD), and the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are cut off. Because the sources of the fourth and sixth field-effect transistors MN2 and MN3 are grounded (GND), the gate voltage (VDD) of the fourth field-effect transistor MN1 is greater than the source voltage (GND), and the gate voltage (VDD) of the sixth field-effect transistor MN3 is greater than the source voltage (GND), turning on the fourth and sixth field-effect transistors MN2 and MN3. When the third and fifth field-effect transistors MP2 and MP3 are turned off, and the fourth and sixth field-effect transistors MN2 and MN3 are turned on, the common-mode adjustment voltage (com point voltage) is pulled up to ground GND. Furthermore, the common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1). When the first common-mode rejection resistor RCMI1 is equal to the first feedback resistor RFB1, I_RCMI and I_RFB are equal. In this way, the common mode current I_RFB flowing into the first common mode input terminal INT_INP is offset by the common mode current I_RCMI flowing out of the first common mode input terminal INT_INP, and no resistance flows through the first integrating capacitor C1, thereby effectively suppressing the voltage disturbance of the first common mode input terminal INT_INP.

[0073] In some embodiments of the present application, if the voltage VOUTN of the first common-mode output terminal is at a high level (VDD) and the voltage VOUTP of the second common-mode output terminal is at a low level (GND), the first logic signal PG is at a high level (VDD), the second logic signal NG is at a low level (GND), the third field-effect transistor MP2, the fourth field-effect transistor MN2, the fifth field-effect transistor MP3 and the sixth field-effect transistor MN3 are all turned off, and the common-mode current I_RFB corresponding to the first feedback resistor RFB1 flows out of the first common-mode input terminal INT_INP, so that the common-mode adjustment voltage (com point voltage) of the differential amplifier circuit 10 is half of the sum of the voltage of the first common-mode input terminal INT_INP and the voltage of the second common-mode input terminal INT_INN, and the common-mode voltage of the differential amplifier circuit 10 is half of the power supply voltage.

[0074] It can be understood that the third field effect transistor MP2 and the fifth field effect transistor MP3 are both P-type field effect transistors (P-channel MOSFET, PMOS), corresponding to P-type field effect transistors, which are turned on when the gate voltage is less than the source voltage, and are otherwise turned off. The fourth field effect transistor MN2 and the sixth field effect transistor MN3 are N-type field effect transistors, corresponding to N-channel MOSFET, NMOS, which are turned on when the gate voltage is greater than the source voltage, and are otherwise turned off.

[0075] Based on this, reference Figure 4When the voltage VOUTP at the first common-mode output terminal is high (VDD) and the voltage VOUTN at the second common-mode output terminal is low (GND), the first logic signal PG is high (VDD) and the second logic signal NG is low (GND). This means that the gate voltages of the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are high (VDD), and the gate voltages of the fourth field-effect transistor MN2 and the sixth field-effect transistor MN3 are both low (GND). Since the sources of the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are the power supply voltage VDD, the gate voltage (VDD) of the third field-effect transistor MP2 is not less than the source voltage (VDD), and the gate voltage (VDD) of the fifth field-effect transistor MP3 is not less than the source voltage (VDD), and the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are cut off. Because the sources of the fourth and sixth field-effect transistors MN2 and MN3 are grounded to GND, the gate voltage (GND) of the fourth field-effect transistor MN1 is no greater than the source voltage (GND), and the gate voltage (GND) of the sixth field-effect transistor MN3 is no greater than the source voltage (GND), thereby turning off the fourth and sixth field-effect transistors MN2 and MN3. When the third field-effect transistors MP2, MP3, MN2, and MN3 are all turned off, and because the first and second field-effect transistors MP1 and MN1 are both turned off, no effective current path is formed between the common-mode adjustment voltage (com point voltage) and either the power supply VDD or the ground terminal GND. The common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1), and I_RFB flows into the first common-mode input terminal INT_INP.

[0076] Based on the above, by setting the common-mode voltage to half of the power supply voltage, the symmetry of the differential amplifier circuit 10 can be ensured, thereby improving the suppression capability of the common-mode signal and effectively suppressing the voltage disturbance of the first common-mode input terminal INT_INP.

[0077] In some embodiments of the present application, if the voltage VOUTP of the first common-mode output terminal is a low level (GND) and the voltage VOUTN of the second common-mode output terminal is a high level (VDD), the first logic signal PG is a high level (VDD), the second logic signal NG is a low level (GND), the third field-effect transistor MP2, the fourth field-effect transistor MN2, the fifth field-effect transistor MP3 and the sixth field-effect transistor MN3 are all turned off, and the common-mode current I_RFB corresponding to the first feedback resistor RFB1 flows into the first common-mode input terminal INT_INP, so that the common-mode adjustment voltage (com point voltage) of the differential amplifier circuit 10 is half of the sum of the voltage of the first common-mode input terminal INT_INP and the voltage of the second common-mode input terminal INT_INN, and the common-mode voltage of the differential amplifier circuit 10 is half of the power supply voltage.

[0078] It can be understood that the third field effect transistor MP2 and the fifth field effect transistor MP3 are both P-type field effect transistors (P-channel MOSFET, PMOS), corresponding to P-type field effect transistors, which are turned on when the gate voltage is less than the source voltage, and are otherwise turned off. The fourth field effect transistor MN2 and the sixth field effect transistor MN3 are N-type field effect transistors, corresponding to N-channel MOSFET, NMOS, which are turned on when the gate voltage is greater than the source voltage, and are otherwise turned off.

[0079] Based on this, reference Figure 4 When the voltage VOUTP at the first common-mode output terminal is at a low level (GND) and the voltage VOUTN at the second common-mode output terminal is at a high level (VDD), the first logic signal PG is at a high level (VDD) and the second logic signal NG is at a low level (GND). This means that the gate voltages of the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are at a high level (VDD), while the gate voltages of the fourth field-effect transistor MN2 and the sixth field-effect transistor MN3 are both at a low level (GND). Since the source voltages of the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are at the power supply voltage VDD, the gate voltage (VDD) of the third field-effect transistor MP2 is not less than the source voltage (VDD), and the gate voltage (VDD) of the fifth field-effect transistor MP3 is not less than the source voltage (VDD), and the third field-effect transistor MP2 and the fifth field-effect transistor MP3 are turned off. Since the source electrodes of the fourth field effect transistor MN2 and the sixth field effect transistor MN3 are grounded GND, the gate voltage (GND) of the fourth field effect transistor MN1 is not greater than the source voltage (GND), and the gate voltage (GND) of the sixth field effect transistor MN3 is not greater than the source voltage (GND), and thus the fourth field effect transistor MN2 and the sixth field effect transistor MN3 are turned off. When the third field effect transistor MP2, the fifth field effect transistor MP3, the fourth field effect transistor MN2, and the sixth field effect transistor MN3 are all turned off. Since the first field effect transistor MP1 and the second field effect transistor MN1 are both turned off, no effective current path is formed. The common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1), and the common-mode current I_RFB flows out of the first common-mode input terminal INT_INP.

[0080] Based on the above, since the common-mode voltage is set to half of the power supply voltage, the symmetry of the differential amplifier circuit 10 can be ensured, thereby improving the suppression capability of the common-mode signal and effectively suppressing the voltage disturbance of the first common-mode input terminal INT_INP.

[0081] It will be appreciated that the above description uses the first common-mode input terminal INT_INP of the differential amplifier circuit 10 in the power amplifier circuit 003 as an example to illustrate the process of suppressing the voltage disturbance at the first common-mode input terminal. In other embodiments of the present application, the voltage disturbance at the second common-mode input terminal INT_INN can be suppressed in a similar manner, which will not be described in detail here.

[0082] It can be understood that in the above four cases where the voltage VOUTP of the first common-mode output terminal and the voltage VOUTN of the second common-mode output terminal are respectively high level, low level, high level and low level, and low level and high level, the corresponding first logic signal, second logic signal, on-off state (such as ON or OFF) of the third field-effect transistor MP2, the fourth field-effect transistor MN2, the fifth field-effect transistor MP3 and the sixth field-effect transistor MN3, I_RFB and I_RCMI are summarized in Table 2, and Table 2 is not repeated here.

[0083] Table 2

[0084]

[0085] In addition, in some embodiments of the present application, the above Figure 3 and Figure 4 The digital logic detection module 201 in the embodiment can also be Figure 5 FIG. 2 is a circuit diagram of the digital logic detection module 201 shown in FIG.

[0086] refer to Figure 5 Specifically, the digital logic detection module 201 includes a NOR gate (NOR), a NAND gate (NAND), a first NOT gate (NOT1) and a second NOT gate (NOT2); the first input terminal of the NOR gate is used to connect to the first common-mode output terminal OUTP, the second input terminal of the NOR gate is used to connect to the second common-mode output terminal OUTN, the output terminal of the NOR gate is connected to the input terminal of the first NOT gate, and the first NOT gate is used to output a first logic signal PG; the first input terminal of the NAND gate is used to connect to the first common-mode output terminal OUTP, the second input terminal of the NAND gate is used to connect to the second common-mode output terminal OUTN, the output terminal of the NAND gate is connected to the input terminal of the second NOT gate, and the second NOT gate is used to output a second logic signal NG.

[0087] It can be understood that the first common-mode output signal VOUTP can be input to the first input terminal of the digital logic detection module 201, and the second common-mode output signal VOUTN can be input to the second input terminal of the digital logic detection module 201. In addition, in a logic circuit, a high level (VDD) can be represented by 1, and a low level (GND) can be represented by 0.

[0088] In some embodiments of the present application, when the first common-mode output signal VOUTP and the second common-mode output signal VOUTN are both at a high level (VDD), the output of the NOR gate (NOR) is 0, and the output of the first NOT gate (NOT1) is 1, then the first logic signal PG is 1. When the output of the NAND gate (NAND) is 0, and the output of the second NOT gate (NOT2) is 1, then the second logic signal PG is 1.

[0089] In some embodiments of the present application, when the first common-mode output signal VOUTP and the second common-mode output signal VOUTN are both at a low level (GND), the output of the NOR gate (NOR) is 1 and the output of the first NOT gate (NOT1) is 0, then the first logic signal PG is 0. When the output of the NAND gate (NAND) is 1 and the output of the second NOT gate (NOT2) is 0, then the second logic signal PG is 0.

[0090] In some embodiments of the present application, when the first common-mode output signal VOUTP is at a high level (VDD) and the second common-mode output signal VOUTN is at a low level (GND), the output of the NOR gate (NOR) is 0 and the output of the first NOT gate (NOT1) is 1, then the first logic signal PG is 1. When the output of the NAND gate (NAND) is 1 and the output of the second NOT gate (NOT2) is 0, then the second logic signal PG is 0.

[0091] In some embodiments of the present application, when the first common-mode output signal VOUTP is at a low level (GND) and the second common-mode output signal VOUTN is at a high level (VDD), the output of the NOR gate (NOR) is 0 and the output of the first NOT gate (NOT1) is 1, then the first logic signal PG is 1. When the output of the NAND gate (NAND) is 1 and the output of the second NOT gate (NOT2) is 0, then the second logic signal PG is 0.

[0092] In some embodiments of the present application, the specific structures of the output common-mode detection circuit 20 and the common-mode disturbance suppression circuit 30 in the common-mode disturbance suppression circuit may be different. For example, Figure 6 A schematic diagram of a power amplifier circuit 004 and a common-mode suppression circuit thereof is shown.

[0093] refer to Figure 6 In the power amplifier circuit 004, the output common-mode detection circuit 20 may include a first common-mode detection resistor R01 and a second common-mode detection resistor R02, wherein the first common-mode detection resistor R01 and the second common-mode detection resistor R02 are equal. The common-mode disturbance suppression circuit 30 includes a first operational amplifier OPA1, a negative feedback resistor R03, a third common-mode suppression resistor RCM3, and a fourth common-mode suppression resistor RCM4, wherein the third common-mode suppression resistor RCM3 and the fourth common-mode suppression resistor RCM4 have equal resistance values.

[0094] Specifically, refer to Figure 6 , the first end of the first common-mode detection resistor R01 is used to be connected to the first common-mode output terminal OUTP, the first end of the second common-mode detection resistor R02 is used to be connected to the second common-mode output terminal OUTN, the second end of the first common-mode detection resistor R01 is connected to the second end of the second common-mode detection resistor R02 and the inverting input terminal of the first operational amplifier OPA1, wherein the input voltage of the positive input terminal of the first operational amplifier OPA1 is half of the power supply voltage; the output terminal of the first operational amplifier OPA1 is connected to the second end of the negative feedback resistor R03, the first end of the third common-mode suppression resistor RCM3 and the fourth common-mode The first end of the suppression resistor RCM4 is connected, the second end of the third common-mode suppression resistor RCM3 is used to be connected to the second common-mode input terminal INT_INN, and the second end of the fourth common-mode suppression resistor RCM4 is used to be connected to the first common-mode input terminal INT_INP; the output common-mode detection circuit 20 is used to generate control information according to the voltage VOUTP of the first common-mode output terminal and the voltage VOUTN of the second common-mode output terminal, and the control information includes a divided voltage generated based on the first common-mode detection resistor R01 and the second common-mode detection resistor R02, and the voltage of the negative input terminal of the first operational amplifier OPA1 is the divided voltage.

[0095] The following combination Figure 6 The power amplifier circuit 004 shown in the figure illustrates the process of improving the voltage disturbance problem at the common-mode input terminal based on the power amplifier circuit 004 and its common-mode suppression circuit.

[0096] In some embodiments of the present application, based on the negative feedback resistor R03 being equal to half of the first common-mode detection resistor RO1, if the voltage VOUTP at the first common-mode output terminal and the voltage VOUTN at the second common-mode output terminal are both at a low level (GND), based on the first operational amplifier OPA1 and the negative feedback resistor R03, the common-mode adjustment voltage of the differential amplifier circuit 10 is equal to the power supply voltage VDD, thereby causing the common-mode current I_RFB corresponding to the first feedback resistor RFB1 of the differential amplifier circuit 10 to flow out of the first common-mode input terminal INT_INP, and the common-mode current I_RCMI corresponding to the common-mode disturbance suppression circuit 30 to flow into the first common-mode input terminal INT_INP, so that no common-mode current flows through the first integrating capacitor C1.

[0097] Specifically, refer to Figure 6The inverting input of the first operational amplifier OPA1 is connected to VOUTP and VOUTN through the first common-mode sense resistor R01 and the second common-mode sense resistor R02, respectively. Both VOUTP and VOUTN are at a low level, GND. The first common-mode sense resistor R01 and the second common-mode sense resistor R02 form a voltage divider, dividing the voltages of VOUTP and VOUTN to the inverting input of the first operational amplifier OPA1. The voltage of the inverting input of the first operational amplifier OPA1 is also GND. Due to the virtual short-circuit characteristic of the operational amplifier, the voltage at the inverting input of the first operational amplifier OPA1 tends to approach the voltage of the positive input of the first operational amplifier OPA1. If the voltage at the positive input of the first operational amplifier OPA1 is VDD / 2, the inverting input of the first operational amplifier OPA1 will also tend to VDD / 2. Based on this, the first operational amplifier OPA1 adjusts its output, causing the voltage at the inverting input of the first operational amplifier OPA1 to increase. This is because negative feedback resistor R03 connects the output of the first operational amplifier OPA1 back to the inverting input, forming a feedback loop. Furthermore, with both VOUTP and VOUTN at GND, the output of the first operational amplifier OPA1, or the common-mode adjustment voltage (i.e., the com point), increases to a voltage of VDD. This allows the current flowing through negative feedback resistor R03 to pull the inverting input to VDD, thereby maintaining the voltages at the inverting and positive inputs as close as possible. The voltage at the positive input is VDD / 2, meaning the inverting input is also pulled close to VDD to maintain current balance. Subsequently, the first operational amplifier OPA1 can adjust its output voltage and drive current to ultimately bring the voltage at the inverting input close to the voltage at the positive input, VDD / 2. Based on the above, the output of the first operational amplifier OPA1, or the com point voltage, or the common-mode adjustment voltage, is VDD. Therefore, based on RCMI1=RCMI2, the common-mode voltage of the differential amplifier circuit is half the power supply voltage through voltage division.

[0098] In addition, the common-mode current I_RCMI corresponding to the third common-mode suppression resistor RCMI3 is equal to VDD / (2*RCMI3). The common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1). When the first common-mode suppression resistor RCMI1 is equal to the first feedback resistor RFB1, I_RCMI and I_RFB are equal. In this way, the common-mode current I_RFB flowing out of the first common-mode input terminal INT_INP is offset by the common-mode current I_RCMI flowing into the first common-mode input terminal INT_INP, and no resistance flows through the first integrating capacitor C1, effectively suppressing the voltage disturbance of the first common-mode input terminal INT_INP.

[0099] In some embodiments of the present application, based on the negative feedback resistor R03 being equal to half of the first common-mode detection resistor RO1, if the voltage VOUTP of the first common-mode output terminal and the voltage VOUTN of the second common-mode output terminal are both at a high level (VDD), the common-mode adjustment voltage of the differential amplifier circuit 10 is made low (GND) based on the first operational amplifier OPA1 and the negative feedback resistor R03, thereby causing the common-mode current I_RFB corresponding to the first feedback resistor RFB1 to flow into the first common-mode input terminal INT_INP, and the common-mode current corresponding to the common-mode disturbance suppression circuit 30 to flow out of the first common-mode input terminal INT_INP, so that no common-mode current flows through the first integrating capacitor C1.

[0100] Specifically, refer to Figure 6 The inverting input of the first operational amplifier OPA1 is connected to VOUTP and VOUTN through the first common-mode sense resistor R01 and the second common-mode sense resistor R02, respectively. Both VOUTP and VOUTN are at a high level (VDD). The first common-mode sense resistor R01 and the second common-mode sense resistor R02 form a voltage divider. The divided voltage based on VOUTP and VOUTN is input to the inverting input of the first operational amplifier OPA1, resulting in a voltage at VDD. Due to the virtual short-circuit characteristic of the operational amplifier, the voltage at the inverting input of the first operational amplifier OPA1 tends to approach the voltage at the positive input of the first operational amplifier OPA1. If the voltage at the positive input of the first operational amplifier OPA1 is VDD / 2, the inverting input of the first operational amplifier OPA1 will also tend to VDD / 2. Based on this, the first operational amplifier OPA1 adjusts its output to reduce the voltage at the inverting input of the first operational amplifier OPA1. This is because the negative feedback resistor R03 connects the output of the first operational amplifier OPA1 back to the reverse input terminal, forming a feedback loop. Therefore, the output terminal of the first operational amplifier OPA1, that is, the common-mode adjustment voltage terminal (that is, the com point), will be reduced to a voltage GND, so that the current passing through the negative feedback resistor R03 can pull the reverse input terminal to GND. This is because the first operational amplifier OPA1 will try to keep the voltage of the reverse input terminal and the positive input terminal equal, and the positive input terminal is VDD / 2, so the negative input terminal will also be pulled close to GND to maintain current balance. In addition, the first operational amplifier OPA1 can also adjust the output voltage and drive current to eventually make the voltage of the reverse input terminal close to the voltage of the positive input terminal VDD / 2.

[0101] In addition, the common-mode current I_RCMI corresponding to the third common-mode suppression resistor RCMI3 is equal to VDD / (2*RCMI3). The common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1). When the first common-mode suppression resistor RCMI1 is equal to the first feedback resistor RFB1, I_RCMI and I_RFB are equal. In this way, the common-mode current I_RFB flowing into the first common-mode input terminal INT_INP is offset by the common-mode current I_RCMI flowing out of the first common-mode input terminal INT_INP, and no resistance flows through the first integrating capacitor C1, effectively suppressing the voltage disturbance of the first common-mode input terminal INT_INP.

[0102] In some embodiments of the present application, based on the negative feedback resistor R03 being equal to half of the first common-mode detection resistor RO1, if the voltage VOUTP of the first common-mode output terminal is at a high level (VDD) and the voltage VOUTN of the second common-mode output terminal is at a low level (GND), based on the first operational amplifier OPA1 and the negative feedback resistor R03, the common-mode adjustment voltage of the differential amplifier circuit 10 is half of the sum of the voltage of the first common-mode input terminal and the voltage of the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

[0103] Specifically, refer to Figure 6 , the inverting input of the first operational amplifier OPA1 is connected to VOUTP and VOUTN through the first common-mode sense resistor R01 and the second common-mode sense resistor R02, respectively. VOUTP is at a high level VDD, and VOUTN is at a low level GND. In this case, the inverting input of the first operational amplifier OPA1 is connected to VOUTP and VOUTN through the first common-mode sense resistor R01 and the second common-mode sense resistor R02, respectively. The first common-mode sense resistor R01 and the second common-mode sense resistor R02 form a voltage divider, dividing the voltages of VOUTP and VOUTN to the inverting input of the first operational amplifier OPA1. When VOUTP is at VDD and VOUTN is at GND, the voltage at the inverting input will be close to VDD / 2.

[0104] It can be understood that the com point is the point where the negative feedback resistor R03 is connected to the output of the first operational amplifier OPA1. Since the output of the first operational amplifier OPA1 is adjusted to maintain the voltage at the negative input terminal close to VDD / 2, the voltage at the com point is also adjusted to close to VDD / 2. The negative feedback resistor R03 is equal to half of the first common-mode detection resistor R01 or the second common-mode detection resistor R02, that is, R03 = 0.5*R01 or R03 = 0.5*R02. In addition, corresponding to the positive input terminal of the first operational amplifier OPA1 being VDD / 2, the output of the first operational amplifier OPA1 is adjusted to maintain the voltage at the negative input terminal of the first operational amplifier OPA1 close to the voltage VDD / 2 of the positive input terminal of the first operational amplifier OPA1. Therefore, the voltage at the com point can be adjusted to close to VDD / 2 through the negative feedback resistor R03 to ensure that the current through the feedback resistor R03 remains balanced between the negative input terminal and the positive input terminal.

[0105] In addition, the common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1), and the common-mode current I_RFB flows into the first common-mode input terminal INT_INP. However, due to the high input impedance characteristics of the first operational amplifier OPA1, the current flowing into the first operational amplifier OPA1 is extremely small and can be approximately considered to be zero. It can be understood that in an ideal operational amplifier, due to the effect of negative feedback, the voltages of the two input terminals (positive input terminal and negative input terminal) of the first operational amplifier OPA1 will be very close, almost equal. This phenomenon is called a virtual short circuit. When the voltage difference between the first common-mode input terminal VOUTP and the second common-mode input terminal VOUTN of the power amplifier circuit 004 is large, the first operational amplifier OPA1 will adjust its output to maintain the balance of the negative feedback loop.

[0106] It is understandable that in other embodiments of the present application, considering the output swing of the first operational amplifier OPA1, the negative feedback resistor R03 may also be smaller than half of the first common-mode detection resistor R01 or the second common-mode detection resistor R02, which is not limited here.

[0107] Based on the above, when the common-mode voltage is set to half of the power supply voltage, i.e., VDD / 2, the symmetry of the differential amplifier circuit 10 is ensured, thereby improving the suppression capability of the common-mode signal, thereby effectively suppressing the voltage disturbance of the first common-mode input terminal INT_INP.

[0108] In some embodiments of the present application, based on the negative feedback resistor R03 being equal to half of the first common-mode detection resistor RO1, if the voltage VOUTN of the first common-mode output terminal is at a low level (GND) and the voltage VOUTN of the second common-mode output terminal is at a high level (VDD), based on the first operational amplifier OPA1 and the negative feedback resistor R03, the common-mode adjustment voltage of the differential amplifier circuit 10 is half of the sum of the voltage of the first common-mode input terminal and the voltage of the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit 10 is half of the power supply voltage.

[0109] Specifically, refer to Figure 6 , the inverting input of the first operational amplifier OPA1 is connected to VOUTP and VOUTN through the first common-mode sense resistor R01 and the second common-mode sense resistor R02, respectively. VOUTP is at a high level VDD, and VOUTN is at a low level GND. In this case, the inverting input of the first operational amplifier OPA1 is connected to VOUTP and VOUTN through the first common-mode sense resistor R01 and the second common-mode sense resistor R02, respectively. The first common-mode sense resistor R01 and the second common-mode sense resistor R02 form a voltage divider, dividing the voltages of VOUTP and VOUTN to the inverting input of the first operational amplifier OPA1. When VOUTP is at GND and VOUTN is at VDD, the voltage at the inverting input will be close to VDD / 2.

[0110] It can be understood that the com point is the point where the negative feedback resistor R03 is connected to the output of the first operational amplifier OPA1. Since the output of the first operational amplifier OPA1 is adjusted to maintain the voltage at the negative input terminal close to VDD / 2, the voltage at the com point is also adjusted to close to VDD / 2. The negative feedback resistor R03 is equal to half of the first common-mode detection resistor R01 or the second common-mode detection resistor R02, that is, R03 = 0.5*R01 or R03 = 0.5*R02. In addition, corresponding to the positive input terminal of the first operational amplifier OPA1 being VDD / 2, the output of the first operational amplifier OPA1 is adjusted to maintain the voltage at the negative input terminal of the first operational amplifier OPA1 close to the voltage VDD / 2 of the positive input terminal of the first operational amplifier OPA1. Therefore, the voltage at the com point can be adjusted to close to VDD / 2 through the negative feedback resistor R03 to ensure that the current through the feedback resistor R03 remains balanced between the negative input terminal and the positive input terminal.

[0111] In addition, the common-mode current I_RFB corresponding to the first feedback resistor RFB1 is equal to VDD / (2*RFB1), and the common-mode current I_RFB flows out of the first common-mode input terminal INT_INP. Due to the high input impedance characteristics of the first operational amplifier OPA1, the current flowing into the first operational amplifier OPA1 is extremely small and can be approximately considered to be zero. It can be understood that in an ideal operational amplifier, due to the effect of negative feedback, the voltages of the two input terminals (positive input terminal and negative input terminal) of the first operational amplifier OPA1 will be very close, almost equal. This phenomenon is called a virtual short circuit. When the voltage difference between the first common-mode input terminal VOUTP and the second common-mode input terminal VOUTN of the power amplifier circuit 004 is large, the first operational amplifier OPA1 will adjust its output to maintain the balance of the negative feedback loop.

[0112] Based on the above, when the common-mode voltage is set to half of the power supply voltage, the symmetry of the differential amplifier circuit 10 is ensured, thereby improving the suppression capability of the common-mode signal, thereby effectively suppressing the voltage disturbance of the first common-mode input terminal INT_INP.

[0113] It can be understood that, in the above four cases where the voltage VOUTP of the first common-mode output terminal and the voltage VOUTN of the second common-mode output terminal are respectively high level, low level, high level and low level, and low level and high level, the corresponding common-mode adjustment voltage (com point voltage), the first feedback current I_RFB and the first common-mode suppression current I_RCMI are summarized in Table 3, and Table 3 is not repeated here.

[0114] Table 3

[0115]

[0116] The present application also provides a power amplifier circuit, including the common-mode suppression circuit and the differential amplifier circuit in the embodiment of the present application.

[0117] For example, Figure 2 、 Figure 3 、 Figure 4 and Figure 6In the power amplifier circuit shown, the differential amplifier circuit 10 may include a modulation module 101, a first comparison amplifier module 102, a second comparison amplifier module 103, a first integral capacitor C1, a second integral capacitor C2, a first feedback resistor RFB1, a second feedback resistor RFB2, and an output driver module 104, wherein the resistance of the first feedback resistor RFB1 is equal to that of the second feedback resistor RFB2, and the first integral capacitor C1 is equal to that of the second integral capacitor C2; the first input terminal of the modulation module 101 is connected to the first common-mode input terminal INT_INP, the first end of the first integral capacitor C1, and the first end of the first feedback resistor RFB1, the second end of the first integral capacitor C1 is connected to the first output terminal of the modulation module 101 and the first input terminal of the first comparison amplifier module 102, the second end of the first feedback resistor RFB1 is connected to the first common-mode output terminal VOUTP, and the modulation module 101 The second input terminal of the first comparative amplification module 102 is connected to the second common-mode input terminal INT_INN, the first terminal of the second integral capacitor C2, and the first terminal of the second feedback resistor RFB2. The second terminal of the second integral capacitor C2 is connected to the second output terminal of the modulation module 101 and the first input terminal of the second comparative amplification module 103. The second end of the second feedback resistor RFB2 is connected to the second common-mode output terminal VOUTN. The second input terminal of the first comparative amplification module 102 is connected to the second input terminal of the second comparative amplification module 103. The output terminal of the first comparative amplification module 102 is connected to the first input terminal of the output driver module 104. The output terminal of the second comparative amplification module 103 is connected to the second input terminal of the output driver module 104. The first output terminal of the output driver module 104 is connected to the first common-mode output terminal VOUTP, and the second output terminal of the output driver module 104 is connected to the second common-mode output terminal VOUTN.

[0118] In addition, the operating principle of the differential amplifier circuit 10 may include: the input signal is input to the modulation module 101 through the first common-mode input terminal INT_INP and the second common-mode input terminal INT_INT respectively. The modulation module 101 processes the input signal and sends it to the first comparison amplifier module 101 and the second comparison amplifier module 102 respectively. The first comparison amplifier module 101 generates a first pulse width modulation (PWM) signal based on the processed input signal, and the second comparison amplifier module 102 generates a second PWM signal based on the processed input signal. Further, the first comparison amplifier module 101 sends the first PWM signal to the output driver module 104, and the second comparison amplifier module 102 sends the second PWM signal to the output driver module 104. The output driver module 104 can output a first common-mode output signal and a second common-mode output signal respectively according to the first PWM signal and the second PWM signal. It can be understood that the first common-mode output signal can be referred to as VOUTP, and the second common-mode output signal can be referred to as VOUTN.

[0119] It can be understood that the circuit structure of the differential amplifier circuit 10 in the present application is only an example. In other embodiments of the present application, the circuit structure of the differential amplifier circuit 10 may be different, which is not limited here.

[0120] By the common-mode suppression circuit provided in the embodiment of the present application, the voltage (VOUTP and VOUTN) of the common-mode output terminal of the differential amplifier circuit 10 is detected by the output common-mode detection circuit 20, and control information that can adjust the common-mode disturbance suppression circuit 30 is generated, so that the common-mode disturbance suppression circuit 30 can adjust the common-mode adjustment voltage based on the control information, so as to make the common-mode current flowing into and out of the same common-mode input terminal (such as INT_INP or INT_INN) of the differential amplifier circuit 10 the same based on the common-mode adjustment voltage (com point voltage). In this way, there is no common-mode current flowing through the integral capacitor C of the differential amplifier circuit 10, which can effectively suppress the voltage disturbance at the common-mode input terminal of the differential amplifier circuit 10. Alternatively, by making the common-mode voltage of the differential amplifier circuit 10 half of the power supply voltage, the symmetry of the differential amplifier circuit 10 is ensured, thereby effectively suppressing the voltage disturbance at the common-mode input terminal of the differential amplifier circuit 10.

[0121] In addition, the common-mode suppression circuit provided in the embodiment of the present application has a small circuit scale and can be implemented with relatively small power consumption and area cost, which can save design resources and has relatively strong competitiveness in low-power design.

[0122] In the embodiment of the present application, based on any one of the common-mode suppression circuits among the power amplifier circuit 001 , the power amplifier circuit 002 , the power amplifier circuit 003 , and the power amplifier circuit 004 , the voltage at the common-mode input terminal can be effectively suppressed.

[0123] For example, Figure 7 A waveform diagram of a common-mode input terminal in a power amplifier circuit is shown to reflect the suppression effect of the voltage at the common-mode input terminal.

[0124] like Figure 7As shown in , based on the input signal being 0, the common-mode output terminal outputs a signal with a 50% duty cycle. When the voltage VOUTP of the first common-mode output terminal and the voltage VOUTN of the second common-mode output terminal are both high or low, and the feedback resistor RFB and the common-mode suppression resistor RCMI in the embodiment of the present application are equal, that is, RFB=RCMI, the common-mode current fed back by I_RFB can be offset by the current provided by I_RCMI, so that no common-mode current flows through the integral capacitor C, that is, the current I_C corresponding to the integral capacitor C is 0. In addition, the voltage of the first common-mode input terminal INT_INP and the voltage of the second common-mode input terminal INT_INN are stable at VDD / 2, and the symmetry of the differential amplifier circuit 10 is ensured, thereby effectively eliminating the voltage fluctuation of the common-mode input terminal.

[0125] The present application also provides a chip, including the power amplifier circuit provided in the embodiments of the present application.

[0126] The present application also provides an electronic device, comprising the chip provided in the embodiments of the present application.

[0127] In the accompanying drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of a structural or method feature in a particular figure does not imply that such feature is required in all embodiments, and in some embodiments, such features may not be included or may be combined with other features.

[0128] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems raised by this application. In addition, in order to highlight the innovative part of this application, the above-mentioned device embodiments of this application do not introduce units / modules that are not closely related to solving the technical problems raised by this application. This does not mean that other units / modules do not exist in the above-mentioned device embodiments.

[0129] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprises a" do not exclude the presence of other identical elements in the process, method, article or device that includes the mentioned elements.

[0130] Although the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims

1. A common mode suppression circuit, characterized in that: Applied to differential amplifier circuit, including: common-mode disturbance suppression circuit and output common-mode detection circuit; The first input terminal of the output common mode detection circuit is used to connect to the first common mode output terminal of the differential amplifier circuit, and the second input terminal of the output common mode detection circuit is used to connect to the second common mode output terminal of the differential amplifier circuit; The output end of the output common mode detection circuit is connected to the input end of the common mode disturbance suppression circuit; The first output terminal of the common-mode disturbance suppression circuit is used to connect to the second common-mode input terminal of the differential amplifier circuit, and the second output terminal of the common-mode disturbance suppression circuit is used to connect to the first common-mode input terminal of the differential amplifier circuit; The output common-mode detection circuit is configured to generate control information according to the voltage of the first common-mode output terminal and the voltage of the second common-mode output terminal; The common-mode disturbance suppression circuit is used to adjust the common-mode voltage of the differential amplifier circuit based on the control information so that the common-mode current flowing into and out of the same common-mode input terminal is the same, or so that the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

2. The common mode suppression circuit according to claim 1, characterized in that: The output common mode detection circuit includes a digital logic detection module, a first input end of the digital logic detection module is used to connect to the first common mode output end, and a second input end of the digital logic detection module is used to connect to the second common mode output end; The digital logic detection module is used to obtain the voltage of the first common-mode output terminal and the voltage of the second common-mode output terminal, and generate control information based on the voltage of the first common-mode output terminal and the voltage of the second common-mode output terminal to control the common-mode disturbance suppression circuit, wherein the control information includes a first logic signal and a second logic signal.

3. The common mode suppression circuit according to claim 2, characterized in that: The common-mode disturbance suppression circuit includes a first field-effect transistor and a second field-effect transistor, a first common-mode suppression resistor and a second common-mode suppression resistor, wherein the first common-mode suppression resistor and the second common-mode suppression resistor have the same resistance value; The source of the first field effect transistor is connected to the power supply terminal, the gate of the first field effect transistor is connected to the first output terminal of the digital logic detection module, and the drain of the first field effect transistor is connected to the drain of the second field effect transistor, the first end of the first common-mode suppression resistor, and the first end of the second common-mode suppression resistor; The gate of the second field effect transistor is connected to the second output terminal of the digital logic detection module, and the source of the second field effect transistor is connected to the ground terminal; The second end of the first common-mode suppression resistor is used to be connected to the second common-mode input terminal, and the second end of the second common-mode suppression resistor is used to be connected to the first common-mode input terminal; The first logic signal is used to control the gate voltage of the first field effect transistor to be a high level or a low level.

4. The common mode suppression circuit according to claim 3, characterized in that: Based on the first feedback resistor of the differential amplifier circuit being equal to the first common-mode suppression resistor, if the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both low, the first logic signal and the second logic signal are both low, the gate voltage of the first field-effect transistor and the gate voltage of the second field-effect transistor are both low, the first field-effect transistor is turned on, the second field-effect transistor is turned off, and the common-mode adjustment voltage of the differential amplifier circuit is high, so that the common-mode current corresponding to the first feedback resistor flows out of the first common-mode input terminal, and the common-mode current corresponding to the first common-mode suppression resistor flows into the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor of the differential amplifier circuit; Based on the first feedback resistor being equal to the first common-mode suppression resistor, if the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both high, then the first logic signal and the second logic signal are both high, the gate voltage of the first field-effect transistor and the gate voltage of the second field-effect transistor are both high, the first field-effect transistor is turned off, the second field-effect transistor is turned on, and the common-mode adjustment voltage of the differential amplifier circuit is low, so that the common-mode current corresponding to the first feedback resistor flows into the first common-mode input terminal, and the common-mode current corresponding to the first common-mode suppression resistor flows out of the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor; If the voltage at the first common-mode output terminal is at a high level and the voltage at the second common-mode output terminal is at a low level, the first logic signal is at a high level and the second logic signal is at a low level, the gate voltage of the first field-effect transistor is at a high level and the gate voltage of the second field-effect transistor is at a low level, and both the first field-effect transistor and the second field-effect transistor are turned off, so that the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage at the first common-mode input terminal and the voltage at the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage; If the voltage at the first common-mode output terminal is low and the voltage at the second common-mode output terminal is high, the first logic signal is high, the second logic signal is low, the gate voltage of the first field-effect transistor is high, the gate voltage of the second field-effect transistor is low, and both the first field-effect transistor and the second field-effect transistor are turned off, so that the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage at the first common-mode input terminal and the voltage at the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

5. The common mode suppression circuit according to claim 2, wherein: The common-mode disturbance suppression circuit includes a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, a first current source, a second current source, a third current source, and a fourth current source, wherein the first current source is equal to a product of a power supply voltage and twice the first feedback resistance of the differential amplifier circuit, and the second current source, the third current source, and the fourth current source are equal; The source of the third field-effect transistor is connected to the first end of the first current source, the second end of the first current source is connected to the power supply end, the gate of the third field-effect transistor is connected to the first output end of the digital logic detection module and the gate of the fifth field-effect transistor, the drain of the third field-effect transistor is connected to the drain of the fourth field-effect transistor, and the drain of the third field-effect transistor is used to be connected to the second common-mode input end; The gate of the fourth field effect transistor is connected to the second output terminal of the digital logic detection module and the gate of the sixth field effect transistor, the source of the fourth field effect transistor is connected to the first terminal of the second current source, and the second terminal of the second current source is connected to the ground terminal; The source of the fifth field effect transistor is connected to the first end of the third current source, the second end of the third current source is connected to the power supply end, the drain of the fifth field effect transistor is used to be connected to the second common mode input end, and the drain of the fifth field effect transistor is connected to the drain of the sixth field effect transistor; The source of the sixth field effect transistor is connected to the first end of the fourth current source, and the second end of the fourth current source is connected to the ground end.

6. The common mode suppression circuit according to claim 5, characterized in that: If the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both low, the first logic signal and the second logic signal are both low, the gate voltage of the third field-effect transistor and the gate voltage of the fourth field-effect transistor are both low, the third field-effect transistor and the fifth field-effect transistor are turned on, the fourth field-effect transistor and the sixth field-effect transistor are turned off, the common-mode adjustment voltage of the differential amplifier circuit is high, the common-mode current corresponding to the first feedback resistor flows out of the first common-mode input terminal, and the common-mode current corresponding to the common-mode disturbance suppression circuit flows into the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor of the differential amplifier circuit; If the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both high, the first logic signal and the second logic signal are both high, the gate voltage of the third field-effect transistor and the gate voltage of the fourth field-effect transistor are both high, the third field-effect transistor and the fifth field-effect transistor are turned off, the fourth field-effect transistor and the sixth field-effect transistor are turned on, the common-mode adjustment voltage of the differential amplifier circuit is low, the common-mode current corresponding to the first feedback resistor flows into the first common-mode input terminal, and the common-mode current corresponding to the common-mode disturbance suppression circuit flows out of the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor; If the voltage of the first common-mode output terminal is at a high level and the voltage of the second common-mode output terminal is at a low level, the first logic signal is at a high level, the second logic signal is at a low level, and the third field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, and the sixth field-effect transistor are all turned off, so that the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage of the first common-mode input terminal and the voltage of the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage; If the voltage of the first common-mode output terminal is at a low level and the voltage of the second common-mode output terminal is at a high level, the first logic signal is at a high level, the second logic signal is at a low level, and the third field-effect transistor, the fourth field-effect transistor, the fifth field-effect transistor, and the sixth field-effect transistor are all turned off, so that the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage of the first common-mode input terminal and the voltage of the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

7. The common mode suppression circuit according to claim 2, characterized in that: The output common mode detection circuit includes a NOR gate, a NAND gate, a first NOT gate and a second NOT gate; The first input terminal of the NOR gate is used to be connected to the first common-mode output terminal, the second input terminal of the NOR gate is used to be connected to the second common-mode output terminal, the output terminal of the NOR gate is connected to the input terminal of the first NOT gate, and the first NOT gate is used to output the first logic signal; The first input end of the NAND gate is used to connect to the first common-mode output end, the second input end of the NAND gate is used to connect to the second common-mode output end, the output end of the NAND gate is connected to the input end of the second NOT gate, and the second NOT gate is used to output the second logic signal.

8. The common mode suppression circuit according to claim 1, wherein: The output common-mode detection circuit includes a first common-mode detection resistor and a second common-mode detection resistor, wherein the first common-mode detection resistor and the second common-mode detection resistor have the same resistance value; The common-mode disturbance suppression circuit includes a first operational amplifier, a negative feedback resistor, a third common-mode suppression resistor and a fourth common-mode suppression resistor, wherein the third common-mode suppression resistor and the fourth common-mode suppression resistor have equal resistance values; The first end of the first common-mode detection resistor is used to be connected to the first common-mode output terminal, the first end of the second common-mode detection resistor is used to be connected to the second common-mode output terminal, and the second end of the first common-mode detection resistor is connected to the second end of the second common-mode detection resistor and the inverting input terminal of the first operational amplifier, wherein the input voltage of the positive input terminal of the first operational amplifier is half of the power supply voltage; The output end of the first operational amplifier is connected to the second end of the negative feedback resistor, the first end of the third common-mode suppression resistor, and the first end of the fourth common-mode suppression resistor, the second end of the third common-mode suppression resistor is used to be connected to the second common-mode input end, and the second end of the fourth common-mode suppression resistor is used to be connected to the first common-mode input end; The output common-mode detection circuit is used to generate control information based on the voltage of the first common-mode output terminal and the voltage of the second common-mode output terminal, where the control information includes a divided voltage generated based on the first common-mode detection resistor and the second common-mode detection resistor, and the voltage of the negative input terminal of the first operational amplifier is the divided voltage.

9. The common mode suppression circuit according to claim 8, characterized in that: Based on the negative feedback resistor being equal to one-half of the first common-mode detection resistor, if the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both at a low level, the common-mode adjustment voltage of the differential amplifier circuit is set to the power supply voltage based on the first operational amplifier and the negative feedback resistor, thereby causing the common-mode current corresponding to the first feedback resistor of the differential amplifier circuit to flow out of the first common-mode input terminal, and the common-mode current corresponding to the common-mode disturbance suppression circuit to flow into the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor; Based on the negative feedback resistor being equal to one-half of the first common-mode detection resistor, if the voltage at the first common-mode output terminal and the voltage at the second common-mode output terminal are both high, the common-mode adjustment voltage of the differential amplifier circuit is set to a low level based on the first operational amplifier and the negative feedback resistor, thereby causing the common-mode current corresponding to the first feedback resistor to flow into the first common-mode input terminal, and the common-mode current corresponding to the common-mode disturbance suppression circuit to flow out of the first common-mode input terminal, so that no common-mode current flows through the first integrating capacitor; Based on the negative feedback resistor being equal to half of the first common-mode detection resistor, if the voltage at the first common-mode output terminal is at a high level and the voltage at the second common-mode output terminal is at a low level, based on the first operational amplifier and the negative feedback resistor, the common-mode adjustment voltage of the differential amplifier circuit is made half of the sum of the voltage at the first common-mode input terminal and the voltage at the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is made half of the power supply voltage; Based on the negative feedback resistor being equal to half of the first common-mode detection resistor, if the voltage at the first common-mode output terminal is at a low level and the voltage at the second common-mode output terminal is at a high level, based on the first operational amplifier and the negative feedback resistor, the common-mode adjustment voltage of the differential amplifier circuit is half of the sum of the voltage at the first common-mode input terminal and the voltage at the second common-mode input terminal, and the common-mode voltage of the differential amplifier circuit is half of the power supply voltage.

10. A power amplifier circuit, characterized in that: The invention comprises the common-mode suppression circuit and the differential amplifier circuit according to any one of claims 1 to 9.

11. The power amplifier circuit according to claim 10, characterized in that: The differential amplifier circuit includes a modulation module, a first comparison amplifier module, a second comparison amplifier module, a first integration capacitor, a second integration capacitor, a first feedback resistor, a second feedback resistor, and an output drive module, wherein the first feedback resistor and the second feedback resistor have the same resistance value, and the first integration capacitor and the second integration capacitor have the same resistance value; a first input terminal of the modulation module connected to the first common-mode input terminal, the first terminal of the first integrating capacitor, and the first terminal of the first feedback resistor; a second terminal of the first integrating capacitor connected to the first output terminal of the modulation module and the first input terminal of the first comparison amplification module; a second terminal of the first feedback resistor connected to the first common-mode output terminal; a second input terminal of the modulation module connected to the second common-mode input terminal, the first terminal of the second integrating capacitor, and the first terminal of the second feedback resistor; a second terminal of the second integrating capacitor connected to the second output terminal of the modulation module and the first input terminal of the second comparison amplification module; and a second terminal of the second feedback resistor connected to the second common-mode output terminal; The second input terminal of the first comparison and amplification module is connected to the second input terminal of the second comparison and amplification module, the output terminal of the first comparison and amplification module is connected to the first input terminal of the output driving module, and the output terminal of the second comparison and amplification module is connected to the second input terminal of the output driving module; The first output end of the output driving module is connected to the first common mode output end, and the second output end of the output driving module is connected to the second common mode output end.

12. A chip, characterized in that: The invention comprises the power amplifier circuit described in claim 10 or 11.

13. An electronic device, characterized in that: Comprising the chip according to claim 12.

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