Bus terminal impedance matching method and device, computer equipment and storage medium

Abstract

The invention relates to the technical field of bus communication, and discloses a bus terminal impedance matching method and device, computer equipment and a storage medium, and the method comprises the steps: issuing a test instruction to a slave through a wireless link, so that the slave switches a terminating resistor to a first gear in a resistor gear scanning sequence; under the initial baud rate, sending preset sample data to the slave through the wireless link and the tested bus, so that the slave calculates the data accuracy according to the received sample data; receiving the data accuracy fed back by the slave through the wireless link, sequentially switching the resistor gears according to the resistor gear scanning sequence, and repeating the test until the test is completed, so as to obtain the data accuracy corresponding to each resistor gear; and determining a target terminating resistance value corresponding to the initial baud rate according to the data accuracy corresponding to each resistance gear. According to the method, the problem that the optimal terminating impedance value and the adaptive highest baud rate of the differential communication line cannot be dynamically and automatically scanned and determined in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of bus communication, and in particular to a bus terminal impedance matching method, device, computer equipment and storage medium. Background Art

[0002] Differential communication lines are widely used in industrial control, smart devices, and other fields, and their signal transmission quality is highly dependent on line impedance matching. Due to factors such as cable length, dynamic changes in the number of nodes, and differences in cable structure (such as wire diameter and shield grounding method), the bus characteristic impedance exhibits dynamic changes. If the end termination resistor does not match the line impedance, it will cause signal reflections, increased bit error rates, limited communication speeds, and even communication interruptions. Traditional solutions rely on manual experience to configure the termination resistors, making them difficult to adapt to complex and changing field environments. They also cannot dynamically optimize matching parameters, resulting in reduced system reliability.

[0003] Existing technologies monitor bus communication status through signal quality assessment, but have significant flaws: First, they can only provide qualitative analysis of signal quality and cannot directly output the optimal termination resistance value suitable for the current line. Adjustment requires manual experience and high technical requirements for operators; second, the testing process is limited by the host's preset baud rate and cannot actively explore the highest baud rate supported by the line and the corresponding optimal impedance parameters, resulting in insufficient communication potential; third, in scenarios with dynamic changes in multiple nodes, there is a lack of adaptive impedance matching capabilities, requiring repeated manual intervention and debugging, which is inefficient and difficult to meet real-time requirements. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a bus terminal impedance matching method, apparatus, computer equipment and storage medium to solve the problem that the existing technology cannot dynamically and automatically scan and determine the optimal termination impedance value of the differential communication line and adapt to the highest baud rate.

[0005] In a first aspect, an embodiment of the present invention provides a bus terminal impedance matching method, which is applied to a host. The method includes:

[0006] Sending a test instruction to the slave device via a wireless link, wherein the test instruction includes an initial baud rate and a resistance range scanning sequence, so that the slave device switches the termination resistor to the first range in the resistance range scanning sequence;

[0007] At the initial baud rate, sending preset sample data to the slave via a wireless link and a bus under test, respectively, so that the slave calculates a data accuracy rate based on the received sample data;

[0008] Receiving the data accuracy fed back by the slave through the wireless link, and switching the resistance gear in sequence according to the resistance gear scanning sequence and repeating the test until all resistance gears in the resistance gear scanning sequence are tested, and obtaining the data accuracy corresponding to each resistance gear;

[0009] The target termination resistance value corresponding to the initial baud rate is determined according to the data accuracy corresponding to each resistance level.

[0010] Furthermore, determining the target termination resistance value corresponding to the initial baud rate according to the data accuracy corresponding to each resistance gear includes:

[0011] Constructing a mapping relationship table between resistance levels and data accuracy, and screening out continuous level intervals where the data accuracy is higher than a preset threshold;

[0012] If there are multiple continuous gear intervals, identifying the interval spans of the multiple continuous gear intervals, and selecting the target gear interval according to the interval spans;

[0013] The middle value of the target gear range is used as the target termination resistance value corresponding to the initial baud rate.

[0014] Furthermore, the method further comprises:

[0015] Monitoring state parameters of the wireless link, wherein the state parameters include but are not limited to packet loss rate and bandwidth;

[0016] Determining whether there is an abnormal event in the wireless link according to the status parameter;

[0017] If the abnormal event occurs, a corresponding abnormal handling mechanism is enabled based on the abnormal event.

[0018] Furthermore, the method further comprises:

[0019] Assign independent master-slave test pairs to each bus;

[0020] Dynamically allocating corresponding test resources according to the physical characteristics of each of the buses;

[0021] The test progress of each of the buses is obtained, and the allocation weights of the test resources of different buses are dynamically adjusted according to the test progress.

[0022] Furthermore, after determining the target termination resistance value corresponding to the initial baud rate according to the data accuracy corresponding to each resistance level, the method further includes:

[0023] Acquiring environmental parameters of the bus under test and distance parameters between the host and the slave;

[0024] Predicting a next candidate baud rate and a resistance level sequence corresponding to the candidate baud rate based on the environmental parameter and the distance parameter;

[0025] The bus terminal impedance matching process is performed using the candidate baud rate and the corresponding resistance gear sequence.

[0026] In a second aspect, an embodiment of the present invention provides a method for testing bus terminal impedance matching, which is applied to a slave device, and the method includes:

[0027] Receive test instructions from the host through a wireless link;

[0028] configuring the dynamically adjustable resistance network to a specified gear according to the test instruction, and starting signal sampling of the bus under test to obtain first sample data;

[0029] Acquire second sample data from the wireless link, and perform clock synchronization calculation on sample data received by the bus under test based on the second sample data to obtain data accuracy of the bus under test;

[0030] The data accuracy is fed back to the host via a wireless link, and the dynamically adjustable resistance network is configured to the next resistance level according to the test instruction to dynamically adjust the resistance network, and the test process is repeated until the test of all set resistance levels is completed.

[0031] Furthermore, configuring the dynamically adjustable resistance network to a specified gear according to the test instruction includes:

[0032] Parsing the resistance level scanning sequence in the test instruction;

[0033] Identifying a designated gear in the resistance gear scanning sequence, and generating a control instruction for the resistance network according to the designated gear;

[0034] The control instruction is used to execute a switching operation of the resistance gear in the resistance network so that the resistance network is adjusted to a specified gear.

[0035] In a third aspect, an embodiment of the present invention provides a bus terminal impedance matching device, which is applied to a host, and the device includes:

[0036] a sending module, configured to send a test instruction to the slave device via a wireless link, wherein the test instruction includes an initial baud rate and a resistance gear scanning sequence, so that the slave device switches the termination resistor to the first gear in the resistance gear scanning sequence;

[0037] a sending module, configured to send preset sample data to the slave device via a wireless link and a bus under test at the initial baud rate, so that the slave device calculates a data accuracy rate based on the received sample data;

[0038] a testing module, configured to receive the data accuracy fed back by the slave via the wireless link, and sequentially switch the resistance gear according to the resistance gear scanning sequence and repeat the test until all resistance gears in the resistance gear scanning sequence are tested, thereby obtaining the data accuracy corresponding to each resistance gear;

[0039] The determination module is used to determine the target termination resistance value corresponding to the initial baud rate according to the data accuracy corresponding to each resistance gear.

[0040] In a fourth aspect, an embodiment of the present invention provides a bus terminal impedance matching test device, which is applied to a slave device, and the device includes:

[0041] A receiving module, used for receiving a test instruction sent by a host through a wireless link;

[0042] a configuration module, configured to configure the dynamically adjustable resistance network to a specified gear according to the test instruction, and start signal sampling of the bus under test to obtain first sample data;

[0043] an acquisition module, configured to acquire second sample data from the wireless link, and perform clock synchronization calculation on the sample data received by the bus under test based on the second sample data to obtain data accuracy of the bus under test;

[0044] The feedback module is used to feed back the data accuracy to the host through a wireless link, and configure the dynamically adjustable resistance network to the next resistance level according to the test instruction to dynamically adjust the resistance network and repeat the test process until the test of all set resistance levels is completed.

[0045] In a fifth aspect, an embodiment of the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0046] In a sixth aspect, an embodiment of the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the method of the first aspect or any corresponding embodiment thereof.

[0047] The method provided in the embodiments of the present application has the following beneficial effects:

[0048] The method provided in the embodiment of the present application can enable the slave to switch the termination resistance position in an orderly manner by issuing a test instruction containing an initial baud rate and a resistance position scanning sequence to the slave, thereby providing a basis for subsequent testing; by sending preset sample data through the wireless link and the bus under test at the initial baud rate and allowing the slave to calculate the data accuracy, the data transmission accuracy under different transmission paths can be obtained; by receiving the data accuracy feedback from the slave and switching the resistance position in sequence and repeating the test, the data accuracy corresponding to each resistance position can be comprehensively collected, providing sufficient data for subsequent analysis; by determining the target termination resistance value corresponding to the initial baud rate based on the data accuracy corresponding to each resistance position, effective screening of the optimal termination resistance value at the initial baud rate is achieved, which overall solves the problem that the existing technology cannot dynamically and automatically scan and determine the optimal termination impedance value of the differential communication line, and lays the foundation for improving the bus signal transmission quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 is a schematic flow chart of a bus terminal impedance matching method according to an embodiment of the present invention;

[0051] Figure 2 1 is a flow chart of a method for testing bus terminal impedance matching according to an embodiment of the present invention;

[0052] Figure 3 is a schematic structural diagram of a master and a slave according to an embodiment of the present invention;

[0053] Figure 4 is a structural block diagram of a bus terminal impedance matching device according to an embodiment of the present invention;

[0054] Figure 5 is a structural block diagram of a bus terminal impedance matching test device according to an embodiment of the present invention;

[0055] Figure 6 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0056] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0057] According to an embodiment of the present invention, a bus terminal impedance matching method, apparatus, computer device, and storage medium are provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0058] In this embodiment, a bus terminal impedance matching method is provided, which is applied to a host. Figure 1 FIG. 1 is a flow chart of a bus terminal impedance matching method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0059] Step S11 : sending a test instruction to the slave via a wireless link, wherein the test instruction includes an initial baud rate and a resistance range scanning sequence, so that the slave switches the termination resistor to the first range in the resistance range scanning sequence.

[0060] In an embodiment of the present application, the initial baud rate is determined according to the preset conditions of the bus under test (such as cable type, length, environmental noise) or the prediction results of the cloud platform empirical model, in order to ensure the stability of the initial test at a lower rate. The resistance gear scanning sequence is dynamically generated based on the theoretical range of bus impedance (such as 10Ω-100kΩ) and environmental parameters (such as temperature and humidity). For example, in high temperature scenarios, the scanning interval needs to be shortened due to the resistance temperature coefficient to avoid invalid testing. The host encapsulates instructions through a wireless communication protocol (such as MQTT / CoAP) and attaches a checksum (such as CRC) to ensure transmission integrity; at the same time, it dynamically compresses the instruction data volume or selects a retransmission mechanism based on the network status (such as bandwidth, delay) to ensure reliable delivery of instructions. After receiving the instruction, the slave parses the resistance gear sequence, switches to the first gear (such as 10Ω) through a digital potentiometer or relay matrix, and feeds back a confirmation signal to the host to form a closed-loop control. If the slave does not respond, the host triggers exception processing (such as switching communication frequency bands or resending instructions) based on network status perception.

[0061] At the wireless command transmission layer, dynamic coding and modulation strategies can also be designed, including:

[0062] When testing instruction encapsulation, the first level of error correction method (such as RS (255,223) error correction code) is first used; real-time channel quality assessment is performed, and the quality of the channel is judged by monitoring key indicators such as packet loss rate and bandwidth; when the packet loss rate exceeds the preset value, it indicates that the current error correction method cannot effectively deal with the error, and it automatically switches to the next level of error correction method (such as Turbo code) for encoding; if the bandwidth is detected to be less than the preset bandwidth, the LZMA compression algorithm is enabled to effectively compress the instruction data to reduce the data volume, thereby ensuring smooth transmission of instructions even in low bandwidth conditions.

[0063] For critical instructions, triple redundancy is used. This means that the same critical control instruction is copied into three copies, each transmitted via different paths or at different times. On the slave side, decoding is performed using a majority decision mechanism. Upon receiving these three instructions, their contents are compared. If the contents of two or three instructions match, the consistent content is used as the final decoding result.

[0064] A channel signature library was developed to record frequency bands that repeatedly experience interference during testing and to create corresponding spectrum signature templates. These templates identify each affected frequency band and accurately identify the specific interference signature. Throughout the test, the current frequency band is monitored in real time, and the detected spectrum signatures are compared with the templates in the channel signature library. If the signature of the current frequency band matches a template for a contaminated frequency band, communication is automatically adjusted to another unaffected frequency band, thereby avoiding interference and ensuring stable command transmission.

[0065] Step S12 : sending preset sample data to the slave via the wireless link and the bus under test respectively at the initial baud rate, so that the slave calculates the data accuracy according to the received sample data.

[0066] In an embodiment of the present application, after setting the initial baud rate (such as 110bps), the host sends preset sample data (such as a test sequence of 10,000 fixed bytes) to the slave synchronously through the wireless link and the bus under test. The bus under test uses differential signals to transmit sample data, while the slave end samples and receives signals in real time through the bus interface; at the same time, the wireless link (such as LTE) transmits the same sample data as a reference. The slave uses a dual-path data synchronization mechanism inside, uses the sample data transmitted by the wireless link as the original template, and uses a clock synchronization algorithm (such as sliding window matching) to align and compare the sample data received by the bus bit by bit to calculate the data accuracy. To ensure test accuracy, the sample data contains a predefined check field (such as a CRC check code). When comparing, the slave not only counts the bit error rate but also verifies the integrity of the data packet. If the bus sample data causes waveform distortion or signal reflection due to impedance mismatch, the slave optimizes the sampling accuracy by triggering a threshold adjustment mechanism (such as dynamically adjusting the comparator reference voltage) through hardware. During the test, the host uses a timestamp to ensure the timing consistency of the wireless link and bus data transmission to avoid comparison errors caused by transmission delays. If the slave detects that the bus data accuracy is lower than a preset threshold (such as 90%), it automatically triggers a partial retransmission request and only retransmits the erroneous data segment instead of the entire data, to improve test efficiency.

[0067] Step S13: receiving the data accuracy fed back by the slave through the wireless link, switching the resistance gear in sequence according to the resistance gear scanning sequence and repeating the test until all resistance gears in the resistance gear scanning sequence are tested, and obtaining the data accuracy corresponding to each resistance gear.

[0068] In an embodiment of the present application, after receiving the data accuracy of the current resistance gear fed back by the slave through the wireless link, the host sends a switching instruction to the slave according to the preset resistance gear scanning sequence (such as a list of resistance values arranged in a step-by-step or specific order from 10Ω to 100kΩ), triggering it to switch the adjustable resistance network to the next gear in the sequence; Subsequently, the host again sends the preset sample data at the same initial baud rate through the tested bus, and the slave synchronously receives the data and calculates the accuracy, and feeds back the test results of the new gear through the wireless link. This process is executed in a loop until all resistance gears in the scan sequence are tested. Finally, the host summarizes the accuracy data corresponding to all gears to form a complete resistance-accuracy mapping relationship, which provides a basis for subsequent screening of the optimal resistance interval. In this process, if the wireless link is abnormal (such as packet loss), the host will dynamically adjust the test rhythm according to the preset strategy, but the gear switching strictly follows the order of the scan sequence to ensure that the test conditions for each resistance value are consistent.

[0069] Step S14 , determining a target termination resistance value corresponding to the initial baud rate according to the data accuracy corresponding to each resistance level.

[0070] In the embodiment of the present application, step S14 includes the following steps A1-A3:

[0071] Step A1: construct a mapping relationship table between resistance levels and data accuracy, and filter out continuous level intervals where the data accuracy is higher than a preset threshold.

[0072] Specifically, the host dynamically constructs a mapping relationship table between resistance gear and accuracy based on the data accuracy corresponding to each resistance gear fed back by the slave (such as accuracy ≥ 90%). The table uses the resistance gear as an index and records the test results (such as accuracy, bit error rate) of each gear at the initial baud rate. The host screens out continuous gear ranges that meet the conditions based on a preset threshold (such as accuracy ≥ 95%). For example, the accuracy of all gears in the 50Ω-150Ω range meets the standard. In order to improve the screening accuracy, the threshold can be dynamically adjusted according to environmental parameters (such as temperature fluctuation range): if the temperature changes drastically, the threshold is appropriately lowered to expand the candidate interval. At the same time, the host eliminates erroneous accuracy data caused by instantaneous interference through an abnormal data elimination algorithm (such as the 3σ principle) to ensure the reliability of the mapping table data.

[0073] Step A2: If there are multiple continuous gear intervals, identify the interval spans of the multiple continuous gear intervals, and select the target gear interval according to the interval spans.

[0074] Specifically, if multiple continuous gear intervals are screened out (for example, 50Ω-150Ω and 180Ω-220Ω both meet the accuracy requirements), the host calculates the resistance span of each interval (such as 100Ω vs 40Ω) through the interval span evaluation algorithm, and prioritizes the interval with the largest span as the target gear interval. This strategy is based on the engineering experience that "the larger the span, the stronger the impedance fault tolerance" to ensure the robustness of the selection. For intervals with similar spans, the host performs weighted corrections based on environmental parameters (such as electromagnetic interference intensity): in high-interference scenarios, a low-resistance interval is selected to reduce signal reflections; in long cable scenarios, a high-resistance interval is selected to match the line impedance. In addition, if the intelligent algorithm prediction model has been trained, the host can input the characteristics of each interval (such as span, average accuracy) into the model and output the optimal interval selection recommendation.

[0075] Step A3: Using the middle value of the target gear range as the target termination resistance value corresponding to the initial baud rate.

[0076] Specifically, after determining the target gear range, the host uses the median optimization method to select the middle value of the range (such as 100Ω for 50Ω-150Ω) as the target termination resistance value. To improve accuracy, when the number of gears in the range is even, the average of the two middle gears is preferred (such as 125Ω for 120Ω and 130Ω). At the same time, the host combines the historical data of the cloud platform (such as the optimal resistance distribution of similar cables in similar environments) to fine-tune the middle value: if the historical data shows that the optimal resistance value in this environment generally tends to the upper limit of the range, a weighted algorithm (such as the middle value × 1.1) is used to generate the final value. In addition, the host associates the target resistance value with environmental parameters (such as the temperature coefficient) and outputs a compensation formula, such as R = 100Ω × (1 + 0.0005 × (T-25℃), for the slave to automatically fine-tune the resistance value in a dynamic environment.

[0077] In the embodiment of the present application, the method further includes steps B1-B3:

[0078] Step B1: monitor the status parameters of the wireless link, where the status parameters include but are not limited to packet loss rate and bandwidth.

[0079] Specifically, the host continuously monitors the status parameters of the wireless link, including packet loss rate, bandwidth, latency, and signal strength, through real-time network probe technology (such as ICMP Ping and TCP throughput testing). The packet loss rate is calculated by counting the loss ratio of test packets transmitted over the wireless link (for example, if 5 out of every 100 test packets are lost, the packet loss rate is 5%); the bandwidth is measured through a bidirectional transmission stress test (such as a UDP stream burst) to measure the upper limit of the current available bandwidth; the latency is calculated using the timestamp synchronization method to calculate the round-trip time (RTT) of the data packet. At the same time, the host integrates an adaptive sampling mechanism to dynamically adjust the monitoring frequency according to the stability of the network: the sampling rate is increased (such as 10 times per second) when the network fluctuates violently, and is reduced to 1 time per second when stable to save resources. The monitoring data is smoothed using a sliding window algorithm (such as a 10-second window) to eliminate instantaneous jitter interference.

[0080] Step B2: Determine whether there is any abnormal event in the wireless link according to the status parameters.

[0081] Specifically, the host analyzes status parameters based on preset multi-dimensional anomaly judgment rules: if the packet loss rate exceeds the threshold (such as >8%), the bandwidth is lower than the minimum requirement (such as <1Mbps), or the delay is continuously higher than the critical value (such as RTT>500ms), it is judged as an abnormal event. The judgment rules support dynamic adjustment. For example, due to enhanced electromagnetic interference in a high temperature environment, the packet loss rate threshold is allowed to be appropriately relaxed (such as increasing it to 10%). At the same time, the host uses a fuzzy logic algorithm to classify abnormal events: mild anomalies (such as a packet loss rate of 5%-8%) trigger a warning but do not interrupt the test; severe anomalies (such as a packet loss rate of >15%) immediately initiate fault isolation. In addition, the host combines historical network baseline data (such as the average bandwidth during normal operation) for comparison to identify abnormal fluctuations that deviate from the baseline by more than 3σ.

[0082] Step B3: If an abnormal event occurs, a corresponding abnormality handling mechanism is activated based on the abnormal event.

[0083] Specifically, when an abnormal event is detected, the host activates a hierarchical processing mechanism based on the type of abnormality: for the problem of high packet loss rate, a dynamic retransmission strategy is initiated (such as selective retransmission of lost key instruction packets), and the test data sending frequency is reduced (such as from 1000 packets per second to 500 packets); if the bandwidth is insufficient, low-priority test tasks (such as fine gear scanning of non-critical buses) are suspended to give priority to protecting the test resources of high-importance buses. For serious faults such as network interruption, the host triggers the link switching protocol, automatically switches to the backup communication method (such as falling back from LTE to WiFi), and resynchronizes the test progress. All exception handling operations are recorded in the log, and alarm information is pushed through the cloud platform. At the same time, the subsequent test plan is adjusted (such as extending the retry interval to 30 seconds) to avoid cascading failures.

[0084] In an embodiment of the present application, the method further includes steps C1-C3:

[0085] In step C1, an independent master-slave test pair is allocated for each bus.

[0086] Specifically, the host assigns a unique identifier to each slave through the wireless communication protocol stack and establishes an independent communication session channel, limiting the issuance of test instructions, data sample transmission, and result feedback to the private link of the corresponding bus test pair. This architecture avoids mutual interference of test parameters (such as baud rate and resistance level sequence) between buses and is particularly suitable for scenarios where multiple heterogeneous bus topologies coexist (such as mixed deployments of CAN, RS485, and Industrial Ethernet), ensuring that the terminal impedance matching test of each bus is independently performed based on its unique physical characteristics.

[0087] Step C2: dynamically allocating corresponding test resources according to the physical characteristics of each bus.

[0088] Specifically, intelligent resource scheduling is implemented based on bus physical parameters (such as cable type, shielding level, and transmission rate requirements). The system utilizes a built-in bus characteristics database. During initialization, bus attributes (such as "unshielded twisted pair - low speed" or "shielded coaxial - high speed") are acquired through cable identifiers or manual input. Differentiated test strategies are generated accordingly. For high-priority or high-bandwidth buses, denser resistance scan levels (such as 1Ω steps) and higher baud rate test sequences are assigned; whereas, for low-speed buses, coarser-grained levels (such as 10Ω steps) and basic rate tests are employed. The dynamic allocation mechanism is reflected in real-time bus test status monitoring. If a bus is detected to have a sudden increase in bit error rate due to impedance mismatch, the system automatically inserts a supplemental test level or reduces the speed for retries. Simultaneously, the test resource quotas for other non-critical buses are dynamically reduced (for example, by extending the interval between level changes), enabling flexible scheduling of test resources. This process is implemented using a weighted round-robin algorithm, with weight coefficients calculated based on bus importance, test schedule urgency, and historical performance data.

[0089] Step C3: Acquire the test progress of each bus and dynamically adjust the allocation weights of test resources of different buses according to the test progress.

[0090] Specifically, progress evaluation indicators include: the proportion of completed resistance levels, the current accuracy gradient change, the environmental interference fluctuation index, etc. The system periodically collects status snapshots of each slave through the wireless link and uses a sliding window algorithm to calculate the "test maturity index" of each bus. For buses approaching the critical point of impedance matching (such as a sudden drop in accuracy from 99% to 95%), fine-level backtesting is automatically triggered and additional time slice resources are allocated to them; while for buses in a stable test phase, their scheduling priority is moderately reduced. Resource weight adjustment is achieved through an improved greedy algorithm, and a global optimization is performed every 5 seconds: the available resource pool (such as 70% of the total wireless bandwidth) is exponentially allocated to buses with lagging progress or high criticality, while ensuring that basic test resources are not deprived. This dynamic adjustment significantly shortens the overall time required for parallel testing of multiple buses, especially in highly differentiated hybrid bus systems, and can improve test efficiency by more than 30% compared to the fixed resource allocation mode.

[0091] A blockchain-based test task allocation mechanism can also be constructed. This mechanism works as follows: First, each slave node submits resource requirements, including parameters such as required bandwidth and time slices, as well as test credits (a custom resource measurement unit within the system). The mechanism automatically prioritizes the test credits, prioritizing the testing requirements of high-priority buses (such as critical signal buses). The system reserves a preset percentage of the basic resource pool to ensure minimum testing requirements for all buses. Second, an evaluation model is constructed that includes three dimensions: urgency (e.g., safety-related tests + a 20% weighting factor); historical quality (average error rate > 1% over the past five tests results in a demotion); and resource utilization (resource utilization < 60% for three consecutive cycles results in a demotion). Weights are updated every 10 seconds, generating a visual resource allocation heat map. Finally, when a node's response latency exceeds 500ms, a migration mechanism is triggered: the current task is automatically split into 10-20 microtasks (e.g., each subtask tests three resistance levels). The Kademlia protocol is used to locate three neighboring nodes with loads < 40%. Nodes with extensive experience testing similar buses (historical accuracy > 98%) are prioritized. Finally, an improved PBFT consensus algorithm is adopted: each test result must be confirmed by more than 2 / 3 of the nodes; if more than 3 nodes return different results, retesting is automatically triggered; the final result error is controlled within the preset range.

[0092] In the embodiment of the present application, after determining the target termination resistance value corresponding to the initial baud rate according to the data accuracy corresponding to each resistance level, steps D1-D3 are further included:

[0093] Step D1, obtaining the environmental parameters of the bus under test and the distance parameters between the master and the slave.

[0094] Specifically, the slave's built-in sensors (such as temperature and humidity sensors and electromagnetic interference detection modules) collect real-time environmental parameters (temperature, humidity, electromagnetic interference intensity, etc.) of the environment in which the bus under test is located. Distance parameters are estimated based on the wireless communication characteristics between the master and slave. Specifically, when using LTE communication, the approximate physical distance between the master and slave is calculated using the location information of the base stations they access. If using WiFi, the relative distance is estimated using signal strength (RSSI) and an attenuation model. These parameters reflect the potential impact of environmental factors on bus impedance characteristics (for example, temperature changes causing drift in the termination resistor value) and the correlation between physical distance and signal transmission quality, providing key input for subsequent prediction models.

[0095] Step D2: predicting the next candidate baud rate and the resistance level sequence corresponding to the candidate baud rate based on the environmental parameters and the distance parameters.

[0096] Specifically, the host uploads the acquired environmental parameters and distance parameters to the cloud platform and uses the cloud-based pre-trained empirical large model for intelligent prediction. The model combines historical test data (such as the offset pattern of the optimal resistance value at different temperatures, the relationship between distance and signal attenuation) and current real-time parameters to dynamically generate optimized candidate baud rates and resistance gear scanning sequences. For example, if the ambient temperature is high and the distance is far, the model may recommend lowering the initial candidate baud rate to avoid signal distortion, and narrowing the resistance scanning range to focus on the theoretical resistance range after temperature compensation (such as 120Ω±ΔT). This process skips redundant gears through intelligent algorithms and directly locks the high-probability optimal parameter combination, significantly reducing the number of tests.

[0097] Step D3: Execute a bus terminal impedance matching process using the candidate baud rate and the corresponding resistance level sequence.

[0098] Specifically, based on the prediction results, the host sends a new candidate baud rate and customized resistance gear sequence to the slave through the wireless link to start the next round of adaptive testing. The slave switches the resistance gear according to the sequence and synchronously performs data transmission and reception and accuracy comparison at the candidate baud rate. During the process, the system continuously monitors environmental changes and network status, and dynamically fine-tunes the test strategy (temporarily inserting denser resistance gears in the event of sudden electromagnetic interference). At the same time, combined with the multi-bus parallel testing mechanism, more resources are allocated to high-priority or better-responsive buses to achieve efficient multi-channel collaborative optimization. Ultimately, through the iterative prediction-test closed loop, it quickly converges to the globally optimal impedance matching solution.

[0099] In the embodiment of the present application, after determining the target termination resistance value corresponding to the initial baud rate, the method further includes: step S15, a dynamic impedance compensation mechanism based on real-time bus signal feature analysis, specifically including the following steps F1-F4:

[0100] Step F1: Establish a three-dimensional quantitative index system for bus signal characteristics.

[0101] Specifically, the slave collects the measured bus waveform data through a high-speed ADC (sampling rate ≥ 10 times the baud rate) and extracts the following core features: a) Time domain features: including rising edge slope (dV / dt), overshoot amplitude (ΔV overshoot ), ringing decay time (τ ringing ); b) Frequency domain characteristics: Calculate the amplitude of the main frequency component of the signal (A) through FFT f0 ) and third harmonic distortion (THD3); c) Eye diagram characteristics: A sliding window segmentation technique is used to generate a real-time eye diagram and calculate the statistical distribution variance σ of the eye height (Eye_Height) and eye width (Eye_Width). For example, on an RS485 bus, the rising edge slope threshold is set to 20V / μs. When the measured value falls below 15V / μs, a waveform degradation warning is triggered.

[0102] Step F2: constructing an impedance compensation amount prediction model.

[0103] Specifically, a prediction model based on a deep residual network (ResNet-18) is trained in the cloud, and the input layer receives the real-time feature vector [ΔV overshoot ,THD3,σ Eye_Height ] and environmental parameters [T, RH, EMI]. The output layer generates three prediction results: a) impedance compensation direction (+ / ΔR); b) absolute value of the compensation amount (ΔR∈1-100Ω); and c) confidence score (0-1). The model is trained using millions of historical test cases and adapted to different bus types through transfer learning. Slaves synchronize model parameters weekly through a differential update mechanism to ensure timely edge inference.

[0104] Step F3: Implement multi-modal dynamic compensation strategy.

[0105] Specifically, graded compensation is initiated based on the prediction results: when the confidence level is >0.9, ΔR is directly applied to adjust the termination resistance; when the confidence level is 0.7-0.9, microstepping is initiated (step size = ΔR / 5); when the confidence level is <0.7, the current resistance value is maintained and feature re-evaluation is triggered. Simultaneously, a feedback learning mechanism is established: the actual improvement in accuracy after compensation is transmitted back to the cloud, dynamically adjusting the model weights. For example, if a prediction of ΔR = +25Ω (confidence level 0.85) shows an improvement in accuracy after implementation, the model's associated weight for this feature combination will be strengthened.

[0106] Step F4: Execute anti-disturbance impedance locking.

[0107] Specifically, when the accuracy enters the stable range (≥99%±0.5%) after three consecutive compensations, the anti-interference state detection is triggered: a pseudo-random interference pulse (amplitude 10%-30% Vpp) is injected within 50ms to monitor the system's ability to maintain the accuracy. If the accuracy fluctuation is <1%, it is determined that the optimal anti-interference impedance has been achieved, and an impedance configuration scheme including the temperature drift compensation formula is generated: R opt(T) = R0×[1+α(T-T0)], where α is adaptively selected based on the material database. Otherwise, return to step F1 to re-extract features and expand the compensation search range.

[0108] The embodiment of the present application solves the technical problems of slow convergence and easy falling into local optimum of traditional scanning methods in complex electromagnetic environments by introducing a closed-loop compensation mechanism driven by signal characteristics. Compared with the fixed resistance scanning sequence in the prior art, impedance matching is based on real-time signal characteristics rather than preset theoretical values, and the true optimal resistance value can still be quickly locked under non-ideal conditions such as cable aging and connector oxidation. Under standard pulse interference, this mechanism reduces the matching time. By fusing environmental sensor data with deep learning predictions, the impedance drift caused by temperature / humidity is automatically compensated. In the vehicle-mounted CAN bus test, compared with the traditional method, this embodiment stabilizes the accuracy fluctuation in the full temperature range of -40°C to 85°C at a higher level. The anti-interference state detection mechanism ensures that the selected termination resistor maintains reliable communication under sudden interference, and the system robustness is verified by injection testing.

[0109] In this embodiment, a bus terminal impedance matching test method is provided, which is applied to a slave. Figure 2 FIG. 1 is a flow chart of a method for testing bus terminal impedance matching according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0110] Step S21: receiving a test instruction sent by a host via a wireless link.

[0111] In an embodiment of the present application, the slave receives a test instruction sent by the host through wireless communication methods such as radio frequency, WiFi or 4G / 5G, including an initial baud rate (such as 110bps), a resistance gear scanning sequence (such as a stepping rule from 10Ω to 100KΩ) and other configuration instructions (such as a sampling period, a data sample length). The test instruction clearly specifies the adjustment logic of the resistor network and the start conditions of the test process. For example, the slave must first switch the resistor network to the first gear of the scanning sequence (such as 10Ω) and synchronously prepare the bus signal sampling module. This step realizes remote parameter synchronization through a wireless link, ensures the consistency of the master-slave test logic, and lays the foundation for subsequent impedance matching tests.

[0112] Step S22 : configuring the dynamically adjustable resistance network to a specified position according to the test instruction, and starting signal sampling of the bus under test to obtain first sample data.

[0113] In the embodiment of the present application, the slave analyzes the received resistance position scanning sequence and generates the corresponding resistance network control instruction (such as the I of the digital potentiometer). 2C command or relay matrix switch control signal), driving the adjustable resistor network to switch to the specified gear (such as the first gear 10Ω). At the same time, the slave device activates the signal sampling module of the bus under test, synchronously captures the bus data at the initial baud rate, and obtains the first sample data (for example, 10,000 preset bytes of actual received data). During this process, the slave device uses a hardware trigger mechanism to ensure strict alignment between the resistor switching and the sampling start timing, avoiding data misalignment caused by delays and ensuring the accuracy of the test data.

[0114] It should be noted that for high-speed bus scenarios, a hardware timestamp synchronization system based on the PTP protocol is designed. A nanosecond-precision timestamp marking module is integrated into the FPGA, and the master-slave clock deviation is automatically calibrated through the loopback test of the tested bus. A double-buffer architecture is adopted in the data comparison stage: the first-level buffer implements coarse-grained sliding window alignment (±5-bit window), and the second-level buffer achieves sub-bit phase calibration through a cross-correlation algorithm. An error pattern recognition module is introduced. When a specific interference pattern (such as periodic pulse noise) is detected, the resampling mechanism is automatically triggered to prevent the accuracy calculation from being affected by single-shot sampling deviation.

[0115] In the embodiment of the present application, configuring the dynamically adjustable resistance network to a specified gear according to the test instruction includes the following steps E1-E3:

[0116] Step E1, parsing the resistance level scanning sequence in the test instruction.

[0117] Specifically, after the slave receives the test instruction sent by the host, it first performs protocol parsing on the data packet in the test instruction and extracts the resistance gear scanning sequence (for example: 10Ω, 20Ω, 50Ω...100kΩ stepping rules or custom discrete sequences). During the parsing process, the slave needs to verify the legitimacy of the sequence (such as whether the resistance range is within 10Ω-100kΩ, whether the step length complies with the preset rules), and identify the specified gear that needs to be executed first in the current test phase (such as the first gear 10Ω). If the scan sequence contains dynamic adjustment logic (such as skipping some gears according to environmental parameters), the slave will synchronously load the associated condition judgment module to provide a decision basis for subsequent gear switching, ensuring that the resistance network adjustment strictly follows the host's test plan.

[0118] Step E2: identifying a designated position in the resistance position scanning sequence, and generating a control instruction for the resistance network according to the designated position.

[0119] Specifically, the slave determines the target gear (such as 10Ω) to be switched based on the analyzed resistance gear scanning sequence, and generates the corresponding control instruction based on the hardware type (digital potentiometer or relay matrix). For example, if a digital potentiometer (such as AD5242) is used, the slave uses I 2The C protocol sends specific register values, configuring their wiper positions to output the target resistance. If a relay matrix is used, GPIOs are used to control the relay switch combinations (e.g., closing relays 1 and 3 to connect a 10Ω resistor). This process requires calibration data to compensate for hardware errors (such as relay contact resistance) to ensure that the actual resistance value deviates from the theoretical value by less than ±1%. Furthermore, the slave device has a built-in command queue management module that supports burst command caching and priority scheduling to prevent control timing disruptions caused by wireless communication delays.

[0120] In step E3, a control instruction is used to execute a switching operation of the resistance level in the resistance network so as to adjust the resistance network to a specified level.

[0121] Specifically, the slave drives the hardware to execute the generated resistance control instruction to complete the physical resistance switching. For the relay matrix, the slave uses a de-bouncing circuit (such as RC filtering + Schmitt trigger) to eliminate the interference of contact jitter on the bus signal, and verifies the actual resistance value in real time through ADC sampling after switching (such as measuring the voltage divider value to inversely calculate the resistance); for digital potentiometers, a soft start function (such as a ramp-type resistance value) is used to avoid sudden current shocks to the bus. After the switching is completed, the slave sends a confirmation signal to the host and starts the internal timer to monitor the gear stabilization time (such as 50ms) to ensure that the resistance network reaches a steady state before triggering the bus signal sampling. This step ensures the accuracy and reliability of resistance adjustment through the "instruction-execution-verification" closed-loop control.

[0122] At the hardware level of the variable resistor network, a multi-stage composite topology is employed to achieve more precise, rapid, and stable resistance adjustment. The main circuit utilizes a 128-position digital potentiometer as the foundational adjustment network, providing a finer resistance adjustment range to meet diverse resistance value requirements in various test scenarios. Furthermore, a dynamic compensation module consisting of a MOSFET array is connected in parallel. This module features fast switching capabilities, enabling dynamic adjustment of resistance values within a short period of time.

[0123] To achieve precise control of the dynamic compensation module, an adaptive PID control algorithm was developed. This algorithm monitors the rising edge overshoot rate of the bus signal in real time. This rising edge overshoot rate is a key indicator of bus signal quality. By monitoring and analyzing this rate, it can accurately determine whether the current resistor network requires dynamic compensation. Based on the collected rising edge overshoot rate, the algorithm automatically calculates the required compensation adjustment to ensure bus signal stability. To further optimize the compensation effect, a compensation parameter library containing 256 sets of optimized coefficients for different temperature-frequency combinations is pre-stored. During actual operation, since temperature and frequency changes affect the performance of the resistor network, it is necessary to select the most appropriate compensation parameters based on the current temperature and frequency conditions. A fuzzy matching algorithm is used to quickly and accurately select the optimal parameter set from the compensation parameter library that best matches the current temperature-frequency combination.

[0124] In practical applications, when bus signal fluctuations occur, the adaptive PID control algorithm responds quickly, calculating the compensation amount based on the acquired rising edge overshoot rate, selecting the optimal parameter set from a compensation parameter library, and then controlling the MOSFET array to quickly adjust the resistance value. Due to the fast switching characteristics of the MOSFET array, the response time of the entire compensation process can be shortened to 200μs, an improvement of two orders of magnitude compared to traditional relay solutions, improving the efficiency of resistance adjustment and system stability. This combination of a multi-order composite topology and an adaptive control algorithm provides strong guarantees for the stable operation of the variable resistor network in complex test environments.

[0125] Step S23 , obtaining second sample data from the wireless link, and performing clock synchronization calculation on the sample data received by the bus under test based on the second sample data to obtain the data accuracy of the bus under test.

[0126] In an embodiment of the present application, the slave receives the original sample data (second sample data) sent by the host through a wireless link, and performs clock synchronization comparison with the first sample data captured locally from the bus. Specifically, the slave adopts a sliding window algorithm or a timestamp alignment method based on a preamble to eliminate the clock offset caused by baud rate deviation or transmission delay, and compares the correctness of the received data bit by bit. For example, if the matching rate between the actual bus received data and the second sample data is 98.5%, the data accuracy under the current resistance gear is determined. This step realizes high-precision data verification through the collaboration of software and hardware to ensure the reliability of bit error rate statistics.

[0127] In step S24, the data accuracy is fed back to the host via the wireless link, and the dynamically adjustable resistance network is configured to the next resistance level according to the test instruction to dynamically adjust the resistance network, and the test process is repeated until the test of all set resistance levels is completed.

[0128] In an embodiment of the present application, the slave will feed back the calculated data accuracy (such as 98.5%) to the host in real time through a wireless link, and automatically switch to the next gear (such as 20Ω) according to the preset resistance gear scanning sequence. During the switching process, the slave avoids the interference of resistance mutation on the bus signal through the relay debouncing circuit or the soft start function of the digital potentiometer. Subsequently, the slave restarts the signal sampling and data comparison process, and executes the loop until all resistance gear tests in the scanning sequence are completed. If the test instruction contains a multi-baud rate iteration strategy, the slave will automatically wait for the host to issue an upshift instruction (such as switching to 115200bps) after completing the full-gear test at the current baud rate, and enter the adaptive matching stage of the higher baud rate to achieve termination resistance optimization in the full parameter space.

[0129] It should be noted that Figure 3 This is a schematic diagram of the structure of the host and slave, such as Figure 3 As shown, the master and slave devices are connected via a bus under test and are both equipped with RF / LTE antennas and wireless communication modules. The master also features a battery, a human-machine interface screen, and a bus interface, while the slave device also has a battery and a bus-terminating variable resistor. The bus terminal impedance matching method presented in this article is centered around this structure. The master device exchanges test instructions and other information with the slave device via a wireless link, performing impedance matching tests and various processing operations. The slave device receives the test instructions and, based on them, configures the resistor network, samples the signal, and calculates the data accuracy, dynamically adjusting the resistor network to complete the test.

[0130] In an embodiment of the present application, an edge computing architecture driven by reinforcement learning (RL) is introduced to achieve end-cloud collaborative impedance matching decision optimization. Specifically, the slave end is equipped with a lightweight RL inference engine to collect bus signal characteristics (such as eye opening, signal overshoot rate) and local environmental parameters in real time, and dynamically generate impedance adjustment actions (such as gear switching step, baud rate increase and decrease thresholds) for the current micro-environment in combination with the global strategy model issued by the host. At the same time, the cloud platform aggregates multi-node training data through a federated learning framework, continuously updates the global RL model and sends it to the terminal, forming a closed-loop optimization of "edge real-time decision-making-cloud cycle evolution". This mechanism breaks through the limitations of traditional fixed scanning strategies. For example, in the case of sudden electromagnetic interference, the slave can skip invalid gears based on the local RL model and directly lock the optimal anti-interference resistance value; and when testing multiple buses in parallel, the host dynamically allocates test resources based on the edge decision feedback of each slave to achieve cross-bus load balancing. This pre-buried point significantly improves impedance matching efficiency and adaptability to complex environments by integrating edge intelligence and cloud collaboration, constituting a core innovation that is different from existing technologies.

[0131] This embodiment also provides a bus terminal impedance matching device and a bus terminal impedance matching test device. The devices are used to implement the above-mentioned embodiments and preferred embodiments, and the details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0132] This embodiment provides a bus terminal impedance matching device, which is applied to a host, such as Figure 4 Shown, including:

[0133] The sending module 41 is used to send a test instruction to the slave through a wireless link, wherein the test instruction includes an initial baud rate and a resistance range scanning sequence, so that the slave switches the termination resistor to the first range in the resistance range scanning sequence;

[0134] The sending module 42 is used to send preset sample data to the slave through the wireless link and the bus under test at the initial baud rate, so that the slave calculates the data accuracy based on the received sample data;

[0135] The test module 43 is used to receive the data accuracy feedback from the slave via the wireless link, and switch the resistance level in sequence according to the resistance level scanning sequence and repeat the test until all resistance levels in the resistance level scanning sequence are tested, thereby obtaining the data accuracy corresponding to each resistance level;

[0136] The determination module 44 is configured to determine a target termination resistance value corresponding to the initial baud rate according to the data accuracy corresponding to each resistance level.

[0137] Furthermore, a determination module is used to construct a mapping relationship table between resistance levels and data accuracy, and to screen out continuous level intervals with data accuracy higher than a preset threshold; if there are multiple continuous level intervals, the interval spans of the multiple continuous level intervals are identified, and the target level interval is selected based on the interval span; the middle value of the target level interval is used as the target termination resistance value corresponding to the initial baud rate.

[0138] Furthermore, the device also includes: a monitoring module for monitoring the status parameters of the wireless link, wherein the status parameters include but are not limited to packet loss rate and bandwidth; judging whether there is an abnormal event in the wireless link based on the status parameters; if there is an abnormal event, enabling a corresponding abnormal handling mechanism based on the abnormal event.

[0139] Furthermore, the device also includes: an allocation module for allocating an independent master-slave test pair for each bus; dynamically allocating corresponding test resources according to the physical characteristics of each bus; obtaining the test progress of each bus, and dynamically adjusting the allocation weight of different bus test resources according to the test progress.

[0140] Furthermore, the device also includes: a prediction module for obtaining the environmental parameters of the bus under test and the distance parameters between the host and the slave; predicting the next candidate baud rate and the resistance gear sequence corresponding to the candidate baud rate based on the environmental parameters and the distance parameters; and executing the bus terminal impedance matching process using the candidate baud rate and the corresponding resistance gear sequence.

[0141] This embodiment provides a bus terminal impedance matching test device, which is applied to a slave, such as Figure 5 Shown, including:

[0142] Receiving module 51, used for receiving the test instruction sent by the host through the wireless link;

[0143] A configuration module 52 is configured to configure the dynamically adjustable resistance network to a specified gear according to a test instruction, and start signal sampling of the bus under test to obtain first sample data;

[0144] an acquisition module 53 for acquiring second sample data from the wireless link, and performing clock synchronization calculation on the sample data received by the bus under test based on the second sample data to obtain data accuracy of the bus under test;

[0145] The feedback module 54 is used to feed back the data accuracy to the host through the wireless link, and configure the dynamically adjustable resistance network to the next resistance level according to the test instruction to dynamically adjust the resistance network and repeat the test process until the test of all set resistance levels is completed.

[0146] Furthermore, the device also includes: a parsing module for parsing the resistance gear scanning sequence in the test instruction; identifying the specified gear in the resistance gear scanning sequence, and generating a control instruction for the resistance network according to the specified gear; using the control instruction to execute the switching operation of the resistance gear in the resistance network so that the resistance network is adjusted to the specified gear.

[0147] See also Figure 6 , Figure 6 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 6As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0148] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0149] The memory 20 stores instructions that can be executed by at least one processor 10, so as to enable at least one processor 10 to execute the method shown in the above embodiment.

[0150] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created based on the use of a computer device for displaying a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0151] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0152] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0153] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0154] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A bus terminal impedance matching method, applied to a host, characterized in that: The method comprises: Sending a test instruction to the slave device via a wireless link, wherein the test instruction includes an initial baud rate and a resistance range scanning sequence, so that the slave device switches the termination resistor to the first range in the resistance range scanning sequence; At the initial baud rate, sending preset sample data to the slave via a wireless link and a bus under test, respectively, so that the slave calculates a data accuracy rate based on the received sample data; Receiving the data accuracy fed back by the slave through the wireless link, and switching the resistance gear in sequence according to the resistance gear scanning sequence and repeating the test until all resistance gears in the resistance gear scanning sequence are tested, and obtaining the data accuracy corresponding to each resistance gear; The target termination resistance value corresponding to the initial baud rate is determined according to the data accuracy corresponding to each resistance level.

2. The method according to claim 1, characterized in that The step of determining the target termination resistance value corresponding to the initial baud rate according to the data accuracy corresponding to each resistance level includes: Constructing a mapping relationship table between resistance levels and data accuracy, and screening out continuous level intervals where the data accuracy is higher than a preset threshold; If there are multiple continuous gear intervals, identifying the interval spans of the multiple continuous gear intervals, and selecting the target gear interval according to the interval spans; The middle value of the target gear range is used as the target termination resistance value corresponding to the initial baud rate.

3. The method according to claim 1, characterized in that The method further comprises: Monitoring state parameters of the wireless link, wherein the state parameters include but are not limited to packet loss rate and bandwidth; Determining whether there is an abnormal event in the wireless link according to the status parameter; If the abnormal event occurs, a corresponding abnormal handling mechanism is enabled based on the abnormal event.

4. The method according to claim 1, wherein The method further comprises: Assign independent master-slave test pairs to each bus; Dynamically allocating corresponding test resources according to the physical characteristics of each of the buses; The test progress of each of the buses is obtained, and the allocation weights of the test resources of different buses are dynamically adjusted according to the test progress.

5. The method according to claim 1, characterized in that After determining the target termination resistance value corresponding to the initial baud rate according to the data accuracy corresponding to each resistance gear, the method further includes: Acquiring environmental parameters of the bus under test and distance parameters between the host and the slave; Predicting a next candidate baud rate and a resistance level sequence corresponding to the candidate baud rate based on the environmental parameter and the distance parameter; The bus terminal impedance matching process is performed using the candidate baud rate and the corresponding resistance gear sequence.

6. A bus terminal impedance matching test method, applied to a slave, characterized in that: The method comprises: Receive test instructions from the host through a wireless link; configuring the dynamically adjustable resistance network to a specified gear according to the test instruction, and starting signal sampling of the bus under test to obtain first sample data; Acquire second sample data from the wireless link, and perform clock synchronization calculation on sample data received by the bus under test based on the second sample data to obtain data accuracy of the bus under test; The data accuracy is fed back to the host via a wireless link, and the dynamically adjustable resistance network is configured to the next resistance level according to the test instruction to dynamically adjust the resistance network, and the test process is repeated until the test of all set resistance levels is completed.

7. The method according to claim 6, characterized in that Configuring the dynamically adjustable resistance network to a specified gear according to the test instruction includes: Parsing the resistance level scanning sequence in the test instruction; Identifying a designated gear in the resistance gear scanning sequence, and generating a control instruction for the resistance network according to the designated gear; The control instruction is used to execute a switching operation of the resistance gear in the resistance network so that the resistance network is adjusted to a specified gear.

8. A bus terminal impedance matching device, applied to a host, characterized in that: The device comprises: a sending module, configured to send a test instruction to the slave device via a wireless link, wherein the test instruction includes an initial baud rate and a resistance gear scanning sequence, so that the slave device switches the termination resistor to the first gear in the resistance gear scanning sequence; a sending module, configured to send preset sample data to the slave device via a wireless link and a bus under test at the initial baud rate, so that the slave device calculates a data accuracy rate based on the received sample data; a testing module, configured to receive the data accuracy fed back by the slave via the wireless link, and sequentially switch the resistance gear according to the resistance gear scanning sequence and repeat the test until all resistance gears in the resistance gear scanning sequence are tested, thereby obtaining the data accuracy corresponding to each resistance gear; The determination module is used to determine the target termination resistance value corresponding to the initial baud rate according to the data accuracy corresponding to each resistance gear.

9. A bus terminal impedance matching test device, applied to a slave, characterized in that: The device comprises: A receiving module, used for receiving a test instruction sent by a host through a wireless link; a configuration module, configured to configure the dynamically adjustable resistance network to a specified gear according to the test instruction, and start signal sampling of the bus under test to obtain first sample data; an acquisition module, configured to acquire second sample data from the wireless link, and perform clock synchronization calculation on the sample data received by the bus under test based on the second sample data to obtain data accuracy of the bus under test; The feedback module is used to feed back the data accuracy to the host through a wireless link, and configure the dynamically adjustable resistance network to the next resistance level according to the test instruction to dynamically adjust the resistance network and repeat the test process until the test of all set resistance levels is completed.

10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 7 by executing the computer instructions.

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