Method, system, device and medium for accessing end device to time delay sensitive network

Abstract

The invention discloses a method, a system, equipment and a medium for an end device to access a time delay sensitive network, and relates to the technical field of network communication, the end device comprises a central processing unit and a hardware module which are in communication connection, the central processing unit is provided with a first memory buffer area, and the first memory buffer area is used for storing periodic stream data. The hardware module comprises a timer and a target port, the method is applied to the hardware module, and the method comprises the following steps: acquiring global synchronization time of the time delay sensitive network, calibrating local time of the end equipment based on the global synchronization time, and calibrating the local time of the end equipment based on the local synchronization time. The timer is configured based on the calibrated local time and a preset period; and under the condition that the timer is triggered, reading the periodic stream data from the first memory buffer area, and sending the periodic stream data to the target port so as to send the periodic stream data to the outside through the target port.

Description

Technical Field

[0001] The present application relates to the field of network communication technology, and in particular to a method, system, device and medium for a terminal device to access a delay-sensitive network. Background Art

[0002] Time-Sensitive Networking (TSN) technology has developed rapidly in recent years. Originally originating in the audio and video industry, it has now expanded into industrial, automotive, aerospace, and other fields. By providing low-latency, highly deterministic data transmission, TSN meets the stringent requirements of scenarios such as industrial automation, intelligent transportation, and airborne control. TSN technology has gradually matured, and numerous companies and organizations both domestically and internationally are actively promoting its development. For example, China Unicom, in collaboration with Intel and others, launched a cloud-native 5G-TSN solution, achieving end-to-end low latency and high-precision synchronization. In the future, as the technology continues to improve and the industry ecosystem gradually establishes, TSN will play a vital role in even more areas.

[0003] However, time synchronization is crucial in a time-sensitive network. The protocol requires a seven-hop synchronization accuracy of ±100ns. This synchronization requirement and precision are extremely high. Furthermore, the entire network uses this synchronized time for global scheduling, and the protocols used also require network-wide time synchronization. Therefore, to access a time-sensitive network, the end device must be able to send data streams at precise intervals. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention of this application is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, an embodiment of the present application provides a method for an end device to access a delay-sensitive network, the method comprising: the end device comprising a central processing unit and a hardware module in communication connection, the central processing unit being provided with a first memory buffer, the first memory buffer being used to store periodic flow data, the hardware module comprising a timer and a target port, the method being applied to the hardware module, the method comprising:

[0006] Obtaining a global synchronization time of a delay-sensitive network, calibrating a local time of the terminal device based on the global synchronization time, and configuring the timer based on the calibrated local time and a preset period;

[0007] When the timer is triggered, the periodic stream data is read from the first memory buffer and sent to the target port, so as to be sent externally through the target port.

[0008] In one embodiment of the present invention, the central processing unit is further provided with a second memory buffer, the second memory buffer being used to store continuous flow data, and when the timer is triggered, the periodic flow data is read from the first memory buffer and sent to the target port, further comprising:

[0009] When the sending of the periodic stream data is completed, the continuous stream data is read from the second memory buffer and sent to the target port, so as to be sent externally through the target port.

[0010] In one embodiment of the present invention, the step of calibrating the local time of the terminal device based on the global synchronization time includes:

[0011] exchanging synchronization messages with a delay-sensitive network based on a time synchronization protocol to calculate a time offset with the delay-sensitive network;

[0012] The time of the hardware module is corrected based on the time offset, and the corrected time is updated to the terminal device through an interrupt mechanism to calibrate the local time of the terminal device.

[0013] In one embodiment of the present invention, when the timer is triggered, the step of reading the periodic stream data from the first memory buffer includes:

[0014] Configure a trigger period and a start time of the hardware timer based on the global synchronization time, and generate a timing interrupt signal according to the trigger period and the start time;

[0015] When the timer is triggered, the periodic stream data is read from the first memory buffer based on the interrupt signal.

[0016] In one embodiment of the present invention, the step of sending the periodic stream data to the target port includes:

[0017] Determining the start time and duration of gated opening according to the transmission delay of the periodic stream data and a preset error margin;

[0018] Configuring a gating state of the target port based on a gating schedule so that the gating of the target port is turned on at the start time and remains turned on for the duration;

[0019] When the gating of the target port is turned on, the continuous flow data transmission of the second memory buffer is blocked, and the periodic flow data is sent to the target port.

[0020] In one embodiment of the present invention, the end device includes a register, and the step of sending the periodic stream data to the target port includes:

[0021] Configuring a timing period of a register, wherein the timing period is consistent with a sending period of the periodic stream data;

[0022] The periodic stream data in the first memory buffer is read and sent based on the timing period.

[0023] In one embodiment of the present invention, the method further comprises:

[0024] When a read / write anomaly is detected in the first memory buffer or the second memory buffer, a data read operation is re-initiated or a redundancy check is performed.

[0025] In a second aspect, the present application proposes a system for an end device to access a delay-sensitive network, the system comprising: a central processing unit and a hardware module;

[0026] The central processing unit is configured to: acquire periodic flow data and continuous flow data, store the periodic flow data in a first memory buffer, and store the continuous flow data in a second memory buffer;

[0027] The hardware module is configured to: obtain the global synchronization time of the delay-sensitive network, calibrate the local time of the terminal device based on the global synchronization time, and configure the timer based on the calibrated local time and a preset period; when the timer is triggered, read the periodic flow data from the first memory buffer and send the periodic flow data to the target port so as to send the periodic flow data externally through the target port.

[0028] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of a method for an end device to access a delay-sensitive network as described in any one of the first aspects above when executing the computer program stored in the memory.

[0029] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a method for a terminal device to access a delay-sensitive network according to any one of the first aspects.

[0030] In summary, an embodiment of the present application provides a method for an end device to access a delay-sensitive network, in which periodic flow data is written into a first memory buffer and continuous flow data is written into a second memory buffer. When the timer is triggered, the periodic flow data is read from the first memory buffer and sent to the target port. When the gate of the target port is turned on, the periodic flow data with high priority is sent first, and precise cycle control is completed using a hardware module. The hardware module can achieve precise time synchronization of ±20ns. Therefore, using hardware for cycle control can control the cycle error from microseconds to nanometers, and the control accuracy is improved by 1000, so that the end device has the ability to accurately send data streams periodically, solving the problem that the periodic flow of the end device accessing the delay-sensitive network cannot be accurately controlled.

[0031] The method for terminal equipment to access a delay-sensitive network proposed in this application, and other advantages, objectives and features of this application will be reflected in part through the following description, and will also be understood by technical personnel in this field through research and practice of this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present description. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0033] Figure 1 A schematic diagram illustrating a process of a method for a terminal device to access a delay-sensitive network provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of the system structure of a terminal device provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the electronic device structure for accessing a delay-sensitive network provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification are described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0037] In this article, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also include elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprising a ..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. The term "two or more" includes two or more than two cases.

[0038] See also Figure 1 , which is a flow diagram of a method for an end device to access a delay-sensitive network provided by an embodiment of the present application. The end device includes a central processing unit and a hardware module in communication connection. The central processing unit is provided with a first memory buffer for storing periodic flow data. The hardware module includes a timer and a target port. The method is applied to the hardware module and may specifically include:

[0039] S110: Acquire a global synchronization time of a delay-sensitive network, calibrate the local time of the terminal device based on the global synchronization time, and configure the timer based on the calibrated local time and a preset period;

[0040] For example, in a delay-sensitive network, there is a global unified time standard, and the end device needs to communicate with other devices in the network through a specific time synchronization protocol, such as the GPTP (Generalized Precision Time Protocol) protocol, to obtain this global synchronization time. Since the local clock of the end device may have errors and be inconsistent with the global synchronization time, the local time needs to be adjusted according to the obtained global synchronization time. In the present invention, when the time of the TSN (Time-Sensitive Networking) hardware module is modified, the time of the CPU (Central Processing Unit) operating system will also be modified synchronously. Although the frequency of the CPU is not modified, the time error of the CPU can be guaranteed to be at the microsecond level. The preset period is determined according to the specific application scenario and business requirements. For example, periodic control flow data will have a fixed sending period. The calibrated local time is used as a benchmark, and the trigger time and period of the timer are set in combination with the preset period to ensure that the timer can be triggered accurately as expected.

[0041] By acquiring globally synchronized time and calibrating local time, the device's time remains highly consistent with the entire network, providing an accurate time reference for subsequent periodic data transmission and reducing data transmission delays and jitter caused by time inconsistencies. Configuring a timer based on the calibrated time and preset period ensures that periodic data is sent at the correct time, meeting the strict time requirements of periodic services in delay-sensitive networks and improving system reliability and stability.

[0042] S120: When the timer is triggered, read the periodic stream data from the first memory buffer, and send the periodic stream data to the target port, so as to send the periodic stream data externally through the target port.

[0043] For example, when the timer reaches a preset trigger time, a trigger signal is generated, notifying the hardware module to perform subsequent operations. The central processing unit pre-stores the periodic stream data generated periodically in a first memory buffer. When the timer is triggered, the hardware module reads this data from the first memory buffer according to the corresponding address information. After reading the periodic stream data, the hardware module transmits it to the target port. The target port then sends the data to the network according to the requirements of the network protocol, thereby realizing the external transmission of the periodic stream data.

[0044] Precise timer triggering ensures that periodic data flows are delivered according to the scheduled cycle, guaranteeing the continuity and stability of periodic services. By reading and sending data directly from the first memory buffer, this reduces the need for intermediate data processing steps, improves the real-time nature of data transmission, and meets the real-time requirements of latency-sensitive networks.

[0045] In summary, the method for an end device to access a delay-sensitive network proposed in an embodiment of the present application is to write periodic flow data into a first memory buffer and continuous flow data into a second memory buffer. When the timer is triggered, the periodic flow data is read from the first memory buffer and sent to the target port. When the gate of the target port is turned on, the periodic flow data with high priority is sent first, and precise cycle control is completed using a hardware module. The hardware module can achieve precise time synchronization of ±20ns. Therefore, using hardware for cycle control can control the cycle error from microseconds to nanometers, and the control accuracy is improved by 1000, so that the end device has the ability to accurately send data streams periodically, solving the problem that the periodic flow of the end device accessing the delay-sensitive network cannot be accurately controlled.

[0046] In some examples, the central processing unit further includes a second memory buffer for storing continuous flow data. When the timer is triggered, the central processing unit reads the periodic flow data from the first memory buffer and sends the periodic flow data to the target port, further comprising:

[0047] When the sending of the periodic stream data is completed, the continuous stream data is read from the second memory buffer and sent to the target port, so as to be sent externally through the target port.

[0048] Exemplarily, the central processing unit further includes a second memory buffer for storing continuous flow data. When a timer is triggered and periodic flow data is read and sent from the first memory buffer, if the periodic flow data has been sent, the continuous flow data is read from the second memory buffer and sent to the target port for external transmission. This achieves the orderly transmission of periodic flow data and continuous flow data. While ensuring the timely transmission of periodic flow data, network resources are rationally utilized to send continuous flow data, thereby improving network resource utilization and avoiding resource waste.

[0049] In some examples, the step of calibrating the local time of the terminal device based on the global synchronized time includes:

[0050] exchanging synchronization messages with a delay-sensitive network based on a time synchronization protocol to calculate a time offset with the delay-sensitive network;

[0051] The time of the hardware module is corrected based on the time offset, and the corrected time is updated to the terminal device through an interrupt mechanism to calibrate the local time of the terminal device.

[0052] For example, the CPU and TSN hardware module are directly connected through PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard). PCIE serves as a data stream transmission channel and a channel for reading TSN hardware module registers. The GPTP software protocol runs on the CPU for sending and receiving messages, so that the TSN module can synchronize the time of the entire network. The specific implementation is as follows: first, based on a time synchronization protocol such as the GPTP protocol, synchronization messages are exchanged with the delay-sensitive network, and the time offset with the network is calculated. Then, the time of the hardware module is corrected according to this time offset, and the interrupt mechanism is used to update the corrected time to the CPU of the end device, thereby completing the calibration of the local time. That is, when the time of the TSN hardware module is modified, the time of the CPU operating system is also modified at the same time. Since the CPU frequency is not modified, the CPU time error is at the microsecond (us) level. At the same time, multiple memory buffers are designed. One of the memory buffers, that is, the second memory buffer, is used for sending continuous low-priority traffic. We use a circular queue to receive and send continuous flow data. The remaining memory buffers are used to send and receive periodic flow data. The application layer software running on the CPU periodically stores the periodic flow data in this memory buffer, that is, the first memory buffer. This period must be smaller than the actual period of message sending. For example, the period of a periodic flow data is 5 milliseconds. The periodic flow data needs to be ready to be written into the first memory buffer at 4.5 milliseconds. The hardware module takes the message out of the first memory buffer at 5 milliseconds and sends the message when the queue door opens.

[0053] The specific implementation method of time calibration is explained in detail. By accurately calculating the time offset and correcting the time, the accuracy of time calibration is improved, ensuring that the local time of the end device is highly consistent with the global synchronization time in the network, providing an accurate time basis for subsequent timing operations.

[0054] In some examples, when the timer is triggered, the step of reading the periodic stream data from the first memory buffer includes:

[0055] Configure a trigger period and a start time of the hardware timer based on the global synchronization time, and generate a timing interrupt signal according to the trigger period and the start time;

[0056] When the timer is triggered, the periodic stream data is read from the first memory buffer based on the interrupt signal.

[0057] For example, the hardware timer's trigger period and start time are configured based on the global synchronization time. These parameters generate a timer interrupt signal, which is then used by the hardware module. When the timer triggers, the hardware module reads the periodic stream data from the first memory buffer based on the interrupt signal. This clarifies the trigger mechanism for reading periodic stream data. By configuring the trigger period and start time to generate a timer interrupt signal, the periodic stream data is ensured to be read at the correct time, improving the accuracy and timeliness of data reading and further enhancing the system's time synchronization and data transmission reliability.

[0058] In some examples, the step of sending the periodic stream data to the target port includes:

[0059] Determining the start time and duration of gated opening according to the transmission delay of the periodic stream data and a preset error margin;

[0060] Configuring a gating state of the target port based on a gating schedule so that the gating of the target port is turned on at the start time and remains turned on for the duration;

[0061] When the gating of the target port is turned on, the continuous flow data transmission of the second memory buffer is blocked, and the periodic flow data is sent to the target port.

[0062] For example, transmission latency refers to the time required for periodic stream data to travel from the transmitter to the destination port. Due to uncertainties in the network environment, unexpected situations such as network congestion and device failures may occur, which can cause fluctuations in transmission latency. The preset error margin is a time reserve to account for these uncertainties. First, the start time and duration of gate opening are determined based on the transmission latency of the periodic stream data and the preset error margin. The start time must ensure that the periodic stream data is ready for transmission when the gate is opened, and that the periodic stream data arrives at the destination port on time, taking into account the transmission latency and error margin. Based on the previously calculated start time and duration of gate opening, the corresponding information is entered into the gate scheduling table. The hardware module will, in accordance with the instructions in the gate scheduling table, promptly open the gate of the destination port at the start time and maintain the gate open for the duration. While gate opening, the transmission of continuous stream data in the second memory buffer is blocked to ensure that the periodic stream data can be smoothly transmitted to the destination port.

[0063] By properly configuring the gating state, periodic flow data is guaranteed to be sent preferentially within a specific time, thus avoiding the interference of continuous flow data on periodic flow data, reducing the transmission delay and packet loss rate of periodic flow data, improving the transmission quality of periodic flow data, and meeting the strict requirements of delay-sensitive networks for periodic flow data transmission.

[0064] In some examples, the end device includes a register, and the step of sending the periodic stream data to a target port includes:

[0065] Configuring a timing period of a register, wherein the timing period is consistent with a sending period of the periodic stream data;

[0066] The periodic stream data in the first memory buffer is read and sent based on the timing period.

[0067] Exemplarily, the end device includes a register, which is a high-speed storage component within the end device for temporarily storing data and instructions. The register's timing period is configured. The timing period refers to the time it takes for the register timer to start timing and trigger an event, such as generating an interrupt signal. This time period must be consistent with the transmission period of the periodic stream data. The transmission / reception of periodic stream data can flexibly select between instruction transmission / reception and timed transmission / reception based on the register configuration. The instruction transmission method notifies the hardware module via the register to initiate transmission and is suitable for data with high real-time requirements. The timed transmission method does not require the hardware module to initiate data transfer via the register. The driver pre-configures a timing period for the buffer management module. After data transfer is enabled, the buffer module periodically transfers data between memories according to the configuration. In other words, the buffer module reads and transmits the periodic stream data in the first memory buffer based on the timing period, without the driver sending instructions. This method offers greater real-time performance, but requires the driver to prepare the data in advance and is suitable for periodic data.

[0068] In some examples, the method further includes:

[0069] When a read / write anomaly is detected in the first memory buffer or the second memory buffer, a data read operation is re-initiated or a redundancy check is performed.

[0070] For example, an exception handling mechanism has been added. When a read or write anomaly is detected in the first or second memory buffer, the data read operation is re-initiated or a redundancy check is performed. This improves the system's fault tolerance. When a read or write anomaly occurs, data errors can be promptly detected and corrected by re-initiating the read operation or performing a redundancy check, ensuring data integrity and accuracy, enhancing system stability and reliability, and reducing system failures caused by data errors.

[0071] The present invention is described in detail below with reference to the embodiments, but they should not be construed as limiting the scope of protection of the present invention.

[0072] Example:

[0073] For example, a vehicle control system operates on the same device with two services: one uses lidar to detect obstacles in a certain direction and regularly transmits the detection results to the intelligent driving system; the other uses cameras to conduct real-time inspections of the vehicle's location and transmit the images to the intelligent driving system. The obstacle detection results are transmitted every 5 milliseconds, with a transmission rate of 1000 bytes and a priority of 6. The real-time video service transmits at a rate of 2 Gbps and a priority of 0. The same monitoring is performed on the four directions of the vehicle body. Then, the switch simultaneously carries 8G video data in four directions and obstacle detection results data in four directions on the port sent to the intelligent driving system. In Ethernet, if multiple ports converge to one port at the same time, a burst will be formed, which will cause switch congestion. Since the switch has a certain amount of cache, the possible result is that the data flow delay jitter during the burst will increase. If the burst duration exceeds the time that the switch cache can withstand, packet loss will occur. Therefore, if there is no gated scheduling protocol (Qbv) for periodic obstacle detection, data will be lost and the delay will increase, affecting the decision-making of the intelligent driving system. Therefore, it is necessary to design a gated switch for this periodic service. When this type of service is transmitted, other services will be blocked. Only after the service is transmitted can other services continue to be transmitted.

[0074] The time required to transmit 1000 bytes on a 10G port is 800 nanoseconds. Since the timing accuracy of this solution is ±100 nanoseconds, a 200 nanosecond margin is left for the duration. The transmission efficiency is 800 / 1000 of the theoretical value, or 80%. The theoretical gating list of ports between the designed switch and the intelligent driving system is shown in Table 1:

[0075]

[0076] Table 1

[0077] To implement this gating information, first of all, the periodic flow data of each end device must be strictly guaranteed to be 5ms. In addition, the periodic flow data must be sent out at a strict reference time point. Assuming that the direct transmission delay from the end device to the switch is 3us, the timing period of the timer buffer configured on end device A is 5ms, and the start time is 0us; the timing period of the timer buffer configured on end device B is 5ms, and the start time is 3us; the timing period of the timer buffer configured on end device C is 5ms, and the start time is 12us; the timing period of the timer buffer configured on end device D is 5ms, and the start time is 19us; at the same time, the CPU software can first store the periodic flow data into the buffer before the corresponding 5ms period starts.

[0078] The hardware module specifically addresses this by setting up a DMA (Direct Memory Access) module to perform memory access operations. DMA can be flexibly adapted to different interconnect bus interfaces through hardware parameterization. By supporting various interconnect protocols, the current solution is flexible and compatible with diverse device types. The DMA module can perform read and write operations on the bus at a higher rate, significantly freeing up CPU computing resources and further expanding the applicability of the current solution.

[0079] A ring queue descriptor management module is set up to exchange information between the driver and the hardware, completing low-priority data flow transmission and reception operations. This module stores the attributes of the ring queue and establishes a cache space for prefetching descriptors in the ring queue. These descriptors record the key parameters required for information exchange between the driver and the hardware, such as the source address, destination address, length of the data transferred, and the type of transfer operation.

[0080] To ensure reliable and efficient information exchange, the ring queue descriptor management module also features an error detection and recovery mechanism. When an error is detected during descriptor transmission or processing, the module immediately takes appropriate recovery measures, such as resending the descriptor and performing data verification and repair, thus ensuring stable system operation.

[0081] A memory fixed cache space management module is set up to manage the buffers with fixed addresses in the memory space to ensure the sending and receiving operations of periodic data streams. These attribute information are the basis for effective management of DMA buffers (memory buffers), and describe the characteristics and status of each DMA buffer in detail and accurately. Specifically, the attribute information includes but is not limited to the starting address of the DMA buffer, the data storage status, such as used, idle, etc., access rights, timing configuration and association identifiers of periodic data streams, etc. Through real-time monitoring and management of these attribute information, the cache space management module can quickly and accurately locate and allocate appropriate DMA buffers to meet the sending and receiving requirements of different data streams. The module stores the attribute information of the DMA buffer internally.

[0082] The length and number of DMABuffers are configurable. This configurability allows the system to flexibly adjust DMA buffer space resource allocation based on the needs of actual application scenarios. In actual applications, different periodic data streams may have different data volumes and transmission frequencies. For example, some periodic data streams may require a larger DMABuffer length to store continuous data blocks, while others may only require a smaller buffer. By setting the configurable length, the system can allocate the most appropriate DMA Buffer length for each data stream, thereby improving memory space utilization.

[0083] Another key innovation is that DMABuffer data transmission / reception can flexibly choose between instruction and scheduled transmission / reception based on register configuration. The instruction transmission method notifies the hardware through registers and is suitable for data with high real-time requirements. The scheduled transmission method does not require register notification of hardware data transfer. The driver pre-configures a timing cycle for the buffer management module. Once the transfer is enabled, the buffer module periodically transfers data between memory according to the configuration without the need for driver-issued instructions. This method has stronger real-time performance, but requires the driver to prepare the data in advance and is suitable for periodic data.

[0084] The data transceiver module drives the exchange of data payloads with the hardware. For data transmission, a send queue management and scheduling algorithm ensures that descriptors are read in an orderly manner according to priority and time sequence. After scheduling, the send module uses the address and length within the descriptor to read the data payload from memory. Message reading and descriptor reading are performed in parallel to improve system efficiency. For data reception, the module is equipped with a large receive buffer capable of quickly storing large amounts of data transmitted from the hardware. Upon arrival, data is first temporarily stored in the receive buffer, where it is then rapidly classified and parsed. Based on the data type and destination address, it is accurately forwarded to the appropriate storage area or processing unit in the system.

[0085] The specific hardware operation process is as follows:

[0086] Data sending: buffer preparation and descriptor construction.

[0087] Based on the requirements of complex and diverse application scenarios, the driver flexibly creates multiple DMA Buffer spaces. During configuration, the memory starting address, maximum length, and status information are provided to the hardware cache management module. These spaces use direct memory access, eliminating the need for descriptor pointing, which can simplify processes and improve efficiency. They are suitable for scenarios with high real-time requirements, such as high-speed data acquisition and real-time video transmission. The driver organizes key information such as the starting address, length, data type identifier, transmission priority, and timing period of the data to be sent into descriptors in a specific format. These descriptors are written into a circular queue controlled by the circular queue descriptor management module through a software interface. The circular queue follows the first-in-first-out principle to ensure order and completeness, providing a foundation for hardware processing.

[0088] When the upper-layer software selects to send data using a descriptor, the driver writes the descriptor into a circular queue according to the rules. It then uses the configuration register to notify the circular queue management module, allowing the hardware to read the descriptor and prepare for data transmission. If fixed-buffer instructions are used for transmission, the driver writes the data to be sent directly into a fixed DMA buffer. Upon completion, the driver configures the register and notifies the DMA space buffer management module, which then initiates subsequent operations based on the signal and the cache strategy. If fixed-buffer periodic transmission is used, the driver must enable the hardware's cycle enable register and periodically write data to the buffer before the timer expires.

[0089] After receiving the hardware start signal, the ring queue descriptor management module collaborates with the DMA module. The DMA module batch-reads descriptors from the ring queue based on memory address information, leveraging parallelism to read multiple descriptors in a short period of time. The descriptors are then transferred to the data transmission module to provide information support for subsequent operations.

[0090] After receiving the descriptor, the data transmission module parses the key information and, using the DMA module, reads the data to be transmitted from memory. This operation strictly adheres to the requirements of the descriptor and the interconnect bus to ensure accuracy and completeness. After reading, it sends the data to the lower-level module and supports error control technology to verify the data and reduce the probability of errors. If there is unsent data in the fixed buffer space, the descriptor reading stage is skipped and the DMA module directly uses the buffer space configuration information to read the data to be transmitted.

[0091] After the data transmission module completes transmission, it sends an interrupt signal to the CPU. The CPU processes the interrupt according to the interrupt priority mechanism, confirms the transmission result, updates the data transmission status flag, and calculates the amount of data sent, providing a basis for resource management and performance evaluation. At the same time, the CPU may trigger subsequent processes, and the driver updates the descriptor status, freeing up ring queue resources to ensure the continuous and efficient data transmission process.

[0092] For periodic data transmission, the data receiving module skips descriptor access operations and periodically reads data directly from system memory, writes it to the corresponding hardware buffer, and updates the corresponding information. This simplifies the operation process and ensures the real-time performance of periodic data. After data reading is completed, the hardware module triggers an interrupt signal to notify the CPU of the data update completion and informs lower-level modules that the latest data has been written. This ensures accurate and complete operation and module coordination.

[0093] When receiving data, cache space is first prepared. After initialization, the driver constructs a receive descriptor before receiving data. This descriptor records information such as the target memory start address, the expected maximum receive length, the data format identifier, and the receive priority. This descriptor is then written sequentially to the circular queue of the circular queue descriptor management module in preparation for reception. Based on application scenario requirements, the driver dynamically creates multiple DMA buffer spaces. During configuration, the memory start address, maximum length, and status information are provided to the hardware cache management module. These spaces utilize direct memory access, eliminating the need for descriptor pointing. This simplifies the process, improves data processing speed and response efficiency, and is suitable for scenarios with high real-time requirements.

[0094] Before lower-level modules send data, the driver precisely configures registers and passes the descriptor count information to the descriptor management module. This module then collaborates with the DMA module, leveraging DMA's powerful memory access capabilities to batch read receive descriptors from a circular queue. Within nanoseconds, the DMA reads multiple descriptors into an internal cache, pre-emptively preparing resources, reducing data reception wait times and improving efficiency.

[0095] The data receiving module captures and analyzes key information such as packet header signatures and data format encoding in real time, applying a built-in classification algorithm for precise classification. Upon completion, descriptors are extracted from the corresponding descriptor ring queue or written directly to a fixed DMA buffer, depending on the category. These descriptors store specific storage strategies and configuration information, ensuring that each type of data is stored in the appropriate memory space based on its characteristics. This enables refined storage management and improves the system's ability to handle diverse data.

[0096] The data receiving module collaborates with the DMA module to accurately write data to the corresponding memory based on the descriptor address information. After writing, the corresponding descriptor fields are accurately filled in based on the data's accompanying information, such as updating the data length and confirming the data type. The updated descriptor is then written back to the original location in the circular queue to ensure consistency between the descriptor and the actual data, providing a basis for subsequent processing. After the write-back is complete, the hardware module triggers an interrupt signal to notify the CPU that the data write is complete, forming a closed loop from reception and storage to descriptor update feedback, ensuring accurate and complete operations and module coordination.

[0097] For periodic data, the data receiving module periodically reads data from the hardware's internal buffer and writes it directly to the corresponding memory space, updating the corresponding information. This bypasses the descriptor prefetching and updating steps, enabling rapid data updates. After the periodic data is written, the data receiving module can notify the CPU of the data write completion using either an interrupt or polling method, depending on the configuration.

[0098] Upon receiving a ring queue interrupt request, or through polling, the driver checks the ring queue descriptor status, comparing the current state with the initial state to determine whether it has been updated by hardware. If so, this indicates that the data block pointed to by the descriptor has been written. The driver then reads the data from memory based on the address and parameters of the updated descriptor. Following the established communication protocol and transmission path, the driver sends the data in an orderly manner to the upper-level application, achieving a seamless transition from hardware reception to data delivery to the upper-level application, supporting the system's data processing flow. Upon receiving a fixed buffer interrupt request, or through polling, the driver checks whether there is received data in the fixed buffer space. If so, the same processing flow as in the previous section is executed.

[0099] like Figure 2 As shown, this application proposes a terminal device, which includes: a central processing unit 21 and a hardware module 22;

[0100] The central processing unit 21 is configured to: acquire periodic flow data and continuous flow data, store the periodic flow data in a first memory buffer, and store the continuous flow data in a second memory buffer;

[0101] The hardware module 22 is configured to: obtain the global synchronization time of the delay-sensitive network, calibrate the local time of the terminal device based on the global synchronization time, and configure the timer based on the calibrated local time and the preset period; when the timer is triggered, read the periodic flow data from the first memory buffer and send the periodic flow data to the target port so as to send the periodic flow data to the outside through the target port.

[0102] The effects of applying the above method in the above system can be found in the description of the above method embodiment, which will not be repeated here.

[0103] like Figure 3 As shown, an embodiment of the present application also provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored on the memory 310 and executable on the processor. When the processor 320 executes the computer program 311, the steps of any of the above-mentioned methods for the terminal device to access a delay-sensitive network are implemented.

[0104] Since the electronic device introduced in this embodiment is a device used to implement an apparatus for a terminal device to access a delay-sensitive network in an embodiment of the present application, based on the method introduced in the embodiment of the present application, technical personnel in this field can understand the specific implementation of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application will not be introduced in detail here. As long as the equipment used by technical personnel in this field to implement the method in the embodiment of the present application falls within the scope of protection to be protected by this application.

[0105] In the specific implementation process, the computer program 311 can be implemented when executed by the processor Figure 1 Any implementation manner in the corresponding embodiments.

[0106] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0107] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-readable program code.

[0108] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0109] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0110] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0111] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the process of the LDPC decoding method of the solid-state drive controller.

[0112] A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)).

[0113] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0114] In the several embodiments provided in this application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0115] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0116] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0117] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0118] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0119] Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.

[0120] Obviously, those skilled in the art may make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if such changes and modifications fall within the scope of the claims of this specification and their equivalents, this specification is intended to include such changes and modifications.

Claims

1. A method for an end device to access a delay-sensitive network, characterized in that: The end device includes a central processing unit and a hardware module in communication connection, the central processing unit is provided with a first memory buffer, the first memory buffer is used to store periodic flow data, the hardware module includes a timer and a target port, and the method is applied to the hardware module, the method comprising: Obtaining a global synchronization time of a delay-sensitive network, calibrating a local time of the terminal device based on the global synchronization time, and configuring the timer based on the calibrated local time and a preset period; When the timer is triggered, the periodic stream data is read from the first memory buffer and sent to the target port, so as to be sent externally through the target port.

2. The method for accessing a delay-sensitive network by an end device according to claim 1, characterized in that: The central processing unit is further provided with a second memory buffer, the second memory buffer being used to store continuous flow data, and when the timer is triggered, reading the periodic flow data from the first memory buffer and sending the periodic flow data to the target port, further comprising: When the sending of the periodic stream data is completed, the continuous stream data is read from the second memory buffer and sent to the target port, so as to be sent externally through the target port.

3. The method for accessing a delay-sensitive network by an end device according to claim 1, wherein: The step of calibrating the local time of the terminal device based on the global synchronization time includes: exchanging synchronization messages with a delay-sensitive network based on a time synchronization protocol to calculate a time offset with the delay-sensitive network; The time of the hardware module is corrected based on the time offset, and the corrected time is updated to the terminal device through an interrupt mechanism to calibrate the local time of the terminal device.

4. The method for accessing a delay-sensitive network by an end device according to claim 1, wherein: When the timer is triggered, the step of reading the periodic stream data from the first memory buffer includes: Configure a trigger period and a start time of the hardware timer based on the global synchronization time, and generate a timing interrupt signal according to the trigger period and the start time; When the timer is triggered, the periodic stream data is read from the first memory buffer based on the interrupt signal.

5. The method for accessing a delay-sensitive network by an end device according to claim 2, wherein: The step of sending the periodic stream data to the target port comprises: Determining the start time and duration of gated opening according to the transmission delay of the periodic stream data and a preset error margin; Configuring a gating state of the target port based on a gating schedule so that the gating of the target port is turned on at the start time and remains turned on for the duration; When the gating of the target port is turned on, the continuous flow data transmission of the second memory buffer is blocked, and the periodic flow data is sent to the target port.

6. The method for accessing a delay-sensitive network by an end device according to claim 5, characterized in that: The terminal device includes a register, and the step of sending the periodic stream data to the target port includes: Configuring a timing period of a register, wherein the timing period is consistent with a sending period of the periodic stream data; The periodic stream data in the first memory buffer is read and sent based on the timing period.

7. The method for accessing a delay-sensitive network by an end device according to claim 1, wherein: The method further comprises: When a read / write anomaly is detected in the first memory buffer or the second memory buffer, a data read operation is re-initiated or a redundancy check is performed.

8. A terminal device, characterized in that: The device includes: a central processing unit and a hardware module; The central processing unit is configured to: acquire periodic flow data and continuous flow data, store the periodic flow data in a first memory buffer, and store the continuous flow data in a second memory buffer; The hardware module is configured to: obtain the global synchronization time of the delay-sensitive network, calibrate the local time of the terminal device based on the global synchronization time, and configure the timer based on the calibrated local time and a preset period; when the timer is triggered, read the periodic flow data from the first memory buffer and send the periodic flow data to the target port so as to send the periodic flow data externally through the target port.

9. An electronic device comprising: A memory and a processor, wherein the processor is configured to implement the steps of a method for an end device to access a delay-sensitive network as described in any one of claims 1 to 7 when executing a computer program stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of a method for an end device to access a delay-sensitive network according to any one of claims 1 to 7 are implemented.

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