Multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor is provided with a multilayer body and external electrodes disposed on at least two or more surfaces of the multilayer body. The laminated body is provided with an inner layer section and two outer layer sections disposed so as to sandwich the inner layer section in the lamination direction. The inner layer portion includes a plurality of first dielectric layers stacked in a stacking direction, and a first internal electrode disposed between two of the plurality of first dielectric layers. Each outer layer portion includes at least one second dielectric layer and a second internal electrode disposed so as to be in contact with the at least one second dielectric layer. The length of the second internal electrode is shorter than the length of the first internal electrode, or the width of the second internal electrode is shorter than the width of the first internal electrode. When each of the outer layer sections is bisected in the lamination direction, the void fraction of a region close to the inner layer section is lower than the void fraction of a region away from the inner layer section.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] In recent years, there has been a demand for improved reliability in multilayer ceramic capacitors for vehicles and electronic devices.

[0003] When miniaturizing electronic devices, there is a demand for miniaturization of the multilayer ceramic capacitors mounted in the electronic devices. When the multilayer ceramic capacitors are miniaturized, stress may be applied to the multilayer ceramic capacitors, causing cracks.

[0004] Patent Document 1 describes a technique in which a conductive resin layer is disposed on an intermediate layer in an external electrode, thereby ensuring moisture-resistant reliability and suppressing the occurrence of cracks in a multilayer ceramic capacitor by stress relaxation provided by the resin.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2019-16781 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] However, Patent Document 1 still has room for improvement in suppressing the occurrence of cracks in the multilayer ceramic capacitor and in miniaturization.

[0010] An object of the present invention is to suppress the occurrence of cracks and achieve miniaturization in a multilayer ceramic capacitor.

[0011] Technical solutions to solve problems

[0012] A multilayer ceramic capacitor according to the present invention comprises a laminate having a first principal surface and a second principal surface opposing each other in a stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; and at least two external electrodes disposed on at least two or more surfaces of the laminate. The laminate comprises an inner layer portion and two outer layer portions disposed so as to sandwich the inner layer portion in the stacking direction. The inner layer portion comprises a plurality of first dielectric layers stacked in the stacking direction; and a first internal electrode disposed between two of the plurality of first dielectric layers and exposed on one or more of the first side surface, the second side surface, the first end surface, and the second end surface. Each outer layer portion comprises at least one second dielectric layer; and a second internal electrode disposed so as to contact the at least one second dielectric layer and exposed on one or more of the first side surface, the second side surface, the first end surface, and the second end surface. The length of the second internal electrode in the longitudinal direction is shorter than the length of the first internal electrode in the longitudinal direction, or the width of the second internal electrode in the width direction is shorter than the width of the first internal electrode in the width direction. When each outer layer portion is divided into two equal parts along the stacking direction, the porosity of a region close to the inner layer portion is lower than the porosity of a region far from the inner layer portion.

[0013] According to the present invention, it is possible to suppress the occurrence of cracks and achieve miniaturization in a multilayer ceramic capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a perspective view of a multilayer ceramic capacitor according to a first embodiment of the present invention.

[0015] Figure 2 yes Figure 1 Cross-sectional view at line II-II.

[0016] Figure 3 yes Figure 1 Cross-sectional view at line III-III.

[0017] Figure 4 It is an exploded perspective view of the inner layer portion according to the first embodiment of the present invention.

[0018] Figure 5 yes Figure 2 Magnified view of area R.

[0019] Figure 6 This is a modification of the first embodiment of the present invention. Figure 1 Same cross-section view.

[0020] Figure 7 It is a perspective view of a multilayer ceramic capacitor according to a second embodiment of the present invention.

[0021] Figure 8 yes Figure 7 Cross-sectional view at line VII-VII.

[0022] Figure 9 It is an exploded perspective view of an inner layer portion according to a second embodiment of the present invention.

[0023] Figure 10 It is a perspective view of a multilayer ceramic capacitor according to a third embodiment of the present invention.

[0024] Figure 11 yes Figure 10 A sectional view taken along line XI-XI.

[0025] Figure 12 It is an exploded perspective view of an inner layer portion according to a third embodiment of the present invention.

[0026] Figure 13 It is an exploded perspective view of an inner layer portion according to a modified example of the third embodiment of the present invention.

[0027] Figure 14 This is a flowchart for explaining the method for manufacturing the multilayer ceramic capacitor according to the first embodiment of the present invention. DETAILED DESCRIPTION

[0028] Hereinafter, modes for implementing the present invention will be described with reference to the accompanying drawings.

[0029] It should be noted that each embodiment illustrates an embodiment of the present invention by way of example, and the present invention is not limited to the contents of the embodiment. In addition, the contents described in different embodiments can also be implemented in combination, and the implementation contents in this case are also included in the present invention. In addition, the drawings are used to help understand the description, and are sometimes schematically depicted. The ratios of the dimensions of the depicted components or components are sometimes inconsistent with the ratios of these dimensions described in the description. In addition, the components described in the description are sometimes omitted in the drawings or depicted with the number omitted.

[0030] 1. Multilayer ceramic capacitors

[0031] (First embodiment)

[0032] A multilayer ceramic capacitor according to a first embodiment of the present invention will be described.

[0033] Figure 1 It is a perspective view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 2 yes Figure 1 Cross-sectional view at line II-II. Figure 3 yes Figure 1 Cross-sectional view at line III-III.

[0034] Note that, in the drawings, the stacking direction X, the width direction Y, and the length direction Z of the multilayer ceramic capacitor 10 may be shown, and these directions may be referred to in the following description.

[0035] Reference Figure 1 The multilayer ceramic capacitor 10 includes a multilayer body 12, a first external electrode 30a, and a second external electrode 30b. In the following description, when there is no need to distinguish between the first external electrode 30a and the second external electrode 30b, one of the external electrodes may be referred to as simply the external electrode 30.

[0036] The stack 12 of this embodiment has a rectangular parallelepiped shape or a roughly rectangular parallelepiped shape as a whole. The stack 12 has a first main surface 12a and a second main surface 12b opposite to each other in the stacking direction X, a first side surface 12c and a second side surface 12d opposite to each other in the width direction Y, and a first end surface 12e and a second end surface 12f opposite to each other in the length direction Z. In this embodiment, the stacking direction X, the width direction Y and the length direction Z are orthogonal to each other. The stack 12 preferably has rounded corners and ridges. The corner refers to the portion where three adjacent faces of the stack 12 intersect. The ridge refers to the portion where two adjacent faces of the stack 12 intersect. Concavoconvexities may also be formed in part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0037] For example, Figure 2 and Figure 3 As shown, the laminate 12 includes an inner layer portion 13, a first outer layer portion 14a, and a second outer layer portion 14b. In the following description, the first outer layer portion 14a and the second outer layer portion 14b may be simply referred to as outer layer portions 14, respectively.

[0038] (Inner layer)

[0039] The inner layer portion 13 includes a plurality of first inner electrodes 13a and a plurality of first dielectric layers 13b. The inner layer portion 13 is located between the first inner electrode 13a closest to the first outer layer portion 14a and the first inner electrode 13a closest to the second outer layer portion 14b. In other words, the inner layer portion 13 is located between the first inner electrode 13a adjacent to the first outer layer portion 14a and the first inner electrode 13a adjacent to the second outer layer portion 14b.

[0040] Multiple first dielectric layers 13b are stacked in the stacking direction X. The material of each first dielectric layer 13b is arbitrary. For example, a dielectric ceramic primarily composed of BaTiO3 can be used as the material for the first dielectric layer 13b. In particular, the material for the first dielectric layer 13b may include multiple crystal grains comprising a perovskite-type compound with BaTiO3 as its basic structure. However, instead of BaTiO3, a dielectric ceramic primarily composed of other compounds such as CaTiO3, SrTiO3, or CaZrO3 can also be used as the material for the first dielectric layer 13b. Alternatively, a material obtained by adding a compound such as a Mn compound, Fe compound, Cr compound, Co compound, or Ni compound to a primary component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3, within a range lower than the primary component, can be used as the material for the first dielectric layer 13b. The thickness of the first dielectric layer 13b, i.e., the dimension in the stacking direction X, is arbitrary, but is preferably 10.0 μm or less, for example.

[0041] Each first inner electrode 13a is arranged between two adjacent dielectric layers in the stacking direction X among the plurality of dielectric layers included in the stacked body 12. The first inner electrode 13a may also be arranged between two adjacent first dielectric layers 13b in the stacking direction X among the plurality of first dielectric layers 13b. The first inner electrode 13a may also be arranged between adjacent first dielectric layers 13b in the stacking direction X and the second dielectric layer 29b of the outer layer portion 14. A first dielectric layer 13b is arranged between two adjacent first inner electrodes 13a in the stacking direction X. The first inner electrode 13a is arranged in contact with the first dielectric layer 13b.

[0042] The first internal electrode 13a of this embodiment is a plate-shaped electrode and extends in the longitudinal direction Z. The first internal electrode 13a has a first end exposed at either the first end face 12e or the second end face 12f and a second end located inside the laminate 12 .

[0043] Reference Figure 2 In this embodiment, each first internal electrode 13a is exposed on either the first end face 12e or the second end face 12f of the stacked body 12. The plurality of first internal electrodes 13a include first internal electrodes 13a that are exposed on the first end face 12e and not on the second end face 12f, and first internal electrodes 13a that are exposed at the end face of the second end face 12f and not on the first end face 12e. The first internal electrodes 13a that are exposed on the first end face 12e and not on the second end face 12f, and the first internal electrodes 13a that are exposed at the end face of the second end face 12f and not on the first end face 12e are alternately arranged in the stacking direction X.

[0044] Figure 4 This is an exploded perspective view of the inner layer portion 13. Figure 4 Each first inner electrode 13a includes an opposing electrode portion 15a and an extraction electrode portion 15b. The opposing electrode portion 15a is the portion of the first inner electrode 13a that opposes the other first inner electrode 13a adjacent in the stacking direction X. The extraction electrode portion 15b is the portion of the first inner electrode 13a other than the opposing electrode portion 15a. Electrostatic capacitance is formed by the opposing electrode portions 15a of two first inner electrodes 13a adjacent in the stacking direction X facing each other with the first dielectric layer 13b interposed therebetween. Each extraction electrode portion 15b is exposed at either the first end face 12e or the second end face 12f.

[0045] The shape of the first inner electrode 13a is not particularly limited, but is preferably rectangular when viewed in the stacking direction X. Furthermore, the corners of the opposing electrode portion 15a may be chamfered or rounded. The corners of the lead electrode portion 15b may also be chamfered or rounded.

[0046] The first inner electrode 13a preferably has a uniform thickness along the width direction Y, that is, a dimension in the stacking direction X. The thickness of the end portions of the first inner electrode 13a in the width direction Y may be thicker than the thickness of the center portion of the first inner electrode 13a in the width direction Y.

[0047] In this embodiment, the main component of the first inner electrode 13a is Cu. However, the main component of the first inner electrode 13a is arbitrary, and other metals such as Ni, Pd, or Ag may be used instead of Cu. Furthermore, the main component of the first inner electrode 13a may be an alloy of Ni, Pd, Ag, Cu, or other metals.

[0048] The thickness of the first inner electrode 13a is arbitrary, but is preferably, for example, not less than 0.2 μm and not more than 2.0 μm.

[0049] (Outer layer)

[0050] Reference Figure 2 and Figure 3 The first outer layer portion 14a and the second outer layer portion 14b are arranged to sandwich the inner layer portion 13 in the stacking direction X. The first outer layer portion 14a is arranged on one side of the inner layer portion 13 in the stacking direction X ( Figure 2 and Figure 3 In other words, the first outer layer portion 14a is arranged on the first main surface 12a side relative to the inner layer portion 13. The second outer layer portion 14b is arranged on the other side of the stacking direction X relative to the inner layer portion 13 ( Figure 2 and Figure 3 In other words, the second outer layer portion 14b is arranged on the second main surface 12b side relative to the inner layer portion 13.

[0051] The outer layer portion 14 includes a plurality of second inner electrodes 29a and a plurality of second dielectric layers 29b. The number of second inner electrodes 29a is not limited to a plurality, and may be one.

[0052] The plurality of second dielectric layers 29b are stacked in the stacking direction X. The material of each second dielectric layer 29b is arbitrary. For example, a dielectric ceramic containing BaTiO3 as a main component can be used as the material for the second dielectric layer 29b. However, instead of BaTiO3, a dielectric ceramic containing other compounds as main components, such as CaTiO3, SrTiO3, or CaZrO3, can also be used as the material for the second dielectric layer 29b. Furthermore, a material obtained by adding a compound such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound as a secondary component to a main component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3, within a range of a smaller content than the main component, can also be used.

[0053] The material of the second dielectric layer 29b can also be formed from a main component different from that of the first dielectric layer 13b. In this case, using a material with a lower dielectric constant than the main component of the first dielectric layer 13b as the main component of the second dielectric layer 29b can separate the region where the maximum capacitance is formed from the substrate, thereby achieving a noise suppression effect. When the dielectric constant of the second dielectric layer 29b is lower than that of the first dielectric layer 13b, the electrostatic capacitance formed in the inner layer 13 can be greater than the electrostatic capacitance formed in the outer layer 14. In other words, the inner layer 13 can become the region where the maximum capacitance is formed in the multilayer ceramic capacitor 10. This allows the distance between the substrate and the region where the maximum capacitance is formed to be greater when the multilayer ceramic capacitor 10 is mounted on a substrate, compared to a case where the region where the maximum capacitance is formed is the outer layer 14. Consequently, vibrations generated in the inner layer 13 are less likely to be transmitted to the substrate, thereby suppressing the generation of sound caused by substrate vibration.

[0054] Each second inner electrode 29a is arranged between two second dielectric layers 29b adjacent to each other in the stacking direction X. The second inner electrode 29a is arranged in contact with the second dielectric layer 29b.

[0055] The second inner electrode 29a of this embodiment is a plate-shaped electrode and extends in the longitudinal direction Z. The second dielectric layer 29b has a first end exposed at either the first end face 12e or the second end face 12f and a second end located inside the laminate 12 .

[0056] The length of the second inner electrode 29a, i.e., the dimension in the longitudinal direction Z, is shorter than the length L1 of the first inner electrode 13a. Specifically, the length L2 of the second inner electrode 29a of the first outer layer portion 14a is shorter than the length L1 of the first inner electrode 13a. Furthermore, the length L3 of the second inner electrode 29a of the second outer layer portion 14b is shorter than the length L1 of the first inner electrode 13a.

[0057] Reference Figure 3 The width of the second inner electrode 29a, i.e., the dimension in the width direction Y, is narrower than the width W1 of the first inner electrode 13a. Specifically, the width W2 of the second inner electrode 29a of the first outer layer portion 14a is narrower than the width W1 of the first inner electrode 13a. Furthermore, the width W3 of the second inner electrode 29a of the second outer layer portion 14b is narrower than the width W1 of the first inner electrode 13a.

[0058] Reference Figure 2 The second inner electrodes 29a are exposed on either the first end face 12e or the second end face 12f of the stacked body 12. In other words, the plurality of second inner electrodes 29a include second inner electrodes 29a that are exposed on the first end face 12e but not on the second end face 12f, and second inner electrodes 29a that are exposed at the end face of the second end face 12f but not on the first end face 12e. The second inner electrodes 29a that are exposed on the first end face 12e but not on the second end face 12f and the second inner electrodes 29a that are exposed at the end face of the second end face 12f but not on the first end face 12e are alternately arranged in the stacking direction X.

[0059] In this embodiment, the second inner electrodes 29a are opposed to each other via the second dielectric layer 29b in the outer layer portion 14, thereby forming an electrostatic capacitor. Figure 6 As in the modified example of the present embodiment shown in FIG. 1 , the two second inner electrodes 29a are arranged so as not to overlap each other in the stacking direction X. Figure 5 As in the modified example shown, the two second inner electrodes 29a are arranged on the same plane. The two second inner electrodes 29a may include a second inner electrode 29a in which one end is exposed at the first end face 12e and the other end is not exposed at the second end face 12f, and a second inner electrode 29a in which one end is exposed at the second end face 12f and the other end is not exposed at the first end face 12e.

[0060] Figure 5 yes Figure 1 Hereinafter, refer to Figure 5 The first outer layer 14a shown in FIG. 1 is described below, but the second outer layer 14b also has the same structure. Figure 5As shown, the second dielectric layer 29b in the outer layer portion 14 includes voids G. When the outer layer portion 14 is bisected along the stacking direction X, the porosity of the second dielectric layer 29b is lower in region A1 close to the inner layer portion 13 than in region A2 farther from the inner layer portion 13. In other words, when the outer layer portion 14 is bisected along the stacking direction X, the porosity of the second dielectric layer 29b in region A1 close to the inner layer portion 13 is lower than the porosity of the second dielectric layer 29b in region A2 farther from the inner layer portion 13. For example, the porosity of region A1 is preferably greater than 1% and less than 4%, while the porosity of region A2 is preferably greater than 4% and less than 10%. By making the porosity of the second dielectric layer 29b lower in the area A1 close to the inner layer portion 13 than in the area A2 far from the inner layer portion 13, the voids act as a buffer material, thereby achieving a stress relaxation effect. In addition, by making the porosity of the area close to the inner layer portion 13 lower, it is possible to prevent moisture that enters through the voids from reaching the inner layer portion 13.

[0061] Alternatively, when the outer layer portion 14 is divided into three equal parts along the stacking direction X, the porosity of the second dielectric layer 29b included in the region closest to the inner layer portion 13 is the lowest, and the porosity of the second dielectric layer 29b increases as it approaches the region farther from the inner layer portion 13.

[0062] The following describes an example method for measuring the porosity of the second dielectric layer 29b. First, a scanning microscope (SEM) was used to observe the exposed cross-sections of each second dielectric layer 29b in a length x height cross-section at the center of the multilayer ceramic capacitor 10 in the width direction Y at 6000x magnification. Images of a 19.5 μm x 10.5 μm field of view were taken at five non-overlapping locations. Based on each SEM image, image analysis was used to calculate the ratio of the area occupied by voids relative to the entire field of view as the porosity for each field of view. The porosity was then calculated as the average value of the five fields of view.

[0063] like Figure 2 As shown, in this embodiment, the height T1 of the first outer layer portion 14a in the stacking direction X is lower than the height T2 of the second outer layer portion 14b in the stacking direction X. This allows for greater distance between the inner layer portion 13, the region generating the maximum capacitance, and the substrate when the second principal surface 12b is used as the mounting surface, thereby achieving a noise suppression effect. It should be noted that the "mounting surface" refers to the surface of the laminate 12 that faces the substrate when the multilayer ceramic capacitor 10 is mounted on the substrate.

[0064] In order to increase the capacitance of the multilayer ceramic capacitor 10, it is necessary to increase the area of each first internal electrode 13a. Therefore, the coverage of the first internal electrode 13a in the width direction Y x the length direction Z is preferably 90% or more. The coverage in the width direction Y x the length direction Z is defined as the area of the stacked body 12 when viewed from above. Figure 1 In the plane of length×width formed by the length L and the width W shown, the ratio is obtained by subtracting the area of the gap provided in the first internal electrode 13a from the area inside the edge of the first internal electrode 13a.

[0065] The higher the surface coverage of the first inner electrode 13a in the width direction Y × length direction Z, the higher the capacitance of the multilayer ceramic capacitor 10. However, even if the surface coverage in the width direction Y × length direction Z is low, the two first dielectric layers 13b arranged on either side of the first inner electrode 13a in the stacking direction X are bonded via a gap. Therefore, the bonding strength between the first dielectric layers 13b is increased, and interlayer delamination is less likely to occur.

[0066] It should be noted that an insulating layer may also be provided on the first side surface 12c and the second side surface 12d of the stack 12, although this is not shown. When an insulating layer is provided, the interface between the first internal electrode 13a and the first dielectric layer 13b, the interface between the first internal electrode 13a and the second dielectric layer 29b, and the interface between the second internal electrode 29a and the second dielectric layer 29b are covered by the insulating layer, thereby suppressing the intrusion of moisture into the stack 12. Furthermore, the insulating layer preferably has the same or similar composition as the first dielectric layer 13b or the second dielectric layer 29b. When the insulating layer has the same or similar composition as the first dielectric layer 13b, the adhesion between the insulating layer and the first dielectric layer 13b is improved. When the insulating layer has the same or similar composition as the second dielectric layer 29b, the adhesion between the insulating layer and the second dielectric layer 29b is improved.

[0067] Alternatively, the insulating layer may be arranged so as to be bonded to the first and second internal electrodes 13a, 29a. In this case, the surface of the insulating layer not bonded to the first and second internal electrodes 13a, 29a becomes the first and second side faces 12c, 12d. In other words, when the insulating layer is bonded to the first and second internal electrodes 13a, 29a, the surface of the insulating layer opposite to the first and second internal electrodes 13a, 29a forms the first and second side faces 12c, 12d of the laminate 12.

[0068] The insulating layer preferably includes an inner layer positioned most inwardly in the width direction Y and an outer layer positioned most outwardly in the width direction. It should be noted that when an inner layer and an outer layer are provided, the boundary between the inner and outer layers can be easily identified by observation using an optical microscope due to the difference in sinterability between the inner and outer layers. In other words, a boundary exists between the inner and outer layers. Multiple boundaries may also exist.

[0069] It should be noted that the insulating layer is not limited to a two-layer structure and may also be a structure of three or more layers. When the insulating layer includes three or more layers, the innermost layer arranged in the width direction Y is defined as the inner layer, and the outermost layer arranged in the width direction Y is defined as the outer layer.

[0070] Stepped layers 16 are arranged on the same plane as the first internal electrode 13a. Without these stepped layers 16, there would be a difference in thickness between the portion where the first internal electrode 13a is arranged and the portion where it is not, potentially causing deformation during pressing during the manufacturing process of the multilayer ceramic capacitor 10, which will be described later. In contrast, in this embodiment, the stepped layers 16 fill the step corresponding to the thickness of the first internal electrode 13a in the stacking direction X, thereby mitigating deformation during pressing during the manufacturing process of the multilayer ceramic capacitor 10. The stepped layers 16 preferably have the same or substantially the same thickness as the first internal electrode 13a arranged on the same plane. The stepped layers 16 preferably have the same or substantially the same composition as the first dielectric layer 13b. Alternatively, the stepped layers 16 may have the same or substantially the same composition as the first internal electrode 13a arranged on the same plane. In this case, the stepped layers 16 need to be spaced apart from the first internal electrode 13a in the width direction Y and the length direction Z to insulate the first internal electrode 13a.

[0071] Stepped layer 17 is arranged on the same plane as second internal electrode 29a. Without stepped layer 17, there would be a difference in thickness between the portion where second internal electrode 29a is arranged and the portion where it is not, potentially causing deformation during pressing during the manufacturing process of multilayer ceramic capacitor 10, described later. In contrast, in this embodiment, stepped layer 17 fills the step corresponding to the thickness of second internal electrode 29a in the stacking direction X, thereby mitigating deformation during pressing during the manufacturing process of multilayer ceramic capacitor 10. Stepped layer 17 preferably has the same or substantially the same thickness as second internal electrode 29a, which is arranged on the same plane. Stepped layer 17 preferably comprises the same or substantially the same composition as second dielectric layer 29b. Alternatively, stepped layer 17 may comprise the same or substantially the same composition as second internal electrode 29a, which is arranged on the same plane. In this case, stepped layer 17 needs to be spaced apart from second internal electrode 29a in width direction Y and length direction Z to insulate the second internal electrode 29a.

[0072] When the stepped layers 16 and 17 are not provided, and a gap is defined between the first inner electrode 13a and the first end face 12e or the second end face 12f, the second inner electrode 29a is preferably arranged at a position parallel to the gap in the stacking direction X. In other words, when the stepped layers 16 and 17 are not provided, the second inner electrode 29a is preferably arranged at a position that does not overlap with the first inner electrode 13a when viewed in the stacking direction X. This ensures that the height of the stack 12 is uniform in the stacking direction X, thereby alleviating deformation caused by a step in the thickness of the first inner electrode 13a in the stacking direction X.

[0073] (External electrode)

[0074] External electrodes 30 are arranged on the first end surface 12 e and the second end surface 12 f of the stacked body 12 .

[0075] A first external electrode 30a is formed on the first end face 12e side of the stack 12. The first external electrode 30a is preferably continuously arranged on the first end face 12e, the first principal surface 12a, and the second principal surface 12b of the stack 12. It should be noted that it is more preferably also arranged on the first side surface 12c and the second side surface 12d. The first external electrode 30a is bonded to the first internal electrode 13a exposed on the first end face 12e of the stack 12 and the second internal electrode 29a exposed on the first end face 12e of the stack 12. Thus, the first external electrode 30a is electrically connected to the first internal electrode 13a and the second internal electrode 29a arranged on the first end face 12e of the stack 12.

[0076] A second external electrode 30b is formed on the second end face 12f of the stack 12. The second external electrode 30b is preferably continuously arranged on the second end face 12f, the first principal face 12a, and the second principal face 12b of the stack 12. It should be noted that it is more preferably also arranged on the first side face 12c and the second side face 12d. The second external electrode 30b is bonded to the first internal electrode 13a exposed on the second end face 12f of the stack 12 and the second internal electrode 29a exposed on the second end face 12f of the stack 12. Thus, the second external electrode 30b is electrically connected to the first internal electrode 13a and the second internal electrode 29a arranged on the second end face 12f of the stack 12.

[0077] like Figure 2 As shown, the external electrode 30 includes a base electrode layer 34 made of a conductive metal and disposed on the laminate 12, a lower plating layer 35 disposed to cover the surface of the base electrode layer 34, and a surface plating layer 36 disposed to cover the surface of the lower plating layer 35. In this embodiment, the lower plating layer 35 is a Ni plating layer, and the surface plating layer 36 is a Sn plating layer.

[0078] The base electrode layer 34 of the first external electrode 30a is formed on the first end surface 12e side of the stack 12. The base electrode layer 34 of the first external electrode 30a is preferably continuously arranged on the first end surface 12e, the first principal surface 12a, and the second principal surface 12b of the stack 12. It should be noted that the base electrode layer 34 of the first external electrode 30a is more preferably also arranged on the first side surface 12c and the second side surface 12d. The base electrode layer 34 of the first external electrode 30a is bonded to the first internal electrode 13a exposed on the first end surface 12e of the stack 12 and the second internal electrode 29a exposed on the first end surface 12e of the stack 12. Thus, the base electrode layer 34 of the first external electrode 30a is electrically connected to the first internal electrode 13a and the second internal electrode 29a arranged on the first end surface 12e of the stack 12.

[0079] The base electrode layer 34 of the second external electrode 30b is formed on the second end face 12f side of the stack 12. The base electrode layer 34 of the second external electrode 30b is preferably continuously arranged on the second end face 12f, the first principal face 12a, and the second principal face 12b of the stack 12. It should be noted that the base electrode layer 34 of the second external electrode 30b is more preferably also arranged on the first side face 12c and the second side face 12d. The base electrode layer 34 of the second external electrode 30b is bonded to the first internal electrode 13a exposed on the second end face 12f of the stack 12 and the second internal electrode 29a exposed on the second end face 12f of the stack 12. Thus, the base electrode layer 34 of the second external electrode 30b is electrically connected to the first internal electrode 13a and the second internal electrode 29a arranged on the second end face 12f of the stack 12.

[0080] The base electrode layer 34 includes at least one selected from a sintered layer and a conductive resin layer described below.

[0081] (In the case of burnt layer)

[0082] The sintered layer includes a glass component and a metal. The glass component includes at least one selected from B, Si, Ba, Mg, Al, and Li. For example, the sintered layer includes at least one metal selected from Cu, Ni, Ag, Pd, an Ag-Ni alloy, and Au. Alternatively, the sintered layer may include the same components as the first dielectric layer 13b, instead of the glass component.

[0083] (Conductive resin layer)

[0084] The conductive resin layer may be disposed on the sintered layer so as to cover the sintered layer, or may be disposed directly on the laminate 12 .

[0085] The conductive resin layer comprises a thermosetting resin and a metal. Because it is composed of a thermosetting resin, it is more flexible than, for example, conductive layers comprising a plated film or a fired product of a conductive paste. Therefore, even when the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks from forming in the multilayer ceramic capacitor 10.

[0086] As the metal contained in the conductive resin layer, Ag, Cu, or alloys thereof can be used. Alternatively, as the metal contained in the conductive resin layer, metal powder coated with Ag can be used. As the metal powder coated with Ag, Cu and Ni are preferably used. Alternatively, as the metal contained in the conductive resin layer, Cu that has been subjected to an anti-oxidation treatment can be used.

[0087] The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable for electrode materials. Furthermore, Ag is a noble metal, so it does not oxidize and has high weather resistance. It should be noted that the reason for using Ag-coated metal is that the base metal can be made of an inexpensive metal while maintaining the aforementioned properties of Ag.

[0088] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, the conductive fillers contained in the conductive resin are in contact with each other, forming an electrical path within the conductive resin layer.

[0089] The metal contained in the conductive resin layer may be in a spherical or flat shape, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0090] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, polyurethane resin, silicone resin, and polyimide resin can be used. Among them, epoxy resin is one of the most suitable resins for the conductive resin layer due to its excellent heat resistance, moisture resistance, and adhesion.

[0091] The conductive resin layer preferably includes a thermosetting resin and a curing agent. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based curing agents can be used.

[0092] (Effect)

[0093] According to the multilayer ceramic capacitor 10 according to this embodiment, the following effects can be achieved.

[0094] When outer layer portion 14 is bisected along stacking direction X, the porosity of second dielectric layer 29b in region A1 close to inner layer portion 13 is lower than the porosity of second dielectric layer 29b in region A2 farther from inner layer portion 13. With this structure, even when internal stress is generated in outer layer portion 14, region A2 having a relatively high porosity can mitigate the stress and suppress the occurrence of cracks.

[0095] Furthermore, this structure can suppress the occurrence of cracks, eliminating the need for a separate member to reinforce the laminate 12. Consequently, the laminate 12 can be made smaller than if a separate member were provided to reinforce the laminate 12.

[0096] Even if moisture intrudes into the voids of outer layer portion 14, the relatively low porosity of second dielectric layer 29b in region A1 near inner layer portion 13 prevents moisture from reaching inner layer portion 13 via voids G. Consequently, the moisture resistance of multilayer ceramic capacitor 10 can be improved.

[0097] The height T2 of the second outer layer portion 14b in the stacking direction X, which is closer to the second principal surface 12b, is greater than the height T1 of the first outer layer portion 14a in the stacking direction X, which is closer to the first principal surface 12a. This structure allows the inner layer portion 13 to be positioned further away from the mounting surface when the second principal surface 12b is used as the mounting surface, compared to when the first principal surface 12a is used as the mounting surface. As a result, vibrations generated by the inner layer portion 13, which creates the greatest capacitance in the laminate 12, are less likely to be transmitted to the substrate, thereby suppressing the generation of vibration noise from the substrate.

[0098] The length L3 of the second inner electrode 29a in the second outer layer portion 14b near the second principal surface 12b is shorter than the length L2 of the second inner electrode 29a in the second outer layer portion 14b near the first principal surface 12a. This structure results in a smaller capacitance formed in the second outer layer portion 14b than in the first outer layer portion 14a. Therefore, when the second principal surface 12b is used as the mounting surface, the vibration transmitted to the substrate can be reduced compared to when the first principal surface 12a is used as the mounting surface. As a result, the generation of vibration noise from the substrate can be suppressed.

[0099] In this embodiment, the first inner electrode 13a is exposed on either the first end face 12e or the second end face 12f, but the present invention is not limited to this. The first inner electrode 13a may also be exposed on either the first side face 12c or the second side face 12d. Similarly, the second inner electrode 29a is exposed on either the first end face 12e or the second end face 12f, but the present invention is not limited to this. The second inner electrode 29a may also be exposed on either the first side face 12c or the second side face 12d.

[0100] In this embodiment, the length L1 of the first inner electrode 13a is longer than the lengths L2 and L3 of the second inner electrode 29a, and the width W1 of the first inner electrode 13a is wider than the widths W2 and W3 of the second inner electrode 29a, but the present invention is not limited to this. When the length L1 of the first inner electrode 13a is longer than the lengths L2 and L3 of the second inner electrode 29a, the width W1 of the first inner electrode 13a may be narrower than the widths W2 and W3 of the second inner electrode 29a. When the width W1 of the first inner electrode 13a is wider than the widths W2 and W3 of the second inner electrode 29a, the length L1 of the first inner electrode 13a may be shorter than the lengths L2 and L3 of the second inner electrode 29a.

[0101] (Second embodiment)

[0102] The following describes a multilayer ceramic capacitor according to a second embodiment of the present invention. The multilayer ceramic capacitor according to the second embodiment has the same structure as the multilayer ceramic capacitor according to the first embodiment, except for the shape and arrangement of the first internal electrodes, the shape and arrangement of the second internal electrodes, the number and structure of the external electrodes, and the provision of surface electrodes on the surface of the laminate. In the second embodiment, identical or similar structures to those in the first embodiment are denoted by identical or similar reference numerals, and detailed descriptions thereof are omitted.

[0103] Figure 7 It is a perspective view of a multilayer ceramic capacitor 110 according to the present embodiment. Figure 8 yes Figure 7 Cross-sectional view at line VII-VII. Figure 9 It is an exploded perspective view of the inner layer portion 113 according to this embodiment.

[0104] Reference Figure 7 The multilayer ceramic capacitor 110 of this embodiment includes a multilayer body 112 and four external electrodes 130a, 130b, 130c, and 130d. In the following description, when there is no need to specifically distinguish between the four external electrodes 130a, 130b, 130c, and 130d, one of the four external electrodes 130a, 130b, 130c, and 130d may be referred to as simply the external electrode 130.

[0105] The external electrodes 130 are disposed at the four corners of the stack 112 when viewed along the stacking direction X. The external electrodes 130 are disposed so as to cover a portion of the first principal surface 112a of the stack 112, a portion of the second principal surface 112b, a portion of either the first side surface 112c or the second side surface 112d, or a portion of either the first end surface 112e or the second end surface 112f. The external electrodes 130 may also be disposed so as not to cover the first principal surface 112a or the second principal surface 112b, thereby reducing the size of the multilayer ceramic capacitor 110 in the stacking direction X. In this case, the external electrodes 130 have a substantially L-shape when viewed along the stacking direction X.

[0106] The ratio W / L of the width W to the length L of the multilayer ceramic capacitor 110 in this embodiment is greater than or equal to 0.85 and less than or equal to 1.0. In this case, the height of the multilayer ceramic capacitor 110, i.e., the dimension in the stacking direction X, is preferably less than or equal to 120 μm. The ratio W / L can be less than 0.85 or greater than 1.0. For example, when the ratio W / L is less than 0.85, the multilayer ceramic capacitor 110, when viewed along the stacking direction X, appears to be closer to a rectangular shape than a square.

[0107] Reference Figure 8 and Figure 9, the first internal electrode 113a of this embodiment has two lead-out electrode portions 115b. Each lead-out electrode portion 115b is exposed on any side surface of the first side surface 112c or the second side surface 112d, and on any end surface of the first end surface 112e or the second end surface 112f. The lead-out electrode portions 115b of the two first internal electrodes 113a opposite to each other in the stacking direction X are led out to two different surfaces. Specifically, in a case where one first internal electrode 113a has a lead-out electrode portion 115b led out to the first side surface 112c and the first end surface 112e, and a lead-out electrode portion 115b led out to the second side surface 12d and the second end surface 12f, the other first internal electrode 113a has a lead-out electrode portion 115b led out to the first side surface 12c and the second end surface 12f, and a lead-out electrode portion 115b led out to the second side surface 12d and the first end surface 12e. In this embodiment, as Figure 9 As shown in FIG. 1 , the lead electrode portion 115 b is continuously exposed from the end surface to the side surface, but the present invention is not limited thereto and may be discontinuously exposed from the end surface to the side surface.

[0108] The second internal electrode 129a is arranged at a position that offsets the lead electrode portion 115b of the first internal electrode 113a in the stacking direction X. In other words, the second internal electrode 129a is arranged at a position that overlaps with the lead electrode portion 115b of the first internal electrode 113a when viewed along the stacking direction X. In addition, the two second internal electrodes 129a can also be arranged on the same plane. The two second internal electrodes 129a arranged on the same plane are arranged so as not to overlap each other when viewed along the stacking direction X. By respectively arranging the second internal electrode 129a on the first outer layer portion 114a and the second outer layer portion 114b, electrical bonding between the first surface electrode 118 and the second surface electrode 119 described later and the first internal electrode 113a via the base electrode layer 134 can be ensured. In addition, by adhering the second internal electrode 129a to the conductive components in the external electrode 130, the adhesion between the stacked body 112 and the external electrode 130 can be improved.

[0109] Reference Figure 8 In this embodiment, four first surface electrodes 118 ( Figure 8 Only two are shown in the figure). In addition, four second surface electrodes 119 ( Figure 8Only two are shown. The first surface electrodes 118 are arranged at the four corners of the first main surface 112a. The second surface electrodes 119 are arranged at the four corners of the second main surface 112b. The first surface electrodes 118 and the second surface electrodes 119 are arranged at positions that offset the lead electrode portion 115b of the first internal electrode 113a in the stacking direction X. In other words, the first surface electrodes 118 and the second surface electrodes 119 are arranged at positions that overlap with the lead electrode portion 115b of the first internal electrode 113a when viewed along the stacking direction X. The first surface electrodes 118 and the second surface electrodes 119 are electrodes that do not form an electrostatic capacitor.

[0110] The first surface electrode 118 and the second surface electrode 119 may have the same shape and size as the second internal electrode 129a. In this case, the first surface electrode 118 and the second surface electrode 119 are preferably made of the same material as the second internal electrode 129a.

[0111] The first surface electrode 118 and the second surface electrode 119 can also be formed by sputtering. In the case where the first surface electrode 118 and the second surface electrode 119 are formed by sputtering, the first surface electrode 118 and the second surface electrode 119 preferably include at least one selected from Ni, Cr, Cu, and Ti. The thickness of the first surface electrode 118 and the second surface electrode 119 formed by the sputtering method is preferably greater than 50 nm and less than 400 nm. As a result, the thickness of the first surface electrode 118 and the second surface electrode 119 in the stacking direction X can be sufficiently thinned, and therefore, the thickness of the stacking direction X of the multilayer ceramic capacitor 110 can be sufficiently thinned. The thickness of the first surface electrode 118 and the second surface electrode 119 in the stacking direction X can be adjusted by changing the distance between the part to be sputtered and the target. In addition, the thickness of the first surface electrode 118 and the second surface electrode 119 can be measured based on the actual observation image, or it can be measured by the following method, which is to use fluorescent X-rays and convert the thickness according to the specified element by the calibration curve method of the metal type.

[0112] The first surface electrode 118 and the second surface electrode 119 may also be fired electrodes. A fired electrode refers to an electrode comprising the same dielectric component as the first dielectric layer 13b or the second dielectric layer 29b. Specifically, if the second dielectric layer 29b comprises CaZrO3, the first surface electrode 118 and the second surface electrode 119 may comprise, for example, Ca, Zr, or CaZrO3. If the second dielectric layer 29b and the first dielectric layer 13b have different components, the first surface electrode 118 and the second surface electrode 119 preferably comprise the same component as the second dielectric layer 29b. This allows for stronger adhesion between the second dielectric layer 29b and the first surface electrode 118 and the second surface electrode 119.

[0113] The metal component of the fired electrode preferably includes Ni. In this case, the first internal electrode 113a preferably includes Ni. By having the fired electrode include the same metal component as the first internal electrode 113a, the stacked body 112, the first surface electrode 118, and the second surface electrode 119 can be fired simultaneously when the stacked body 112 is fired.

[0114] The fired electrode is formed by printing a conductive paste for the Ni fired electrode onto a dielectric sheet using screen printing or other methods and then firing. By applying the conductive paste thinly or reducing the dielectric component contained in the conductive paste, the Ni particles bond together during firing, forming a discontinuous fired electrode. Discontinuously forming the fired electrode means that the fired electrode is arranged discontinuously when viewed along the width direction Y.

[0115] like Figure 8 As shown, the external electrode 130 includes a base electrode layer 134 made of a conductive metal and disposed on the laminate 112, a lower plating layer 135 disposed to cover the surface of the base electrode layer 134, and a surface plating layer 136 disposed to cover the surface of the lower plating layer 135. In this embodiment, the lower plating layer 135 is a Ni plating layer, and the surface plating layer 136 is a Sn plating layer. Figure 8 In the embodiment, the base electrode layer 134, the lower plating layer 135, and the surface plating layer 136 are arranged in this order, but the base electrode layer, the surface plating layer, the lower plating layer, and the surface plating layer may be arranged in this order.

[0116] The base electrode layer 134 is preferably formed by a direct plating layer. A direct plating layer refers to a plating layer that directly covers the surface of the stack 112. By using the base electrode layer 134 as a direct plating layer, the thickness of the external electrode 130 in each direction can be reduced, thereby miniaturizing the stacked ceramic capacitor. The metal ratio per unit volume of the direct plating layer is preferably greater than 99 volume percent. Direct plating can also have a double-layer plating layer with different metal particle sizes. In this case, it is preferred that the plating layer with a large metal particle size is arranged on the side close to the stack 12, and the plating layer with a small metal particle size is arranged on the side away from the stack 112.

[0117] The multilayer ceramic capacitor 110 according to the second embodiment has the same operational effects as those of the multilayer ceramic capacitor 10 according to the first embodiment.

[0118] (Third embodiment)

[0119] A multilayer ceramic capacitor 210 according to a third embodiment of the present invention will be described below. The multilayer ceramic capacitor 210 according to the third embodiment has the same structure as the multilayer ceramic capacitor 10 according to the first embodiment, except for its overall shape. In the third embodiment, components identical or similar to those in the first embodiment are denoted by identical or similar reference numerals, and detailed descriptions thereof are omitted.

[0120] Figure 10 It is a perspective view of a multilayer ceramic capacitor 210 according to the present embodiment. Figure 11 yes Figure 10 A sectional view taken along line XI-XI. Figure 12 It is an exploded perspective view of the inner layer portion 13 according to this embodiment.

[0121] Reference Figure 10 In this embodiment, the length L of the multilayer ceramic capacitor 210 is shorter than the width W of the multilayer ceramic capacitor 210 .

[0122] Reference Figure 11 and Figure 12 Each first internal electrode 13a is exposed on either the first end face 12e or the second end face 12f. Figure 13 As in the modified example of the present embodiment shown, each first inner electrode 13a is exposed on either the first end face 12e or the second end face 12f, the first side face 12c, and the second side face 12d.

[0123] The multilayer ceramic capacitor 210 according to the third embodiment has the same operational effects as those of the multilayer ceramic capacitor 10 according to the first embodiment.

[0124] 2. Manufacturing Method of Multilayer Ceramic Capacitors

[0125] Below, refer to Figure 14 , a method for manufacturing a multilayer ceramic capacitor is described. Figure 6 This is a flowchart for illustrating a method for manufacturing a multilayer ceramic capacitor. It should be noted that the following description uses the method for manufacturing the multilayer ceramic capacitor 10 according to the first embodiment as an example. The multilayer ceramic capacitor 110 according to the second embodiment and the multilayer ceramic capacitor 210 according to the third embodiment can be manufactured using the same manufacturing method as the multilayer ceramic capacitor 10 according to the first embodiment. Furthermore, the following description assumes that the base electrode layer 34 is a sintered layer.

[0126] In step S1, a dielectric sheet, a conductive paste for internal electrodes, and a conductive paste for external electrodes are prepared. The dielectric sheet, the conductive paste for internal electrodes, and the conductive paste for external electrodes contain a binder and a solvent.

[0127] In step S2, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet, thereby forming an inner layer dielectric sheet having an internal electrode pattern for the inner layer portion 13 printed thereon. For example, the conductive paste for the internal electrodes may be printed on the dielectric sheet by screen printing or gravure printing.

[0128] Furthermore, in step S2, a conductive paste for internal electrodes is printed on the dielectric sheet in a predetermined pattern, thereby forming a first outer layer dielectric sheet having the internal electrode pattern of the first outer layer portion 14a printed thereon. Similarly, a conductive paste for internal electrodes is printed on the dielectric sheet in a predetermined pattern, thereby forming a second outer layer dielectric sheet having the internal electrode pattern of the second outer layer portion 14b printed thereon. For example, the conductive paste for internal electrodes can be printed on the dielectric sheet by screen printing or gravure printing.

[0129] In step S3 , a plurality of inner layer portion dielectric sheets are stacked and pressed in a stacking direction by, for example, isostatic pressing, thereby forming an inner layer portion stacked block.

[0130] Furthermore, in step S3, a plurality of first outer layer dielectric sheets are stacked, for example, by isostatic pressing in the stacking direction, thereby forming a first outer layer laminated block. Specifically, the first outer layer laminated block is formed by repeatedly stacking and pressing the first outer layer dielectric sheets. Therefore, the density of the first outer layer dielectric sheets at the beginning of stacking increases, while the density of the first outer layer dielectric sheets at the end of stacking decreases. In other words, the earlier the first outer layer dielectric sheets are stacked, the lower the porosity, while the later the dielectric sheets are stacked, the higher the porosity. Furthermore, in other words, the more dielectric sheets are located to one side of the stacking direction, the lower the porosity, while the more dielectric sheets are located to the other side of the stacking direction, the higher the porosity. To adjust the porosity of the first outer layer dielectric sheets, the amount of binder contained in the stacked first outer layer dielectric sheets can also be adjusted. By preparing dielectric sheets having varying thicknesses or compositions as the laminated first outer layer portion dielectric sheets, a first outer layer portion laminated block having a desired structure can be obtained.

[0131] Furthermore, in step S3, a plurality of second outer layer dielectric sheets are stacked, for example, by isostatic pressing in the stacking direction, thereby forming a second outer layer laminated block. Specifically, the second outer layer laminated block is formed by repeatedly stacking and pressing the second outer layer dielectric sheets. Therefore, the second outer layer dielectric sheets at the beginning of stacking have a higher density, while the second outer layer dielectric sheets at the end of stacking have a lower density. In other words, the earlier the second outer layer dielectric sheets are stacked, the lower the porosity, while the later the second outer layer dielectric sheets are stacked, the higher the porosity. Furthermore, in other words, the more dielectric sheets are positioned to one side of the stacking direction, the lower the porosity, while the more dielectric sheets are positioned to the other side of the stacking direction, the higher the porosity. To adjust the porosity of the second outer layer dielectric sheets, the amount of binder contained in the stacked second outer layer dielectric sheets can also be adjusted. By preparing dielectric sheets having different thicknesses or compositions as the laminated second outer layer portion dielectric sheets, a second outer layer portion laminated block having a desired structure can be obtained.

[0132] In step S4, the first outer layer portion laminated block, the inner layer portion laminated block, and the second outer layer portion 14b laminated block are stacked, for example, by isostatic pressing and pressing along the stacking direction, thereby obtaining a laminated block. At this time, the region with a lower porosity in the first outer layer portion laminated block is arranged near the inner layer portion laminated block, and the region with a higher porosity is arranged away from the inner layer portion laminated block. In addition, the region with a lower porosity in the second outer layer portion laminated block is arranged near the inner layer portion laminated block, and the region with a higher porosity is arranged away from the inner layer portion laminated block.

[0133] In step S5 , the stacked body block is cut into predetermined sizes to produce stacked chips. At this time, the corners and ridges of the stacked chips may be rounded by barrel grinding or the like.

[0134] In step S6 , the stacked small pieces are fired to form the stacked body 12 according to the present embodiment.

[0135] In step S7 , a conductive paste containing a glass component and a metal is applied to the first end surface 12 e and the second end surface 12 f of the laminate 12 by, for example, dipping, and then sintered to form the base electrode layer 34 .

[0136] In step S8, a plating layer is formed on the surface of the base electrode layer 34. Specifically, a lower plating layer 35, which is a Ni plating layer, and a surface plating layer 36, which is a Sn plating layer, are sequentially formed on the base electrode layer 34, which is a sintered layer. The lower plating layer 35 and the surface plating layer 36 are formed, for example, by a barrel plating method.

[0137] It should be noted that when the base electrode layer 34 is a conductive resin layer, in step S7, a conductive resin paste including a thermosetting resin and a metal component is applied to the first end face 12e and the second end face 12f of the stack 12, and then heat treated to form a conductive resin layer.

[0138] It should be noted that, as in the second embodiment, when the base electrode layer 134 is a directly plated layer, in step S7, plating is performed on the first end surface 112e and the second end surface 112f of the stacked body 112. Electrolytic plating is preferably used as the plating process. Barrel plating is preferably used as the plating process.

[0139] It should be noted that, as in the second embodiment, when the first surface electrode 118 is disposed on the first principal surface 112a of the laminate 112, a dielectric sheet printed with the pattern of the first surface electrode 118 may be laminated on the outermost side in step S3, thereby forming a first outer layer portion laminate block having the first surface electrode 118. Similarly, when the second surface electrode 119 is disposed on the second principal surface 112b of the laminate 112, a dielectric sheet printed with the pattern of the first surface electrode 118 may be laminated on the outermost side in step S3, thereby forming a first outer layer portion laminate block having the first surface electrode 118. In this case, the roughness, thickness, and density (coverage) of the first surface electrode 118 and the second surface electrode 119 are the same.

[0140] It should be noted that, as described above, the embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. That is, various modifications can be made to the above-described embodiments with respect to mechanism, shape, material, quantity, position, or arrangement, etc., without departing from the technical concept and purpose of the present invention, and such modifications are also included in the present invention.

[0141] Description of Reference Numerals

[0142] 10 multilayer ceramic capacitors;

[0143] 12 laminates;

[0144] 13 inner part;

[0145] 13a first internal electrode;

[0146] 13b a first dielectric layer;

[0147] 14 outer part;

[0148] 14a first outer portion;

[0149] 14b second outer part;

[0150] 29a second inner electrode;

[0151] 29b a second dielectric layer;

[0152] 30 external electrodes;

[0153] 30a first external electrode;

[0154] 30b Second external electrode.

Claims

1. A multilayer ceramic capacitor comprising: a stacked body having a first main surface and a second main surface opposing each other in a stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; and At least two external electrodes are arranged on at least two surfaces of the stacked body, The laminated body comprises: inner layer; and Two outer layer parts are arranged to sandwich the inner layer part in the stacking direction, The inner layer portion comprises: a plurality of first dielectric layers stacked in the stacking direction; and The first inner electrode is disposed between two of the plurality of first dielectric layers and is exposed on at least one of the first side surface, the second side surface, the first end surface, and the second end surface. Each outer layer has: at least one second dielectric layer; and The second inner electrode is arranged in contact with the at least one second dielectric layer and is exposed on at least one of the first side surface, the second side surface, the first end surface, and the second end surface. The length of the second inner electrode in the longitudinal direction is shorter than the length of the first inner electrode in the longitudinal direction, or the width of the second inner electrode in the width direction is shorter than the width of the first inner electrode in the width direction, When each outer layer portion is divided into two equal parts along the stacking direction, the porosity of a region close to the inner layer portion is lower than the porosity of a region far from the inner layer portion.

2. The multilayer ceramic capacitor according to claim 1, wherein When the outer layer portion of the two outer layer portions close to the first main surface is set as the first outer layer portion and the outer layer portion of the two outer layer portions close to the second main surface is set as the second outer layer portion, the height of the second outer layer portion in the stacking direction is higher than the height of the first outer layer portion in the stacking direction.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein When the outer layer portion close to the first main surface of the two outer layer portions is set as the first outer layer portion, and the outer layer portion close to the second main surface of the two outer layer portions is set as the second outer layer portion, the length of the second internal electrode in the first outer layer portion in the longitudinal direction is longer than the length of the second internal electrode in the second outer layer portion in the longitudinal direction.

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