Method and circuit for detecting safe working area of electronic resistance wire in slow start stage

Abstract

The invention discloses a method and a circuit for detecting a safe working area of an electronic resistance wire in a slow start stage, and relates to the technical field of server board cards, compared with an existing scheme, the method only introduces an analog-to-digital sampling technology to simulate voltage at the two ends of the electronic resistance wire and current flowing through the electronic resistance wire, so that the circuit complexity is reduced, and the detection efficiency is improved. In addition, the voltage at the two ends of the electronic resistance wire and the current flowing through the electronic resistance wire are simulated, and finally, the electronic resistance wire is determined to be abnormal in the slow start stage under the condition that the average power is not in the safe working area, so that the detection of the safe working area can be completed, the circuit complexity can be reduced, and the reliability is improved. Therefore, no extra time sequence risk is generated, and the problems that the complexity of a detection circuit is improved and the extra time sequence risk is possibly generated due to the fact that a plurality of extra hardware modules need to be introduced in a safe working area detection method in an existing scheme are solved.

Description

Technical Field

[0001] The present application relates to the technical field of server boards, and in particular to a method for detecting a safe working area of an electronic resistance wire during a soft start-up phase, an electronic resistance wire circuit, and a server board. Background Art

[0002] In the field of integrated circuits, EEPROM (Electrically Erasable Programmable Read-Only Memory) is roughly divided into two types. One is the typical EEPROM, such as Flash EEPROM, which requires a programming voltage to erase or program data. The other is a variant of EEPROM, called SOA (Secure One-time Authentication) EEPROM, such as EFUSE (Electronic Fuse). Its programming and erasure are completed by opening or closing one or more conductive paths. Once programmed, the conductive path is permanently opened or closed. Therefore, SOA EEPROM can be regarded as a programmable binary memory.

[0003] When using an SOA EEPROM, it's important to ensure that its energy consumption stays within its secure operating area (SOA) to prevent damage. SOA refers to the maximum energy the EEPROM can consume during operation. When the operating energy of an EEPROM exceeds its SOA, permanent damage may occur. Therefore, SOA detection is a critical component of SOA EEPROM operation. Its function is to control the EEPROM's startup phase to ensure that its energy consumption remains within the SOA.

[0004] Existing safe operating area detection methods often require the introduction of multiple additional hardware modules, such as voltage and current sensors, precision resistors, and analog switches. These hardware modules not only increase costs but also consume more packaging space. Furthermore, the introduction of these hardware modules increases the complexity of the detection circuitry, potentially introducing additional timing risks. Summary of the Invention

[0005] The present application provides a safe working area detection method for an electronic resistance wire in the slow start-up phase, an electronic resistance wire circuit and a server board, so as to at least solve the problem that the safe working area detection method of the existing solution needs to introduce multiple additional hardware modules, which increases the complexity of the detection circuit and may cause additional timing risk problems.

[0006] The present application provides a safe working area detection method for an electronic resistance wire in a slow start-up phase. The safe working area detection method is applied to an electronic resistance wire circuit, and the electronic resistance wire circuit includes an electrically connected microprocessor and an electronic resistance wire EFUSE, including: when an enable pin of the microprocessor is enabled, using analog-to-digital sampling technology to simulate the voltage at both ends of the electronic resistance wire and the current flowing through the electronic resistance wire to obtain analog voltage and analog current, respectively; obtaining average power according to a preset sampling interval, analog voltage, analog current and duration of the slow start-up phase, the preset sampling interval is a preset value of the sampling interval of the analog-to-digital sampling technology; when the average power is within the safe working area, determining that the electronic resistance wire is normal in the slow start-up phase; when the average power is not within the safe working area, determining that the electronic resistance wire is abnormal in the slow start-up phase.

[0007] The present application also provides an electronic resistance wire circuit, including: an electronic resistance wire EFUSE; a differential amplifier module, the non-inverting input end of the differential amplifier module is electrically connected to the input end of the electronic resistance wire, the inverting input end of the differential amplifier module is electrically connected to the output end of the electronic resistance wire, and the differential amplifier module is used to amplify the voltage difference between the two ends of the electronic resistance wire and output it; an analog resistor; a microprocessor, the first analog-to-digital sampling end of the microprocessor is electrically connected to the first end of the analog resistor and the mirror current source pin of the electronic resistance wire respectively, the second end of the analog resistor is grounded, the second analog-to-digital sampling end of the microprocessor is electrically connected to the output end of the differential amplifier module, and the microprocessor is used to execute any one of the safe working area detection methods for the electronic resistance wire in the slow start-up phase.

[0008] The present application also provides a server board, which includes: any electronic resistance wire circuit.

[0009] Through this application, compared with the existing solution, only analog-to-digital sampling technology is introduced to simulate the voltage at both ends of the electronic resistor wire and the current flowing through the electronic resistor wire, thereby reducing the circuit complexity. In addition, the voltage at both ends of the electronic resistor wire and the current flowing through the electronic resistor wire are simulated. Finally, when the average power is not within the safe working area, it is determined that the electronic resistor wire is abnormal in the slow start stage. Therefore, this application can complete the safe working area detection and reduce the circuit complexity, so that no additional timing risks will be generated. This solves the problem that the safe working area detection method of the existing solution needs to introduce multiple additional hardware modules, which increases the complexity of the detection circuit and may generate additional timing risk problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 A flow chart of a method for detecting a safe operating area of an electronic resistance wire during a slow start-up phase provided in an embodiment of the present application;

[0012] Figure 2 A flow chart of another method for detecting a safe operating area of an electronic resistance wire during a slow start-up phase provided in an embodiment of the present application;

[0013] Figure 3 A schematic diagram of an electronic resistance wire circuit provided in an embodiment of the present application;

[0014] Figure 4 A schematic diagram of another electronic resistance wire circuit provided in an embodiment of the present application;

[0015] Figure 5 A schematic diagram of the connection between the pressure relief module and the microprocessor provided in an embodiment of the present application.

[0016] The above drawings include the following reference numerals:

[0017] 100, EFUSE; 200, differential amplifier module; 300, analog resistor; 400, microprocessor; 500, pressure relief module; 600, timer. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0019] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0020] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0021] The embodiments of the present application provide a method for detecting the safe working area of an electronic resistance wire during the soft start phase. The method is described in detail in conjunction with the execution flow of the method for detecting the safe working area of an EFUSE during the soft start phase.

[0022] like Figure 1 As shown, the safe operating area detection method is applied to an EFUSE circuit, which includes an electrically connected microprocessor (MCU) and an electronic resistance wire EFUSE, and includes the following steps:

[0023] Step S101, when the enable pin of the microprocessor is enabled, analog-to-digital sampling technology is used to simulate the voltage across the electronic resistance wire and the current flowing through the electronic resistance wire to obtain analog voltage and analog current respectively;

[0024] Step S102, obtaining average power according to a preset sampling interval, the analog voltage, the analog current, and the duration of the soft start phase, where the preset sampling interval is a preset value of a sampling interval of an analog-to-digital sampling technology (ADC sampling technology);

[0025] The preset sampling interval can be set differently for staff based on different EFUSE specifications.

[0026] Step S103 , when the average power is within the safe operating area, determining that the electronic resistance wire is normal in the soft start phase; when the average power is not within the safe operating area, determining that the electronic resistance wire is abnormal in the soft start phase.

[0027] In step S103, by calculating the average power and comparing it with the safe operating area (SOA), it is possible to accurately determine whether the EFUSE remains within the safe operating area (SOA) during the soft startup phase. This method takes into account the cumulative effect of power over time, enabling a more comprehensive assessment of the EFUSE's operating status and ensuring it is not compromised by transient high power draw. Implementing this step effectively safeguards the long-term stability and reliability of the EFUSE. It also provides circuit designers with clear design boundaries, guiding them on how to set appropriate current and voltage thresholds to protect the entire system from overload. Through precise measurement and calculation, the microprocessor can collect detailed data that can be used for system-level optimization analysis. For example, based on the SOA test results, designers can adjust circuit parameters such as input voltage, load matching, or cooling system design to improve overall circuit efficiency and performance while ensuring the safe operation of each component. Implementing the safe operating area detection method provides a basis for early fault diagnosis. When the MCU detects that the average power is outside the SOA range, fault isolation can be immediately performed to prevent further escalation. In addition, by monitoring the relationship between average power and SOA over a long period of time, potential EFUSE problems can be predicted, and preventive measures can be taken to reduce system maintenance costs and downtime.

[0028] In the above steps, compared with the existing solution, only analog-to-digital sampling technology is introduced to simulate the voltage at both ends of the electronic resistance wire EFUSE and the current flowing through the EFUSE, thereby reducing the circuit complexity. In addition, the voltage at both ends of the electronic resistance wire EFUSE and the current flowing through the EFUSE are simulated. Finally, when the average power is not within the safe working area, it is determined that the EFUSE is abnormal in the slow start phase. Therefore, the present application can complete SOA detection and reduce circuit complexity, thereby not generating additional timing risks, thereby solving the problem that the safe working area detection method of the existing solution needs to introduce multiple additional hardware modules, which increases the complexity of the detection circuit and may generate additional timing risk problems.

[0029] In one embodiment of the present application, the electronic resistance wire circuit also includes an analog resistor and a differential amplifier module, the first end of the analog resistor is electrically connected to the mirror current source pin of EFUSE and the first analog-to-digital sampling terminal of the microprocessor, respectively, the second end of the analog resistor is grounded, the non-inverting input terminal of the differential amplifier module is electrically connected to the input terminal of EFUSE, and the reverse input terminal of the differential amplifier module is electrically connected to the output terminal of EFUSE. Step S101 uses analog-to-digital sampling technology to simulate the voltage at both ends of the electronic resistance wire EFUSE and the current flowing through EFUSE to obtain the analog voltage and analog current respectively, including: obtaining the current of the mirror current source pin of EFUSE; determining the analog current as the product of the current flowing through the analog resistor and a preset proportional coefficient, and the current flowing through the analog resistor is the ratio of the voltage at both ends of the analog resistor to the resistance value of the analog resistor; obtaining the output voltage of the output terminal of the differential amplifier module, and using the output voltage as the analog voltage.

[0030] Through the IMON pin (also known as the current mirror pin), the EFUSE provides a current signal proportional to the actual current flowing through it. This proportionality factor (e.g., 10μA / A) is pre-set to ensure linearity and accuracy in current detection. After the analog current signal is converted to a voltage signal via an analog resistor, the MCU uses the ADC to measure this voltage, accurately reproducing the actual current magnitude. This approach avoids the complexity and inaccuracy of directly measuring large currents while leveraging the stability of small currents to improve overall current sensing accuracy. During the soft-start phase, both voltage and current are constantly changing. By continuously sampling the IMON current and the voltage across the EFUSE, the MCU can calculate the instantaneous power in real time. This enables the MCU to promptly detect power anomalies. For example, if the instantaneous power exceeds a predetermined threshold, it can take immediate action, such as shutting down the EFUSE or triggering a discharge, thereby protecting the circuit from damage caused by excessive power loss. The differential amplifier module amplifies the voltage difference across the EFUSE to a range more convenient for ADC measurement. This not only improves the sensitivity of voltage measurement but also ensures that the ADC can accurately read and convert voltage signals even under large voltage variations under varying operating conditions, thereby improving the adaptability and reliability of the entire detection system. The use of a mirrored current source and differential amplifier simplifies the circuit design for current and voltage detection. Compared to directly measuring current or using a high-precision voltmeter, this approach reduces the need for complex external sensors, lowers costs, and improves circuit stability.

[0031] In one embodiment of the present application, the average power is obtained based on the preset sampling interval, analog voltage, analog current and duration of the soft start phase, including: determining the total power of EFUSE as the product of the preset sampling interval, analog voltage and analog current; determining the average power as the ratio of the total power to the duration of the soft start phase.

[0032] By summing the product of the analog voltage and current within each sampling interval, the total power experienced by the EFUSE during the soft-start phase can be accurately calculated. This method leverages the high precision of sampling technology and time discretization to ensure accurate and reliable power calculations and avoid uncertainty caused by instantaneous power fluctuations. The characteristics of the soft-start phase dictate that voltage, current, and power vary over time. Using pre-set sampling intervals, the microprocessor can track these parameter changes in real time and dynamically calculate the total power. This method enables timely detection of power anomalies, providing essential data support for implementing protective measures and ensuring the safe operation of the EFUSE and the entire circuit system. Calculating the average power as the ratio of total power to the duration of the soft-start phase provides a holistic view of power consumption during the soft-start phase. Average power is a key metric for assessing whether the EFUSE is operating within its safe operating area. It comprehensively considers the cumulative effect of power over time and the impact of duration, providing an objective basis for determining the EFUSE's operating status. Based on the calculated average power, designers can adjust circuit parameters such as input voltage and load matching to optimize EFUSE performance and ensure safe operation. Furthermore, by comparing average power with the SOA range, protection strategies can be intelligently adjusted. For example, when power approaches the SOA boundary, the discharge circuit can be triggered early to prevent EFUSE overload damage. Continuously monitoring average power and comparing it with the SOA range facilitates early detection of potential faults, such as overheating or overload. Upon detecting an anomaly, the microprocessor can immediately take action, such as disabling an enable signal or initiating a protection mechanism, effectively preventing more serious problems caused by EFUSE failures. Automating the calculation of average power and real-time comparison of SOA ranges reduces the need for human intervention and improves the efficiency of circuit testing and monitoring. The microprocessor's high-speed processing capabilities enable rapid response and intelligent circuit protection, which is particularly important in high-density circuit environments such as large-scale server boards.

[0033] In one embodiment of the present application, the EFUSE circuit also includes a pressure relief module, which includes a fifth resistor module, a sixth resistor module, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first end of the fifth resistor module is electrically connected to the GPIO interface of the microprocessor, the second end of the fifth resistor module is electrically connected to the base of the first transistor, the collector of the first transistor is electrically connected to the base of the second transistor, the emitter of the second transistor is electrically connected to the input end of the EFUSE, the collector of the second transistor is electrically connected to the first end of the sixth resistor module, and the second end of the sixth resistor module is electrically connected to the base of the first transistor. The method further comprises: electrically connecting the collector of the third transistor, the base of the third transistor, and the base of the fourth transistor, respectively; the collector of the fourth transistor is electrically connected to the output end of the EFUSE; the emitters of the fourth transistor, the emitters of the third transistor, and the emitters of the first transistor are grounded, respectively; and in the process of obtaining the average power according to the preset sampling interval, the analog voltage, the analog current, and the duration of the slow-start phase, the method further comprises: when the instantaneous current or instantaneous power of the EFUSE in the slow-start phase exceeds the standard, controlling the EFUSE to stop working and simultaneously controlling the pressure relief module to relieve the pressure of the EFUSE.

[0034] The pressure relief module's real-time response mechanism rapidly identifies transient current or power anomalies caused by an EFUSE overload. Once an overload condition is detected, the microprocessor immediately shuts down the EFUSE and simultaneously activates the pressure relief module, rapidly reducing the voltage and stored energy across the EFUSE to prevent further damage. This rapid response mechanism is crucial for protecting sensitive circuits from overvoltage and overcurrent. By controlling the pressure relief module to relieve the EFUSE pressure, component damage and circuit failure caused by overload can be effectively avoided, significantly improving system safety and reliability. Even under extreme conditions, this mechanism ensures that the EFUSE does not exceed its safe operating range, providing an additional layer of protection. Combining the pressure relief module with the intelligent control of the microprocessor achieves intelligent circuit protection. The microprocessor not only monitors current and voltage but also automatically determines whether to trigger the pressure relief mechanism based on preset sampling intervals and safe operating ranges. This provides continuous protection from overload threats without manual intervention, enhancing automation and system stability. By effectively responding before or in the early stages of a fault, maintenance requirements and downtime caused by EFUSE overload can be significantly reduced. This is particularly important for devices that require continuous and stable operation, such as server boards. It ensures that the system quickly returns to normal in the event of an overload, avoiding prolonged system outages and data loss. The pressure relief module can quickly release stored energy in overload conditions, not only protecting the EFUSE but also preventing unnecessary energy waste. Through intelligent control, pressure relief is activated only when necessary, enabling more efficient energy utilization, reducing overall energy consumption, and improving energy efficiency. As an independent circuit module, the pressure relief module can be flexibly integrated into different circuit designs. This modular design allows for rapid adjustment and upgrade of protection mechanisms in different application scenarios without changing the entire circuit layout, improving design efficiency and adaptability.

[0035] Wherein, when it is determined that the EFUSE is abnormal in the soft start phase, the method further includes: generating abnormal prompt information to prompt that the EFUSE is abnormal in the soft start phase.

[0036] Abnormal prompt information can immediately notify the system administrator or design engineer that the operating status of EFUSE is out of the normal range, which can trigger an immediate response, such as system shutdown, fault isolation or emergency maintenance, thereby preventing potential circuit damage from expanding and reducing data loss or system downtime. Abnormal prompts are not limited to simple warnings, but can also include detailed fault information, such as instantaneous power values, voltage and current peaks, duration, etc. This information helps to quickly locate the cause of the problem. Whether it is a circuit design defect, component aging or external environmental factors, in-depth analysis and rapid repair can be carried out based on the abnormal prompt information. Abnormal prompt information can be recorded in the system log to provide data support for subsequent fault analysis and prevention. By analyzing the log, the design team can identify common failure modes, optimize circuit design, and enhance the robustness and reliability of the system.

[0037] like Figure 2 As shown, the method of the present application includes:

[0038] In the first step, the MCU sends an enable signal EN high level to EFUSE, causing EFUSE to enter the slow start phase.

[0039] In the second step, when EN is high, the MCU controls the timer to start timing, and ADC1 and ADC2 start AD conversion with a sampling interval of Tsample.

[0040] In the third step, the MCU continuously reads the AD conversion results Ii and Vi (i represents the i-th sampling) of ADC1 and ADC2, multiplies the two results together, and then multiplies them by Tsample to obtain the energy consumed by EFUSE during the time interval Tsample: Ii*Vi*Tsample. The MCU then integrates the calculated result to obtain the total energy consumption.

[0041] Step 4: When the MCU detects that the PG signal from EFUSE has gone high, indicating the end of the soft-start phase, the MCU turns off the timer, ADC1, and ADC2, reads the timer count as the soft-start phase duration T, and then divides the accumulated energy P by the time T to obtain the average power W = P / T.

[0042] The fifth step is to compare the average power W and duration T calculated above with the SOA range required by the product manual to determine whether they exceed the standard requirements. If so, an error is reported.

[0043] Step 6: If the MCU does not detect the PG signal going high within a reasonable time range, it means that an abnormality occurs in the EFUSE soft start phase and an error is reported.

[0044] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0045] An embodiment of the present application further provides a device for detecting a safe working area of an electronic resistance wire during a slow start-up phase.

[0046] For the description of the features in the embodiment corresponding to the device for detecting the safe working area of the electronic resistance wire in the slow start-up phase, please refer to the relevant description of the embodiment corresponding to the method for detecting the safe working area of the electronic resistance wire in the slow start-up phase, which will not be repeated here.

[0047] like Figure 3 As shown, the device includes:

[0048] The first processing module is used to simulate the voltage at both ends of the EFUSE and the current flowing through the EFUSE by using analog-to-digital sampling technology when the enable pin of the microprocessor is enabled, so as to obtain analog voltage and analog current respectively;

[0049] a second processing module, configured to obtain the average power according to a preset sampling interval, the analog voltage, the analog current, and the duration of the soft start phase, wherein the preset sampling interval is a preset value of the sampling interval of the analog-to-digital sampling technology;

[0050] The third processing module is configured to determine that the EFUSE is normal in the soft start phase when the average power is within the safe working area; and determine that the EFUSE is abnormal in the soft start phase when the average power is not within the safe working area.

[0051] In the above-mentioned device, compared with the existing solution, only analog-to-digital sampling technology is introduced to simulate the voltage at both ends of the electronic resistance wire EFUSE and the current flowing through the EFUSE, thereby reducing the circuit complexity. In addition, the voltage at both ends of the electronic resistance wire EFUSE and the current flowing through the EFUSE are simulated. Finally, when the average power is not within the safe working area, it is determined that the EFUSE is abnormal in the slow start phase. Therefore, the present application can complete SOA detection and reduce circuit complexity, thereby not generating additional timing risks, thereby solving the problem that the safe working area detection method of the existing solution needs to introduce multiple additional hardware modules, which increases the complexity of the detection circuit and may generate additional timing risk problems.

[0052] In one embodiment of the present application, the EFUSE circuit also includes an analog resistor and a differential amplifier module, the first end of the analog resistor is electrically connected to the mirror current source pin of the EFUSE and the first analog-to-digital sampling terminal of the microprocessor respectively, the second end of the analog resistor is grounded, the non-inverting input terminal of the differential amplifier module is electrically connected to the input terminal of the EFUSE, and the inverting input terminal of the differential amplifier module is electrically connected to the output terminal of the EFUSE. The first processing module includes a first acquisition submodule, a first processing submodule and a second acquisition submodule. The first acquisition submodule is used to obtain the current of the mirror current source pin of the EFUSE; the first processing submodule is used to determine that the analog current is the product of the current flowing through the analog resistor and a preset proportional coefficient, and the current flowing through the analog resistor is the ratio of the voltage at both ends of the analog resistor to the resistance value of the analog resistor; the second acquisition submodule is used to obtain the output voltage of the output terminal of the differential amplifier module, and use the output voltage as the analog voltage.

[0053] Through the IMON pin (also known as the current mirror pin), the EFUSE provides a current signal proportional to the actual current flowing through it. This proportionality factor (e.g., 10μA / A) is pre-set to ensure linearity and accuracy in current detection. After the analog current signal is converted to a voltage signal via an analog resistor, the MCU uses the ADC to measure this voltage, accurately reproducing the actual current magnitude. This approach avoids the complexity and inaccuracy of directly measuring large currents while leveraging the stability of small currents to improve overall current sensing accuracy. During the soft-start phase, both voltage and current are constantly changing. By continuously sampling the IMON current and the voltage across the EFUSE, the MCU can calculate the instantaneous power in real time. This enables the MCU to promptly detect power anomalies. For example, if the instantaneous power exceeds a predetermined threshold, it can take immediate action, such as shutting down the EFUSE or triggering a discharge, thereby protecting the circuit from damage caused by excessive power loss. The differential amplifier module amplifies the voltage difference across the EFUSE to a range more convenient for ADC measurement. This not only improves the sensitivity of voltage measurement but also ensures that the ADC can accurately read and convert voltage signals even under large voltage variations under varying operating conditions, thereby improving the adaptability and reliability of the entire detection system. The use of a mirrored current source and differential amplifier simplifies the circuit design for current and voltage detection. Compared to directly measuring current or using a high-precision voltmeter, this approach reduces the need for complex external sensors, lowers costs, and improves circuit stability.

[0054] In one embodiment of the present application, the second processing module includes a second processing sub-module and a third processing sub-module, the second processing sub-module is used to determine the total power of EFUSE as the product of a preset sampling interval, an analog voltage and an analog current; the third processing sub-module is used to determine the average power as the ratio of the total power to the duration of the soft start phase.

[0055] By summing the product of the analog voltage and current within each sampling interval, the total power experienced by the EFUSE during the soft-start phase can be accurately calculated. This method leverages the high precision of sampling technology and time discretization to ensure accurate and reliable power calculations and avoid uncertainty caused by instantaneous power fluctuations. The characteristics of the soft-start phase dictate that voltage, current, and power vary over time. Using pre-set sampling intervals, the microprocessor can track these parameter changes in real time and dynamically calculate the total power. This method enables timely detection of power anomalies, providing essential data support for implementing protective measures and ensuring the safe operation of the EFUSE and the entire circuit system. Calculating the average power as the ratio of total power to the duration of the soft-start phase provides a holistic view of power consumption during the soft-start phase. Average power is a key metric for assessing whether the EFUSE is operating within its safe operating area. It comprehensively considers the cumulative effect of power over time and the impact of duration, providing an objective basis for determining the EFUSE's operating status. Based on the calculated average power, designers can adjust circuit parameters such as input voltage and load matching to optimize EFUSE performance and ensure safe operation. Furthermore, by comparing average power with the SOA range, protection strategies can be intelligently adjusted. For example, when power approaches the SOA boundary, the discharge circuit can be triggered early to prevent EFUSE overload damage. Continuously monitoring average power and comparing it with the SOA range facilitates early detection of potential faults, such as overheating or overload. Upon detecting an anomaly, the microprocessor can immediately take action, such as disabling an enable signal or initiating a protection mechanism, effectively preventing more serious problems caused by EFUSE failures. Automating the calculation of average power and real-time comparison of SOA ranges reduces the need for human intervention and improves the efficiency of circuit testing and monitoring. The microprocessor's high-speed processing capabilities enable rapid response and intelligent circuit protection, which is particularly important in high-density circuit environments such as large-scale server boards.

[0056] In one embodiment of the present application, the EFUSE circuit also includes a pressure relief module, which includes a fifth resistor module, a sixth resistor module, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first end of the fifth resistor module is electrically connected to the GPIO interface of the microprocessor, the second end of the fifth resistor module is electrically connected to the base of the first transistor, the collector of the first transistor is electrically connected to the base of the second transistor, the emitter of the second transistor is electrically connected to the input end of the EFUSE, the collector of the second transistor is electrically connected to the first end of the sixth resistor module, and the second end of the sixth resistor module is electrically connected to the third transistor. The collector of the transistor, the base of the third transistor, and the base of the fourth transistor are electrically connected; the collector of the fourth transistor is electrically connected to the output end of the EFUSE; the emitters of the fourth transistor, the third transistor, and the first transistor are grounded, respectively. The apparatus further includes a fourth processing module configured to, in the process of obtaining average power based on a preset sampling interval, an analog voltage, an analog current, and a duration of the slow-start phase, control the EFUSE to stop operating if the instantaneous current or instantaneous power of the EFUSE during the slow-start phase exceeds a standard, and simultaneously control the pressure relief module to relieve pressure on the EFUSE.

[0057] The pressure relief module's real-time response mechanism rapidly identifies transient current or power anomalies caused by an EFUSE overload. Once an overload condition is detected, the microprocessor immediately shuts down the EFUSE and simultaneously activates the pressure relief module, rapidly reducing the voltage and stored energy across the EFUSE to prevent further damage. This rapid response mechanism is crucial for protecting sensitive circuits from overvoltage and overcurrent. By controlling the pressure relief module to relieve the EFUSE pressure, component damage and circuit failure caused by overload can be effectively avoided, significantly improving system safety and reliability. Even under extreme conditions, this mechanism ensures that the EFUSE does not exceed its safe operating range, providing an additional layer of protection. Combining the pressure relief module with the intelligent control of the microprocessor achieves intelligent circuit protection. The microprocessor not only monitors current and voltage but also automatically determines whether to trigger the pressure relief mechanism based on preset sampling intervals and safe operating ranges. This provides continuous protection from overload threats without manual intervention, enhancing automation and system stability. By effectively responding before or in the early stages of a fault, maintenance requirements and downtime caused by EFUSE overload can be significantly reduced. This is particularly important for devices that require continuous and stable operation, such as server boards. It ensures that the system quickly returns to normal in the event of an overload, avoiding prolonged system outages and data loss. The pressure relief module can quickly release stored energy in overload conditions, not only protecting the EFUSE but also preventing unnecessary energy waste. Through intelligent control, pressure relief is activated only when necessary, enabling more efficient energy utilization, reducing overall energy consumption, and improving energy efficiency. As an independent circuit module, the pressure relief module can be flexibly integrated into different circuit designs. This modular design allows for rapid adjustment and upgrade of protection mechanisms in different application scenarios without changing the entire circuit layout, improving design efficiency and adaptability.

[0058] The device further includes a generating module for generating abnormal prompt information when it is determined that the EFUSE is abnormal in the soft start phase, to prompt that the EFUSE is abnormal in the soft start phase.

[0059] Abnormal prompt information can immediately notify the system administrator or design engineer that the operating status of EFUSE is out of the normal range, which can trigger an immediate response, such as system shutdown, fault isolation or emergency maintenance, thereby preventing potential circuit damage from expanding and reducing data loss or system downtime. Abnormal prompts are not limited to simple warnings, but can also include detailed fault information, such as instantaneous power values, voltage and current peaks, duration, etc. This information helps to quickly locate the cause of the problem. Whether it is a circuit design defect, component aging or external environmental factors, in-depth analysis and rapid repair can be carried out based on the abnormal prompt information. Abnormal prompt information can be recorded in the system log to provide data support for subsequent fault analysis and prevention. By analyzing the log, the design team can identify common failure modes, optimize circuit design, and enhance the robustness and reliability of the system.

[0060] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps of any of the above-mentioned embodiments of the method for detecting a safe working area of EFUSE in a soft startup phase.

[0061] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned embodiments of the method for detecting a safe working area of EFUSE in a soft start phase when running.

[0062] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0063] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned methods for detecting a safe working area of EFUSE in a soft start phase are implemented.

[0064] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps of any of the above-mentioned EFUSE safe working area detection method embodiments in the soft startup phase.

[0065] The present application also provides an electronic resistance wire circuit, such as Figure 3As shown, it includes: an electronic resistance wire EFUSE100; a differential amplifier module 200, wherein the non-inverting input terminal of the differential amplifier module 200 is electrically connected to the input terminal VIN of the EFUSE100, and the inverting input terminal of the differential amplifier module 200 is electrically connected to the output terminal VOUT of the EFUSE100, and the differential amplifier module 200 is used to amplify the voltage difference between the two ends of the EFUSE100 and output it; an analog resistor 300; and a microprocessor 400, wherein the first analog-to-digital sampling terminal of the microprocessor 400 is electrically connected to the first end of the analog resistor 300 and the mirror current source pin of the electronic resistance wire EFUSE100 respectively, the second end of the analog resistor 300 is grounded, and the second analog-to-digital sampling terminal of the microprocessor 400 is electrically connected to the output terminal of the differential amplifier module 200, and the microprocessor 400 is used to execute any one of the safe working area detection methods of the EFUSE100 in the soft start phase.

[0066] Compared with the existing solution, only analog-to-digital sampling technology is introduced to simulate the voltage at both ends of the electronic resistance wire EFUSE and the current flowing through the EFUSE, thereby reducing the circuit complexity. In addition, the voltage at both ends of the electronic resistance wire EFUSE and the current flowing through the EFUSE are simulated. Finally, when the average power is not within the safe working area, it is determined that the EFUSE is abnormal in the slow start phase. Therefore, the present application can complete SOA detection and reduce circuit complexity, thereby not generating additional timing risks, thereby solving the problem that the safe working area detection method of the existing solution needs to introduce multiple additional hardware modules, which increases the complexity of the detection circuit and may generate additional timing risk problems.

[0067] In one embodiment of the present application, Figure 4 As shown, the differential amplifier module 200 includes a differential amplifier opa1, a first resistor module R1, a second resistor module R2, a third resistor module R3 and a fourth resistor module R4, the first end of the second resistor module R2 is electrically connected to the input end of EFUSE100, the first end of the first resistor module R1 is electrically connected to the output end of EFUSE100, the second end of the second resistor module R2 is electrically connected to the non-inverting input end of the differential amplifier opa1 and the first end of the fourth resistor module R4, the second end of the first resistor module R1 is electrically connected to the inverting input end of the differential amplifier opa1 and the first end of the third resistor module R3, the second end of the fourth resistor module R4 is grounded, and the output end of the differential amplifier opa1 is electrically connected to the second end of the third resistor module R3 and the second analog-to-digital sampling end of the microprocessor 400.

[0068] Each resistor module can include multiple resistors connected in series or parallel. opa1 forms a differential amplifier circuit with resistor modules R1, R2, R3, and R4. Typically, R1 = R2 and R3 = R4. The differential amplifier amplifies the voltage difference across the EFUSE and outputs it. The output signal, V_EFUSE, is connected to the MCU's ADC2 input channel for analog-to-digital sampling. The sampling result reflects the voltage difference across the EFUSE.

[0069] The differential amplifier OPA1 accurately amplifies the voltage difference across the EFUSE, namely the difference between V_IN and V_OUT. Carefully selected resistors (R1, R2, R3, and R4) ensure stable signal amplification, thereby improving voltage measurement accuracy. This is crucial for detecting the SOA of the EFUSE during its soft startup phase. The differential amplifier OPA1 has an excellent common-mode rejection ratio (CMRR), effectively filtering out common-mode noise at the input, such as power supply fluctuations or electromagnetic interference, and amplifying only the differential-mode signal—the actual voltage difference. This design ensures accurate voltage measurement across the EFUSE even in harsh electromagnetic environments, improving system robustness and reliability. The balanced resistor network formed by R1, R2, R3, and R4 ensures signal linearity and stability. This means the amplified voltage signal maintains a good linear relationship with the original voltage difference, without distortion. This is crucial for calculating power and determining SOA based on voltage and current. The second end of the third resistor module R3 is directly connected to the second analog-to-digital sampling terminal of the microprocessor 400, simplifying the interface design between the microprocessor and the differential amplifier module. The microprocessor can directly read the amplified voltage signal for subsequent A / D conversion and data analysis without the need for additional signal conditioning circuitry, saving cost and circuit space. The differential amplifier, combined with a specific resistor configuration, can extend the signal's dynamic range. This means that even if the voltage difference across the EFUSE varies significantly, the differential amplifier module can still provide a reliable signal output, allowing the microprocessor to accurately capture subtle voltage changes. This is crucial for monitoring voltage fluctuations during the soft start process.

[0070] In one embodiment of the present application, Figure 5As shown, the electronic resistance wire circuit also includes: a pressure relief module 500, which includes: a fifth resistor module R5, a sixth resistor module R6, a first transistor Q1, a second transistor Q2, a third transistor Q2 and a fourth transistor Q4, a first end of the fifth resistor module R5 is electrically connected to the serial interface of the microprocessor 400, a second end of the fifth resistor module R5 is electrically connected to the base of the first transistor Q1, a collector of the first transistor Q1 is electrically connected to the base of the second transistor Q2, and a collector of the second transistor Q2 is electrically connected. The emitter is electrically connected to the input terminal VIN of EFUSE100, the collector of the second triode Q2 is electrically connected to the first end of the sixth resistor module R6, the second end of the sixth resistor module R6 is electrically connected to the collector of the third triode Q2, the base of the third triode Q2 and the base of the fourth triode Q4 respectively, the collector of the fourth triode Q4 is electrically connected to the output terminal VOUT of EFUSE100, and the emitter of the fourth triode Q4, the emitter of the third triode Q2 and the emitter of the first triode Q1 are grounded respectively.

[0071] During the EFUSE soft-start phase, the MCU detects an instantaneous current or power exceeding the specified limit and immediately pulls the EN signal low, disabling EFUSE operation. Simultaneously, it sends a high discharge signal, turning on NPN transistor Q1. This turns the base of PNP transistor Q2 low, turning it on and applying voltage VIN to resistor R2. NPN transistors Q3 and Q4 form a mirror current source. Because their bases are connected together and their emitters are grounded, their Vbe (the voltage difference between the transistor's base and collector) is equal, resulting in equal base currents. Q3 and Q4 are designed with identical model parameters, ensuring equal current amplification. Therefore, the same current flows through Q3's collector as through Q4's collector. Since the voltage between Q3's collector and emitter is approximately zero, the voltage across R2 can be assumed to be equal to VIN, resulting in a current equal to VIN / R2. This causes VOUT to discharge at a current equal to VIN / R2. Compared with the pure resistance discharge method, this method has a constant discharge current, which can ensure that the voltage is reduced to 0. The pure resistance discharge method has a large initial discharge current when the VOUT voltage is high, and the discharge current decreases as the voltage drops, making it difficult to reduce the VOUT voltage to 0 in a short time.

[0072] The pressure relief module responds quickly when the EFUSE enters an abnormal state. Through a carefully designed series of transistors and resistor networks, it effectively dissipates the energy stored in the EFUSE. This mechanism prevents excess energy from accumulating in the EFUSE, preventing damage to the device and even the entire circuit due to overvoltage and overheating. When the EFUSE experiences an abnormal operation, the microprocessor 400 automatically triggers the pressure relief module without manual intervention. This automated process not only improves response speed but also reduces maintenance time and costs, ensuring the system's self-protection in the event of a problem and minimizing the risk of equipment downtime. By establishing a pressure relief path between the EFUSE input (VIN) and output (VOUT), the pressure relief module prevents abnormal voltage and current from affecting downstream circuits. This design is particularly important for protecting sensitive components from overvoltage shocks, maintaining the stability and safety of the entire circuit. As a standalone circuit module, the pressure relief module can be easily integrated or replaced with existing circuit designs. This modular approach allows designers to adjust the pressure relief module's parameters, such as resistor values and transistor types, to optimize performance based on specific application requirements, improving design efficiency and circuit adaptability.

[0073] In one embodiment of the present application, Figure 4 As shown, the electronic resistance wire circuit further includes a timer 600 , which is electrically connected to the microprocessor 400 . The timer 600 is used to record the duration of the EFUSE 100 in the soft start phase.

[0074] Timer 600 is used to count the duration of the soft start phase. When the MCU sends a high level EN to EFUSE, the timer is started. When the MCU detects that the PG signal sent by EFUSE becomes high, the timer is turned off and the count value of the timer is read at the same time. The count value is the duration of the soft start phase.

[0075] Timer 600 accurately records the duration of the EFUSE entering the slow-start phase and ultimately stabilizing its output. This precise time measurement is crucial for evaluating the EFUSE's performance, helping to determine whether it operates according to the expected timing and ensuring the safety and effectiveness of the slow-start process. The duration of the slow-start phase is a key parameter for calculating average power. Using the time recorded by timer 600, microprocessor 400 can calculate the average power throughout the slow-start phase and determine whether the EFUSE is operating within its safe operating area (SOA), effectively preventing overload and thermal damage. The slow-start phase duration data recorded by timer 600 can be used by microprocessor 400 to dynamically adjust circuit parameters such as input voltage, load matching, or the triggering conditions of the discharge mechanism. This adjustment based on real-time data optimizes the operating efficiency of the EFUSE and the entire circuit while ensuring its long-term stability and reliability.

[0076] The MCU sends the EN enable signal to control the EFUSE on and off. When the EN signal is low, the EFUSE is off. When the EN signal is high, the EFUSE first enters the slow-start phase. During this phase, the EFUSE controls the conduction speed to prevent the output voltage from rising too quickly and causing excessive inrush current. After the slow-start phase, the output voltage VOUT is very close to the input voltage VIN. At this time, the EFUSE sets the PG signal high, indicating that the output voltage is normal.

[0077] The present application also provides a server card, comprising: any electronic resistance wire circuit. Compared to existing solutions, this system only introduces analog-to-digital sampling technology to simulate the voltage across the electronic resistance wire (EFUSE) and the current flowing through the EFUSE, thereby reducing circuit complexity. Furthermore, the voltage across the electronic resistance wire (EFUSE) and the current flowing through the EFUSE are simulated, and finally, when the average power is not within the safe operating area, the system determines that the EFUSE is abnormal during the slow startup phase. This allows the present application to perform SOA detection while reducing circuit complexity, thereby avoiding additional timing risks. This resolves the problem that the safe operating area detection method of existing solutions requires the introduction of multiple additional hardware modules, which increases the complexity of the detection circuit and may generate additional timing risks.

[0078] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0079] It should be noted that the above electrical connection can be a direct electrical connection or an indirect electrical connection. Direct electrical connection means that two devices are directly connected, and indirect electrical connection means that other devices such as capacitors and resistors are connected between the connected A and B.

[0080] The above describes in detail the EFUSE safe working area detection method, EFUSE circuit, and server board provided by this application during the soft startup phase. This document uses specific examples to illustrate the principles and implementation methods of this application. The above examples are intended only to facilitate understanding of the method and core concepts of this application. It should be noted that those skilled in the art may make various improvements and modifications to this application without departing from the principles of this application, and such improvements and modifications fall within the scope of protection of the claims of this application.

Claims

1. A method for detecting the safe working area of an electronic resistance wire during a slow start phase, characterized in that: The safe operating area detection method is applied to an electronic resistance wire circuit, wherein the electronic resistance wire circuit includes a microprocessor and an electronic resistance wire electrically connected, including: When the enable pin of the microprocessor is enabled, analog-to-digital sampling technology is used to simulate the voltage across the two ends of the electronic resistance wire and the current flowing through the electronic resistance wire to obtain analog voltage and analog current respectively; Obtaining average power according to a preset sampling interval, the analog voltage, the analog current, and a duration of a soft start phase, wherein the preset sampling interval is a preset value of a sampling interval of the analog-to-digital sampling technology; When the average power is within the safe working area, it is determined that the electronic resistance wire is normal in the slow start phase; when the average power is not within the safe working area, it is determined that the electronic resistance wire is abnormal in the slow start phase.

2. The method for detecting the safe working area of an electronic resistance wire in a slow start phase according to claim 1, characterized in that: The electronic resistance wire circuit also includes an analog resistor and a differential amplifier module. The first end of the analog resistor is electrically connected to the mirror current source pin of the electronic resistance wire and the first analog-to-digital sampling terminal of the microprocessor respectively, the second end of the analog resistor is grounded, the non-inverting input end of the differential amplifier module is electrically connected to the input end of the electronic resistance wire, and the inverting input end of the differential amplifier module is electrically connected to the output end of the electronic resistance wire. The analog-to-digital sampling technology is used to simulate the voltage at both ends of the electronic resistance wire and the current flowing through the electronic resistance wire to obtain the analog voltage and the analog current respectively, including: Obtaining the current of the mirror current source pin of the electronic resistance wire; Determine the analog current as the product of the current flowing through the analog resistor and a preset proportional coefficient, where the current flowing through the analog resistor is the ratio of the voltage across the analog resistor to the resistance value of the analog resistor; An output voltage of an output terminal of the differential amplifier module is obtained, and the output voltage is used as the analog voltage.

3. The method for detecting the safe working area of an electronic resistance wire in a slow start phase according to claim 1, characterized in that: Obtaining average power according to a preset sampling interval, the simulated voltage, the simulated current, and the duration of the soft start phase, including: Determine the total power of the electronic resistance wire as the product of the preset sampling interval, the analog voltage and the analog current; The average power is determined as a ratio of the total power to the duration of the soft start phase.

4. The method for detecting the safe working area of an electronic resistance wire in a slow start phase according to claim 1, characterized in that: The electronic resistance wire circuit also includes a pressure relief module, which includes a fifth resistor module, a sixth resistor module, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first end of the fifth resistor module is electrically connected to the GPIO interface of the microprocessor, the second end of the fifth resistor module is electrically connected to the base of the first transistor, the collector of the first transistor is electrically connected to the base of the second transistor, the emitter of the second transistor is electrically connected to the input end of the electronic resistance wire, the collector of the second transistor is electrically connected to the first end of the sixth resistor module, the second end of the sixth resistor module is electrically connected to the collector of the third transistor, the base of the third transistor, and the base of the fourth transistor, respectively, the collector of the fourth transistor is electrically connected to the output end of the electronic resistance wire, and the emitter of the fourth transistor, the emitter of the third transistor, and the emitter of the first transistor are grounded respectively. In the process of obtaining the average power according to the preset sampling interval, the analog voltage, the analog current, and the duration of the soft start phase, The method further comprises: When the instantaneous current or instantaneous power of the electronic resistance wire exceeds the standard during the slow start phase, the electronic resistance wire is controlled to stop working, and the pressure relief module is controlled to relieve the pressure of the electronic resistance wire.

5. The method for detecting the safe working area of an electronic resistance wire in a slow start phase according to claim 1, characterized in that: When it is determined that the electronic resistance wire is abnormal in the slow start phase, the method further includes: An abnormal prompt message is generated to prompt that the electronic resistance wire is abnormal during the slow start phase.

6. An electronic resistance wire circuit, characterized in that: include: Electronic resistance wire; A differential amplifier module, wherein the non-inverting input terminal of the differential amplifier module is electrically connected to the input terminal of the electronic resistance wire, the inverting input terminal of the differential amplifier module is electrically connected to the output terminal of the electronic resistance wire, and the differential amplifier module is used to amplify the voltage difference between the two ends of the electronic resistance wire and output it; Simulated resistor; A microprocessor, wherein the first analog-to-digital sampling terminal of the microprocessor is electrically connected to the first end of the analog resistor and the mirror current source pin of the electronic resistance wire respectively, the second end of the analog resistor is grounded, and the second analog-to-digital sampling terminal of the microprocessor is electrically connected to the output end of the differential amplifier module, and the microprocessor is used to execute the safe working area detection method of the electronic resistance wire in the slow start phase according to any one of claims 1 to 5.

7. The electronic resistance wire circuit according to claim 6, characterized in that: The differential amplifier module includes a differential amplifier, a first resistor module, a second resistor module, a third resistor module and a fourth resistor module. The first end of the second resistor module is electrically connected to the input end of the electronic resistance wire, the first end of the first resistor module is electrically connected to the output end of the electronic resistance wire, the second end of the second resistor module is electrically connected to the non-inverting input end of the differential amplifier and the first end of the fourth resistor module, the second end of the first resistor module is electrically connected to the inverting input end of the differential amplifier and the first end of the third resistor module, the second end of the fourth resistor module is grounded, and the output end of the differential amplifier is electrically connected to the second end of the third resistor module and the second analog-to-digital sampling end of the microprocessor.

8. The electronic resistance wire circuit according to claim 6, characterized in that: The electronic resistance wire circuit also includes: a pressure relief module, which includes: a fifth resistance module, a sixth resistance module, a first triode, a second triode, a third triode and a fourth triode, the first end of the fifth resistance module is electrically connected to the serial interface of the microprocessor, the second end of the fifth resistance module is electrically connected to the base of the first triode, the collector of the first triode is electrically connected to the base of the second triode, the emitter of the second triode is electrically connected to the input end of the electronic resistance wire, the collector of the second triode is electrically connected to the first end of the sixth resistance module, the second end of the sixth resistance module is respectively electrically connected to the collector of the third triode, the base of the third triode and the base of the fourth triode, the collector of the fourth triode is electrically connected to the output end of the electronic resistance wire, and the emitter of the fourth triode, the emitter of the third triode and the emitter of the first triode are respectively grounded.

9. The electronic resistance wire circuit according to any one of claims 6 to 8, characterized in that: The electronic resistance wire circuit further includes a timer, which is electrically connected to the microprocessor and is used to record the duration of the electronic resistance wire in the slow start phase.

10. A server board, characterized in that: include: The electronic resistance wire circuit according to any one of claims 6 to 9.

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