Server board plug-in and pull-out times recording device and server

Abstract

The present application provides a device for recording the number of plug-in and unplugging times of a server board and a server, wherein the device includes a backplane and a mainboard, a first connector of the mainboard is used to connect to a second connector of the backplane, and the mainboard includes a processor and a memory; a first pin and a second pin of the first connector are respectively connected to a first energy storage device and a power path control device, and two pins on the second connector corresponding to the first pin and the second pin of the first connector are short-circuited; a first power terminal of the mainboard is connected to an external power supply, the first power terminal is connected to the power path control device through a step-down circuit, the power path control device is connected to a power supply pin of the processor, and the output voltage of the step-down circuit is greater than the voltage of the first energy storage device; the processor is configured to: in response to receiving a physical contact signal of the first connector, update the number of plug-in and unplugging times recorded in the memory to the number of plug-in and unplugging times plus one during the initialization process; this solution can effectively improve the accuracy of recording the number of board and card unplugging times.

Description

Technical Field

[0001] The present application relates to the technical field of server boards, and in particular to a device for recording the number of times a server board is plugged in and out, and a server. Background Art

[0002] In modern data centers, cloud computing infrastructure, storage facilities, and enterprise-level server clusters, hardware boards (such as PCIe expansion cards, storage controllers, backplanes, and power boards) often require frequent plugging and unplugging due to their modular design to accommodate hardware upgrades, fault replacements, and maintenance needs. However, board connectors (also known as terminals), especially high-density connectors, have a limited physical lifespan. Frequent plugging and unplugging can lead to impedance anomalies and reduced reliability due to terminal wear. Therefore, it is necessary to record the number of plug-in and unplug cycles to ensure timely replacement before any board failures occur.

[0003] In the related art, the main methods of recording the number of plug-in and unplugging times of server boards include manually recording the number of plug-in and unplugging times and writing the number of power-on times of the board into the memory as the number of plug-in and unplugging times. The method of manually registering maintenance logs by operation and maintenance personnel has problems such as easy omissions or errors, increased workload, and failure to ensure standardized records of operation and maintenance personnel; the solution of writing the number of power-on times into a non-volatile storage chip to assist in determining the number of plug-in and unplugging times of the board has the problem of inaccurate counting. Summary of the Invention

[0004] The present application provides a server board plug-in and pull-out number recording device and a server, which can improve the accuracy of recording the board card plug-in and pull-out number.

[0005] In order to solve the above technical problems, the present disclosure provides a server board plug-in and pull-out count recording device, the device comprising a backplane and a mainboard, a first connector of the mainboard being connected to a second connector of the backplane, and the mainboard comprising a processor and a memory; a first pin and a second pin of the first connector being connected to a first energy storage device and a power path control device, respectively, and two pins of the second connector corresponding to the first pin and the second pin of the first connector being short-circuited; a first power terminal of the mainboard being connected to an external power supply via a second power terminal of the backplane, the first power terminal being connected to the power path control device via a step-down circuit, the power path control device being connected to a power supply pin of the processor, the output voltage of the step-down circuit being greater than the voltage of the first energy storage device; and the processor being configured to:

[0006] In response to receiving a physical contact signal from the first connector, the plug-in and unplug-count recorded in the memory is updated to the plug-in and unplug-count plus one during the initialization process.

[0007] An embodiment of the present disclosure further provides a server, which includes any server board plug-in and pull-out times recording device provided by an embodiment of the present disclosure.

[0008] The present disclosure provides a server board plug-in and pull-out count recording device, which is connected to a first energy storage device through a first pin, and a second pin is connected to the first pin by short-circuiting two corresponding pins on a backplane, so as to provide a processor with another power supply in addition to the external power supply, and the power supply of the first energy storage device and the external power supply are combined into a power supply circuit through a power path control device, so as to realize switching between the first energy storage device and the external power supply, so that when there is no external power supply (such as power-off maintenance of the server, accidental plug-in and pull-out during transportation), the board plug-in and pull-out count can be effectively recorded normally when the whole machine is not powered on, thus realizing passive plug-in and pull-out counting; this solution uses the physical contact signal (power-on) of the connector to trigger the counting of the plug-in and pull-out counts during the initialization process, which can ensure real-time response of the plug-in and pull-out action, and after the plug-in and pull-out, the processor gives priority to reading the current plug-in and pull-out count value from the memory and performing atomic update (i.e., a single operation is completed) The process of "read-update-write" is realized to achieve single-cycle writing and avoid data inconsistency caused by power failure. Therefore, this solution can accurately record the number of board plug-ins and unplugs in any scenario (such as hot plug-in and non-power plug-in), avoid omissions and errors, and improve the accuracy of recording the number of board plug-ins, so as to accurately predict and report risks in a timely manner, and eliminate a series of problems caused by excessive board plug-in and unplugging. Furthermore, this solution uses a diode controller or an ideal diode controller to realize the automatic switching and isolation of the two power supplies of the external power supply and the first energy storage device, realizing seamless power switching, avoiding voltage backflow and transient conflicts, ensuring the stability of the counting process, and achieving ultra-high reliability of the device. In addition, this solution only needs to add two power supply pins to the connector, without the need to modify the main structure of the server backplane, adapting to the existing hardware ecosystem, and achieving compatibility and low cost.

[0009] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0011] Figure 1 A schematic structural diagram of a server board plug-in and pull-out times recording device provided by an embodiment of the present disclosure;

[0012] Figure 2 A schematic diagram of the working process of a device for recording the number of server card insertions and removals provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0014] Explanation of terms:

[0015] CPLD: Utilizes programming technologies such as CMOS, EPROM, EEPROM, flash memory, and SRAM to create a high-density, high-speed, and low-power programmable logic device. CMOS stands for Complementary Metal Oxide Semiconductor. EPROM stands for Erasable Programmable Read-Only Memory, a type of ROM. EEPROM (Electrically Erasable Programmable Read-Only Memory) is an electrically erasable programmable read-only memory and a non-volatile memory.

[0016] FPGA (Field Programmable Gate Array) field programmable gate array;

[0017] MCU is the abbreviation of Microcontroller Unit;

[0018] BMC, Baseboard Management Controller, baseboard management controller;

[0019] FLASH memory is a type of memory device and is a non-volatile memory.

[0020] Frequent plugging and unplugging of connectors can lead to problems such as terminal wear, impedance anomalies, reduced reliability, and high maintenance costs. Terminal wear means oxidation of the metal contacts and loss of elasticity, resulting in poor contact or signal loss. Impedance anomalies mean that after the designed plug-in and unplug times are exceeded, the impedance of the high-speed link becomes abnormal, bit errors increase, and ultimately lead to communication errors. Reliability decreases mean that after the designed plug-in and unplug times are exceeded, the board failure rate increases significantly, which may cause system downtime or data errors. High maintenance costs mean that in the absence of life warnings, the operation and maintenance team finds it difficult to replace boards in a timely manner, resulting in passive repairs and business interruptions. Analysis found that the number of plug-in and unplug times is recorded by manual registration of maintenance logs by operation and maintenance personnel. Manual registration of maintenance logs by operation and maintenance personnel is prone to omissions or errors; it increases workload and cannot force all operation and maintenance personnel and testers to record; and only inferring the degree of wear through physical inspection after a failure occurs cannot prevent risks. The BMC / CPLD or MCU in the related art writes the power-on count into a non-volatile chip (EEPROM / FLASH) to assist in determining the number of board plug-in and pull-out times. This solution not only relies on external power supply but also has large errors and cannot accurately record the actual number of board plug-in and pull-out times. The reasons are: if the controller is powered on without being plugged in or out during the power-on process, the BMC will incorrectly record a plug-in and pull-out count; if the in-place signal change is recorded, when the controller is inserted or unplugged, the in-place signal changes. At this time, the BMC / CPLD or MCU is not powered on or has been powered off, and thus cannot be recorded. The fatal disadvantage of this solution is that if the board is plugged in or out when the entire machine is not powered on, it cannot be effectively recorded, resulting in inaccurate counting.

[0021] The following describes a server board plug-in and pull-out times recording device and a server according to an embodiment of the present disclosure with reference to the accompanying drawings.

[0022] Figure 1 FIG. 1 is a structural diagram of a device for recording the number of server card insertions and removals according to an embodiment of the present disclosure. Figure 1 As shown, the server board plug-in and pull-out number recording device includes a backplane and a mainboard, the first connector of the mainboard is used to connect to the second connector of the backplane, and the mainboard includes a processor and a memory; the first pin and the second pin of the first connector are respectively connected to the first energy storage device and the power path control device, and the two pins of the second connector corresponding to the first pin and the second pin of the first connector are short-circuited; the first power terminal of the mainboard is connected to the external power supply through the second power terminal of the backplane, the first power terminal is connected to the power path control device through a step-down circuit, the power path control device is connected to the power supply pin of the processor, and the output voltage of the step-down circuit is greater than the voltage of the first energy storage device; the processor is configured to: in response to receiving a physical contact signal of the first connector, update the plug-in and pull-out number recorded in the memory to the plug-in and pull-out number plus one during the initialization process.

[0023] In some embodiments, the processor is configured to: in response to receiving a physical contact signal from the first connector, during an initialization process, turn on power to the memory, read the plug-in count in the memory, increment the plug-in count by one, and rewrite the count into the memory.

[0024] In some embodiments, the power path control device includes a diode controller or an ideal diode controller, such as the LTC4412 power path controller; the first connector may be a high-density connector, the first energy storage device may be a button battery, the physical contact signal of the first connector refers to a transient conduction signal generated during the insertion and removal of the first connector, and the processor may be a device such as an MCU and a CPLD. As an example, the main power supply of the motherboard, i.e., the external power supply, has a voltage of 12V, the button battery has a voltage of 3V, and the output voltage of the step-down circuit is 3.3V, i.e., the output voltage of the step-down circuit is greater than the voltage of the button battery; thus, when the external 12V power supply is active, the button battery has no output, thereby conserving as much power as possible from the button battery.

[0025] Based on the above structure, Figure 1 , using two pins of the backplane connector, the backplane is directly short-circuited, the first pin in the motherboard connector is connected to the button battery, and the second pin is connected to the power pin of the processor through the power path control device; the power path control device combines the power supply of the button battery and the external power supply to form a power circuit, and powers the connected processor through the power circuit; when the external power supply is valid, the external power supply is used to supply power and block the discharge of the first energy storage device; when the external power supply fails, it automatically switches to the first energy storage device for power supply.

[0026] The server board plug-in and pull-out count recording device of the disclosed embodiment is connected to the first energy storage device through the first pin, and the second pin is connected to the first pin by short-circuiting the two corresponding pins on the backplane, so as to provide the processor with another power supply in addition to the external power supply. The power supply of the first energy storage device and the external power supply are combined into a power supply circuit through the power path control device, so as to realize the switching between the first energy storage device and the external power supply, so that when there is no external power supply (such as power-off maintenance of the server, accidental plug-in and pull-out during transportation), the board plug-in and pull-out count can be effectively recorded normally when the whole machine is not powered on, thus realizing passive plug-in and pull-out counting; this solution uses the physical contact signal (power-on) of the connector to trigger the counting of the plug-in and pull-out counts during the initialization process, which can ensure real-time response of the plug-in and pull-out action. After the plug-in and pull-out, the processor gives priority to reading the current plug-in and pull-out count value from the memory and performing atomic update (i.e., a single operation is completed) The process of "read-update-write" is realized to achieve single-cycle writing and avoid data inconsistency caused by power failure. Therefore, this solution can accurately record the number of board plug-ins and unplugs in any scenario (such as hot plug-in and non-power plug-in), avoid omissions and errors, and improve the accuracy of recording the number of board plug-ins, so as to accurately predict and report risks in a timely manner, and eliminate a series of problems caused by excessive board plug-in and unplugging. Furthermore, this solution uses a diode controller or an ideal diode controller to realize the automatic switching and isolation of the two power supplies of the external power supply and the first energy storage device, realizing seamless power switching, avoiding voltage backflow and transient conflicts, ensuring the stability of the counting process, and achieving ultra-high reliability of the device. In addition, this solution only needs to add two power supply pins to the connector, without the need to modify the main structure of the server backplane, adapting to the existing hardware ecosystem, and achieving compatibility and low cost.

[0027] Based on any of the above embodiments, Figure 1 As shown, the first data acquisition pin of the processor is connected to the output end of the step-down circuit, and the processor is configured to: after adding one to the number of plug-in and unplugging times and rewriting it into the memory, read the output voltage of the step-down circuit through the first data acquisition pin; determine whether the output voltage of the step-down circuit is abnormal; when the output voltage of the step-down circuit is abnormal, turn off the power supply of the memory and enter the first working mode. In some embodiments, the first working mode of the processor is the sleep mode, and the second working mode is the normal power supply mode. That is, after recording the number of plug-in and unplugging times, the device also implements voltage monitoring logic: detects the status of the external power supply in real time through the ADC pin and dynamically adjusts the operating mode of the processor; that is, when the output voltage of the step-down circuit collected through the ADC pin is abnormal, the processor enters a low-power mode, such as the sleep mode.

[0028] As an implementation, the processor is configured to shut down the memory power supply and switch the main frequency to the first operating mode when the output voltage of the step-down circuit is abnormal. In other words, the processor switches its main frequency based on the state of the external power supply, such as running at full speed when powered by an external power supply and reducing it to 32kHz when powered by a coin cell battery, thus achieving dynamic power management and low-power design. In one example, the processor current in sleep mode is less than 2µA. Powered by a coin cell battery, it can support tens of thousands of plug-in and unplug cycles (a coin cell battery has a lifespan of more than 10 years in typical scenarios). For example, using a CR2032 coin cell battery with a capacity of 220mAh, the processor can be used in sleep mode for 12.5 years.

[0029] Based on the above structure, after recording the number of plug-in and unplugging times, this solution obtains the power supply status of the external power supply by collecting and judging whether the output voltage of the step-down circuit is normal. When it is judged that the external power supply is not supplying power, the power supply of the memory is turned off and the device enters the low-power mode. That is, when the external power supply is valid, the external power supply is used to supply power and the discharge of the first energy storage device is blocked; when the external power supply fails, the device automatically switches to the first energy storage device for power supply and triggers the processor to enter the low-power mode, thereby realizing dynamic power management and low-power design, and achieving ultra-long life and low maintenance cost; the device can support the low-power mode of the microcontroller.

[0030] The memory of this device can be a built-in memory or an external memory, such as a built-in EEPROM or an external EEPROM, FRAM or other non-volatile memory. If the memory of this device is an external memory, then Figure 1 In the dashed portion shown, the mainboard also includes a first MOS element, a gate of the first MOS element being connected to a first control signal pin of the processor, and a first pole and a second pole of the first MOS element being connected to a power pin of the processor and a power pin of an external memory, respectively. The processor is configured to: in response to receiving a physical contact signal from the first connector, turn on power to the memory via the first MOS element during an initialization process, read the number of plug-in / plug-out times in the memory, increment the number by one, and rewrite the number to the memory; and when the output voltage of the step-down circuit is abnormal, turn off power to the memory via the first MOS element and enter a sleep mode.

[0031] That is to say, if this device uses an external memory, the power supply of the memory is controlled by MOS. When the power supply of the external power supply is normal, the processor controls the MOS to turn on through the IO pin, and the memory works normally; when the external power supply is abnormal, when a button battery is used for power supply, in order to minimize the consumption of the button battery, the processor controls the MOS to turn off through the IO pin, that is, to turn off the power supply of the memory.

[0032] If the device's memory is built-in, Figure 1The dashed portion in the figure is deleted, and the processor is configured to: in response to receiving a physical contact signal from the first connector, turn on power to the memory during initialization, read the plug-in / plug-out count from the memory, increment the plug-in / plug-out count by one, and then rewrite the count to the memory. In other words, if the device uses built-in memory, the processor directly controls the turning on and off of power to the memory.

[0033] Based on the above structure, the device of this embodiment can turn on the power of the memory before recording the number of plugging and unplugging, and turn off the power of the memory after recording the number of plugging and unplugging when the external power supply is abnormal, so as to achieve low power consumption.

[0034] In some embodiments, the processor's first interrupt pin is connected to the output of the step-down circuit. The processor is configured to: wake up when the first interrupt pin receives a high level and read the output voltage of the step-down circuit via the first data acquisition pin; determine whether the output voltage of the step-down circuit is abnormal; and enter the second operating mode when the output voltage of the step-down circuit is normal. In one implementation, the first data acquisition pin and the first interrupt pin are the same pin. That is, the processor uses its own ADC pin to simultaneously collect the output voltage of the step-down circuit for the interrupt pin, which is used to determine whether to enter low-power mode and to implement interrupt wake-up when the external power supply is normal, thus saving processor pins and achieving reasonable performance.

[0035] Based on the above structure, the device can wake up the processor in time when receiving a high level through the interrupt pin, so that the processor switches to the normal working mode and realizes the normal operation of the device.

[0036] In order to clearly illustrate the above embodiment, a specific example is now used for illustration. The following example takes the memory as an external memory as an example to illustrate the workflow of the server board plug-in and plug-out times recording device of this embodiment. Figure 2As shown in the figure, when the backplane 12V is present, after the motherboard is plugged into the backplane, 12V is connected to the motherboard through the power connector (i.e., the power terminals). The step-down circuit outputs 3.3V to power the processor. At this time, because the button battery voltage is lower than the step-down circuit output voltage, the button battery does not discharge. After the processor is powered on, the program begins running. After the peripherals are initialized, the MOS controller turns on the memory power supply. The plug-in and unplug count recorded in the memory is read, incremented by 1, and written to the memory. Afterwards, the output voltage of the step-down circuit is sampled via the ADC pins and is normal. The processor program runs normally and waits for a read instruction from the CPU or BMC. When the backplane 12V is absent (i.e., the motherboard is plugged in and unplugged without external power), after the motherboard is plugged into the backplane, the button battery powers the processor through the two pins of the connector. After the processor is powered on, the program begins running. After the peripherals are initialized, the MOS controller turns on the memory power supply. The plug-in and unplug count recorded in the memory is read, incremented by 1, and written to the memory. Afterwards, the ADC detects the step-down circuit output voltage and finds it abnormal. The processor enters low-power mode, with a current of less than 2µA, and waits for an external interrupt to wake it up. When the processor is in low-power mode and the backplane is connected to an external power supply, the 12V input outputs a 3.3V voltage through the step-down circuit. The processor is awakened after receiving a high level on its interrupt pin. After waking up, the processor collects the output voltage of the step-down circuit through the ADC and finds that it is normal. The processor program runs normally and waits for the read instruction from the CPU or BMC.

[0037] It should be noted that this solution is also applicable to the life management of other modular hardware, such as pluggable SSDs and hot-swappable fans, as well as the reliability monitoring of industrial equipment such as PLC modules and robot joint plug-in interfaces.

[0038] Embodiments of the present application also provide a server comprising any of the aforementioned server board plug-in / plug-out count recording devices. In some embodiments, the server comprises a central controller, communicatively coupled to a processor, such as a baseboard management system (BMC) or a CPU. The central controller is configured with a server board life management system, which is configured to: visualize the number of plug-in / plug-out counts in response to a request to query the motherboard's plug-in / plug-out counts; and issue an alarm when the number of plug-in / plug-out counts exceeds a threshold.

[0039] Based on the above structure, the server of this embodiment integrates the server board card plug-in and unplugging times recording device of the above embodiment. The device communicates with the BMC / CPU, and can realize remote query and threshold alarm of the plug-in and unplugging times, as well as visual display of the board card health status, so as to obtain accurate card plug-in and unplugging times, and conduct real-time monitoring and alarm of the card plug-in and unplugging times, so as to accurately predict and report risks in a timely manner, and eliminate a series of problems caused by excessive board card plug-in and unplugging times.

[0040] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0041] The above is a detailed introduction to a target detection method provided by the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core ideas. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present disclosure, several improvements and modifications can be made to the present disclosure, and these improvements and modifications also fall within the scope of protection of the claims of the present disclosure.

Claims

1. A device for recording the number of times a server card is plugged in and out, the device comprising a backplane and a mainboard, wherein a first connector of the mainboard is used to connect to a second connector of the backplane, and the mainboard comprises a processor and a memory; characterized in that: The first pin and the second pin of the first connector are connected to the first energy storage device and the power path control device, respectively, and the two pins of the second connector corresponding to the first pin and the second pin of the first connector are short-circuited; the first power terminal of the mainboard is connected to an external power supply through the second power terminal of the backplane, the first power terminal is connected to the power path control device through a step-down circuit, and the power path control device is connected to the power supply pin of the processor, and the output voltage of the step-down circuit is greater than the voltage of the first energy storage device; the processor is configured as follows: In response to receiving a physical contact signal from the first connector, during an initialization process, power is turned on for the memory, a plug-in / plug-out count is read from the memory, the plug-in / plug-out count is incremented by one, and then re-written into the memory; The first data acquisition pin of the processor is connected to the output end of the step-down circuit. The processor is further configured to: read the output voltage of the step-down circuit through the first data acquisition pin after the number of plug-in and unplugging times is incremented by one and rewritten into the memory; determine whether the output voltage of the step-down circuit is abnormal; and when the output voltage of the step-down circuit is abnormal, turn off the power supply to the memory and enter the first working mode.

2. The device according to claim 1, characterized in that The power path control device includes a diode controller or an ideal diode controller.

3. The device according to claim 1, characterized in that The processor is an external memory, and the mainboard further includes a first MOS element, wherein a gate of the first MOS element is connected to a first control signal pin of the processor, and a first electrode and a second electrode of the first MOS element are respectively connected to a power supply pin of the processor and a power supply pin of the external memory; the processor is configured as follows: In response to receiving a physical contact signal from the first connector, power is turned on to the memory through the first MOS element during initialization, the plugging and unplugging times in the memory are read, and the plugging and unplugging times are incremented by one and then rewritten into the memory.

4. The device according to claim 3, characterized in that The processor is configured to: When the output voltage of the step-down circuit is abnormal, the power supply to the memory is turned off through the first MOS element and the memory enters a sleep mode.

5. The device according to claim 1, characterized in that The first interrupt pin of the processor is connected to the output end of the step-down circuit, and the processor is configured to: When the first interrupt pin receives a high level, it is awakened and reads the output voltage of the step-down circuit through the first data acquisition pin; determining whether the output voltage of the step-down circuit is abnormal; When the output voltage of the step-down circuit is normal, the second working mode is entered.

6. The device according to claim 5, characterized in that The first data acquisition pin and the first interrupt pin are the same pin.

7. The device according to claim 1, characterized in that The physical contact signal of the first connector refers to an instantaneous conduction signal formed during the plugging and unplugging process of the first connector.

8. The device according to claim 1, characterized in that The processor is configured to: When the output voltage of the step-down circuit is abnormal, the power supply of the memory is turned off, and the main frequency is switched to enter the first working mode.

9. The device according to claim 8, characterized in that The first operating mode of the processor is a sleep mode, and the second operating mode is a normal power supply mode.

10. The device according to claim 1, characterized in that The first energy storage device is a button battery, the voltage of the button battery is 3 volts, and the output voltage of the step-down circuit is 3.3 volts under normal circumstances.

11. The device according to claim 1, characterized in that The processor is one of MCU and CPLD.

12. A server, characterized in that: The server includes the server board plug-in and pull-out times recording device according to any one of claims 1 to 11.

13. The server according to claim 12, wherein: The server includes a central controller, which is in communication with the processor and is a BMC or a CPU; the central controller is configured with a server board life management system, which is used to: In response to a request to query the number of plug-in and unplug-out times of the motherboard, visualizing the number of plug-in and unplug-out times; When the number of plugging and unplugging times exceeds a threshold, an alarm is issued.

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