Cache line management method, shift register, controller and storage medium

Abstract

The invention discloses a cache line management method, a shift register, a controller and a storage medium, and relates to the technical field of storage, the method comprises the following steps: obtaining a first cache group and a first register table corresponding to the first cache group, the first cache group comprising N cache lines, and the first register table comprising N line sequences; under the condition that the first cache group does not hit the cache line to be accessed, a target line sequence is determined from the N line sequences, and the target line sequence corresponds to a first cache line included in the first cache group; and replacing the first cache line with the to-be-accessed cache line to obtain a second cache group, accessing data of the to-be-accessed cache line, and modifying the target line sequence. According to the method and the device, the problem that each row needs to be modified due to the fact that the row and the column where the corresponding point in the bitmap is located need to be modified in a replacement algorithm for determining the replaced storage row in the related technology is solved, the hardware design difficulty and hardware resources and energy consumption consumed by a circuit are reduced, and the access efficiency and the cache hit efficiency are improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a cache line management method, a shift register, a controller, and a storage medium. Background Art

[0002] Cache is one of the key components in modern computer systems, used to improve data access speed and program execution efficiency. Cache reduces the time it takes to read from main memory for frequently accessed data or instructions, thereby improving system performance. In current mainstream computer systems, a multi-level storage structure is usually designed. Cache, as a higher-level storage component, focuses on improving access speed and access hit rate. Therefore, the higher the cache level, the smaller the capacity. In order to solve the problem of limited cache capacity, a set-associative mapping method is often used to map the limited cache space to the main memory space. Since the cache space is limited, when the cache is full, there must be a replacement algorithm to determine which storage lines should be retained and which storage lines should be replaced.

[0003] The replacement algorithm for determining the replacement storage line is usually to set the row of the corresponding point in the bitmap to 1 and clear the column to 0 each time a cache line in the cache group is accessed, and then obtain a bitmap based on this recording method, and then determine the cache line to be replaced based on the bitmap. In this way, since each access requires a bitmap, the cache line to be replaced is replaced. Figure 1 Modifications are performed row by row, while cache memory array hardware typically requires read and write operations row by row, which is hardware-inefficient. Modifying a column in the bitmap requires modifying every row. Furthermore, because the number of cache lines accessed varies, modification methods vary, increasing hardware design complexity and circuit resource and energy consumption. Summary of the Invention

[0004] The present application provides a cache line management method, shift register, controller and storage medium to at least solve the problem in the related art that a replacement algorithm for determining a storage line to be replaced requires modifying both the row and column where the corresponding point in the bitmap is located, resulting in the need to modify each row, increasing the difficulty of hardware design and the hardware resources and energy consumption of the circuit.

[0005] The present application provides a cache line management method, the method comprising: obtaining a first cache group and a first register table corresponding to the first cache group, the first cache group including N cache lines, the first register table including N row sequences, each row sequence corresponding one-to-one to each cache line, N ≥ 1 and being a positive integer; in the event that the first cache group misses a cache line to be accessed, determining a target row sequence from the N row sequences, the target row sequence corresponding to the first row sequence included in the first cache group, the cache line to be accessed being a cache line required to be accessed by a processor core; replacing the first cache line with the cache line to be accessed to obtain a second cache group, accessing data of the cache line to be accessed included in the second cache group, and modifying the target row sequence.

[0006] The present application also provides a cache line management device, which includes: an acquisition module, used to acquire a first cache group and a first register table corresponding to the first cache group, the first cache group including N cache lines, the first register table including N row sequences, each row sequence corresponding to each cache line one-to-one, N ≥ 1 and is a positive integer; a processing module, used to determine a target row sequence from the N row sequences when the first cache group misses the cache line to be accessed, the target row sequence corresponds to the first row sequence included in the first cache group, and the cache line to be accessed is the cache line that the processor core needs to access; the processing module is also used to replace the first cache line with the cache line to be accessed to obtain a second cache group, and access the data of the cache line to be accessed included in the second cache group, and modify the target row sequence.

[0007] The present application also provides a controller, comprising: a storage unit for storing a computer program; and a processing unit for implementing the steps of any of the above cache line management methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned cache line management methods are implemented.

[0009] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above cache line management methods when executed by a processor.

[0010] Through the present application, since the target row sequence can be determined from N row sequences, the cache line to be replaced can be determined based on each row sequence. In addition, after replacing the first cache line with the cache line to be accessed and accessing the data of the cache line to be accessed, it is only necessary to modify the target row sequence without modifying the columns in the first register table. This at least solves the problem in the related art that the replacement algorithm needs to modify both the row and column where the corresponding point in the bitmap is located, resulting in the need to modify each row. This reduces the difficulty of hardware design, reduces the hardware resources and energy consumption of the circuit, and improves access efficiency and cache hit efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A topological diagram of a cache line management system provided in an embodiment of the present application;

[0013] Figure 2 A hardware circuit implementation diagram of a shift register provided in an embodiment of the present application;

[0014] Figure 3 A flowchart of a cache line management method provided in an embodiment of the present application;

[0015] Figure 4 A schematic diagram of a first register table and a shift register group provided in an embodiment of the present application;

[0016] Figure 5 A schematic diagram of changes in the values stored in the shift register provided in an embodiment of the present application;

[0017] Figure 6 A flowchart of another cache line management method provided in an embodiment of the present application;

[0018] Figure 7 A structural block diagram of a cache line management device provided in an embodiment of the present application;

[0019] Figure 8 A schematic diagram of the hardware structure of a controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0022] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0023] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the cache line management method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0024] The embodiments of the present application are applied to scenarios where cached data is accessed. In such scenarios, a set-associative mapping approach is often used to map limited cache space to main memory. The cache reduces the time it takes to read from main memory by accessing frequently accessed data or instructions, thereby improving system performance.

[0025] In an embodiment of the present application, accessing data in a cache line may be reading data from the cache line or writing data into the cache line. The present application is applicable to any scenario in which a cache line to be replaced is determined by a replacement algorithm.

[0026] In related technologies, when a cache is full, a replacement mechanism or replacement algorithm is used to determine which cache lines of stored data should be retained and which cache lines should be replaced. Common replacement algorithms include the Random Replacement Algorithm (RAND), the First In First Out (FIFO), and the Least Recently Used (LRU).

[0027] Among them, the LRU replacement algorithm can make better use of the principle of locality to improve the cache hit rate. The traditional LRU replacement algorithm can be implemented in a variety of ways, including but not limited to software, hardware, or a combination of the two. Software implementation is usually based on linked lists or arrays, which will result in additional central processing unit (CPU) overhead, high access delay and power consumption, and more complex software and hardware collaborative implementation. Hardware implementation relies on various dedicated circuits. In addition, the replacement algorithm needs to modify the rows and columns of the corresponding points in the bitmap, resulting in the need to modify each row, and because the number of ways to access the cache line is different, the modification method is different, which increases the difficulty of hardware design and the hardware resources and energy consumption of the circuit.

[0028] In order to solve the above technical problems, an embodiment of the present application can provide a cache line management method, which includes: obtaining a first cache group and a first register table corresponding to the first cache group; when the first cache group misses the cache line to be accessed, determining a target row sequence from N row sequences; replacing the first cache line with the cache line to be accessed, obtaining a second cache group, accessing the data of the cache line to be accessed included in the second cache group, and modifying the target row sequence. In this way, since the target row sequence can be determined from N row sequences, it means that the cache line to be replaced is determined based on each row sequence. In addition, after replacing the first cache line with the cache line to be accessed and accessing the data of the cache line to be accessed, it is only necessary to modify the target row sequence without modifying the columns in the first register table, so as to at least solve the problem in the related art that the replacement algorithm for determining the replaced storage line requires modifying both the row and column where the corresponding point in the bitmap is located, resulting in the need to modify each row, increasing the difficulty of hardware design and the hardware resources and energy consumption of the circuit, thereby improving access efficiency.

[0029] Below Figure 1 Taking the cache line management system shown as an example, the method provided in the embodiment of the present application is described.

[0030] like Figure 1 As shown, Figure 1 A topological diagram of a cache line management system provided in an embodiment of the present application. Figure 1 In the embodiment, the cache line management system 100 includes a cache line management device 101 , a cache 102 , a processor core 103 , a register 104 and a cache controller 105 .

[0031] The cache line management device 101 of the embodiment of the present application can be any device with communication and computing functions. For example, the cache line management device 101 can be a replacement algorithm logic controller.

[0032] The cache 102 of the embodiment of the present application can be any type of cache that is used to improve data access speed and program execution efficiency. The cache 102 includes multiple cache groups, each of which includes multiple cache lines. For example, each cache group can include 4 cache lines or 8 cache lines. The number of cache lines included in each cache group is consistent.

[0033] The processor core 103 of the embodiment of the present application may be a key execution unit of a central processing unit and is connected to a cache controller 105 .

[0034] The register 104 of the embodiment of the present application includes multiple register groups. Figure 1 In the FPGA, each register group includes four shift registers. Each shift register corresponds to a cache line one by one.

[0035] The shift register is used to complete the function of the counter and sort the cache lines corresponding to the shift register according to the numerical order of the output sum. Figure 2 As shown, Figure 2 A hardware circuit implementation diagram of the shift register provided in the embodiment of the present application. Figure 2 In the shift register, the main components include multiple 2-to-1 data selectors and multiple triggers, and adopt a parallel input and parallel output design.

[0036] The plurality of triggers include a first trigger, a second trigger, a third trigger, and a fourth trigger; and the plurality of data selectors include a first data selector, a second data selector, a third data selector, and a fourth data selector.

[0037] exist Figure 2 In the example, port 1 is used to input the control signal. When the control signal is 0, it instructs the shift register to perform a shift operation. When the control signal is 1, it instructs the shift register to perform a set operation.

[0038] Port 2 is used to input a first input signal, wherein the first input signal is a 0 signal.

[0039] Port 3 is used to input a clock signal, wherein each of the multiple flip-flops is triggered by the clock signal.

[0040] Port 4 is used to input the hold signal. When the hold signal is 1, it indicates that the shift register is invalid for shift or set operations. The output of the shift register remains unchanged. When the hold signal is 0, it indicates that the shift register can be shifted or set.

[0041] Port 5 is used to input a second input signal, wherein the second input signal is a 1 signal.

[0042] The first data selector receives a first input signal and a second input signal, determines one of the two input signals as a first output signal based on a control signal, and sends the first output signal to the first flip-flop.

[0043] The first trigger receives the first output signal and the hold signal, generates a second output signal, and transmits the second output signal to the second data selector. Figure 2 , the second output signal is the output signal of the Q3 port.

[0044] The second data selector receives the second output signal and the second input signal, determines one of the two input signals as a third output signal based on the control signal, and sends the third output signal to the second flip-flop.

[0045] The second trigger receives the third output signal and the hold signal, generates a fourth output signal, and transmits the fourth output signal to the third data selector. Figure 2 , the fourth output signal is the output signal of the Q2 port.

[0046] The third data selector receives the fourth output signal and the second input signal, determines one of the two input signals as a fifth output signal based on the control signal, and sends the fifth output signal to the third flip-flop.

[0047] The third trigger receives the fifth output signal and the hold signal, generates a sixth output signal, and transmits the sixth output signal to the fourth data selector. Figure 2 , the sixth output signal is the output signal of the Q1 port.

[0048] The fourth data selector receives the sixth output signal and the second input signal, determines one of the two input signals as a seventh output signal based on the control signal, and sends the seventh output signal to the fourth flip-flop.

[0049] The fourth trigger receives the seventh output signal and the hold signal to generate an eighth output signal. Figure 2 , the eighth output signal is the output signal of the Q0 port.

[0050] The second, fourth, sixth, and eighth output signals are the corresponding outputs of the shift register. The output signals corresponding to all outputs of the shift register, namely, ports Q3, Q2, Q1, and Q0, are the 4-bit values of the shift register. The cache line management device 101 can sort the corresponding cache lines based on the numerical order of the sum of all outputs.

[0051] The cache controller 105 in the embodiment of the present application may be a controller of the cache 102 .

[0052] exist Figure 1 In this example, the cache banks use a 4-way set-associative cache structure, meaning each bank consists of four cache lines. Accordingly, 4-way set-association employs a 4-bit shift register. As can be appreciated, M-way set-association employs M-bit shift registers. Alternatively, other set-associative structures with different numbers of ways can be used, and full connectivity can be considered an extreme case of multi-way set-association.

[0053] Figure 1 The cache line management system shown is for illustrative purposes only and is not intended to limit the technical solutions of this application. Those skilled in the art will appreciate that, in a specific implementation, the cache line management system may further include more register groups and cache groups, and the number of register groups and cache groups may also be determined based on specific needs and is not limited.

[0054] The following describes the method in detail in conjunction with the execution flow of the cache line management method.

[0055] The embodiment of the present application provides a cache line management method, which is applied to Figure 1 The cache line management device shown is as Figure 3 As shown, Figure 3 A flowchart of a cache line management method provided in an embodiment of the present application, the cache line management method comprising the following steps:

[0056] S301: Acquire a first cache group and a first register table corresponding to the first cache group.

[0057] The first cache group includes N cache lines, where N is greater than or equal to 1 and is a positive integer, and N can be a power of 2.

[0058] The first register table of the embodiment of the present application includes N row sequences, each row sequence corresponds to each cache line. Each row sequence includes the N-bit value of each shift register corresponding to each cache line. For example, Figure 2 For example, Figure 2 The N-bit value of the shift register is the output signal of the Q3 port, Q2 port, Q1 port, and Q0 port, and each row sequence includes a 4-bit value.

[0059] In some optional embodiments, a cache line management device receives an access request from a processor core, obtains a first cache group corresponding to the cache group address in the cache based on the cache group address of the cache group to be accessed; obtains each row sequence from each shift register corresponding to each cache line in the N cache lines; and obtains a first register table based on the N row sequences and the N corresponding relationships.

[0060] Each corresponding relationship is a one-to-one correspondence between each row sequence and each cache line.

[0061] The access request carries the address information of the cache line to be accessed. The address information includes the cache bank address of the cache bank to be accessed and the address of the cache line to be accessed. The cache line to be accessed is the cache line that the processor core needs to access.

[0062] Example 1, such as Figure 4 As shown, Figure 4 A schematic diagram of a first register table and a shift register group provided in an embodiment of the present application. Figure 4 In the example, the first register table stores a 4×4-bit value for a shift register in a 4-way set-associative cache. Taking the first row sequence as an example, the first row sequence stores a 4-bit value (also called a sorted value) for a cache line, where the leftmost bit is the most significant bit (MSB) and the rightmost bit is the least significant bit (LSB).

[0063] S302 : When the first cache set misses the cache line to be accessed, determine a target row sequence from the N row sequences.

[0064] The target row sequence corresponds to the first cache row included in the first cache group.

[0065] In some optional embodiments, when the first cache group misses the cache line to be accessed, it is detected whether there is a row sequence in the N row sequences whose most significant bit in the N-bit value is the first value; if not, the first row sequence in the first register table is determined as the target row sequence; if so, N-1 alternative row sequences are determined based on the most significant bit in the N-bit value of each row sequence; and the target row sequence is determined from the N-1 alternative row sequences based on the N-1-bit value of each alternative row sequence in the N-1 alternative row sequences.

[0066] The most significant bit corresponding to each candidate row sequence is not the first value. The first value is 1 or 0.

[0067] The N-1-bit value is the N-1-bit value excluding the most significant bit in each row sequence. For example, in Example 1, the N-1-bit value is the remaining 3-bit value excluding the leftmost MSB bit in each row sequence.

[0068] The numerical sum corresponding to each first row sequence is the smallest numerical sum among the N-1 numerical sums.

[0069] In one example, a cache line management device calculates the sum of the N-1-bit values based on the N-1-bit value of each candidate row sequence to obtain the N-1 numerical sum corresponding to the N-1 candidate row sequences; based on the N-1 numerical sum, at least one first row sequence is determined from the N-1 candidate row sequences; if the number of the first row sequences is one, the first row sequence is determined as the target row sequence; if the number of the first row sequences is multiple, the number of ways of the cache line corresponding to each first row sequence is obtained; based on the number of ways, the first row sequence with the smallest number of ways is determined as the target row sequence.

[0070] Example 2. Taking the first register table in Example 1 as an example, when the first cache group misses the cache line to be accessed, three alternative row sequences are determined to be row sequence 0, row sequence 1, and row sequence 3 based on the leftmost MSB bit of the 4-bit value of each row sequence; based on the remaining 3-bit values of each of the three alternative row sequences except the leftmost MSB bit, the sum of the remaining 3-bit values of each of the three alternative row sequences is calculated to obtain the three numerical sums corresponding to the three alternative row sequences, which are respectively the numerical sum corresponding to row sequence 0 is 2, the numerical sum corresponding to row sequence 1 is 3, and the numerical sum corresponding to row sequence 3 is 0; based on the three numerical sums, a first row sequence is determined from the three alternative row sequences to be row sequence 3, that is, row sequence 3 is determined as the target row sequence.

[0071] It can be understood that the cache line management device can quickly locate the MRU position according to whether the MSB bit is 1, and can sort the row sequences corresponding to other cache lines outside the MRU position, and only needs to calculate based on the remaining bit values of the non-MSB bits of other rows to determine the target row sequence, thereby reducing the number of bits required to judge when determining the cache line corresponding to the target row sequence and optimizing hardware resources.

[0072] Optionally, if there are multiple first row sequences, the cache row management device obtains the number of accesses of each first row sequence and the first weight corresponding to the number of accesses; obtains the number of ways of the cache row corresponding to each first row sequence and the second weight corresponding to the number of ways; and determines the target row sequence from the multiple cache rows based on the number of accesses, the first weight, the number of ways and the second weight.

[0073] In one example, based on a preset formula, the number of accesses, the first weight, the number of ways, and the second weight, the least recently used score of each first row sequence in several first row sequences is determined; and the cache row corresponding to the highest least recently used score among the several least recently used scores is determined as the target row sequence.

[0074] The preset formula can be

[0075] S iThe least recently used score for each first row sequence; A i is the number of visits to each first row sequence; W A is the first weight; B i is the number of ways for each first row sequence; W B is the second weight.

[0076] As you can understand, based on the number of cache line accesses and the number of ways in the cache line, the lower the number of accesses and the higher the way number, the higher the cache line's least recently used score. Therefore, based on this score, infrequently accessed cache lines are replaced first, freeing up space for more frequently accessed data. This ensures that cache space is always occupied by frequently accessed data, significantly improving cache hit rates and reducing performance losses caused by cache misses. This helps select more appropriate cache lines when cache space is limited, improving overall performance.

[0077] Before determining the target row sequence from the N row sequences, the cache row management device queries whether the first cache group stores data corresponding to the cache row address to be accessed based on the cache row address to be accessed; if not, it is determined that the first cache group misses the cache row to be accessed.

[0078] Optionally, if the cache line management device finds that the first cache group includes the cache line to be accessed, it determines that the first cache group hits the cache line to be accessed, and accesses the data in the cache line to be accessed; and based on the replacement algorithm, detects whether the most significant bit in the second row sequence corresponding to the cache line to be accessed is the first value; if so, sends a hold signal to each shift register corresponding to each cache line in the N cache lines to keep the first register table unchanged. If it is detected that the most significant bit in the second row sequence is not the first value, all N-bit values in the second row sequence are set to the first value, and the N-bit values of the other row sequences are shifted right by one bit, and the most significant bit of the N-bit values of the other row sequences is filled with the second value.

[0079] When the first value is 1, the second value may be 0. When the first value is 0, the second value may be 1.

[0080] The other row sequences are any other row sequences in the first register table except the second row sequence.

[0081] It is understandable that after the cache line management device determines that the first cache group hits the cache line to be accessed, it detects whether the MSB bit stored in the shift register corresponding to the cache line to be accessed is 1. If the MSB bit is 1, it means that the cache line to be accessed is already in the most recently used (MRU) position, and there is no need to update all the values in the first register table. That is, the shift registers corresponding to the cache lines on all ways in the first cache group where the cache line to be accessed is located remain unchanged (that is, the hold signal in the hardware circuit of the shift register is set to 1).

[0082] If the MSB bit is 0, it means that the cache line to be accessed is not in the MRU position. The N-bit value of the shift register corresponding to the cache line to be accessed needs to be set to 1 for the entire row, indicating that the cache line to be accessed is placed in the MRU position, and the shift registers corresponding to other ways in the first cache group where the cache line to be accessed is located are shifted right by the entire row, and the MSB bit is filled with 0.

[0083] The above operation on the value in the shift register is the operation of sorting cache lines in the Least Recently Used (LRU) replacement algorithm.

[0084] S303: Replace the first cache line with the cache line to be accessed to obtain a second cache group, access the data of the cache line to be accessed included in the second cache group, and modify the target line sequence.

[0085] In one example, cache line management is based on the address of the cache line to be accessed, data of the first row sequence is replaced to obtain the cache line to be accessed, the cache group including the cache line to be accessed is determined as the second cache group, and the data of the cache line to be accessed included in the second cache group is accessed, and based on the replacement algorithm, all N-bit values corresponding to the target row sequence are set to the first value, and the N-bit values corresponding to other row sequences are shifted.

[0086] The replacement algorithm of the embodiment of the present application is introduced below by taking the change of data in the shift register corresponding to each cache line when accessing each cache line in a cache group in sequence as an example.

[0087] like Figure 5 As shown, Figure 5 Schematic diagram of the change of the stored value in the shift register provided in the embodiment of the present application. From a to i, it represents the change of the data in the shift register corresponding to a cache group in sequence. Taking the value of all sequence rows in the initial register table of a as 0, accessing Way0 (accessing the first cache line in the cache group), Way1 (accessing the second cache line in the cache group), Way2 (accessing the third cache line in the cache group), Way3 (accessing the fourth cache line in the cache group), Way1, Way1, Way3 and Way1 as an example.

[0088] Access Way0: Set the N-bit value corresponding to Way0 in a to 1, and shift the other rows to the right, filling the MSB bit with 0 to obtain b.

[0089] Access Way1: Set the N-bit value corresponding to Way1 in b to 1, and shift the other rows to the right, filling the MSB bit with 0 to obtain c.

[0090] Access Way2: Set the N-bit value corresponding to Way2 in c to 1, and shift the other rows to the right, filling the MSB bit with 0 to obtain d.

[0091] Access Way3: Set the N-bit value corresponding to Way3 in d to 1, and shift the other rows to the right, filling the MSB bit with 0 to obtain e.

[0092] Access Way1: Set the N-bit value corresponding to Way1 in e to 1, and shift the other rows to the right, filling the MSB bit with 0 to obtain f.

[0093] Access Way1: Since the MSB of the N-bit value corresponding to Way1 in f is 1, Figure f remains unchanged and g is obtained.

[0094] Access Way3: Set the N-bit value corresponding to Way3 in g to 1, and shift the other rows to the right, filling the MSB bit with 0 to obtain h.

[0095] Access Way1: Set the N-bit value corresponding to Way0 in h to 1, and shift the other rows to the right, filling the MSB bit with 0 to obtain i.

[0096] It can be understood that when the first register table is as shown in i, if a cache miss occurs in a cache line of the cache group, the cache line corresponding to the smallest way number, ie Way0, needs to be selected as the cache line to be replaced.

[0097] Specifically, when the shift register updates the sorting information of the corresponding cache line, when other cache lines are hit and the shift register of the corresponding cache line needs to be shifted, the cache line management device controls the hold signal to be set to 0 through the replacement algorithm logic controller, and the input of the shift and set 1 port is 0; when the corresponding cache line is selected, it is detected whether the MSB bit, that is, the output of the Q3 port, is 1; if the output of the Q3 port is 0, then the cache line needs to be replaced, and the hold signal is controlled to be set to 0 through the replacement algorithm logic controller, and the shift and set 1 port input is controlled to be 1; if the output of the Q3 port is 1, it means that the cache line is in the MRU position, and the replacement algorithm logic controller controls the hold signals of all ways in the group where the cache line is located to be set to 1 to indicate that the input of the shift and set 1 port is invalid, and the outputs of the Q3 port, Q2 port, Q1 port, and Q0 port remain unchanged.

[0098] It can be understood that in other cases where the shift register receives a hold signal set to 1, the data stored in the shift register remains unchanged and the output remains unchanged.

[0099] As can be understood, the cache line management device is based on a replacement algorithm, which allows the shift register to perform operations on the entire line when shifting or setting a bit, without the need for other complex operations. In addition, the mechanism that keeps the shift register unchanged (keeping the signal set to 1) can keep the data in the shift register unchanged when the same path is frequently accessed, and restrict other operations, reducing multiple update operations at the same cache line location. This mechanism can significantly reduce energy consumption, thereby reducing hardware overhead and energy consumption, and improving access efficiency.

[0100] Based on the above Figure 3 In the method shown, a cache line management device can obtain a first cache group and a first register table corresponding to the first cache group; when the first cache group misses the cache line to be accessed, determine a target row sequence from N row sequences; replace the first cache line with the cache line to be accessed to obtain a second cache group, access the data of the cache line to be accessed included in the second cache group, and modify the target row sequence.

[0101] Since the target row sequence can be determined from the N row sequences, the cache line to be replaced can be determined based on each row sequence. Furthermore, after replacing the first cache line with the cache line to be accessed and accessing the data in the cache line to be accessed, only the target row sequence needs to be modified, without modifying the columns in the first register table. This at least solves the problem in related arts where the replacement algorithm needs to modify both the row and column of the corresponding point in the bitmap, resulting in the need to modify each row. This reduces the difficulty of hardware design, reduces hardware resources and energy consumption of the circuit, and improves access efficiency and cache hit efficiency.

[0102] The embodiment of the present application provides another cache line management method, such as Figure 6 As shown, Figure 6 A flowchart of another cache line management method provided in an embodiment of the present application, the cache line management method comprising the following steps:

[0103] S601: Receive an access request and start accessing the cache.

[0104] S602: Query whether the cache stores data corresponding to the cache line to be accessed.

[0105] S603: If not, calculate the N-1-bit values of the N-1 row sequences corresponding to the non-MRU positions in the cache group where the cache line to be accessed is located to obtain N-1 numerical sums, and determine several first row sequences based on the N-1 numerical sums.

[0106] S604: Determine whether the number of the first row sequences is one.

[0107] S605: If yes, the first row sequence is determined as the target row sequence, and data replacement is performed.

[0108] S606: If not, the first row sequence with the smallest number of paths is determined as the target row sequence, and data replacement is performed.

[0109] S607: After data replacement, access the cache line to be accessed.

[0110] S608: If it is found that the cache memory stores data corresponding to the cache line to be accessed, the cache line to be accessed is accessed and subsequent operations are performed.

[0111] S609: Detect whether the MSB bit of the row sequence corresponding to the cache row to be accessed is 1.

[0112] S610: If yes, keep the values stored in all shift registers corresponding to all cache lines unchanged.

[0113] S611: If not, set the N-bit value in the row sequence corresponding to the cache row to be accessed to 1, and right-shift the N-bit values in other row sequences.

[0114] The description of the features of the embodiment corresponding to the above S601 to S610 can refer to the relevant description of the embodiment corresponding to the cache line management method of the above S301 to S303, and will not be repeated here.

[0115] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0116] The embodiment of the present application also provides a cache line management device, such as Figure 7 As shown, Figure 7 This is a structural block diagram of a cache line management device provided in an embodiment of the present application; the device includes:

[0117] The acquisition module 701 is configured to acquire a first cache group and a first register table corresponding to the first cache group, wherein the first cache group includes N cache lines, and the first register table includes N row sequences, each row sequence corresponds to each cache line one-to-one, and N is a positive integer.

[0118] The processing module 702 is used to determine a target row sequence from N row sequences when the first cache group misses the cache line to be accessed, where the target row sequence corresponds to the first cache line included in the first cache group, and the cache line to be accessed is the cache line that the processor core needs to access.

[0119] The processing module 703 is further configured to replace the first cache line with the cache line to be accessed to obtain a second cache group, access the data of the cache line to be accessed included in the second cache group, and modify the target line sequence.

[0120] In some optional embodiments, the acquisition module 701 is specifically used to receive an access request from a processor core, where the access request carries address information of a cache line to be accessed, and the address information includes a cache group address of a cache group to be accessed; based on the cache group address of the cache group to be accessed, a first cache group corresponding to the cache group address is obtained in the cache; each row sequence is obtained from each shift register corresponding to each cache line in the N cache lines, each row sequence includes an N-bit value of each shift register; based on the N row sequences and N corresponding relationships, a first register table is obtained, where each corresponding relationship is a one-to-one correspondence between each row sequence and each cache line.

[0121] In some optional embodiments, the address information includes the address of the cache line to be accessed, and the processing module 702 is further used to query whether the first cache group stores data corresponding to the cache line address to be accessed based on the cache line address to be accessed; if not, it is determined that the first cache group misses the cache line to be accessed.

[0122] In some optional embodiments, the processing module 702 is specifically used to detect whether there is a row sequence in the N row sequences whose most significant bit in the N-bit value is the first value when the first cache group misses the cache line to be accessed; if not, the first row sequence in the first register table is determined as the target row sequence; if so, N-1 alternative row sequences are determined based on the most significant bit in the N-bit value of each row sequence, and the most significant bit corresponding to each alternative row sequence is not the first value; based on the N-1-bit value of each alternative row sequence in the N-1 alternative row sequences, the target row sequence is determined from the N-1 alternative row sequences, and the N-1-bit value is the N-1-bit value other than the most significant bit in each row sequence.

[0123] In some optional embodiments, the processing module 702 is further specifically configured to calculate the sum of the N-1-bit values based on the N-1-bit value of each candidate row sequence to obtain the N-1 numerical sums corresponding to the N-1 candidate row sequences; based on the N-1 numerical sums, determine a number of first row sequences from the N-1 candidate row sequences, the numerical sum corresponding to each first row sequence being the smallest numerical sum among the N-1 numerical sums; if the number of the first row sequences is one, determine the first row sequence as the target row sequence; if the number of the first row sequences is multiple, obtain the number of ways of the cache rows corresponding to each first row sequence in the number of first row sequences; based on the number of ways, determine the first row sequence with the smallest number of ways as the target row sequence.

[0124] In some optional embodiments, the processing module 702 is further used to determine that the first cache group hits the cache line to be accessed if it is queried that the first cache group includes the cache line to be accessed, and access the data of the cache line to be accessed; detect whether the most significant bit in the second row sequence corresponding to the cache line to be accessed is the first value; and if so, send a hold signal to each shift register corresponding to each cache line in the N cache lines to keep the first register table unchanged.

[0125] In some optional embodiments, the processing module 702 is further configured to, if it is detected that the most significant bit in the second row sequence is not the first value, set all N-bit values in the second row sequence to the first value, shift the N-bit values of other row sequences right by one position, and fill the most significant bit of the N-bit values of other row sequences with the second value, where the other row sequence is any other row sequence in the first register table except the second row sequence.

[0126] For descriptions of features in the embodiments corresponding to the cache line management device, reference may be made to the relevant descriptions of the embodiments corresponding to the cache line management method, which will not be described in detail here.

[0127] The embodiment of the present application also provides a controller, such as Figure 8 As shown, Figure 8 A hardware structure diagram of a controller provided in an embodiment of the present application, the controller includes a processing unit 10 and a storage unit 20, the storage unit 20 stores a computer program, and the processing unit 10 is configured to run the computer program to execute the steps in any of the above-mentioned cache line management method embodiments.

[0128] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above cache line management method embodiments when running.

[0129] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0130] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above cache line management method embodiments are implemented.

[0131] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-mentioned cache line management method embodiments.

[0132] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0133] The above is a detailed introduction to the cache line management method, shift register, controller and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A cache line management method, characterized in that: The method includes: Obtain a first cache group and a first register table corresponding to the first cache group, wherein the first cache group includes N cache lines, the first register table includes N row sequences, each row sequence corresponds to each cache line one-to-one, and N is ≥ 1 and is a positive integer; In the case that the first cache group misses the cache line to be accessed, determining a target row sequence from the N row sequences, the target row sequence corresponding to the first cache line included in the first cache group, and the cache line to be accessed is the cache line required to be accessed by the processor core; The first cache line is replaced with the cache line to be accessed to obtain a second cache group, and the data of the cache line to be accessed included in the second cache group is accessed, and the target line sequence is modified.

2. The method according to claim 1, characterized in that The acquiring of the first cache group and the first register table corresponding to the first cache group includes: receiving an access request from the processor core, the access request carrying address information of the cache line to be accessed, the address information including a cache group address of the cache group to be accessed; Based on the cache group address of the cache group to be accessed, obtaining the first cache group corresponding to the cache group address in the cache; Obtaining each of the row sequences from each shift register corresponding to each of the N cache lines, each of the row sequences including an N-bit value of each shift register; The first register table is obtained based on the N row sequences and N corresponding relationships, where each corresponding relationship is a one-to-one correspondence between each row sequence and each cache line.

3. The method according to claim 2, characterized in that The address information includes an address of a cache line to be accessed, and the method further includes: Based on the cache line address to be accessed, querying whether the first cache group stores data corresponding to the cache line address to be accessed; If not, it is determined that the first cache group misses the cache line to be accessed.

4. The method according to claim 2, characterized in that The determining of a target row sequence from the N row sequences when the first cache group misses a cache row to be accessed comprises: In a case where the first cache group misses the cache line to be accessed, detecting whether there is a row sequence in the N row sequences whose most significant bit in the N-bit value is the first value; If not, determining the first row sequence in the first register table as the target row sequence; If so, determining N-1 candidate row sequences according to the most significant bit of the N-bit value of each row sequence, wherein the most significant bit corresponding to each candidate row sequence is not the first value; The target row sequence is determined from the N-1 candidate row sequences based on an N-1-bit value of each of the N-1 candidate row sequences, wherein the N-1-bit value is an N-1-bit value excluding the most significant bit in each of the row sequences.

5. The method according to claim 4, characterized in that The determining the target row sequence from the N-1 candidate row sequences based on the N-1 bit value of each of the N-1 candidate row sequences includes: Calculating the sum of the N-1-bit values based on the N-1-bit value of each candidate row sequence to obtain the N-1 value sum corresponding to the N-1 candidate row sequences; Based on the N-1 numerical value sums, determining a plurality of first row sequences from the N-1 candidate row sequences, wherein the numerical value sum corresponding to each first row sequence is the smallest numerical value sum among the N-1 numerical value sums; If the number of the plurality of first row sequences is one, determining the first row sequence as the target row sequence; If there are multiple first row sequences, obtaining a way number of a cache line corresponding to each of the first row sequences; Based on the number of ways, the first row sequence with the smallest number of ways is determined as the target row sequence.

6. The method according to claim 4, characterized in that The method further comprises: If it is found that the first cache group includes the cache line to be accessed, determining that the first cache group hits the cache line to be accessed, and accessing the data of the cache line to be accessed; Detecting whether the most significant bit in the second row sequence corresponding to the cache line to be accessed is the first value; If so, a hold signal is sent to each shift register corresponding to each of the N cache lines to keep the first register table unchanged.

7. The method according to claim 6, characterized in that The method further comprises: If it is detected that the most significant bit in the second row sequence is not the first value, all N-bit values in the second row sequence are set to the first value, the N-bit values of other row sequences are shifted right by one bit, and the most significant bit of the N-bit values of the other row sequences is supplemented with the second value. The other row sequence is any row sequence other than the second row sequence in the first register table.

8. A shift register, characterized in that: The shift register includes a plurality of flip-flops and a plurality of data selectors; the plurality of flip-flops include a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop; the plurality of data selectors include a first data selector, a second data selector, a third data selector, and a fourth data selector; wherein each of the plurality of flip-flops is triggered by a clock signal; The first data selector receives a first input signal and a second input signal, determines one of the two input signals as a first output signal based on a control signal, and sends the first output signal to a first trigger; The first flip-flop receives the first output signal and the hold signal, generates a second output signal, and transmits the second output signal to the second data selector; the second data selector receives the second output signal and the second input signal, and determines one of the two input signals as a third output signal based on the control signal, and transmits the third output signal to the second flip-flop; The second flip-flop receives the third output signal and the hold signal, generates a fourth output signal, and transmits the fourth output signal to a third data selector; The third data selector receives the fourth output signal and the second input signal, determines one of the two input signals as a fifth output signal based on the control signal, and sends the fifth output signal to a third flip-flop; The third flip-flop receives the fifth output signal and the hold signal, generates a sixth output signal, and transmits the sixth output signal to a fourth data selector; The fourth data selector receives the sixth output signal and the second input signal, determines one of the two input signals as a seventh output signal based on the control signal, and sends the seventh output signal to a fourth flip-flop; The fourth flip-flop receives the seventh output signal and the hold signal to generate an eighth output signal; The second output signal, the fourth output signal, the sixth output signal and the eighth output signal serve as corresponding output results of the shift register.

9. A controller, characterized in that: include: a storage unit for storing a computer program; A processing unit, configured to implement the steps of the cache line management method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the cache line management method according to any one of claims 1 to 7.

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