Method and device for CPU simulation synchronization between simulators based on FPGA and CPU

Abstract

The invention discloses a method and device for CPU simulation synchronization between simulators based on an FPGA and a CPU, and the method comprises the steps: a CPU real-time synchronization device issues a CPU operation instruction to a plurality of real-time simulators through an optical fiber, the FPGA of each device receives the instruction and then uploads the instruction to a communication core, and the instruction is distributed to all simulation cores through an inter-core shared memory; each simulation core generates a CPU state signal before a period is cut off and feeds back the CPU state signal to the communication core, the communication core summarizes the CPU state signals of each simulation core and executes an AND operation, a generated device-level synchronization confirmation signal is issued to the FPGA, and the FPGA sends the signal to a CPU real-time synchronization device through an optical fiber; the device receives the synchronization confirmation signal of each device to summarize and judge the synchronization state of each device in the current period, and determines whether to generate the running instruction of each CPU in the next period according to the judgment result; compared with the prior art, the parallel simulation of strict and accurate synchronization of CPUs among a plurality of real-time simulation devices is realized, and the CPU simulation synchronization result of a large-scale electrical system is ensured to be accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of real-time simulation, in particular to a method and device for CPU simulation synchronization between simulators based on FPGA and CPU. Background Art

[0002] With the rapid development of power systems, renewable energy stations, and industrial control, system scale and complexity are growing exponentially. Mathematical models for large-scale power grids, renewable energy stations, or complex electromechanical systems require high-precision solutions. Single-core CPUs cannot meet real-time requirements, and traditional single-core or single-device simulations face the bottleneck of insufficient computing power. Applications like renewable energy stations require simultaneous hardware-in-the-loop testing of multiple device controllers, requiring simultaneous multi-core and multi-device simulation.

[0003] However, in synchronous parallel simulation applications with multiple CPUs and multiple devices, due to reasons such as unbalanced computing task loads or communication delays, one CPU may fail to complete its computing task in the current cycle, resulting in a computation timeout and asynchronous data interaction with other CPUs. Synchronous parallel simulation requires strict time synchronization between multiple cores and multiple devices, otherwise errors will be introduced and even system instability will occur. Therefore, a method and device for CPU simulation synchronization between simulators based on FPGA and CPU are provided. Summary of the Invention

[0004] The purpose of the present invention is to address the problem that the CPUs fail to strictly synchronize in existing multi-CPU and multi-device parallel simulation applications, resulting in data asynchrony, errors, and even system instability. A method and device for CPU simulation synchronization between simulators based on FPGA and CPU are provided, which can realize parallel simulation with strict and accurate CPU synchronization between multiple real-time simulation devices, and ensure accurate CPU simulation synchronization results of large-scale electrical systems.

[0005] To achieve the above object, the present invention provides the following technical solution: a method for CPU simulation synchronization between simulators based on FPGA and CPU, comprising the following steps:

[0006] Step 1: At the beginning of each simulation cycle, the CPU real-time synchronization device sends the running instruction CPU_REQ of the CPU simulation core of each simulator device through the optical fiber;

[0007] The CPU real-time synchronization device transmits the CPU operation instruction CPU_REQ to each real-time simulator device through the optical fiber port, supporting a maximum of 16 devices. The instruction format adopts a custom protocol encapsulation and contains the following fields:

[0008] Frame header (2 bytes): 55aa55aa55aa55aa;

[0009] Run instruction (1 byte): CPU run instruction CPU_REQ;

[0010] Frame tail (2 bytes): 1000000000000000;

[0011] Step 2: Each real-time simulator device FPGA receives the CPU running instruction and uploads the instruction to the CPU communication core (core0) in the device. The communication core receives the running instruction CPU_REQ uploaded by FPGA and sends the instruction to other simulation cores (core 1～i )middle;

[0012] If the real-time simulator device contains i+1 CPU cores, core0 is a dedicated communication core responsible for communication and data exchange with FPGA and other simulation cores. 1～i It is a simulation core used to perform simulation calculation tasks, including the following steps:

[0013] Step 201: The FPGA of each device receives the operation instruction CPU_REQ through the optical fiber, and parses and verifies the instruction;

[0014] Step 202: After the instruction parsing is completed, the FPGA transmits the instruction to the CPU communication core (core 0) via the PCIE bus;

[0015] Step 203: After receiving the CPU execution instruction CPU_REQ, the CPU communication core sends the instruction to other simulation cores (core1 to corei) in the simulator through the inter-core shared memory. The inter-core shared memory is a high-speed cache area that can be directly accessed between multiple simulation cores in the CPU, supporting low-latency, high-efficiency data sharing and fast communication.

[0016] Step 3: Each CPU simulation core can start the current cycle model operation only after receiving the CPU operation instruction; each simulation core will generate the corresponding CPU status signal S before the end of the current cycle i and sends the status signal to the communication core through the shared memory between CPU cores;

[0017] Step 301: Each CPU simulation core can start the computing task of the current cycle only after receiving the CPU operation instruction CPU_REQ;

[0018] Step 302: Each simulation core (core1-i) generates a CPU status signal S before the current CPU calculation cycle ends. i ,

[0019] in:

[0020]

[0021] Each simulation core has a built-in hardware timer. If the calculation is completed within the cycle, a signal S is generated. i =1, if the calculation is not completed before the end of the period, automatically mark S i =0;

[0022] Step 303: Each simulation core sends a CPU status signal S to the communication core (core0) through the inter-core shared memory. i :

[0023] Step 4: The communication core receives the status signal S of all simulation cores i , and perform a global logic "AND" operation on the signal to generate a device-level synchronization confirmation signal CPU_ACK, and send this signal to the device FPGA;

[0024] Step 401: The communication core receives the CPU status signal S of all simulation cores. i The signal is stored in the status register. Before the cycle ends, the communication core performs a global logical "AND" operation on the CPU status signal to generate a device-level synchronization confirmation signal CPU_ACK, where:

[0025]

[0026] Step 402: The communication core sends the CPU_ACK signal to the FPGA via the high-speed PCIE bus.

[0027] Step 5: The FPGA sends the synchronization confirmation signal CPU_ACK to the CPU real-time synchronization device via the optical fiber;

[0028] Step 6: The CPU real-time synchronization device waits for each real-time simulator to return a synchronization confirmation signal CPU_ACK, and ends this simulation cycle after receiving the synchronization confirmation signals CPU_ACK from all devices;

[0029] Step 601: The CPU real-time synchronization device receives a synchronization confirmation signal CPU_ACK sent from each simulator device via a high-speed optical fiber interface;

[0030] Step 602: The CPU real-time synchronization device summarizes the synchronization status, stores each received synchronization confirmation signal CPU_ACK into the synchronization status table, and marks the corresponding device as completed;

[0031] Step 603: Before the current cycle ends, the CPU real-time synchronization device traverses the synchronization status table and performs an AND operation on the synchronization confirmation signal CPU_ACK of each device to generate a global synchronization status flag Global_Sync. If the total number of devices is M, then:

[0032]

[0033] Step 604: The CPU real-time synchronization device determines whether to generate the operation instructions of each CPU in the next cycle according to the global synchronization status flag Global_Sync:

[0034] If Global_Sync = 1, that is, the CPU simulation cores in all devices have completed calculations in the current cycle, the device will perform the following operations:

[0035] (a) The CPU real-time synchronization device will generate the operation instruction (CPU_REQ) of each CPU for the next cycle;

[0036] (b) The device clears the synchronization status table of the current cycle, ends the current simulation cycle, and prepares to receive the synchronization confirmation signal of each device in the next cycle;

[0037] If Global_Sync = 0, that is, the CPU simulation core in the device has not completed the calculation in the current cycle, the device will perform the following operations:

[0038] (a) The device system enters the delay waiting stage and suspends issuing the CPU operation instructions for the next cycle;

[0039] (b) The current synchronization status table is not reset, and the missing synchronization confirmation signal is continuously monitored until the CPU_ACK of all emulators is received.

[0040] A device for synchronizing CPU simulation between simulators based on FPGA and CPU is used to implement the above-mentioned method for synchronizing CPU simulation between simulators based on FPGA and CPU.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] The present invention adopts a CPU real-time synchronization device to ensure strict synchronous simulation of a total of 4 CPU simulation cores of two simulators. The two simulators perform high-speed interaction of simulation data through optical fiber. At the same time, the clock synchronization of each device is ensured by connecting a clock line with the CPU real-time synchronization device, thereby realizing strict and accurate synchronous parallel simulation of a total of 4 CPU simulation cores between the two real-time simulation devices, and ensuring the accuracy of the CPU simulation synchronization results of the main network IEEE118 node electrical system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A flowchart of a method for synchronizing CPU simulation between emulators based on FPGA and CPU according to the present invention;

[0044] Figure 2 Schematic diagram of a device for CPU simulation synchronization between emulators based on FPGA and CPU according to the present invention;

[0045] Figure 3This is a signal diagram of the CPU real-time synchronization device of the present invention;

[0046] Figure 4 This is the real-time result waveform of the synchronous parallel simulation of multiple devices and multiple CPU cores of the main network IEEE118 node of the present invention. DETAILED DESCRIPTION

[0047] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more precise definition of the protection scope of the present invention.

[0048] Embodiment 1: A method for synchronizing CPU simulation between emulators based on FPGA and CPU, comprising the following steps:

[0049] Step 1: At the beginning of each simulation cycle, the CPU real-time synchronization device sends the running instruction CPU_REQ of the CPU simulation core of each simulator device through the optical fiber;

[0050] In step 1, if Figure 1 As shown in the figure, the CPU real-time synchronization device transmits the CPU operation instruction CPU_REQ to each real-time simulator device through optical fiber, supporting a maximum of 16 devices. The instruction format is encapsulated using a custom protocol and contains the following fields:

[0051] Frame header (2 bytes): 55aa55aa55aa55aa;

[0052] Run instruction (1 byte): CPU run instruction CPU_REQ;

[0053] Frame tail (2 bytes): 1000000000000000;

[0054] Step 2: Each real-time simulator device FPGA receives the CPU running instruction and uploads the instruction to the CPU communication core (core0) in the device. The communication core receives the running instruction CPU_REQ uploaded by FPGA and sends the instruction to other simulation cores (core 1～i )middle;

[0055] In step 2, if Figure 2 As shown, if the real-time simulator device contains i+1 CPU cores, core0 is a dedicated communication core responsible for communication and data interaction with FPGA and other simulation cores, core 1～i It is a simulation core used to perform simulation calculation tasks, including the following steps:

[0056] Step 201: The FPGA of each device receives the operation instruction CPU_REQ through the optical fiber, and parses and verifies the instruction;

[0057] Step 202: After the instruction parsing is completed, the FPGA transmits the instruction to the CPU communication core (core 0) via the PCIE bus;

[0058] Step 203: After receiving the CPU execution instruction CPU_REQ, the CPU communication core sends the instruction to other simulation cores (core1 to corei) in the simulator through the inter-core shared memory. The inter-core shared memory is a high-speed cache area that can be directly accessed between multiple simulation cores in the CPU, supporting low-latency, high-efficiency data sharing and fast communication.

[0059] Step 3: Each CPU simulation core can start the current cycle model operation only after receiving the CPU operation instruction; each simulation core will generate the corresponding CPU status signal S before the end of the current cycle i and sends the status signal to the communication core through the shared memory between CPU cores;

[0060] Step 3 includes the following steps:

[0061] Step 301: After receiving the CPU execution instruction CPU_REQ, each CPU simulation core starts the simulation calculation task of the current cycle;

[0062] Step 302: Each simulation core (core1-i) generates a CPU status signal S before the current CPU calculation cycle ends. i ,

[0063] in:

[0064]

[0065] Each simulation core has a built-in hardware timer. If the calculation is completed within the cycle, a signal S is generated. i =1, if the calculation is not completed before the end of the period, automatically mark S i =0;

[0066] Step 33: Each simulation core sends a CPU status signal S to the communication core (core0) through the inter-core shared memory i :

[0067] Step 4: The communication core receives the status signal S of all simulation cores i , and perform a global logic "AND" operation on the signal to generate a device-level synchronization confirmation signal CPU_ACK, and send this signal to the device FPGA;

[0068] Step 4 includes the following steps:

[0069] Step 401: The communication core receives the CPU status signals Si from all simulation cores and stores them in the status register. Before the cycle ends, the communication core performs a global logical AND operation on the CPU status signals to generate a device-level synchronization confirmation signal CPU_ACK, where:

[0070]

[0071] Step 402: The communication core sends the CPU_ACK signal to the FPGA via the high-speed PCIE bus.

[0072] Step 5: The FPGA sends the synchronization confirmation signal CPU_ACK to the CPU real-time synchronization device via the optical fiber;

[0073] Step 6: The CPU real-time synchronization device waits for each real-time simulator to return a synchronization confirmation signal CPU_ACK, and ends this simulation cycle after receiving the synchronization confirmation signals CPU_ACK from all devices;

[0074] like Figure 3 Step 6 includes the following steps:

[0075] Step 601: The CPU real-time synchronization device receives a synchronization confirmation signal CPU_ACK sent from each simulator device via a high-speed optical fiber interface;

[0076] Step 602: The CPU real-time synchronization device summarizes the synchronization status, stores the received synchronization confirmation signals CPU_ACK from each device into the synchronization status table, and marks the corresponding device as completed;

[0077] Step 603: Before the current cycle ends, the CPU real-time synchronization device traverses the synchronization status table and performs an AND operation on the synchronization confirmation signal CPU_ACK of each device to generate a global synchronization status flag Global_Sync. If the total number of devices is M, then:

[0078]

[0079] Step 604: The CPU real-time synchronization device determines whether to generate the operation instructions of each CPU in the next cycle according to the global synchronization status flag Global_Sync:

[0080] If Global_Sync = 1, that is, the CPU simulation cores in all devices have completed calculations in the current cycle, the device will perform the following operations:

[0081] (a) The CPU real-time synchronization device will generate the operation instruction (CPU_REQ) of each CPU for the next cycle;

[0082] (b) The device clears the synchronization status table of the current cycle, ends the current simulation cycle, and prepares to receive the synchronization confirmation signal of each device in the next cycle;

[0083] If Global_Sync = 0, that is, the CPU simulation core in the device has not completed the calculation in the current cycle, the device will perform the following operations:

[0084] (a) The device system enters the delay waiting stage and suspends issuing the CPU operation instructions for the next cycle;

[0085] (b) The current synchronization status table is not reset, and the missing synchronization confirmation signal is continuously monitored until the CPU_ACK of all emulators is received;

[0086] In the above system, data is exchanged between devices through optical fibers, and the CPU real-time synchronization device ensures clock synchronization of all devices by sending clock signals to each real-time simulator.

[0087] Example 2: Real-time simulation results analysis of the main network IEEE118 node multi-core model parallel simulation;

[0088] The performance of strictly synchronized, real-time parallel simulations across multiple CPUs and multiple devices was verified using the main grid IEEE118 node model as an example. The IEEE118 node model is a standard test system widely used in power system analysis. Its complex structure and rich parameters make it suitable for studying the dynamic characteristics of power grids, economic optimization, and coordinated multi-energy dispatch. It is a crucial tool for power system algorithm verification and smart grid research.

[0089] The grid consists of 118 three-phase nodes, 177 lines, 54 synchronous generators, 83 loads, and nine transformers. Voltage levels are 20kV, 138kV, and 345kV, and the total generated power of all units is 4,377.4MW.

[0090] The grid model is divided into four cores, running on two real-time simulators, with two cores running in each real-time simulator. The computational step size of each CPU simulation core is 50us. Among them, there are 40 three-phase nodes in Simulator A Core 1, including 3 transformers, 16 synchronous machines, 58 lines, and 29 loads; there are 19 three-phase nodes in Simulator A Core 2, including 1 transformer, 11 synchronous machines, 31 lines, and 14 loads; there are 24 three-phase nodes in Simulator B Core 1, including 2 transformers, 12 synchronous machines, 34 lines, and 17 loads; there are 35 three-phase nodes in Simulator B Core 2, including 3 transformers, 15 synchronous machines, 45 lines, and 23 loads. The modules contained in each core and the actual running time of each CPU are shown in Table 1.

[0091] Table 1. Modules included in each core of the IEEE118 node and actual running time

[0092]

[0093] The present invention provides a method and device for CPU simulation synchronization between FPGA-based and CPU-based simulators. A CPU real-time synchronization device is used to ensure strict synchronous simulation of a total of four CPU simulation cores in two simulators. Simulation data is exchanged between the two simulators at high speed via optical fiber. Clock synchronization of each device is ensured by connecting a clock line to the CPU real-time synchronization device. This enables strict and precise parallel simulation of a total of four CPU simulation cores between the two real-time simulation devices, ensuring accurate CPU simulation synchronization results for the main network IEEE 118 node electrical system.

[0094] Figure 4 (a), (b), (c), and (d) show the current and voltage waveforms at the 138kV node of simulator A core 1 and simulator B core 1, respectively. The voltage and current have good sinusoidal properties, the waveforms are smooth, and the main grid model operates stably. This CPU simulation synchronization method can achieve strict synchronous parallel real-time simulation hardware-in-the-loop testing of multiple CPUs and multiple real-time simulation devices.

[0095] The above embodiments merely illustrate the implementation methods of the present invention. Although the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the scope of the present invention, and these modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A method for synchronizing CPU simulation between emulators based on FPGA and CPU, characterized by: The specific steps include: Step 1: At the beginning of each simulation cycle, the CPU real-time synchronization device sends the running instruction CPU_REQ of the CPU simulation core of each simulator device through the optical fiber; Step 2: Each real-time simulator device FPGA receives the CPU running instruction and uploads the instruction to the device CPU communication core (core0). The communication core receives the running instruction CPU_REQ uploaded by FPGA and sends the instruction to other simulation cores (core 1～i )middle; Step 3: Each CPU simulation core can start the current cycle model operation only after receiving the CPU operation instruction; each simulation core will generate the corresponding CPU status signal S before the end of the current cycle i and sends the status signal to the communication core through the shared memory between CPU cores; Step 4: The communication core receives the status signal S of all simulation cores i , and perform a global logic "AND" operation on the signal to generate a device-level synchronization confirmation signal CPU_ACK, and send this signal to the device FPGA; Step 5: Each real-time simulator FPGA sends a synchronization confirmation signal CPU_ACK to the CPU real-time synchronization device via an optical fiber; Step 6: The CPU real-time synchronization device waits for each real-time simulator to return a synchronization confirmation signal CPU_ACK, and ends this simulation cycle after receiving the synchronization confirmation signals CPU_ACK from all devices.

2. The method for CPU simulation synchronization between emulators based on FPGA and CPU according to claim 1, wherein: Step 2 includes the following steps: Step 201: The FPGA of each device receives the operation instruction CPU_REQ through the optical fiber, and parses and verifies the instruction; Step 202: After the instruction is parsed, the FPGA transmits the instruction to the CPU communication core (core 0) via the PCIE bus; Step 203: After the CPU communication core receives the CPU execution instruction CPU_REQ, it sends the instruction to other simulation cores (core1~i) in the simulator through the inter-core shared memory. The inter-core shared memory is a high-speed cache area that can be directly accessed between multiple simulation cores inside the CPU, supporting low-latency and high-efficiency data sharing and fast communication.

3. The method for CPU simulation synchronization between emulators based on FPGA and CPU according to claim 1, wherein: Step 3 includes the following steps: Step 301: Each CPU simulation core can start the computing task of the current cycle only after receiving the CPU operation instruction CPU_REQ; Step 302: Each simulation core (core1-i) generates a CPU status signal S before the current CPU calculation cycle ends. i , in: Step 303: Each simulation core sends a CPU status signal S to the communication core (core0) through the inter-core shared memory. i .

4. The method for CPU simulation synchronization between emulators based on FPGA and CPU according to claim 1, wherein: Step 4 includes the following steps: Step 401: The communication core receives the CPU status signal S of all simulation cores. i , and perform a global logic "AND" operation on the signal to generate a device-level synchronous confirmation signal CPU_ACK, where: Step 402: The communication core sends the CPU_ACK signal to the FPGA via the high-speed PCIE bus.

5. The method for CPU simulation synchronization between emulators based on FPGA and CPU according to claim 1, wherein: Step 6 includes the following steps: Step 601: The CPU real-time synchronization device receives a synchronization confirmation signal CPU_ACK sent from each simulator device via a high-speed optical fiber interface; Step 602: The CPU real-time synchronization device summarizes the synchronization status, stores each received synchronization confirmation signal CPU_ACK into the synchronization status table, and marks the corresponding device as completed; Step 603: Before the current cycle ends, the CPU real-time synchronization device traverses the synchronization status table and performs an AND operation on the synchronization confirmation signal CPU_ACK of each device to generate a global synchronization status flag Global_Sync. If the total number of devices is M, then: Step 604: The CPU real-time synchronization device determines whether to generate the operation instructions of each CPU in the next cycle according to the global synchronization status flag Global_Sync: If Global_Sync = 1, that is, the CPU simulation cores in all devices have completed calculations in the current cycle, the device will perform the following operations: (a) The CPU real-time synchronization device will generate the operation instruction (CPU_REQ) of each CPU for the next cycle; (b) The device clears the synchronization status table of the current cycle, ends the current simulation cycle, and prepares to receive the synchronization confirmation signal of each device in the next cycle; If Global_Sync = 0, that is, the CPU simulation core in the device has not completed the calculation in the current cycle, the device will perform the following operations: (a) The device system enters the delay waiting stage and suspends issuing the CPU operation instructions for the next cycle; (b) The current synchronization status table is not reset, and the missing synchronization confirmation signal is continuously monitored until the CPU_ACK of all emulators is received.

6. The method for CPU simulation synchronization between emulators based on FPGA and CPU according to claim 1, wherein: In step 2, the FPGA of each real-time simulator device is used to connect to the optical fiber for high-speed interaction of simulation data.

7. The method for CPU simulation synchronization between emulators based on FPGA and CPU according to claim 1, wherein: In step 5, the CPU real-time synchronization device and each real-time simulator are connected by a clock synchronization line to ensure that the clocks of each device are synchronized.

8. A device for synchronizing CPU simulation between emulators based on FPGA and CPU, characterized by: A method for implementing CPU simulation synchronization between FPGA-based and CPU-based simulators as described in any one of claims 1-7.

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