Fault preprocessing method and device, equipment and storage medium

Abstract

The invention discloses a fault preprocessing method and device, equipment and a storage medium, and relates to the technical field of servers, and the method comprises the steps: predicting a first fault which may occur in a future target time period of a first integrated circuit and a first probability of occurrence of the first fault based on the historical operation information of the first integrated circuit; thus, the target preprocessing operation matched with the first fault can be executed for the first fault of which the first probability is within the preset probability range before the first integrated circuit has not occurred the first fault, and the first fault is avoided or repaired in advance, so that the first fault is prevented from occurring. The first fault which may occur in the first integrated circuit in the future target time period is avoided or repaired in advance, so that the stability and reliability of the integrated circuit can be improved, and the problem that the stability and reliability of the integrated circuit in the related technology are relatively low is solved.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a fault preprocessing method, apparatus, device, and storage medium. Background Art

[0002] In servers, the stability and reliability of certain integrated circuits (ICs) are crucial to their proper operation. Currently, some technologies collect and analyze IC operating data to monitor IC failures. In the event of an IC failure, an alarm is generated, allowing maintenance personnel to promptly address the issue and ensure proper server operation. However, these technologies only generate alarms after the IC has already failed. This means that by the time the IC failure is detected, the server's operational status may have already been affected. In other words, the stability and reliability of ICs remain relatively low. Summary of the Invention

[0003] The present application provides a fault preprocessing method, a fault preprocessing device, an electronic device, a computer-readable storage medium, and a computer program product to at least solve the problem of relatively low stability and reliability of integrated circuits in related technologies.

[0004] This application provides a fault pre-processing method, including:

[0005] Acquire historical operation information of a first integrated circuit, where the first integrated circuit is used to run target firmware, the historical operation information including at least one of historical hardware operation information and historical firmware operation information of the first integrated circuit;

[0006] Inputting the historical operation information into a fault prediction model to obtain a fault prediction result, the fault prediction result including a first fault that may occur in the first integrated circuit within a future target time period and a first probability of the first fault occurring;

[0007] If the first probability is within a preset probability range, a target pre-processing operation matching the first fault is performed, where the target pre-processing operation is used to prevent the first fault from occurring in the first integrated circuit.

[0008] The present application also provides a fault pre-processing device, comprising:

[0009] an information acquisition module, configured to acquire historical operation information of a first integrated circuit, where the first integrated circuit is configured to run target firmware, the historical operation information comprising at least one of historical hardware operation information and historical firmware operation information of the first integrated circuit;

[0010] a prediction module, configured to input the historical operation information into a fault prediction model to obtain a fault prediction result, wherein the fault prediction result includes a first fault that may occur in the first integrated circuit within a future target time period and a first probability of the first fault occurring;

[0011] A preprocessing module is configured to execute a target preprocessing operation that matches the first fault if the first probability is within a preset probability range, wherein the target preprocessing operation is configured to prevent the first fault from occurring in the first integrated circuit.

[0012] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned fault preprocessing methods when executing the computer program.

[0013] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned fault preprocessing methods are implemented.

[0014] In the technical solutions of some embodiments of the present application, based on historical operating information of a first integrated circuit, a first fault that may occur in the first integrated circuit within a future target time period and a first probability of the first fault occurring are predicted. In this way, before the first fault occurs in the first integrated circuit, a targeted preprocessing operation matching the first fault can be performed for a first fault whose first probability falls within a preset probability range, thereby preemptively avoiding or repairing the first fault and preventing the first fault from occurring. Because the first fault that may occur in the first integrated circuit within the future target time period is preemptively avoided or repaired, the stability and reliability of the integrated circuit can be improved, thereby resolving the relatively low stability and reliability issues of integrated circuits in related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 A flowchart of a fault pre-processing method provided in some embodiments of the present application;

[0017] Figure 2 An interactive schematic diagram of a fault pre-processing method provided in some embodiments of the present application;

[0018] Figure 3 A schematic diagram of a module of a fault pre-processing device provided in some embodiments of the present application;

[0019] Figure 4 A schematic diagram of a module of an electronic device provided for some embodiments of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or precedence.

[0022] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0023] In servers, some integrated circuits (ICs) run firmware to perform key operations during server operation. For example, the Basic Input / Output System (BIOS) can be considered a type of firmware. During the server startup process, the BIOS runs the integrated circuits that perform operations such as hardware initialization, power-on self-test, bootloader loading, and operating system startup. A failure in the integrated circuit running the BIOS can directly impact the server's startup and operation.

[0024] Integrated circuit (IC) failures typically include hardware failures and firmware failures. Hardware failures refer to physical hardware failure or malfunction of the IC, such as physical damage to the IC, excessive temperatures, voltage fluctuations, or loose physical connections between ICs. Firmware failures refer to errors in the firmware running on the IC, such as firmware version conflicts, firmware configuration errors, and firmware vulnerabilities.

[0025] Currently, some technologies monitor integrated circuit (IC) faults by collecting and analyzing their operational data. Specifically, this operational data can include hardware and firmware data. Hardware data includes, but is not limited to, the IC's operating voltage, component temperature, number of reboots, and firmware refreshes. Firmware data includes, but is not limited to, firmware operation logs. For example, if the collected operational data reveals that the IC's operating voltage significantly exceeds the rated operating voltage, it can be determined that the IC may have been damaged by the overvoltage. For another example, if the IC supports 100 firmware refreshes, and the collected firmware refresh count indicates that the firmware has been refreshed more than 100 times, it can be determined that the IC has failed. For another example, if the firmware operation log contains information such as server startup failure or firmware startup error codes, it can be determined that the IC has failed.

[0026] In these technologies, faults can usually only be detected when the hardware firmware has already failed. That is, when the integrated circuit fault is monitored, the operating status of the server may have been affected, and the stability and reliability of the integrated circuit are still relatively low.

[0027] In view of this, the present application provides a fault pre-processing method that can perform pre-processing operations in advance before an integrated circuit fault occurs to prevent the fault from occurring. In this way, the operating status of the server is not affected by the integrated circuit fault, greatly improving the stability and reliability of the integrated circuit.

[0028] The fault preprocessing method can be applied to a fault preprocessing system, or can be applied to an electronic device that runs a fault preprocessing system. Electronic devices may include, but are not limited to, a cloud management device of a server, a management controller in a server, and the like. Specifically, when the cloud management device runs the fault preprocessing system, the cloud management device can be connected to the server for communication. Based on technologies such as sensors and monitoring software, the cloud management device can collect operating information of a specified integrated circuit in the server, and based on the operating information, predict possible future failures of the integrated circuit, and then send control instructions to the server to perform preprocessing operations to prevent failures from occurring. When the management controller in the server runs the fault preprocessing system, the operations performed by the management controller are similar to those performed by the cloud management device, and will not be repeated here.

[0029] See also Figure 1 , which is a flow chart of a fault preprocessing method provided in some embodiments of the present application. Figure 1 In the fault pre-processing method, the fault pre-processing method includes the following steps:

[0030] Step S101 : acquiring historical operation information of a first integrated circuit, where the first integrated circuit is used to run target firmware, and the historical operation information includes at least one of historical hardware operation information and historical firmware operation information of the first integrated circuit.

[0031] Regarding the integrated circuit, firmware, hardware operation information, and firmware operation information, please refer to the above description and will not be repeated here. The target firmware may include but is not limited to BIOS firmware, BMC (Baseboard Management Controller) firmware, RAID (Redundant Array of Independent Disks) firmware, etc.

[0032] A sampling point may be set at a first preset time interval (e.g., 1 minute). At each sampling point, hardware and firmware operating information of the first integrated circuit may be collected. The collected information may be stored in a storage medium as historical operating information of the first integrated circuit. Thus, in step S101, historical operating information may be obtained from the storage medium.

[0033] In this embodiment, the hardware operation information and firmware operation information of the first integrated circuit within a specified time period before the current time point can be obtained as historical operation information. For example, assuming the current time point is 22:30, the hardware operation information and firmware operation information of the first integrated circuit from 22:20 to 22:30 can be obtained as historical operation information. The specified time period can be set according to actual needs, and this application does not impose any restrictions on this.

[0034] Step S102 : inputting historical operation information into a fault prediction model to obtain a fault prediction result, wherein the fault prediction result includes a first fault that may occur in the first integrated circuit within a future target time period and a first probability of the first fault occurring.

[0035] The fault prediction model can be a trained time series model. By analyzing the time series characteristics of historical operating information, the fault prediction model can predict the first fault that may occur in the first integrated circuit within a future target time period and the first probability of the first fault occurring. The future target time period can be set as needed, such as the next 10 minutes or the next 3 hours. This application does not impose any restrictions on this.

[0036] The fault prediction result may include multiple first faults and the first probability corresponding to each first fault. For example, the fault prediction result may include the following: the probability of fault A occurring is 30%; the probability of fault B occurring is 85%; and the probability of fault C occurring is 90%. Of course, it is understood that the fault prediction result may also include only one first fault and the first probability corresponding to the first fault, or if the first integrated circuit will not experience any faults within the target time period, the fault prediction result may be empty.

[0037] Step S103 : If the first probability is within a preset probability range, executing a target preprocessing operation that matches the first fault, where the target preprocessing operation is used to prevent the first fault from occurring in the first integrated circuit.

[0038] Specifically, when the first probability is within a preset probability range, it indicates that there is a high probability that the first integrated circuit will experience the first fault within the target time period. For example, assuming the preset probability range is 80% to 100%, this means that when the first probability is greater than 80%, there is a high probability that the first integrated circuit will experience the first fault within the target time period. In this case, a targeted preprocessing operation matching the first fault can be executed to prevent the first fault from occurring.

[0039] The target preprocessing operation can be understood as an early repair or avoidance operation for the first fault. Different first faults can match different target preprocessing operations. For example, suppose the first fault A is "the total number of firmware refreshes for the first integrated circuit will exceed the maximum number supported by the first integrated circuit", and the first fault B is "a version conflict will occur during the operation of the target firmware". For the above-mentioned first fault A, it means that the service life of the first integrated circuit has been reached and it cannot be repaired. In this case, the integrated circuit running the target firmware can be switched from the first integrated circuit to the second integrated circuit in advance before the first fault A occurs, thereby avoiding the occurrence of the first fault A. For the above-mentioned first fault B, it means that there is an error in the target firmware. In this case, the version of the target firmware can be updated in advance before the first fault B occurs. This version update process can be regarded as an early repair of the first fault B.

[0040] Of course, it is understandable that different first faults can also match the same target pre-processing operation. For example, suppose first fault C is "the target firmware version is too low during operation" and first fault D is "the target fault will encounter error code 0001 during operation." If the cause of first fault D is that the target firmware version is too low, then the target pre-processing operation matching first faults C and D can be the same, that is, the target firmware version is upgraded in advance before first faults C and D occur. In this way, first faults C and D can be repaired in advance at the same time.

[0041] In step S103, if there are multiple first faults whose first probabilities are within a preset probability range, and the target processing operations for the multiple first fault matches are different, the target pre-processing operations for each first fault match can be performed sequentially to prevent the occurrence of these first faults. If the target pre-processing operations for the multiple first fault matches are the same, the target pre-processing operation can be performed only once for the multiple first fault matches.

[0042] The electronic device executing the method of the present application can execute the target preprocessing operation by issuing a control instruction, for example, issuing a switching instruction to switch the integrated circuit running the target firmware from the first integrated circuit to the second integrated circuit.

[0043] In summary, in the technical solutions of some embodiments of the present application, based on historical operating information of a first integrated circuit, a first fault that may occur in the first integrated circuit within a future target time period and a first probability of the first fault occurring are predicted. In this way, before the first fault occurs in the first integrated circuit, a targeted preprocessing operation matching the first fault can be performed for a first fault whose first probability falls within a preset probability range, thereby preemptively avoiding or repairing the first fault and preventing the first fault from occurring. Because the first fault that may occur in the first integrated circuit within the future target time period is preemptively avoided or repaired, the stability and reliability of the integrated circuit can be improved, thereby resolving the relatively low stability and reliability issues of integrated circuits in related technologies.

[0044] The solution of this application is further explained below.

[0045] In some embodiments, if a second fault, different from the first fault, occurs in the first integrated circuit within a target time period, this indicates that the fault prediction model's prediction is inaccurate. In this case, the prediction logic of the fault prediction model can be optimized based on the historical operating information and the second fault. For example, the second fault can be used as a label, the historical operating information can be input into the fault prediction model, and the model parameters of the fault prediction model can be fine-tuned to achieve the purpose of optimizing the prediction logic. After the prediction logic optimization is completed, the historical operating information is input into the fault prediction model. The resulting fault prediction result can include the second fault and a second probability of the second fault occurring, and the second probability is within a preset probability range.

[0046] In the above embodiment, the fault prediction model may be optimized online during actual use of the fault prediction model, thereby improving the prediction accuracy of the fault prediction model.

[0047] In some embodiments, in the above step 103, a target preprocessing operation that matches the first fault can be searched based on a pre-established operation library. Specifically, the operation library may include at least one fault and at least one preprocessing operation associated with each fault. For any fault, when the fault is associated with multiple preprocessing operations, it means that in order to prevent the occurrence of the fault, there may be multiple different preprocessing operations. In the actual operation process, it is sufficient to execute one of the preprocessing operations. Each preprocessing operation may have a reliability, and the reliability represents the success rate of the preprocessing operation in preventing the occurrence of the fault. For ease of understanding, Table 1 gives an example of an operation library:

[0048] Table 1 Operation Library

[0049]

[0050] Table 1 uses Fault A as an example. If the probability of Fault A occurring in the first integrated circuit during a future target period falls within a preset probability range, either preprocessing operation A1 or preprocessing operation A2 can be performed to prevent Fault A from occurring. When preprocessing operation A1 is performed, the success rate for preventing Fault A is 0.95, while when preprocessing operation A2 is performed, the success rate for preventing Fault A is 0.7.

[0051] Based on the above description, in step 103, when executing the target preprocessing operation that matches the first fault, a pre-established operation library can be accessed and the first fault and the preprocessing operation associated with the first fault can be searched in the operation library. If the first fault is associated with multiple preprocessing operations, the preprocessing operation with the highest reliability associated with the first fault is selected as the target preprocessing operation and executed.

[0052] In the above embodiment, the pre-processing operation with the highest reliability associated with the first fault is used as the target pre-processing operation, which can improve the success rate of avoiding or repairing the first fault.

[0053] In some embodiments, after executing a target preprocessing operation, if a first fault occurs in the first integrated circuit within a target time period, the target preprocessing operation failed to prevent the occurrence of the first fault. In this case, the actual processing operation used to resolve the first fault can be obtained. The actual processing operation refers to the actual operation performed by maintenance personnel to resolve the first fault after the first fault actually occurred. If the preprocessing operation associated with the first fault in the operation library includes the actual processing operation, the reliability of the actual processing operation can be increased, and the reliability of the target preprocessing operation can be reduced.

[0054] Specifically, the single change rate of reliability can be set, such as 0.05. When the target preprocessing operation is used to prevent the first fault from occurring, each time it fails, the reliability of the target preprocessing operation can be gradually reduced according to the single change rate until the reliability of the target preprocessing operation changes to 0. Conversely, when the target preprocessing operation is used to prevent the first fault from occurring, each time it succeeds, the reliability of the target preprocessing operation can be gradually increased according to the single change rate until the reliability of the target preprocessing operation changes to 1. Similarly, the reliability of the actual processing operation can also be adjusted according to a similar principle. For example, assuming that the current reliability of the target preprocessing operation is 0.95 and the current reliability of the actual processing operation is 0.8. After the first failure to prevent the first fault based on the target preprocessing operation, if the first fault is successfully resolved based on the actual processing operation, the reliability of the target preprocessing operation can be adjusted to 0.9, and at the same time, the reliability of the actual processing operation can be adjusted to 0.85. After the target preprocessing operation fails to prevent the first fault from occurring again for the second time, if the first fault is successfully resolved again based on the actual processing operation, the reliability of the target preprocessing operation can be adjusted to 0.85, and the reliability of the actual processing operation can be adjusted to 0.9.

[0055] In this way, after multiple adjustments, the reliability of each preprocessing operation in the operation library can be relatively accurate. After taking the preprocessing operation with the highest reliability as the target preprocessing operation, the success rate of preventing the first fault from occurring can be relatively high, thereby further improving the reliability and stability of the first integrated circuit.

[0056] In some embodiments, if the pre-processing operation associated with the first fault in the operation library does not include the actual processing operation, the actual processing operation can be used as the pre-processing operation, and the first fault can be associated with the actual processing operation. After establishing the association between the first fault and the actual processing operation, the reliability of the actual processing operation can be set to a preset initial reliability, such as 0.5. In the subsequent fault handling process, when preventing the first fault from occurring based on the actual processing operation, the reliability of the actual processing operation can be dynamically adjusted based on the number of successes and failures.

[0057] In some embodiments, the target preprocessing operation of the present application may include at least one of the following operations 11) and 12):

[0058] 11) When the first fault is unrepairable, the integrated circuit running the target firmware is switched from the first integrated circuit to a second integrated circuit, where the second integrated circuit is a backup integrated circuit running the target firmware. Specifically, the first integrated circuit and the second integrated circuit may be a primary integrated circuit and a backup integrated circuit deployed in the server for running the target firmware, and the target firmware is stored in both the first integrated circuit and the second integrated circuit. Under normal circumstances, the first integrated circuit can run the target firmware, while the second integrated circuit may not. However, after the integrated circuit running the target firmware is switched from the first integrated circuit to the second integrated circuit, the first integrated circuit can stop running the target firmware and the second integrated circuit can run the target firmware instead. In this way, when the first fault of the first integrated circuit is unrepairable, the normal operation of the target firmware and the normal operation of the server can be guaranteed. For example, if the first integrated circuit is damaged due to excessive operating voltage, the first fault of the first integrated circuit is unrepairable. In this case, the integrated circuit running the target firmware can be switched from the first integrated circuit to the second integrated circuit, and the second integrated circuit can run the target firmware. Because the integrated circuit switch is performed before the first fault occurs in the first integrated circuit, the operation of the server will not be affected by the failure of the first integrated circuit, greatly improving the stability and reliability of the integrated circuit.

[0059] In some embodiments, when switching an integrated circuit running target firmware from a first integrated circuit to a second integrated circuit, a consistency comparison can be performed between the target firmware in the first integrated circuit and the target firmware in the second integrated circuit. If the consistency comparison passes, the integrated circuit running the target firmware can be switched from the first integrated circuit to the second integrated circuit. Specifically, a first hash value can be generated for the target firmware in the first integrated circuit and a second hash value can be generated for the target firmware in the second integrated circuit based on the SHA-256 or MD5 algorithm. If the first hash value and the second hash value are the same, it indicates that the consistency comparison has passed; if the first hash value and the second hash value are different, it indicates that the consistency comparison has failed.

[0060] In the above embodiment, consistency comparison can ensure the accuracy of the target firmware in the second integrated circuit, preventing tampering with the target firmware in the second integrated circuit while the first integrated circuit is running the target firmware. It is understandable that if the target firmware in the second integrated circuit is tampered with, then after the integrated circuit running the target firmware is switched from the first integrated circuit to the second integrated circuit, the second integrated circuit is likely to experience a malfunction caused by incorrect target firmware execution, thereby affecting the normal operation of the server. Therefore, performing consistency comparison on the target firmware before switching integrated circuits can further improve the reliability of the integrated circuits.

[0061] 12) When the first fault is a repairable fault, repair the first fault, wherein repairing the first fault includes repairing a hardware fault of the first integrated circuit and / or repairing a firmware error of the target firmware.

[0062] In some embodiments, when repairing a firmware error in the target firmware, the target firmware in the first integrated circuit can be copied to a firmware cache, and the target firmware can be repaired in the firmware cache to obtain the repaired target firmware. Since the target firmware is repaired in the firmware cache (i.e., the target firmware is not repaired directly in the first integrated circuit), the first integrated circuit can continue to run the pre-repair target firmware during the target firmware repair process without interrupting server operation, thereby ensuring the stability and reliability of the integrated circuit.

[0063] After the target firmware is repaired, the repaired target firmware can be used to replace the target firmware in the first integrated circuit, so that the first integrated circuit can run the repaired target firmware. In this way, the target firmware is repaired in advance before the target firmware is released, thereby ensuring the stability and reliability of the integrated circuit.

[0064] Furthermore, during the repair process of the target firmware, repair errors may occur. In the event of a firmware repair error, after the repaired target firmware is replaced in the first integrated circuit, the first integrated circuit may experience a firmware operation error. To avoid affecting the normal operation of the server, the repaired target firmware can be promptly rolled back to the pre-repair target firmware.

[0065] In view of this, in some embodiments, when repairing a firmware error in the target firmware, the target firmware in the first integrated circuit can also be copied to the firmware backup area. If the first integrated circuit fails to run the repaired target firmware, the target firmware in the firmware backup area can be used to replace the target firmware in the first integrated circuit, thereby rolling back the target firmware in the first integrated circuit. In this way, in the event of a firmware repair error, the impact on the server can be minimized.

[0066] Furthermore, in some embodiments, after the target firmware is copied to the firmware backup area, the hash value of the target firmware in the firmware backup area can be periodically updated at a second preset time interval, and the hash values at different time points can be saved. Before using the target firmware in the firmware backup area to replace the target firmware in the first integrated circuit, the hash values at each time point can be checked to see if they are consistent. If they are consistent, the target firmware can be rolled back. If they are inconsistent, it indicates that the target firmware in the firmware backup area has been tampered with, and the rollback of the target firmware can be stopped. In this way, the wrong target firmware can be prevented from being replaced in the first integrated circuit, thereby ensuring the security of the server.

[0067] In some embodiments, key operations in fault pre-processing can be saved to the blockchain. These key operations may include, but are not limited to, switching integrated circuits, upgrading / modifying / rolling back target firmware, etc. This ensures traceability of operations.

[0068] In some embodiments, before the above step S102, the fault prediction model may be trained based on the following steps 21) to 24).

[0069] 21) Simulating the first integrated circuit and a plurality of different faults that may occur in the first integrated circuit through a simulation environment, and collecting hardware operation information and firmware operation information of the first integrated circuit as first sample data before the fault occurs.

[0070] 22) Simulating the first integrated circuit and the normal operating state of the first integrated circuit through a simulation environment, and collecting hardware operating information and firmware operating information of the first integrated circuit as second sample data when the first integrated circuit is in the normal operating state.

[0071] 23) The first sample data is labeled with the fault identifier of each fault, and the second sample data is labeled with the status identifier representing the normal operating status.

[0072] 24) Training a fault prediction model based on the labeled first sample data and the second sample data.

[0073] In the above embodiment, relatively rich sample data can be collected by simulating the simulation environment. Based on the rich sample data, the training accuracy of the fault prediction model can be improved.

[0074] See also Figure 2 , which is an interactive schematic diagram of the fault preprocessing method provided in some embodiments of the present application. Figure 2 In the embodiment of the present invention, the decision module 211, the repair module 212, the image management module 213 and the data preprocessing module 214 can be deployed in an electronic device that executes the method of the present application. The dynamic switching controller 221, the baseboard management controller 222, the first integrated circuit 223, the second integrated circuit 224 and the data acquisition module 225 can be deployed in a server. Among them, the data acquisition module 225 may include but is not limited to sensors, data acquisition software, etc. Based on the data acquisition module 225, the hardware operation data and firmware operation data (i.e., hardware operation information and firmware operation information) of the first integrated circuit 223 and the second integrated circuit 224 can be collected. After these data are processed by the data preprocessing module 214 (such as data cleaning, data format conversion, etc.), they can be saved to the decision module 211 as historical operation data (i.e., historical operation information).

[0075] If the decision module 211 determines, based on historical operating data, that the first integrated circuit 223 has a first, unrepairable fault, it may issue a first switching instruction to the dynamic switching controller 221. Based on the first switching instruction, the dynamic switching controller 221 may issue a second switching instruction to the baseboard management controller 222. Based on the second switching instruction, the baseboard management controller 222 may switch between the first integrated circuit 223 and the second integrated circuit 224 running the target firmware.

[0076] If the decision module 211 determines based on historical operating data that the target firmware in the first integrated circuit 223 needs to be repaired, it can issue a repair instruction to the repair module 212. The repair module 212 can perform operations such as repair, backup, and rollback on the target firmware in the first integrated circuit 223 through the image management module 213.

[0077] This completes the entire description of the application method.

[0078] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0079] See also Figure 3 , which is a module diagram of a fault preprocessing device provided in some embodiments of the present application. Figure 3 In the present invention, the fault preprocessing device includes:

[0080] An information acquisition module 301 is configured to acquire historical operation information of a first integrated circuit, where the first integrated circuit is configured to run target firmware, the historical operation information including at least one of historical hardware operation information and historical firmware operation information of the first integrated circuit;

[0081] A prediction module 302 is configured to input historical operation information into a fault prediction model to obtain a fault prediction result, wherein the fault prediction result includes a first fault that may occur in the first integrated circuit within a future target time period and a first probability of the first fault occurring;

[0082] The preprocessing module 303 is configured to execute a target preprocessing operation that matches the first fault if the first probability is within a preset probability range, wherein the target preprocessing operation is configured to prevent the first fault from occurring in the first integrated circuit.

[0083] In some embodiments, the prediction module 302 is further configured to:

[0084] If a second fault different from the first fault occurs in the first integrated circuit within the target time period, the prediction logic of the fault prediction model is optimized based on the historical operating information and the second fault. After the prediction logic optimization is completed, the historical operating information is input into the fault prediction model, and the obtained fault prediction result includes the second fault and a second probability of the second fault occurring, and the second probability is within a preset probability range.

[0085] In some embodiments, the pre-processing module 303 is specifically configured to:

[0086] Accessing a pre-established operation library, the operation library including at least one fault and at least one pre-processing operation associated with each fault, wherein for any fault, when the fault is associated with multiple pre-processing operations, each pre-processing operation has a reliability, and the reliability represents a success rate of the pre-processing operation in preventing the fault from occurring;

[0087] Searching for a first fault and a pre-processing operation associated with the first fault in an operation library;

[0088] If the first fault is associated with multiple pre-processing operations, the pre-processing operation with the highest reliability associated with the first fault is used as the target pre-processing operation, and the target pre-processing operation is executed.

[0089] In some embodiments, the pre-processing module 303 is further configured to:

[0090] After executing the target pre-processing operation, if the first integrated circuit has a first fault within the target time period, obtaining an actual processing operation for resolving the first fault;

[0091] If the pre-processing operation associated with the first fault includes the actual processing operation in the operation library, the reliability of the actual processing operation is increased, and the reliability of the target pre-processing operation is decreased;

[0092] If the pre-processing operation associated with the first fault does not include the actual processing operation in the operation library, the actual processing operation is used as the pre-processing operation, and the first fault is associated with the actual processing operation.

[0093] In some embodiments, the target preprocessing operation performed by the preprocessing module 303 includes at least one of the following operations:

[0094] When the first fault is an unrepairable fault, switching the integrated circuit running the target firmware from the first integrated circuit to a second integrated circuit, wherein the second integrated circuit is a candidate integrated circuit running the target firmware;

[0095] When the first fault is a repairable fault, the first fault is repaired, wherein repairing the first fault includes repairing a hardware fault of the first integrated circuit and / or repairing a firmware error of the target firmware.

[0096] In some embodiments, when repairing a firmware error of the target firmware, the pre-processing module 303 is further configured to:

[0097] Copying the target firmware in the first integrated circuit to the firmware cache area and the firmware backup area;

[0098] Repairing the target firmware in the firmware cache area to obtain the repaired target firmware;

[0099] replacing the target firmware in the first integrated circuit with the repaired target firmware;

[0100] If the first integrated circuit fails to run the repaired target firmware, the target firmware in the first integrated circuit is replaced with the target firmware in the firmware backup area to roll back the target firmware in the first integrated circuit.

[0101] In some embodiments, the pre-processing module 303 is specifically configured to:

[0102] A consistency comparison is performed between the target firmware in the first integrated circuit and the target firmware in the second integrated circuit. If the consistency comparison passes, the integrated circuit running the target firmware is switched from the first integrated circuit to the second integrated circuit.

[0103] For the description of the features in the embodiment corresponding to the fault pre-processing device, reference can be made to the relevant description of the embodiment corresponding to the sample data processing method, which will not be repeated here.

[0104] See also Figure 4 An embodiment of the present application further provides an electronic device, comprising a memory 10 and a processor 20, wherein the memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any one of the above-mentioned fault preprocessing method embodiments.

[0105] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned fault preprocessing method embodiments when running.

[0106] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0107] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned fault preprocessing method embodiments are implemented.

[0108] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned fault preprocessing method embodiments are implemented.

[0109] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0110] The above is a detailed introduction to a fault pre-processing method, device, equipment and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A fault preprocessing method, characterized in that: The method comprises: Acquire historical operation information of a first integrated circuit, where the first integrated circuit is used to run target firmware, the historical operation information including at least one of historical hardware operation information and historical firmware operation information of the first integrated circuit; Inputting the historical operation information into a fault prediction model to obtain a fault prediction result, the fault prediction result including a first fault that may occur in the first integrated circuit within a future target time period and a first probability of the first fault occurring; If the first probability is within a preset probability range, a target pre-processing operation matching the first fault is performed, where the target pre-processing operation is used to prevent the first fault from occurring in the first integrated circuit.

2. The method according to claim 1, characterized in that The method further comprises: If a second fault different from the first fault occurs in the first integrated circuit within the target time period, the prediction logic of the fault prediction model is optimized based on the historical operation information and the second fault, wherein after the prediction logic optimization is completed, the historical operation information is input into the fault prediction model, and the obtained fault prediction result includes the second fault and a second probability of the occurrence of the second fault, and the second probability is within the preset probability range.

3. The method according to claim 1 or 2, characterized in that The performing of a target pre-processing operation matching the first fault includes: accessing a pre-established operation library, the operation library including at least one fault and at least one pre-processing operation associated with each fault, wherein for any of the faults, when the fault is associated with multiple pre-processing operations, each pre-processing operation has a reliability, the reliability representing a success rate of the pre-processing operation in preventing the fault from occurring; Searching the operation library for the first fault and a pre-processing operation associated with the first fault; If the first fault is associated with multiple pre-processing operations, the pre-processing operation with the highest reliability associated with the first fault is used as the target pre-processing operation, and the target pre-processing operation is executed.

4. The method according to claim 3, characterized in that The method further comprises: After executing the target pre-processing operation, if the first fault occurs in the first integrated circuit within the target time period, obtaining an actual processing operation for resolving the first fault; If, in the operation library, the pre-processing operation associated with the first fault includes the actual processing operation, the reliability of the actual processing operation is increased, and the reliability of the target pre-processing operation is decreased; If the pre-processing operation associated with the first fault in the operation library does not include the actual processing operation, the actual processing operation is used as the pre-processing operation, and the first fault is associated with the actual processing operation.

5. The method according to claim 1 or 2, characterized in that The target preprocessing operation includes at least one of the following operations: When the first fault is an unrepairable fault, switching the integrated circuit running the target firmware from the first integrated circuit to a second integrated circuit, wherein the second integrated circuit is a backup integrated circuit running the target firmware; When the first fault is a repairable fault, the first fault is repaired, wherein repairing the first fault includes repairing a hardware fault of the first integrated circuit and / or repairing a firmware error of the target firmware.

6. The method according to claim 5, characterized in that When repairing the firmware error of the target firmware, the method further includes: Copying the target firmware in the first integrated circuit to a firmware cache area and a firmware backup area; Repairing the target firmware in the firmware cache area to obtain repaired target firmware; replacing the target firmware in the first integrated circuit with the repaired target firmware; If the first integrated circuit fails to run the repaired target firmware, the target firmware in the first integrated circuit is replaced with the target firmware in the firmware backup area to roll back the target firmware in the first integrated circuit.

7. The method according to claim 5, characterized in that Switching the integrated circuit running the target firmware from the first integrated circuit to the second integrated circuit includes: A consistency comparison is performed on the target firmware in the first integrated circuit and the target firmware in the second integrated circuit. If the consistency comparison passes, the integrated circuit running the target firmware is switched from the first integrated circuit to the second integrated circuit.

8. A fault pre-processing device, characterized in that: The device comprises: an information acquisition module, configured to acquire historical operation information of a first integrated circuit, where the first integrated circuit is configured to run target firmware, the historical operation information comprising at least one of historical hardware operation information and historical firmware operation information of the first integrated circuit; a prediction module, configured to input the historical operation information into a fault prediction model to obtain a fault prediction result, wherein the fault prediction result includes a first fault that may occur in the first integrated circuit within a future target time period and a first probability of the first fault occurring; A preprocessing module is configured to execute a target preprocessing operation that matches the first fault if the first probability is within a preset probability range, wherein the target preprocessing operation is configured to prevent the first fault from occurring in the first integrated circuit.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the fault preprocessing method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the fault preprocessing method according to any one of claims 1 to 7.

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