Preparation method of FD-SOI substrate structure through hydrogen and carbon ion implantation process

Abstract

The invention discloses a preparation method of an FD-SOI substrate structure through a hydrogen and carbon ion implantation technology, and belongs to the technical field of semiconductor design and manufacturing, and the preparation method comprises the following steps: preparing a first wafer and a second wafer; performing thermal oxidation treatment on the surface of the first wafer; performing hydrogen ion implantation and carbon ion implantation on the first wafer; combining the surface of the insulating oxide layer of the first wafer with a second wafer through a bonding process; stripping the first wafer along the hydrogen injection layer, forming a top-layer silicon film on the second wafer on the part, except the insulating oxide layer, of the remaining first wafer, and recrystallizing the top-layer silicon film through thermal annealing treatment; and etching the top-layer silicon thin film to be below the carbon injection layer through wet etching treatment, so that the top-layer silicon thin film reaches the required thickness. The substrate structure prepared by the method is smooth in surface, few in surface and structure internal defects, controllable in top silicon film thickness and good in film uniformity, and is especially suitable for forming a nanoscale ultrathin film.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor design and manufacturing, and in particular relates to a method for preparing an FD-SOI substrate structure through a hydrogen and carbon ion implantation process. Background Art

[0002] As bulk CMOS (bulk silicon CMOS) technology nodes move below 28nm and transistor feature sizes continue to shrink, short channel effects (SCE) are becoming increasingly prominent, necessitating innovative manufacturing processes for further advancement. Traditional planar MOSFET structures are no longer suitable. Among potential technologies, FD-SOI (Fully Depleted Silicon on Insulator) technology is highly competitive and a promising solution for advanced chips. Transistors fabricated with FD-SOI technology utilize a thin silicon film that defines the source-drain junction depth and depletion region, mitigating short channel effects such as DIBL (Drain Induced Barrier Lowering), further improving device subthreshold characteristics, and reducing static power consumption. Furthermore, FD-SOI transistors require no channel doping, avoiding effects such as RDF (Random Dopant Fluctuation) and reduced carrier mobility, maintaining a stable threshold voltage (Vth). Unlike the 3D transistor structure used in the FinFET process, FD-SOI is a planar process technology that effectively reduces process complexity. Compared with traditional bulk silicon technology, FD-SOI provides better transistor electrostatic characteristics, and the buried oxide layer can reduce the parasitic capacitance between the source and drain. In addition, this technology can effectively limit the flow of electrons between the source and drain, significantly reducing the device's leakage current performance. In addition to controlling the gate, FD-SOI can also control transistor behavior through the device's bottom substrate, achieving back bias control.

[0003] However, if transistors with smaller feature sizes are to be obtained, an ultra-thin top silicon film needs to be formed in the FD-SOI substrate structure. The existing preparation method is to use chemical mechanical polishing to form the film layer structure, but there is a problem of difficulty in controlling the layer thickness, and the wafer edge (Wafer Edge) is prone to a large thickness drop (for example, more than 10%), and surface scratches may also occur. In the existing FD-SOI technology, the prepared top silicon film is relatively thick, so the impact of the above defects on performance is not very significant; for ultra-thin top silicon films, such as nanometer-level, the above defects will significantly affect performance. Therefore, a new preparation method is needed to achieve a thinner top silicon film and higher dimensional accuracy. Summary of the Invention

[0004] Based on the technical problems existing in the prior art, the present invention provides a method for preparing an FD-SOI substrate structure through a hydrogen and carbon ion implantation process, which solves the problems in the prior art of the FD-SOI substrate structure in which the thickness of the top silicon ultra-thin film is difficult to control, the film thickness at the crystal edge is uneven, and there are many defects. The method achieves beneficial effects such as more controllable process precision, a smoother device surface, and fewer internal defects, thereby significantly reducing the characteristic size of semiconductor devices and improving the performance of semiconductor devices.

[0005] According to the technical solution of the present invention, the present invention provides a method for preparing an FD-SOI substrate structure by hydrogen and carbon ion implantation, comprising the following steps performed in sequence:

[0006] Step S1, preparing a first wafer and a second wafer, where both the first wafer and the second wafer are bare wafer substrates;

[0007] Step S2, performing thermal oxidation treatment on the surface of the first wafer to form an insulating oxide layer on the surface of the first wafer;

[0008] Step S3, performing hydrogen ion implantation and carbon ion implantation processes on the first wafer, so that a hydrogen implantation layer is formed below the insulating oxide layer of the first wafer, and a carbon implantation layer is formed between the hydrogen implantation layer and the insulating oxide layer;

[0009] Step S4, after cleaning the surfaces of the first wafer and the second wafer, bonding the surface of the insulating oxide layer of the first wafer to the second wafer through a bonding process;

[0010] Step S5, peeling the first wafer along the hydrogen implantation layer, forming a top silicon film on the second wafer at the portion of the remaining first wafer outside the insulating oxide layer, and then performing a thermal annealing process to recrystallize the top silicon film;

[0011] Step S6: etching the top silicon film to below the carbon implantation layer by wet etching, so that the top silicon film reaches a desired thickness.

[0012] In some embodiments, the insulating oxide layer is a silicon dioxide layer.

[0013] In some embodiments, in step S3 , the dosage of hydrogen ion implantation is higher than the dosage of carbon ion implantation.

[0014] In some embodiments, in step S3, the process parameters of hydrogen ion implantation include implantation energy: 50 keV to 200 keV, and implantation dose: 1×1016 atoms / cm2 to 1×1018 atoms / cm2; and / or, the process parameters of carbon ion implantation include implantation energy: 50 eV to 10 keV, and implantation dose: 1×1014 atoms / cm2 to 1×1016 atoms / cm2.

[0015] In some embodiments, in step S3 , the temperature condition for hydrogen ion implantation is ≤60° C.; and / or the temperature condition for carbon ion implantation is ≤0° C.

[0016] In some embodiments, in step S4, the bonding process is a low-temperature bonding process, and the bonding process temperature is ≤200°C.

[0017] In some embodiments, in step S5 , the thermal annealing treatment is a high-temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is ≥500° C.

[0018] In some embodiments, after step S6, the top silicon film reaches a desired ultra-thin thickness, which is ≤20 nm.

[0019] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0020] In the preparation method of the FD-SOI substrate structure of the present invention through the hydrogen and carbon ion implantation process, an ion implantation and a wet etching process are combined; by injecting hydrogen ions, a relatively flat weakened layer is formed at a certain depth position on the substrate surface to facilitate subsequent stripping; then carbon ions are injected to form a relatively flat ion diffusion barrier layer at another relatively shallow depth position, and the larger carbon ions are used to block the diffusion of hydrogen ions to the substrate surface. At the same time, the carbon ions will not cause changes to the top silicon film on the device; the ion diffusion barrier layer formed by the carbon ion implantation is also a wet etching barrier layer. When the wet etching process is subsequently performed, when etching reaches the wet etching barrier layer, the etching speed will slow down significantly. The occurrence of this phenomenon indicates that the etching has reached the position of this layer. At this time, stopping etching can retain the required film thickness. In this way, the top silicon film can be effectively controlled to reach the required ultra-thin thickness, and the wet etching process makes the film uniform, which can achieve a thickness drop of less than 2% and no surface defects. The surface of the FD-SOI substrate structure prepared by the method of the present invention is relatively flat, with few surface and internal defects of the structure, and can maintain good single crystallinity. The method of the present invention is particularly suitable for situations where advanced processes require the top silicon film to reach an ultra-thin thickness of nanometer level, and can form the required high-quality nanometer-level ultra-thin film, which is of great significance for the application of FD-SOI technology in semiconductor devices with smaller feature sizes. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a flow chart of the method provided by the present invention.

[0022] Figures 2 to 8 It is a structural schematic diagram of the process of gradually obtaining the FD-SOI substrate structure using the method of the present invention.

[0023] Description of reference numerals in the accompanying drawings:

[0024] A. First wafer; B. Second wafer; 1. Insulating oxide layer; 2. Hydrogen injection layer; 3. Carbon injection layer; 4. Top silicon film; 5. Substrate. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0026] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features of the embodiments of the present invention may be combined with each other.

[0027] It should be noted that the concepts of "first" and "second" mentioned in the present invention are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0028] It should be noted that the modifications of "one" and "multiple" mentioned in the present invention are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0029] The present invention provides a method for preparing an FD-SOI substrate structure by hydrogen and carbon ion implantation processes, in other words, a method for preparing an FD-SOI substrate structure including hydrogen and carbon ion implantation processes, belonging to the field of semiconductor design and manufacturing. A typical preparation method includes: (1) preparing two wafer substrate bare chips A and B; (2) performing thermal oxidation treatment on the surface of wafer A; (3) performing hydrogen ion implantation and low-temperature carbon ion implantation processes on wafer A; (4) cleaning the surfaces of wafers A and wafer B first, and then performing low-temperature bonding; (5) peeling wafer A to form a top silicon film, and then performing high-temperature thermal annealing treatment to allow the top silicon film to recrystallize; (6) using wet etching to etch the top silicon to an ultra-thin film. Without changing the FD-SOI substrate structure, the present invention improves the preparation method of FD-SOI, solving the problems in the prior art of the FD-SOI substrate structure such as the difficulty in controlling the thickness of the top silicon ultra-thin film, the uneven thickness of the crystal edge film, and the large number of defects. The present invention achieves beneficial effects such as more controllable process precision, a smoother device surface, and fewer internal defects, thereby significantly reducing the characteristic size of semiconductor devices and improving the performance of semiconductor devices.

[0030] See also Figures 1 to 8 The present invention provides a method for preparing an FD-SOI substrate structure through hydrogen and carbon ion implantation, comprising the following steps performed in sequence.

[0031] Step S1, prepare a first wafer A and a second wafer B, both of which are wafer substrate bare chips. This step S1 corresponds to Figure 2 The initial state is shown.

[0032] Step S2, thermally oxidize the surface of the first wafer A to form a high-quality insulating oxide layer 1 on the surface of the first wafer A. In the embodiment, the insulating oxide layer 1 is a silicon dioxide layer. The state after this step S2 is as follows Figure 3 shown.

[0033] In step S3, hydrogen ion implantation and carbon ion implantation are performed on the first wafer A. Through the two ion implantation processes, a hydrogen implantation layer 2 is formed below the insulating oxide layer 1 of the first wafer A, and a carbon implantation layer 3 is formed between the hydrogen implantation layer 2 and the insulating oxide layer 1. In a typical embodiment, the two ion implantation processes in step S3 are to sequentially implant a high dose of hydrogen ions (at room temperature) and a low dose of carbon ions (at low temperature). The state of hydrogen ion implantation in this step S3 is as follows: Figure 4 As shown, the state of low temperature carbon ion implantation is as follows Figure 5 shown.

[0034] Step S4, after cleaning the surfaces of the first wafer A and the second wafer B, the surface of the insulating oxide layer 1 of the first wafer A is bonded to the second wafer B through a bonding process. In the embodiment, the bonding process is performed by flipping the first wafer A over and placing it upside down on the upper surface of the second wafer B. Preferably, the bonding process is a low-temperature bonding process, and the bonding process temperature is, for example, ≤200°C. The state after this step S4 is as follows Figure 6 shown.

[0035] In step S5, the first wafer A is peeled off along the hydrogen injection layer 2 (i.e., based on the precise position of the weakened layer region formed in the previous step), and the remaining first wafer A forms the top silicon film 4 on the second wafer B in the portion outside the insulating oxide layer 1, and then the top silicon film 4 is recrystallized by thermal annealing. Preferably, the thermal annealing is a high-temperature thermal annealing, and the temperature of the thermal annealing is, for example, ≥500°C. The state of the peeling process in this step S5 is as follows: Figure 7 shown.

[0036] Step S6, etching the top silicon film 4 to below the carbon injection layer 3 by wet etching, so that the top silicon film 4 reaches the desired thickness; wherein, the carbon injection layer 3 formed by wet etching and the previous process can accurately control the thickness of the top silicon film 4. Preferably, after step S6, the top silicon film 4 reaches the desired ultra-thin thickness, which is ≤20nm. The state after this step S6 is as follows Figure 8 As shown, an FD-SOI substrate structure is obtained, which is a substrate 5 (formed by the second wafer B), an insulating oxide layer 1 and a top silicon film 4 stacked in sequence.

[0037] The key concepts and principles of the present invention are as follows.

[0038] In step S3, hydrogen ions are first implanted. These smaller ions are driven deeper into the substrate, forming a bubble-like structure that serves as a weakened layer within the substrate structure, also known as hydrogen-implanted layer 2. Because this layer is a weak link in the substrate, it can be stripped along this layer in step S5, yielding a preliminary top layer structure for the FD-SOI. High-dose hydrogen ion implantation is preferred because, compared to low-dose implantation, high-dose implantation can make hydrogen-implanted layer 2 more flat, resulting in a smoother surface after stripping.

[0039] After the hydrogen ion implantation, carbon ions are then implanted to form a barrier layer, namely the carbon implantation layer 3. The injected hydrogen diffuses, forming the carbon implantation layer 3 above the hydrogen implantation layer 2. Since the carbon ions are larger, they can block the diffusion of hydrogen, preventing hydrogen from diffusing above the carbon implantation layer 3. This ensures that the portion above the carbon implantation layer 3 (i.e., the resulting top silicon film 4) is free of hydrogen, thus avoiding any impact on device performance. The carbon ion implantation is preferably low-dose, as a small amount of carbon has little effect on the performance of silicon substrate devices. However, it is also considered doping and is sufficient to achieve its effect. Too much carbon is not necessary, as it can have negative effects, such as negative electrical effects, significant lattice damage, and impact on the recrystallization repair process during subsequent thermal annealing.

[0040] For the diffusion of hydrogen ions, the carbon injection layer 3 is an ion diffusion barrier, and for the wet etching step, the carbon injection layer 3 is also a wet etching barrier. When wet etching is performed in step S6, the etching speed above the carbon injection layer 3 (i.e., the etching speed for the silicon substrate) will be very fast. When etching to the carbon injection layer 3, the etching speed will be significantly reduced. If the carbon injection layer 3 is completely etched away and the substrate below is continued to be etched, the etching speed will become faster again. Therefore, it can be known that the substrate has been etched to the position of the carbon injection layer 3 through the etching speed (which will be directly reflected in the corresponding etching equipment or can be obtained in real time through data processing). This makes it easy to stop etching through manual control or automatic system control, so that the top silicon film 4 retains the required ultra-thin thickness.

[0041] As a supplemental note, the depth of hydrogen-implanted layer 2 and carbon-implanted layer 3 is determined by the implantation energy. For the same type of ions, a greater implantation energy results in deeper ion penetration below the substrate surface. Consistent implantation of ions with consistent energy results in a layer structure of a specific depth. The implantation depths and corresponding implantation energies of hydrogen-implanted layer 2 and carbon-implanted layer 3 are designed to achieve the desired effect, particularly for carbon ion implantation. The location of carbon-implanted layer 3 is directly related to the thickness of the resulting top silicon film 4.

[0042] Preferably, in step S3, the dose of hydrogen ion implantation is higher than the dose of carbon ion implantation. Further, the process parameters of hydrogen ion implantation include, for example, implantation energy: 50keV to 200keV, implantation dose: 1×1016atoms / cm2 to 1×1018atoms / cm2; and / or the process parameters of carbon ion implantation include, for example, implantation energy: 50eV to 10keV (more preferably 50eV to 5keV), implantation dose: 1×1014atoms / cm2 to 1×1016atoms / cm2.

[0043] Preferably, in step S3, the temperature condition for hydrogen ion implantation is ≤60°C; and / or the temperature condition for carbon ion implantation is ≤0°C. Carbon ion implantation uses a low-temperature ion implantation process, which can avoid ion diffusion during ion implantation and control the uniform implantation of carbon ions into a specific location within the substrate with precise positioning and a narrow distribution range, thereby forming a precisely positioned and flat carbon implantation layer 3. Similarly, the hydrogen ion implantation temperature should not be too high. Furthermore, when low-temperature implantation is used, a lower dose can be selected to further avoid lattice damage and reduce defects.

[0044] In summary, in the preparation method of the FD-SOI substrate structure of the present invention through the hydrogen and carbon ion implantation process, an ion implantation and a wet etching process are combined; by injecting hydrogen ions, a relatively flat weakened layer is formed at a certain depth position on the substrate surface to facilitate subsequent stripping; then carbon ions are injected to form a relatively flat ion diffusion barrier layer at another relatively shallow depth position, and the larger carbon ions are used to block the diffusion of hydrogen ions to the substrate surface. At the same time, the carbon ions will not cause changes to the top silicon film on the device; the ion diffusion barrier layer formed by the carbon ion implantation is also a wet etching barrier layer. When the wet etching process is subsequently performed, when the wet etching barrier layer is etched, the etching speed will be reduced. It becomes much slower. The occurrence of this phenomenon indicates that the etching has reached the position of this layer. Stopping etching at this time can retain the required film thickness. In this way, the top silicon film can be effectively controlled to reach the required ultra-thin thickness, and the wet etching process makes the film uniform, which can achieve a thickness drop of less than 2% and no surface defects. The surface of the FD-SOI substrate structure prepared by the method of the present invention is relatively flat, with few surface and internal defects of the structure, and can maintain good single crystallinity. The method of the present invention is particularly suitable for situations where advanced processes require the top silicon film to reach an ultra-thin thickness of nanometer level, and can form the required high-quality nano-level ultra-thin film, which is of great significance for the application of FD-SOI technology in semiconductor devices with smaller feature sizes.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents (for example, the first wafer A and the second wafer B can be made of single crystal silicon or other materials). These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing an FD-SOI substrate structure by hydrogen and carbon ion implantation, characterized in that: The method comprises the following steps in sequence: Step S1, preparing a first wafer (A) and a second wafer (B), wherein the first wafer (A) and the second wafer (B) are both wafer substrate bare dies; Step S2, performing thermal oxidation treatment on the surface of the first wafer (A) to form an insulating oxide layer (1) on the surface of the first wafer (A); Step S3, performing hydrogen ion implantation and carbon ion implantation processes on the first wafer (A), so that a hydrogen implantation layer (2) is formed below the insulating oxide layer (1) of the first wafer (A), and a carbon implantation layer (3) is formed between the hydrogen implantation layer (2) and the insulating oxide layer (1); Step S4, after cleaning the surfaces of the first wafer (A) and the second wafer (B), the surface of the insulating oxide layer (1) of the first wafer (A) is bonded to the second wafer (B) through a bonding process; Step S5, peeling the first wafer (A) along the hydrogen injection layer (2), forming a top silicon film (4) on the second wafer (B) on the remaining portion of the first wafer (A) outside the insulating oxide layer (1), and then performing a thermal annealing treatment to recrystallize the top silicon film (4); Step S6, etching the top silicon film (4) to below the carbon injection layer (3) by wet etching, so that the top silicon film (4) reaches a desired thickness.

2. The method for preparing the FD-SOI substrate structure by hydrogen and carbon ion implantation according to claim 1, characterized in that: The insulating oxide layer (1) is a silicon dioxide layer.

3. The method for preparing the FD-SOI substrate structure by hydrogen and carbon ion implantation according to claim 1, characterized in that: In step S3 , the dosage of hydrogen ion implantation is higher than the dosage of carbon ion implantation.

4. The method for preparing the FD-SOI substrate structure by hydrogen and carbon ion implantation according to claim 1, characterized in that: In step S3, the process parameters of hydrogen ion implantation include implantation energy: 50keV to 200keV, implantation dose: 1×1016atoms / cm2 to 1×1018atoms / cm2; And / or, process parameters of carbon ion implantation include implantation energy: 50 eV to 10 keV, implantation dose: 1×10 14 atoms / cm 2 to 1×10 16 atoms / cm 2 .

5. The method for preparing the FD-SOI substrate structure by hydrogen and carbon ion implantation according to claim 1, characterized in that: In step S3, the temperature condition for hydrogen ion implantation is ≤60°C; And / or, the temperature condition of carbon ion implantation is ≤ 0°C.

6. The method for preparing the FD-SOI substrate structure by hydrogen and carbon ion implantation according to claim 1, characterized in that: In step S4, the bonding process is a low-temperature bonding process, and the bonding process temperature is ≤200°C.

7. The method for preparing the FD-SOI substrate structure by hydrogen and carbon ion implantation according to claim 1, characterized in that: In step S5 , the thermal annealing treatment is a high-temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is ≥500° C.

8. The method for preparing the FD-SOI substrate structure by hydrogen and carbon ion implantation according to claim 1, characterized in that: After step S6, the top silicon film (4) reaches the required ultra-thin thickness, which is ≤20 nm.

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