A clock generation circuit applied to a successive approximation analog-to-digital converter

Abstract

The application discloses a clock generation circuit applied to a successive approximation type analog-digital converter and belongs to the technical field of clock generation circuit design of an analog-digital converter, wherein the high level of an input signal CLK_IN of a clock generation module enables a PMOS transistor M3 to charge a capacitor array, so that a Vint signal gradually rises, the Vint signal is compared with VCM through MOS transistors M4-M10, and a clock with a duty cycle close to a target value is obtained. According to the application, a clock with a preliminary precision duty cycle is obtained through the method of an analog integrator, and the duty cycle is finely adjusted through adaptive adjustment logic; the sampling time of the SAR ADC can keep a stable duty cycle under PVT, only a small clock jitter is introduced to the clock falling edge, and meanwhile, the sampling performance of the high-speed SAR ADC can be ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of clock generation circuit design for analog-to-digital converters, and in particular relates to a clock generation circuit applied to a successive approximation analog-to-digital converter. Background Art

[0002] Successive approximation register analog-to-digital converters (SAR ADCs) are widely used in modern integrated circuit design due to their low power consumption and small size. With the continuous evolution of semiconductor process nodes, the sampling rate of SAR ADCs has also increased significantly. SAR ADCs that use asynchronous timing control (asynchronous SAR ADCs) eliminate the reliance on external high-frequency clocks, thus avoiding the design complexity and power consumption issues associated with high-frequency clock distribution, thereby demonstrating performance advantages in high-speed applications. However, in high-speed operation, the conversion time of SAR ADCs increases significantly, often exceeding half of the system clock cycle. In this case, if a sampling clock with a 50% duty cycle (i.e., a sampling window of half a clock cycle) is used, the actual available conversion time will not be sufficient to complete the entire analog-to-digital conversion process, resulting in performance degradation such as reduced conversion accuracy and increased bit error rate.

[0003] To achieve a narrower sampling window (i.e., a sampling clock with a smaller duty cycle) to extend conversion time, a conventional approach utilizes a high-frequency multiplier clock. While this approach effectively generates the required small-duty-cycle sampling clock, its implementation relies on an additional high-frequency clock source, increasing system complexity and power consumption. In applications where a high-frequency clock source is unavailable, alternative approaches often employ clock generation methods based on digital delay lines. However, such methods are significantly affected by variations in process corners and operating voltage and temperature (PVT), making it difficult to precisely control the delay. This results in insufficient duty cycle accuracy and poor stability, making the generated sampling clock unable to meet the stringent sampling clock timing accuracy requirements of high-speed, high-precision SAR ADCs. Summary of the Invention

[0004] The purpose of the present invention is to provide a clock generation circuit for a successive approximation analog-to-digital converter, which obtains a duty cycle clock with preliminary accuracy by simulating an integrator and fine-tunes the duty cycle through adaptive adjustment logic, thereby solving the problems raised in the above-mentioned background technology.

[0005] To achieve the above object, the present invention provides the following technical solution: a clock generation circuit for a successive approximation analog-to-digital converter, the clock generation circuit comprising a clock generation module and a clock duty cycle adjustment logic circuit;

[0006] The high level of the clock generation module's input signal CLK_IN causes PMOS transistor M3 to charge the capacitor array, causing the Vint signal to gradually rise. MOS transistors M4-M10 then compare the Vint signal with the VCM signal to obtain a clock with a duty cycle that is initially close to the target value. AND gate I1 allows the falling edge of signal CLKO to pass only through I0, I2, and I1, ensuring that the falling edge does not introduce clock jitter due to the comparison of MOS transistors M4-M10. CLKO is the output clock of the successive approximation analog-to-digital converter. The clock duty cycle adjustment logic circuit then controls the charging time of different clock signals through PMOS transistors M14 and NMOS transistors M11, converting the duty cycle information in the time domain into a voltage, which serves as the input signal for comparator ICMP. After the output signal DP of comparator ICMP undergoes logical statistical processing, when more than half of the comparators determine that they are 1, the accumulator controls cap_clt. <n:1>Adding gears allows the capacitor array to increase the access capacitance, so that the duty cycle is reduced; and when more than half of the comparator judgments are 0, the accumulator controls cap_clt <n:1>By downshifting, the capacitor array reduces the connected capacitance, thereby increasing the duty cycle; eventually, after multiple rounds of iterations, the output clock CLKO will be adjusted to the target duty cycle.

[0007] Preferably, the input signal CLK_IN of the clock generation module is converted into a signal CKIN_B through the inverter I0, CKIN_B is connected to the gates of the NMOS tube M1 and the PMOS tube M2, and the source of the NMOS tube M1 is connected to the ground GND; the drains of the NMOS tube M1 and the PMOS tube M2 are connected together and connected to the line Vint; the source of the PMOS tube M2 is connected to the drain of the tail current device PMOS tube M3; the source of the tail current device PMOS tube M3 is connected to the power supply VDD, and the gate is connected to the bias voltage VBP; the top plate of the capacitor of the N-bit capacitor array is connected to the Vint line, and the bottom plate of each capacitor is connected to a switch, the other side of the switch is connected to the ground GND, and the control signal of the switch is the control signal cap_ctl of the N-bit switch capacitor array. <n:1>; NMOS transistors M5 and M6 form a differential input pair, the gate terminal of NMOS transistor M5 is connected to the Vint line, and the gate terminal of NMOS transistor M6 is connected to the common mode voltage VCM, where VCM is the input common mode level; the source terminals of NMOS transistors M5 and M6 are connected together and connected to the drain terminal of tail current source NMOS transistor M4; the source terminal of tail current source NMOS transistor M4 is connected to ground GND, and the gate terminal is connected to bias voltage IB; the drain terminals of PMOS transistors M7 and M8 are connected to the drain terminals of NMOS transistors M5 and M6 respectively, and PMOS transistors M7 and M The gate terminals of the NMOS transistors M8 and M9 are connected together and connected to the drain terminal of the PMOS transistor M8; the drain terminal of the PMOS transistor M7 is also connected to the gate terminals of the NMOS transistors M9 and PMOS transistors M10; the drain terminals of the NMOS transistors M9 and PMOS transistors M10 are connected together and connected to one input terminal of the AND gate I1; the source terminals of the NMOS transistors M9 and PMOS transistors M10 are connected to the ground GND and the power supply VDD, respectively; the input signal CKIN_B is connected to the other input terminal of the AND gate I1 after passing through the inverter I2; the output clock of the AND gate I1 is CLKO.

[0008] Preferably, in the clock duty cycle adjustment logic circuit, the output of the inverter I2 is connected to the input of the delay module I5 and is connected to one of the input terminals of the AND gate I6. At the same time, the output of the inverter I2 is connected to the other input terminal of the AND gate I6. The output of the AND gate I6 is connected to the CKSW signal line and is connected to the CKSWB signal line through the inverter I7. The output of the inverter I2 is also connected to the input terminal of the inverter I3. The output of the inverter I3 is connected to the CLKO1 signal line and is connected to the CKO1B signal line after passing through the inverter I4. The NMOS transistor M17, The gate terminals of M16 and M11 are connected to the input current source IB, wherein the drain terminal of NMOS transistor M17 is also connected to IB, and the source terminals of NMOS transistors M17, M16 and M11 are connected to ground; the drain terminal of NMOS transistor M16 is connected to the bias voltage VBP, which is connected to the drain and source terminals of PMOS transistor M15; the gate terminal of PMOS transistor M14 is connected to VBP, the source terminal is connected to the power supply VDD, and the drain terminal is connected to the source terminal of PMOS transistor M13; the gate terminal of PMOS transistor M13 is connected to the CLKO1 signal line, and the drain terminal is connected to the drain terminal of NMOS transistor M12 and to the VCP signal line; the gate terminal of NMOS transistor M12 is connected to the CLKO signal line, and the source terminal is connected to the drain terminal of M11; the positive and negative differential input signals of comparator ICMP are connected to the VCP and VCN signal lines respectively, and the output of comparator ICMP is connected to signal line DP; capacitors CL1 and CL2 are connected to the VCP and VCN signal lines respectively, wherein CL1, The capacitance value of CL2 is the same; switches S2 and S1 are connected to the VCP and VCN signal lines respectively, and the other ends of switches S2 and S1 are connected to the input common mode voltage VCM. The control signal of switches S2 and S1 is CKSW; the output signal DP of comparator ICMP is connected to the input clock CK terminal of D-type flip-flop I8;

[0009] Among them, the input ports of the D-type trigger are the input signal Q terminal and the input reset terminal R terminal, and the output ports of the D-type trigger are the output forward data terminal D terminal and the output reverse data terminal DB terminal.

[0010] Preferably, the output signal DP line of the comparator ICMP is connected to the CK terminal of the D flip-flop I8, the output DB terminal of the D flip-flop I8 is connected to the Q terminal of I8 and the CK terminal of the D flip-flop I9, the output DB terminal of the D flip-flop I9 is ​​connected to the Q terminal of the D flip-flop I9 and the CK terminal of the D flip-flop I10, the output DB terminal of the D flip-flop I10 is connected to the Q terminal of the D flip-flop I10 and the CK terminal of the D flip-flop I11, the output DB terminal of the D flip-flop I11 is connected to the Q terminal of I11 and the input terminal of the inverter I12, and the output terminal of the inverter I12 is connected to the D terminal of the accumulator I13; the CKO1B signal line is connected to the CK terminal of the D flip-flop I14, the output DB terminal of the D flip-flop I14 is connected to the Q terminal of the D flip-flop I14 and the CK terminal of the D flip-flop I15; the output DB terminal of the D flip-flop I15 is connected to the Q terminal of the D flip-flop I15 and the CK terminal of the D flip-flop I116; the output DB terminal of the D flip-flop I16 is connected to the D flip-flop I1 6 and the CK terminal of the D flip-flop I17; the output DB terminal of the D flip-flop I17 is connected to the Q terminal of the D flip-flop I18 and the CK terminal of the D-type flip-flop I18; the output DB terminal of the D flip-flop I18 is connected to the Q terminal of the D flip-flop I18; the D terminals of the D flip-flops I14 and I15 are respectively connected to the two input terminals of the NAND gate I22; the D terminals of the D flip-flops I16 and I17 are respectively connected to the two input terminals of the NAND gate I21; the output terminals of the NAND gates I21 and I22 are respectively connected to the two input terminals of the NOR gate I23; one of the input terminals of the AND gate I24 is connected to the CKO1B signal line, and the other input terminal is connected to the output of the NOR gate I23; the output terminal D of the D flip-flop I18 is connected to the input terminal A of the delay unit I19, the output O terminal of the delay unit I19 is connected to one of the input terminals of the OR gate I20, and the other input terminal of the OR gate I20 is connected to the input reset signal rst; the output terminal of the OR gate I20 outputs the cnt_rst signal.

[0011] Preferably, the reset terminals R of the D flip-flops I8-I11 and I14-I18 are all connected to the output terminal cnt_rst of the OR gate I20; the accumulator I13 outputs the control signal cap_clt of the N-bit DAC. <n:1>, control signal cap_clt <n:1>Input to the switch control signal line of the N-bit capacitor array CDAC; the accumulator I13 detects the D end at the rising edge of the CK end. When the CK end is a rising edge, D is 1, and its output signal cap_clt <n:1>Add 1; when the CK terminal is a rising edge, D is 0, and its output signal cap_clt <n:1>Minus 1; when the output signal cap_clt <n:1>When all are 1, the gear is no longer increased but the output signal cap_clt is maintained. <n:1>All are 1; when the output signal cap_clt <n:1>When all are 0, the gear is no longer increased but the output signal cap_clt is maintained. <n:1>All 0s.

[0012] Preferably, the clock generating circuit configures the duty cycle of the output clock by adjusting the ratio of the PMOS tube M14 and the NMOS tube M11. When the duty cycle of the input signal is 50%, if a 25% duty cycle is obtained, the current of the NMOS tube M11 is twice that of the PMOS tube M14.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] The present invention discloses a clock generation circuit for a successive approximation analog-to-digital converter (SAR ADC). The circuit obtains a duty cycle clock with preliminary accuracy through an analog integrator and fine-tunes the duty cycle through adaptive adjustment logic. The circuit enables the SAR ADC's sampling time to maintain a stable duty cycle under PVT (process, voltage, temperature) conditions and introduces only minimal clock jitter on the falling edge of the clock, thereby ensuring the sampling performance of the high-speed SAR ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The present invention is a circuit connection diagram of a clock generation circuit applied to a successive approximation analog-to-digital converter. DETAILED DESCRIPTION

[0016] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0017] Successive approximation register analog-to-digital converters (SAR ADCs) are widely used in modern integrated circuit design due to their low power consumption and small size. With the continuous evolution of semiconductor process nodes, the sampling rate of SAR ADCs has also increased significantly. SAR ADCs that use asynchronous timing control (asynchronous SAR ADCs) eliminate the reliance on external high-frequency clocks, thus avoiding the design complexity and power consumption issues associated with high-frequency clock distribution, thereby demonstrating performance advantages in high-speed applications. However, in high-speed operation, the conversion time of SAR ADCs increases significantly, often exceeding half of the system clock cycle. In this case, if a sampling clock with a 50% duty cycle (i.e., a sampling window of half a clock cycle) is used, the actual available conversion time will not be sufficient to complete the entire analog-to-digital conversion process, resulting in performance degradation such as reduced conversion accuracy and increased bit error rate.

[0018] To achieve a narrower sampling window (i.e., a sampling clock with a smaller duty cycle) to extend conversion time, a conventional approach utilizes a high-frequency multiplier clock. While this approach effectively generates the required small-duty-cycle sampling clock, its implementation relies on an additional high-frequency clock source, increasing system complexity and power consumption. In applications where a high-frequency clock source is unavailable, alternative approaches often employ clock generation methods based on digital delay lines. However, such methods are significantly affected by variations in process corners and operating voltage and temperature (PVT), making it difficult to precisely control the delay. This results in insufficient duty cycle accuracy and poor stability, making the generated sampling clock unable to meet the stringent sampling clock timing accuracy requirements of high-speed, high-precision SAR ADCs.

[0019] To this end, the present invention provides a clock generation circuit for a successive approximation analog-to-digital converter, which obtains a duty cycle clock with preliminary accuracy through an analog integrator method and fine-tunes the duty cycle through adaptive adjustment logic, thereby solving the problems existing in the prior art.

[0020] like Figure 1 As shown, a clock generation circuit applied to a successive approximation analog-to-digital converter according to an embodiment of the present invention is composed of two parts: a clock generation module and a clock duty cycle adjustment logic.

[0021] The input clock CLK_IN of the clock generation module is obtained through the inverter I0 to obtain CKIN_B. CKIN_B is connected to the gates of the NMOS tube (N-type metal-oxide-semiconductor) M1 and the PMOS tube (P-type metal-oxide-semiconductor) M2. The source of M1 is connected to the ground GND. The drains of M1 and M2 are connected together and connected to the line Vint. The source of the PMOS tube M2 is connected to the drain of the tail current device PMOS tube M3. The source of M3 is connected to the power supply VDD, and the gate of M3 is connected to the bias voltage VBP. The top plate of the capacitor of the N-bit capacitor array is connected to the Vint line, and the bottom plate of each capacitor is connected to a switch. The other side of the switch is connected to the ground. The control signal of the switch is the control signal cap_ctl of the N-bit switch capacitor array. <n:1>NMOS transistors M5 and M6 form a differential input pair. M5's gate is connected to Vint, and M6's gate is connected to the common-mode voltage VCM, where VCM is the input common-mode voltage, typically set to half of VDD. The sources of M5 and M6 are connected together and to the drain of tail current source NMOS transistor M4. M4's source is connected to ground, and its gate is connected to bias voltage IB. The drains of PMOS transistors M7 and M8 are connected to the drains of M5 and M6, respectively, and the gates of M7 and M8 are connected together and to the drain of M8. The drain of M7 is also connected to an inverter connected to the gates of NMOS transistor M9 and PMOS transistor M10. The drains of M9 and M10 are connected together and to one input of AND gate I1. The sources of M9 and M10 are connected to ground and the power supply, respectively. The input clock CKINB passes through inverter I2 and is connected to the other input of AND gate I1. The output CLKO of the AND gate I1 is the output clock of a clock generating circuit for a successive approximation analog-to-digital converter of the present invention.

[0022] The clock duty cycle adjustment logic consists of the following components: the output of inverter I2 is connected to the input of delay module I5, which is then fed into one input of AND gate I6. The output of I2 is connected to the other input of AND gate I6. The output of I6 is connected to the CKSW signal line, which then passes through inverter I7 to the CKSWB signal line. The output of inverter I2 is also connected to inverter I3, which then passes through inverter I4 to the CKO1B signal line. The gates of NMOS transistors M17, M16, and M11 are connected to input current source IB, with the drain of M17 also connected to IB. The sources of M17, M16, and M11 are connected to ground. The drain of M16 is connected to bias voltage VBP, which is connected to the drain and source of PMOS transistor M15. The gate of M14 is connected to VBP, the source to power supply VDD, and the drain to the source of PMOS transistor M13. The source terminal of M13 is connected to the CLKO1 signal line, and its drain terminal is connected to the drain terminal of NMOS transistor M12, which is also connected to the VCP signal line. The gate terminal of NMOS transistor M12 is connected to the CLKO signal line, and its source terminal is connected to the drain terminal of M11. The positive and negative differential input signals of comparator ICMP are connected to the VCP and VCN signal lines, respectively, and the comparator output is connected to DP. Capacitors CL1 and CL2 are connected to the VCP and VCN signal lines, respectively, with the capacitance values ​​of CL1 and CL2 being identical. Switches S2 and S1 are connected to the VCP and VCN signal lines, respectively. The other terminals of both switches are connected to the input common-mode voltage VCM. The control signal for both switches is CKSW. The output of the comparator is connected to the clock input CK of D-type flip-flop I8. The input ports of the D-type flip-flop are the input signal Q and the input reset terminal R, and the output ports are the output positive data terminal D and the output negative data terminal DB.

[0023] The comparator output signal DP line is connected to the CK terminal of D flip-flop I8. The output DB terminal of I8 is connected to the Q terminal of I8 and the CK terminal of D flip-flop I9. The output DB terminal of I9 is ​​connected to the Q terminal of I9 and the CK terminal of D flip-flop I10. The output DB terminal of I10 is connected to the Q terminal of I10 and the CK terminal of D flip-flop I11. The output DB terminal of I11 is connected to the Q terminal of I11 and the D terminal of inverter I12, which is connected to accumulator I13. CKO1B is connected to the CK terminal of D flip-flop I14. The output DB terminal of I14 is connected to the Q terminal of I14 and the CK terminal of D flip-flop I15. The output DB terminal of I15 is connected to the Q terminal of I15 and the CK terminal of D flip-flop I116. The output DB terminal of I16 is connected to the Q terminal of I16 and the CK terminal of D flip-flop I17. The output DB terminal of I17 is connected to the Q terminal of I18 and the CK terminal of D flip-flop I18. The output DB terminal of I18 is connected to the Q terminal of I18. The D terminals of I14 and I15 are connected to the two inputs of NAND gate I22, respectively. The D terminals of I16 and I17 are connected to the two inputs of NAND gate I21, respectively. The outputs of I21 and I22 are connected to the two inputs of NOR gate I23, respectively. One input of AND gate I24 is connected to CKO1B, and the other input is connected to the output of I23. The output terminal D of I18 is connected to the input terminal A of delay unit I19. The output terminal O of I19 is connected to one input of OR gate I20, and the other input of I20 is connected to the input reset signal rst. The output of I20 outputs the cnt_rst signal. The reset terminals R of D flip-flops I8-I11, I14-I18 are all connected to the cnt_rst signal. Accumulator I13 outputs the N-bit DAC control signal cap_clt. <n:1>The accumulator I13 detects the D terminal at the rising edge of the CK terminal. When the CK terminal is a rising edge, D is 1, and its output signal cap_clt <n:1>Add 1; when the CK terminal is a rising edge, D is 0, and its output signal cap_clt <n:1>Subtract 1; when cap_clt <n:1>When all 1, no more gears are added but all 1 are maintained; when cap_clt <n:1>When all 0, no longer increase the gear and maintain all 0;

[0024] By adjusting the ratio of PMOS M14 and NMOS M11, the duty cycle of the output clock can be configured. When the input signal has a 50% duty cycle, a 25% duty cycle is desired, and the current of M11 is twice that of M14.

[0025] Working sequence: the high level of input signal CLK_IN charges the capacitor array with the tail current source M3, so that the Vin signal gradually rises, and after M4-M10 and shaping, a clock signal with a duty cycle close to the target value is obtained. The AND gate of I1 makes the falling edge steeper, and the CLK0 is obtained as the sampling clock of the successive approximation ADC. The charging time of M14 and M11 controls different clock signals, which converts the time domain duty cycle information into voltage as the input signal of the comparator ICMP. After the statistical processing of the logic of the comparator output signal DP, when more than half of the comparator decisions are 1, the accumulator controls cap_clt <n:1>Add gears to connect more capacitors to the capacitor array, so that the duty cycle is reduced; when more than half of the comparator judgments are 0, the accumulator controls cap_clt <n:1>By downshifting, more capacitors are connected to the capacitor array, increasing the duty cycle. After multiple iterations, the output clock CLKO will be adjusted to the target duty cycle.

[0026] The present invention discloses a clock generation circuit for a successive approximation analog-to-digital converter (SAR ADC). The circuit obtains a duty cycle clock with preliminary accuracy through an analog integrator and fine-tunes the duty cycle through adaptive adjustment logic. The circuit enables the SAR ADC's sampling time to maintain a stable duty cycle under PVT (process, voltage, temperature) conditions and introduces only minimal clock jitter on the falling edge of the clock, thereby ensuring the sampling performance of the high-speed SAR ADC.

[0027] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0028] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A clock generating circuit for a successive approximation analog-to-digital converter, characterized in that: The clock generation circuit consists of two parts: a clock generation module and a clock duty cycle adjustment logic circuit; The input signal CLK_IN of the clock generation module is converted into a signal CKIN_B through the inverter I0. CKIN_B is connected to the gates of the NMOS transistor M1 and the PMOS transistor M2. The source of the NMOS transistor M1 is connected to the ground GND. The drains of the NMOS transistor M1 and the PMOS transistor M2 are connected together and connected to the Vint line at the same time. The source of the PMOS transistor M2 is connected to the drain of the tail current device PMOS transistor M3; the source of the tail current device PMOS transistor M3 is connected to the power supply VDD, and the gate is connected to the bias voltage VBP; the top plate of the capacitor of the N-bit capacitor array is connected to the Vint line, and the bottom plate of each capacitor is connected to a switch, and the other side of the switch is connected to the ground GND. The control signal of the switch is the control signal cap_ctl of the N-bit capacitor array. <n:1> The NMOS transistors M5 and M6 form a differential input pair. The gate terminal of the NMOS transistor M5 is connected to the Vint line, and the gate terminal of the NMOS transistor M6 is connected to the common mode voltage VCM. The source terminals of the NMOS transistors M5 and M6 are connected together and connected to the drain terminal of the tail current source NMOS transistor M4. The source terminal of the tail current source NMOS transistor M4 is connected to the ground GND, and the gate terminal is connected to the bias voltage IB. The drain terminals of the PMOS transistors M7 and M8 are connected to the drain terminals of the NMOS transistors M5 and M6 respectively, and the gate terminals of the PMOS transistors M7 and M8 are connected. Together, they are connected to the drain of the PMOS transistor M8; the drain of the PMOS transistor M7 is also connected to the gates of the NMOS transistor M9 and the PMOS transistor M10; the drains of the NMOS transistor M9 and the PMOS transistor M10 are connected together and to one input of the AND gate I1; the source of the NMOS transistor M9 and the PMOS transistor M10 are connected to the ground GND and the power supply VDD, respectively; the signal CKIN_B passes through the inverter I2 and is connected to the other input of the AND gate I1; the output clock of the AND gate I1 is CLKO; In the clock duty cycle adjustment logic circuit, the output of the inverter I2 is connected to the input of the delay module I5 and one of the inputs of the AND gate I6. At the same time, the output of the inverter I2 is connected to the other input of the AND gate I6. The output of the AND gate I6 is connected to the CKSW signal line and then to the CKSWB signal line through the inverter I7. The output of the inverter I2 is also connected to the input of the inverter I3. The output of the inverter I3 is connected to the CLKO1 signal line and then to the CKO1B signal line after passing through the inverter I4. The NMOS transistor M17, The gate terminals of M16 and M11 are connected to the input current source IB, wherein the drain terminal of NMOS transistor M17 is also connected to IB, and the source terminals of NMOS transistors M17, M16 and M11 are connected to ground; the drain terminal of NMOS transistor M16 is connected to the bias voltage VBP, which is connected to the drain and source terminals of PMOS transistor M15; the gate terminal of PMOS transistor M14 is connected to VBP, the source terminal is connected to the power supply VDD, and the drain terminal is connected to the source terminal of PMOS transistor M13; the source terminal of PMOS transistor M13 is connected to the CLKO1 signal line, and the drain terminal is connected to the drain terminal of NMOS transistor M12 and to the VCP signal line; the gate terminal of NMOS transistor M12 is connected to the CLKO signal line, and the source terminal is connected to the drain terminal of M11; the positive and negative differential input signals of comparator ICMP are connected to the VCP and VCN signal lines respectively, and the output of comparator ICMP is connected to signal line DP; capacitors CL1 and CL2 are connected to the VCP and VCN signal lines respectively, wherein CL1, The capacitance value of CL2 is the same; switches S2 and S1 are connected to the VCP and VCN signal lines respectively, and the other ends of switches S2 and S1 are connected to the input common mode voltage VCM. The control signal of switches S2 and S1 is CKSW; the output signal DP of comparator ICMP is connected to the input clock CK terminal of D-type flip-flop I8; Among them, the input ports of the D-type trigger are the input signal Q terminal and the input reset terminal R terminal, and the output ports of the D-type trigger are the output forward data terminal D terminal and the output reverse data terminal DB terminal.

2. The clock generating circuit for a successive approximation analog-to-digital converter according to claim 1, wherein: The output signal DP line of the comparator ICMP is connected to the CK terminal of the D flip-flop I8, the output DB terminal of the D flip-flop I8 is connected to the Q terminal of I8 and the CK terminal of the D flip-flop I9, the output DB terminal of the D flip-flop I9 is ​​connected to the Q terminal of the D flip-flop I9 and the CK terminal of the D flip-flop I10, the output DB terminal of the D flip-flop I10 is connected to the Q terminal of the D flip-flop I10 and the CK terminal of the D flip-flop I11, the output DB terminal of the D flip-flop I11 is connected to the Q terminal of I11 and the input terminal of the inverter I12, and the output terminal of the inverter I12 is connected to the D terminal of the accumulator I13; The CKO1B signal line is connected to the CK terminal of the D flip-flop I14, and the output DB terminal of the D flip-flop I14 is connected to the Q terminal of the D flip-flop I14 and the CK terminal of the D flip-flop I15; The output DB terminal of the D flip-flop I15 is connected to the Q terminal of the D flip-flop I15 and the CK terminal of the D flip-flop I116; The output DB terminal of the D flip-flop I16 is connected to the Q terminal of the D flip-flop I16 and the CK terminal of the D flip-flop I17; The output DB terminal of the D flip-flop I17 is connected to the Q terminal of the D flip-flop I18 and the CK terminal of the D flip-flop I18; The output DB terminal of the D flip-flop I18 is connected to the Q terminal of the D flip-flop I18; The D ends of the D flip-flops I14 and I15 are respectively connected to the two input ends of the NAND gate I22; the D ends of the D flip-flops I16 and I17 are respectively connected to the two input ends of the NAND gate I21; the output ends of the NAND gates I21 and I22 are respectively connected to the two input ends of the NOR gate I23; one of the input ends of the AND gate I24 is connected to the CKO1B signal line, and the other input end is connected to the output of the NOR gate I23; the output end D of the D flip-flop I18 is connected to the input end A of the delay unit I19, the output end O of the delay unit I19 is connected to one of the input ends of the OR gate I20, and the other input end of the OR gate I20 is connected to the input reset signal rst; the output end of the OR gate I20 outputs the cnt_rst signal.

3. The clock generating circuit for a successive approximation analog-to-digital converter according to claim 2, wherein: The reset terminals R of the D flip-flops I8-I11 and I14-I18 are connected to the output terminal cnt_rst of the OR gate I20; the accumulator I13 outputs the control signal cap_clt of the N-bit capacitor array. <n:1>, control signal cap_clt <n:1>Input to the switch control signal line of the N-bit capacitor array; the accumulator I13 detects the D end at the rising edge of the CK end. When the CK end is a rising edge, D is 1, and its control signal cap_clt <n:1>Add 1; when the CK terminal is rising, D is 0, and its control signal cap_clt <n:1>Minus 1; when the control signal cap_clt <n:1>When all are 1, the gear is no longer increased but the control signal cap_clt is maintained. <n:1>All are 1; when the control signal cap_clt <n:1>When all are 0, the gear is no longer increased but the control signal cap_clt is maintained. <n:1> All 0s.< / n:1> 4. The clock generating circuit for a successive approximation analog-to-digital converter according to any one of claims 1 to 3, wherein: The clock generation circuit configures the duty cycle of the output clock by adjusting the ratio of the PMOS transistor M14 and the NMOS transistor M11. When the duty cycle of the input signal is 50%, if a 25% duty cycle is obtained, the current of the NMOS transistor M11 is made twice that of the PMOS transistor M14.

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