Improved top surface for junction termination extension of semiconductor devices

Abstract

The present disclosure proposes a semiconductor device comprising a semiconductor body, where the semiconductor body comprises one or more recessed regions in a P-doped junction termination extension (JTE) region, where the depth of the recessed regions is less than the depth of the JTE region; and an N + implant on a top surface of the JTE region such that the N + implant forms a portion of the mesa region between the recessed regions. A method of manufacturing such a semiconductor device is also presented.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. More particularly, the present disclosure relates to an improved top surface for a junction termination extension (JTE) of a semiconductor device. Background Art

[0002] Most planar and trench power devices are based on one or more n-type / p-type junctions. When the active part of the junction is toward the side of the device, very high electric fields can occur under reverse voltage bias due to the junction curvature or trench angle.

[0003] Therefore, peripheral protection, also known as edge termination, may be required. Edge termination is a critical component of power devices. Passivation charge in the termination can cause reliability failures, low reverse blocking capability, and low unclamped inductive load switching (UIS) robustness.

[0004] Reliable and robust high-voltage devices require effective edge termination structures to protect the device periphery, enabling blocking values close to the ideal 1D avalanche voltage values to be achieved. Several physical limitations make the design of edge terminations in, for example, silicon carbide (SiC) quite complex. The main limitation is the low diffusion coefficient of dopant atoms within the semiconductor. Deep junctions (greater than 1μm) are difficult to achieve, and lateral dopant diffusion is very limited. In addition, the higher interface trap levels observed at the SiC / passivation interface relative to silicon also affect the efficiency of standard Si termination architectures in SiC power devices. Charge can accumulate at the interface, causing breakdown voltage instability and early failure, especially with temperature.

[0005] In bipolar transistors, there are parasitic components such as collector-base and emitter-base junction capacitances, which can affect the high-frequency performance of the transistor. JTE technology involves intentionally adding lightly doped regions (usually P-type regions) near the collector or emitter junction to create a gradual transition between the highly doped and lightly doped regions. This helps to reduce the capacitance at the junction, which in turn reduces the impact on the high-frequency response of the transistor. In addition, JTE distributes the electric field laterally from the active area to the edge of the die in a way that the peak field can be minimized and no lateral or terminal breakdown occurs. At the same time, the terminals should be able to resist the movement or accumulation of charge under stress testing or operating conditions.

[0006] A common SiC termination design is the JTE. It can be used to reduce the effects of unwanted parasitic elements in device structures and improve performance. The breakdown voltage of the JTE region in rectifiers is highly sensitive to the doping concentration of the JTE (not limited to low p-type). This also means that the JTE termination is sensitive to charge accumulation in the region. Summary of the Invention

[0007] The summary of the aspects of the specific examples disclosed herein is as follows. It should be understood that these aspects are merely provided to the reader with a brief overview of these specific embodiments and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may encompass a number of aspects and / or combinations of aspects that may not be elaborated.

[0008] The present disclosure is directed to overcoming the shortcomings identified in the Background section. More specifically, the present disclosure is directed to reducing the electric field in the critical interface region between the JTE and the passivation stack.

[0009] This disclosure proposes an "inverted" Kao ring structure in the JTE region, which can be formed by a dry etching step followed by an N+ region implant. The distributed N+ Kao ring structure balances the charge in the terminal and distributes the electric field, making it more resilient to doping and charge variations. Due to the distributed implant, forming the Kao ring structure through a dry etching process allows for very fine patterning without corner effects.

[0010] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method may include forming one or more recessed regions in a P-doped junction termination extension (JTE) implant of a semiconductor body. The depth of the recessed regions may be less than the depth of the JTE implant. The method may also include forming an N+ implant on a top surface of the JTE implant, such that the N+ implant forms a portion of a mesa region between the recessed regions.

[0011] In one embodiment, the depth of the recessed region may be less than half the depth of the JTE implant.

[0012] In one embodiment, the method may include forming an N+ implant by one of ion implantation or during epitaxial growth.

[0013] In one embodiment, the method includes forming a plurality of N+ implants on a top surface of the JTE implant, wherein doping decreases from the top surface of the JTE implant downward.

[0014] In one embodiment, the method includes forming a plurality of N+ implants using multiple implant steps with increasing dose and energy, generating a graded doping profile where the doping decreases from the top surface of the JTE implant downward.

[0015] In one embodiment, the plurality of N+ implants may be two N+ implants.

[0016] In one embodiment, the method may include forming a plurality of recessed regions having a substantially constant width and a substantially constant spacing.

[0017] In one embodiment, the method may include forming a plurality of recessed regions having increasing spacing along an outer edge of the JTE implant from the active area to the terminal end.

[0018] In one embodiment, the method may include etching a further recessed region outside the JTE implant and near the edge of the mold.The further recessed region is etched during the same process used to form the recessed region in the JTE.

[0019] In one embodiment, the method may further include forming an N+ implant on top of the further recessed region during the same process used to form the N+ implant on top of the JTE implant.

[0020] In one embodiment, the method may include forming a P-compensation implant at the bottom of the recessed region.

[0021] In one embodiment, the method may include forming a P+ implant on a top surface of the JTE implant and below the N+ implant. The P+ implant may form a portion of the recessed region.

[0022] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a semiconductor body. The semiconductor body may include one or more recessed regions in a P-doped junction termination extension (JTE) region. The depth of the recessed regions may be less than the depth of the JTE region. The semiconductor body may further include an N+ implant on a top surface of the JTE region, such that the N+ implant forms a portion of a mesa region between the recessed regions.

[0023] In one embodiment, the semiconductor device may include a plurality of N+ implants on a top surface of a JTE implant, wherein the doping decreases from the top surface of the JTE region downward.

[0024] In one embodiment, the semiconductor body may include a P-compensation implant at the bottom of the recessed region.

[0025] In one embodiment, the semiconductor body may include a P+ implant below the top surface of the JTE implant and the N+ implant, such that the P+ implant forms part of the recessed region.

[0026] In one embodiment, a semiconductor device may be formed using a method having one or more of the above-described features. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings, wherein corresponding reference characters indicate corresponding parts, and wherein:

[0028] Figures 1 to 4 shows a cross-sectional side view of an exemplary embodiment of a semiconductor body;

[0029] Figure 5 schematically illustrates a semiconductor device including a semiconductor body according to an exemplary embodiment; and

[0030] Figure 6 A flow chart illustrating a method of an exemplary embodiment is shown.

[0031] The drawings are intended for illustration purposes only and are not intended to limit the scope of protection defined by the claims. DETAILED DESCRIPTION

[0032] It will be readily understood that the components of the embodiments described herein and in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of various embodiments, as illustrated in the accompanying drawings, is not intended to limit the scope of the present disclosure but is merely representative of various embodiments. Although various aspects of the embodiments are illustrated in the accompanying drawings, unless otherwise indicated, the drawings are not necessarily drawn to scale.

[0033] The embodiments described are to be considered in all respects as illustrative and not restrictive. Therefore, the scope of the present disclosure is indicated by the appended claims rather than by this detailed description. All changes within the meaning and scope of the equivalents of the claims are included within their scope.

[0034] References throughout this specification to features, advantages, or similar language do not imply that all features and advantages achieved through the present disclosure should be or are any single example of the present disclosure. Rather, language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described with respect to an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same example.

[0035] Moreover, the features, advantages and characteristics of the present disclosure may be combined in any appropriate manner in one or more embodiments. Those skilled in the relevant art will recognize that, based on the description herein, the present disclosure may be practiced without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of the present disclosure. References throughout this specification to "one embodiment," "an embodiment," or similar language refer to specific features, structures, or characteristics described with respect to the illustrated embodiment that are included in at least one embodiment of the present disclosure. Therefore, all phrases in this specification "in one embodiment," "in an embodiment," and similar language may, but do not necessarily, refer to the same embodiment.

[0036] Improved terminal behavior can be achieved by implanting the top surface of the JTE with counter-doping (i.e., N+ doping versus P- doping in the JTE) and etching recessed regions. Different recessed regions can have different geometries within the JTE, i.e., different widths and / or spacings. This can reduce the electric field at the JTE surface and modulate lateral doping across the same terminal.

[0037] Further improvements in termination behavior may be obtained by including deeper N+ implants, incorporating P-compensation implants at the bottom of the recessed region, and / or P-compensation implants below the N+ region with the goal of avoiding electric fields penetrating the PN junction.

[0038] Figure 1 An exemplary embodiment of a semiconductor body 100 is shown, including a P-type doped JTE 102 having a recessed region 104 and an N+ implant 106 on the top surface. Thus, the N+ implant on the top surface of the JTE implant can form part of the mesa region between the recessed regions. Recessed regions 104 can be etched within JTE 102, for example, using a dry etch. The N+ layer 106 can be separated by etching.

[0039] In one example, the P-doped layer 102 may have a doping between 3E16 cm-3 and 8E17 cm-3, preferably 1E17 cm-3, and a depth between 0.5 um and 1.5 um, preferably 1 um.

[0040] In one example, the N+ region 106 may have a doping between 1E18 cm-3 and 1E20 cm-3, preferably 1E19 cm-3, and a depth between 0.1 um and 0.3 um, preferably 0.2 um.

[0041] The recessed region may have a depth less than half the depth of the JTE 102, and preferably less than 0.5 um.

[0042] In the preferred embodiment, the recessed regions 104 have a constant width and spacing, ie, a width ranging from 0.5um to 1.5um and a spacing of 3um to 5um, preferably a pitch of 5um with a width of 1um and a spacing of 4um.

[0043] In another embodiment, the spacing between the recessed regions is not constant and increases, for example, by 50%, along the outer edge of the JTE 102 from the active area to the terminal.

[0044] In one exemplary embodiment, the N+ layer 106 may be formed by ion implantation. In another exemplary embodiment, the N+ layer 106 may be formed during epitaxial growth.

[0045] The semiconductor body 100 may comprise a suitable passivation layer in the form of a single layer or a passivation layer stack (not shown in the figures) comprising an oxide-based and a nitride-based dielectric layer. The passivation layer may cover the entire termination region.

[0046] The use of a recessed region 104 within the JTE 102 in combination with a shallow N+ implant 106 on the top surface reduces the occurrence of single electric field peaks. The Kao ring structure allows the electric field to be split and thus distributed along the JTE region 102. This advantageously reduces electric field peaks at the JTE surface where interface states exist, caused by passivation layer deposition and / or other process steps (e.g., oxidation or etching). High electric fields in surface regions with high interface state density can trigger carrier capture or emission, ultimately leading to increased leakage and unstable termination behavior due to unbalanced operation of the JTE, especially under high bias and temperature conditions.

[0047] Furthermore, the use of etched regions of possibly different widths and / or spacings allows for lateral modulation of JTE doping, where doping control along the termination region is defined by the geometry of the recessed region. Advantageously, this allows for improved and more flexible control of lateral doping relative to using standard known implantation techniques.

[0048] During the same implantation step used to form the channel stop region at the die edge, an N+ implant can be implemented, typically at least in high voltage power devices. This can be achieved by extending the outermost recessed region 208 into the channel stop layer, as shown in FIG. Figure 2 Therefore, a semiconductor body 100 with improved JTE operation can be obtained by using a device / process architecture with reduced process complexity and production cost.

[0049] Figure 2 An exemplary embodiment of a semiconductor body 200 is shown, comprising a P-type doped JTE 202 having a recessed region 204 and a plurality of N+ implants 206, 207 with a graded doping on the top surface. The recessed region 204 can be etched inside the JTE 202, for example using a dry etch. The N+ layer 206 can be separated by etching.

[0050] and Figure 1 Similar to the N+ implant 106 present on the top surface in the example of Figure 2 In the example of FIG. 1 , a plurality of N+ implants 206 , 207 may be present on the top surface and the top surface of the stopping region 208 .

[0051] The plurality of N+ implants 206 , 207 are formed using multiple implantation steps with increasing dose and energy, generating a graded doping profile where the doping decreases from the surface to the bottom of the JTE 202 .

[0052] exist Figure 2In the example shown in FIG. 4 , two N-type implant regions are formed on top of the JTE 202 , with a first implant region 206 having a higher doping level at the top side and a second implant region 207 having a reduced doping level towards the end of the JTE 202 .

[0053] In one example, the first surface region 206 may have a doping of approximately 1E18 cm-3 to 1E20 cm-3 and a depth of 0.1 um to 0.3 um, while the deeper second surface region 207 may have a doping of approximately 1E17 cm-3 to 1E19 cm-3 and a depth of 0.2 um to 0.4 um.

[0054] Compared to Figure 1 The graded doping profile can help further reduce the electric field at the JTE surface and the corners of the recessed region due to the presence of multiple N+ implants 206, 207 at the top surface. In addition, the graded doping profile can help reduce implant damage at the bottom of the recessed region 204, which is typically a severe defect due to the etching process used to form the recessed region.

[0055] Figure 3 An exemplary embodiment of a semiconductor body 300 is shown, comprising a P-type doped JTE 302 having a recessed region 304, an N+ implant 306 at the top surface, and a P- compensation implant 310 at the bottom of the recessed region 304. Figure 1 Similar to the semiconductor body 100 , a P-compensation implant 310 is added at the bottom of the recessed region 304 .

[0056] In another exemplary embodiment (not shown), a P-compensation implant similar to P-compensation implant 310 may be used in Figure 2 semiconductor body 200 .

[0057] A P-compensation layer 310 may be used to balance any remaining doping in the tail of the implant. In one example, the P-compensation implant 310 may have a doping of approximately the JTE doping + 10%.

[0058] Figure 4 An exemplary embodiment of a semiconductor body 400 is shown, including a P-type doped JTE 402 having a recessed region 404, an N+ implant 406 at the top surface, and a P- compensating implant 410 above the JTE 402 and below the N+ implant 406. Figure 1 Similar to the semiconductor body 100 , a P− compensation implant 410 is added above the JTE 402 and below the N+ implant 406 to form part of the recessed region.

[0059] Semiconductor body 400 may include a P+ layer 410 at the surface of JTE 402 below N+ region 406. P+ layer 410 creates a more pronounced doping transition to N+ layer 406 and may facilitate very fine lateral dimensions of N+ region 406 because the PN junction can be triggered earlier.

[0060] The P+ layer 410 may be defined by implantation. In one example, the P+ layer 410 has a doping between 1E18 cm<-3> and 1E20 cm<-3>, preferably 1E19 cm<-3>, and a depth between 0.2 um and 0.4 um, preferably 0.3 um.

[0061] The present disclosure can be advantageously used in semiconductor devices such as power devices (Schottky, PN and MPS diodes, field effect transistors, JFETs), in particular such semiconductor devices comprising wide bandgap semiconductor materials such as SiC or gallium nitride (GaN). Figure 5 An abstract representation of an embodiment of a semiconductor body 500 , such as semiconductor body 100 , 200 , 300 , or 400 , in a semiconductor device 550 is shown.

[0062] Figure 6 An exemplary embodiment of a method 600 for fabricating a semiconductor device, such as semiconductor device 550, is shown. Dashed boxes and dashed lines depict optional steps.

[0063] In step 602, one or more recessed regions 104, 204, 304, 404 may be formed in the P-doped junction termination extension (JTE) implant 102, 202, 302, 402 of the semiconductor body 100, 200, 300, 400, 500. The depth of the recessed region may be less than the depth of the JTE implant. In one exemplary embodiment, the depth of the recessed region may be less than half the depth of the JTE implant.

[0064] In step 604, an N+ implant 106, 206, 306, 406 may be formed on the top surface of the JTE implant such that the N+ implant forms a portion of the mesa region between the recessed regions. In one exemplary embodiment, the N+ implant may be formed by ion implantation or during epitaxial growth.

[0065] A plurality of N+ implants, such as two N+ implants, may be formed on the top surface of the JTE implant, with doping decreasing downward from the top surface of the JTE implant, via step 606. In one exemplary embodiment, the plurality of N+ implants may be formed using multiple implant steps with increasing dose and energy to generate a graded doping profile, with doping decreasing downward from the top surface of the JTE implant.

[0066] A plurality of recessed regions having substantially constant width and substantially constant spacing may be formed via step 608. Alternatively, a plurality of recessed regions having increasing spacing along the outer edge of the JTE implant from the active area to the terminal may be formed via step 610.

[0067] In step 612, further recessed regions may be etched outside the JTE implant and near the edges of the mold. The further recessed regions may be etched during the same process 602, 608, 610 used to form the recessed regions in the JTE.

[0068] In step 614 , during the same process 604 used to form the N+ implant on top of the JTE implant, an N+ implant may be formed on top of the further recessed region.

[0069] In step 616 , a P-compensation implant may be formed at the bottom of the recessed region.

[0070] In step 618 , a P+ implant may be formed on top of the JTE implant and below the N+ implant such that the P+ implant forms a portion of the mesa region between the recessed regions.

[0071] It will be appreciated that the steps may be performed in a different order, depending on the production process of the semiconductor body.

Claims

1. A method (600) for manufacturing a semiconductor device, comprising: forming (602) one or more recessed regions in a P-doped junction termination extension (JTE) implant of a semiconductor body such that a depth of the recessed regions is less than a depth of the JTE implant; and An N+ implant is formed (604) on a top surface of the JTE implant such that the N+ implant forms a portion of a mesa region between the recessed regions.

2. The method of claim 1, wherein the depth of the recessed region is less than half the depth of the JTE implant.

3. A method according to any one of the preceding claims, wherein the method comprises forming the N+ implant by one of ion implantation or during epitaxial growth.

4. The method of any of the preceding claims, wherein the method comprises forming (606) a plurality of N+ implants at the top surface of the JTE implant, wherein doping decreases from the top surface downwardly of the JTE implant.

5. The method of claim 4, wherein the method comprises forming the plurality of N+ implants using a plurality of implantation steps with increasing dose and energy, generating a graded doping profile in which doping decreases from the top surface of the JTE implant downward.

6. The method according to any one of claims 1 to 5, wherein the method comprises forming (608) a plurality of recessed regions having a substantially constant width and a substantially constant spacing.

7. The method according to any one of claims 1 to 6, wherein the method comprises forming (610) a plurality of recessed regions having increasing spacing along an outer edge of the JTE implant from an active area to a terminal end.

8. The method of any of the preceding claims, further comprising etching (612) a further recessed area outside the JTE implant and near an edge of a mold, wherein the further recessed area is etched during the same process used to form the recessed area in the JTE.

9. The method of claim 8, further comprising forming (614) an N+ implant on top of the further recessed region during the same process used to form the N+ implant on top of the JTE implant.

10. The method of any of the preceding claims, further comprising forming (616) a P-compensation implant at the bottom of the recessed area.

11. The method of any of the preceding claims, further comprising forming (618) a P+ implant on a top surface of the JTE implant and beneath the N+ implant such that the P+ implant forms a portion of the mesa region between the recessed regions.

12. A semiconductor device (550), comprising a semiconductor body (100, 200, 300, 400, 500), wherein the semiconductor body comprises: One or more recessed regions (104, 204, 304, 404) in a P-doped junction termination extension JTE region (102, 202, 302, 402), wherein the depth of the recessed regions is less than the depth of the JTE region; and An N+ implant (106, 206, 306, 406) is formed on the top surface of the JTE region so that the P+ implant forms a portion of the mesa region between the recessed regions.

13. The semiconductor device of claim 12, comprising a plurality of N+ implants (206, 207) at the top surface of the JTE implant, wherein doping decreases downward from the top surface of the JTE region.

14. The semiconductor device according to any one of claims 12-13, wherein the semiconductor body further comprises a P-compensation implant (310) at the bottom of the recessed region.

15. The semiconductor device of claim 12, formed using the method of any one of claims 1-11.

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