Terminal structure of semiconductor device and semiconductor device

Abstract

The invention relates to a terminal structure of a semiconductor device and the semiconductor device, and the terminal structure comprises a first conductive type substrate, a first conductive type epitaxial layer, a second conductive type first terminal column and a second conductive type second terminal column, the at least two second conduction type first terminal columns are sequentially arranged in the first direction, the thicknesses of the second conduction type first terminal columns in the first direction are gradually increased, and the at least two second conduction type second terminal columns are arranged on the sides, opposite to the semiconductor device cellular area, of the second conduction type first terminal columns; according to the invention, the thickness of the super junction columns in the terminal area is distributed along the curve in the first direction, the voltage resistance of the terminal area is improved, the possibility of breakdown in advance is reduced, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic structures, and in particular to a terminal structure of a semiconductor device and a semiconductor device. Background Art

[0002] Semiconductor devices are electronic devices with conductivity between that of good conductors and insulators. They use the special electrical properties of semiconductor materials to perform specific functions. They are core components of power electronics systems and can be used to generate, control, receive, transform, amplify signals and perform energy conversion. Their performance directly affects energy conversion efficiency and system reliability. Superjunction technology is widely used in the field of power semiconductor devices due to its high efficiency and low loss characteristics.

[0003] In a superjunction semiconductor structure, by adopting an alternating p-column and n-column structure in its cell region, significant optimization of the device's conduction loss and voltage resistance performance can be achieved. The terminal structure of a traditional superjunction semiconductor device usually adopts multiple P-columns and N-columns that are the same as those in the cell region, and the size of its P-columns is consistent with the size of the P-columns in the cell region.

[0004] Although this structure can also play the role of the terminal structure itself, its withstand voltage is lower than that of the cell area, causing the semiconductor to break down prematurely in the terminal area and poor reliability. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a terminal structure of a semiconductor device and a semiconductor device, so as to solve the technical problems of low terminal withstand voltage and poor reliability in the prior art.

[0006] The present invention provides a terminal structure of a semiconductor device, comprising: a first conductive type substrate; A first conductive type epitaxial layer is provided on the front surface of the first conductive type substrate; There are at least two first terminal pillars of the second conductivity type, which are arranged in sequence along the first direction and whose thickness increases gradually along the first direction; There are at least two second conductive type second terminal pillars, which are arranged on the side of the second conductive type first terminal pillar facing away from the semiconductor device cell area. The second conductive type second terminal pillars are arranged in sequence along the first direction and their thickness gradually decreases along the first direction.

[0007] Optionally, x second-conductivity-type first terminal pillars are arranged in sequence along the first direction starting from close to the semiconductor device cell region, wherein the thickness of the xth second-conductivity-type first terminal pillar along the first direction is not less than the thickness of the x-1th second-conductivity-type first terminal pillar along the first direction, and the thickness of the xth second-conductivity-type first terminal pillar is greater than the thickness of the 1st second-conductivity-type first terminal pillar.

[0008] Optionally, there are y second-conductivity-type second terminal pillars arranged in sequence along the first direction starting from the second-conductivity-type first terminal pillar, wherein the thickness of the yth second-conductivity-type second terminal pillar along the first direction is not greater than the thickness of the y-1th second-conductivity-type second terminal pillar along the first direction, and the thickness of the yth second-conductivity-type second terminal pillar is less than the thickness of the 1st second-conductivity-type second terminal pillar.

[0009] Optionally, the second conductive type first terminal pillar and the second conductive type second terminal pillar have the same length along the second direction.

[0010] Optionally, the number of the second conductive type first terminal pillars is less than the number of the second conductive type second terminal pillars.

[0011] Optionally, a first conductive type terminal post is provided between two adjacent second conductive type first terminal posts, between two adjacent second conductive type second terminal posts, and between an adjacent second conductive type first terminal post and a second conductive type second terminal post; The ratio of the thickness of the second conductive type first terminal column to the adjacent first conductive type terminal column near the cell area along the first direction is the same as the ratio of the thickness of the second conductive type second terminal column to the adjacent first conductive type terminal column near the cell area along the first direction.

[0012] Optionally, a field oxide layer is provided on the front surface of the first conductive type epitaxial layer, and the field oxide layer is provided on the first conductive type epitaxial layer in regions corresponding to the second conductive type first terminal pillar and the second conductive type second terminal pillar.

[0013] The present invention provides a semiconductor device, comprising a cell region and a terminal region, wherein the terminal region comprises a terminal structure of the semiconductor device, and the cell region and the terminal region share a first conductive type substrate and a first conductive type epitaxial layer; The cellular region includes: At least two second conductive type columns are provided, extending from the front side to the back side of the first conductive type epitaxial layer; A second conductive type body region is provided on the front surface of the first conductive type epitaxial layer and is located within the first conductive type epitaxial layer; A first conductive type source region is disposed on the front side of the second conductive type body region and is located within the second conductive type body region; a gate structure, arranged between two adjacent second-conductivity-type main pillars and on the front surface of the second-conductivity-type epitaxial layer; an insulating dielectric layer, disposed on a front surface of the second conductive type body region, wherein a plurality of metal contact through-holes are formed in the insulating dielectric layer, the plurality of metal contact through-holes being disposed corresponding to the second conductive type pillars and communicating with the second conductive type pillars and the first conductive type source region; a front metal layer, disposed on the front surface of the insulating dielectric layer, wherein a portion of the front metal layer located at the metal contact through-hole extends into the metal contact through-hole until the metal contact through-hole is completely filled; The back metal layer is arranged on the back side of the first conductive type substrate.

[0014] Optionally, the thickness of the second conductive type column along the first direction is not greater than the thickness of the second conductive type first terminal column along the first direction.

[0015] Optionally, the gate structure includes a first trench opened on the front surface of the first conductive type epitaxial layer, a gate is arranged in the first trench, and a gate oxide layer is arranged between the gate and the inner wall of the first trench.

[0016] The technical solution of the present invention has the following advantages: 1. The terminal structure of the semiconductor device provided by the present invention is achieved by arranging a first terminal column of the second conductivity type and a second terminal column of the second conductivity type in the terminal region, and the first terminal column of the second conductivity type increases along the first direction, and the second terminal column of the second conductivity type decreases along the first direction. By changing the thickness along the first direction, the thickness curve distribution of the super junction column in the terminal region is adjusted, the voltage resistance of the terminal region is improved, the possibility of premature breakdown is reduced, and the reliability of the device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 is a schematic diagram of the overall structure of the semiconductor device of the present invention; Figure 2 for Figure 1 Enlarged view of part A in the middle.

[0019] Description of reference numerals: 1. Terminal region; 2. Cell region; 3. First conductive type substrate; 4. First conductive type epitaxial layer; 5. Second conductive type first terminal pillar; 6. Second conductive type second terminal pillar; 7. Field oxide layer; 8. Second conductive type pillar; 9. Second conductive type body region; 10. First conductive type source region; 11. Gate structure; 111. First trench; 112. Gate; 113. Gate oxide layer; 114. Shielding gate; 12. Insulating dielectric layer; 13. Front metal layer; 14. Back metal layer; 15. Metal contact hole; 16. First conductive type terminal pillar. DETAILED DESCRIPTION

[0020] Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, and not all, of the embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the description of the present invention without inventive effort are intended to fall within the scope of protection of the present invention.

[0021] Unless otherwise specified or limited, the terms "disposed," "installed," and "connected" should be interpreted broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; and direct or indirect connections through an intermediary. Those skilled in the art will understand the specific meanings of these terms based on the specific circumstances.

[0022] The directions or positional relationships indicated by terms such as "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inside" and "outside" are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience and simplification of description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, they should not be understood as limiting the present invention.

[0023] The terms "first," "second," "third," etc. are merely used to distinguish between elements of similar nature and do not indicate or imply relative importance or a particular order.

[0024] The terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than the listed elements and may also include additional elements not specifically listed.

[0025] The direction indicated by the arrow M in the figure is the first direction, and the direction indicated by the arrow N is the second direction.

[0026] Example Reference Figure 1 As shown, the present invention provides a terminal structure of a semiconductor device, which is arranged in a terminal area 1 of the semiconductor device. The terminal structure of the semiconductor device includes a first conductive type substrate 3, a first conductive type epitaxial layer 4, a second conductive type first terminal column 5 and a second conductive type second terminal column 6, wherein the first conductive type substrate 3 selects N-type silicon as a substrate, the first conductive type epitaxial layer 4 is arranged on the front side of the first conductive type substrate 3, the first conductive type epitaxial layer 4 is grown by an epitaxial process, the first conductive type epitaxial layer 4 is arranged on the front side of the first conductive type substrate, and at least two second conductive type first terminal columns 5 are arranged and arranged in sequence along a first direction. And its thickness gradually increases along the first direction, at least two second conductive type second terminal pillars 6 are provided, the number of second conductive type first terminal pillars 5 is less than the number of the second conductive type second terminal pillars 6, the second conductive type first terminal pillar 5 and the second conductive type second terminal pillar 6 are both provided on the front side of the first conductive type epitaxial layer 4 and extend toward the first conductive type substrate 3 until they extend into a columnar shape, and the second conductive type second terminal pillar 6 is provided on the side of the second conductive type first terminal pillar 5 that is away from the semiconductor device cell region 2, the second conductive type second terminal pillars 6 are arranged in sequence along the first direction and the thickness gradually decreases along the first direction.

[0027] By arranging a second conductive type first terminal column 5 and a second conductive type second terminal column 6 in the terminal area 1, and the second conductive type first terminal column 5 increases along the first direction, and the second conductive type second terminal column 6 decreases along the first direction, by changing the thickness of the second conductive type first terminal column 5 and the second conductive type second terminal column 6 along the first direction, the thickness curve of the super junction column in the terminal area 1 is distributed, the withstand voltage of the terminal area 1 is improved, the possibility of premature breakdown is reduced, and the reliability of the device is improved.

[0028] Specifically, x second conductive type first terminal pillars 5 are sequentially arranged along the first direction starting from the semiconductor device cell region 2, wherein the thickness of the xth second conductive type first terminal pillar 5 along the first direction is not less than the thickness of the x-1th second conductive type first terminal pillar 5 along the first direction, and the thickness of the xth second conductive type first terminal pillar 5 is greater than the thickness of the 1st second conductive type first terminal pillar 5, ensuring that the second conductive type first terminal pillar 5 can gradually increase in thickness along the first direction. In this embodiment, there are three second conductive type first terminal pillars 5, and the thickness from left to right along the first direction is set to 5 microns, 6 microns and 7 microns. There is no unique limitation on the number of second conductive type first terminal pillars 5, and it can be set according to actual production and specific products. In this embodiment, it is only for illustration, so the number is set to three; the second conductive type second terminal pillar 6 starts from the second conductive type first terminal pillar 5 along the first direction. There are y second-conductivity-type second terminal pillars 6 arranged in sequence in the first direction, wherein the thickness of the y-th second-conductivity-type second terminal pillar 6 along the first direction is not greater than the thickness of the y-1-th second-conductivity-type second terminal pillar 6 along the first direction, and the thickness of the y-th second-conductivity-type second terminal pillar 6 is less than the thickness of the 1st second-conductivity-type second terminal pillar 6, ensuring that the thickness of the second-conductivity-type second terminal pillar 6 can gradually decrease along the first direction, and the thickness of the second-conductivity-type second terminal pillar 6 on the far left in the figure along the first direction is less than the thickness of the second-conductivity-type first terminal pillar 5 closest to it along the first direction. In this embodiment, there are five second-conductivity-type second terminal pillars 6, and the thickness from left to right along the first direction is set to 6 microns, 5 microns, 5 microns, 4 microns and 4 microns respectively. There is no unique limitation on the number of second-conductivity-type second terminal pillars 6, and it can be set according to actual production and specific products. In this embodiment, it is only for illustration, so the number is set to five.

[0029] In addition, the number of the second conductive type first terminal pillars 5 is less than the number of the second conductive type second terminal pillars 6, and the second conductive type first terminal pillars 5 and the second conductive type second terminal pillars 6 have the same length along the second direction. The second conductive type first terminal pillars 5 and the second conductive type second terminal pillars 6 do not need to adjust their depths during production, so there is no need to change the production process too much. It is only necessary to adjust the blocking area during photolithography blocking. If the depth is inconsistent, it is necessary to adjust the photolithography parameters during photolithography, and the adjustment is cumbersome. Each different depth needs to be photolithographically performed independently, and the production efficiency is low.

[0030] As a specific embodiment, part of the first conductive type epitaxial layer 4 between two adjacent second conductive type first terminal pillars 5, between two adjacent second conductive type second terminal pillars 6, and between adjacent second conductive type first terminal pillars 5 and second conductive type second terminal pillars 6 is set as a first conductive type terminal pillar 16, and the ratio of the thickness of the second conductive type first terminal pillar 5 and its adjacent first conductive type terminal pillar 16 on the side close to the cell region 2 along the first direction is the same as the ratio of the thickness of the second conductive type second terminal pillar 6 and its adjacent first conductive type terminal pillar 16 on the side close to the cell region 2 along the first direction. Therefore, when the thickness of the second conductive type second terminal pillar 6 and the second conductive type first terminal pillar 5 increases or decreases, the corresponding first conductive type terminal pillar 16 will be adjusted accordingly, thereby avoiding inconsistent proportions, which requires adjusting the concentration of the second conductive type ions to ensure charge balance.

[0031] As a specific embodiment, a field oxide layer 7 is provided on the front side of the first conductive type epitaxial layer 4. The field oxide layer 7 is provided in the area corresponding to the second conductive type first terminal column 5 and the second conductive type second terminal column 6 on the first conductive type epitaxial layer 4. The terminal area 1 is blocked and isolated by the field oxide layer 7.

[0032] Example 2 Reference Figure 1 and 2 As shown, this embodiment provides a semiconductor device, further comprising a terminal region 1 and a cell region 2, wherein the terminal region 1 is provided with a terminal structure of the semiconductor device in Example 1, the cell region 2 and the terminal region 1 share a first conductive type substrate 3 and a first conductive type epitaxial layer 4, the cell region 2 comprises a second conductive type body region 9, a second conductive type column 8, a gate structure 11 and a first conductive type source region 10, wherein the second conductive type body region 9 is provided on the front surface of the first conductive type epitaxial layer 4 and is located in the first conductive type epitaxial layer 4, the second conductive type body region 9 and the first conductive type epitaxial layer 4 have the same width, at least two second conductive type columns 8 are provided, and the second conductive type columns 8 extend from the front surface of the first conductive type epitaxial layer 4 having the second conductive type body region 9 to the back surface of the first conductive type epitaxial layer 4, until extending from the second conductive type body region 9 to the first conductive type epitaxial layer 4 below the second conductive type body region 9.

[0033] At least one gate structure 11 is provided correspondingly, and a gate structure 11 is provided between each of two adjacent second conductivity type columns 8. The gate structure 11 also extends from the front surface of the first conductivity type epitaxial layer 4 having the second conductivity type body region 9 to the back surface of the first conductivity type epitaxial layer 4, until it extends from the second conductivity type body region 9 to the first conductivity type epitaxial layer 4 below the second conductivity type body region 9. The first conductive type source region 10 is arranged on the front side of the second conductive type body region 9 and is located in the second conductive type body region 9. In this embodiment, a plurality of first conductive type source regions 10 are provided, and each gate structure 11 corresponds to two first conductive type source regions 10, which are respectively located on both sides of the gate structure 11 toward the second conductive type column 8, and extend toward the second conductive type column 8 and contact the second conductive type column 8.

[0034] The gate structure 11 is configured as a trench gate. The gate structure 11 includes a first trench 111 opened on the front surface of the first conductive type epitaxial layer 4. The first trench 111 extends from the front surface of the first conductive type epitaxial layer 4 having the second conductive type body region 9 to the back surface of the first conductive type epitaxial layer 4 until it extends into the first conductive type epitaxial layer 4 on the back surface of the second conductive type body region 9. A gate 112 is arranged in the first trench 111. A gate oxide layer 113 is arranged between the gate 112 and the inner wall of the first trench 111. The gate 112 is separated by the gate oxide layer 113 and the inner wall of the first trench 111. The gate 112 is conductive polysilicon. The thickness of the gate oxide layer 113 between the gate 112 and the bottom wall of the first trench 111 is greater than the thickness of the gate oxide layer 113 between the gate 112 and the inner side wall of the first trench 111. The thicker gate oxide layer 113 at the bottom can improve the gate oxygen reliability of the device.

[0035] The thickness of the second conductive type column 8 along the first direction is less than the thickness of the second conductive type first terminal column 5 along the first direction, and the length of the second conductive type column 8 along the second direction is the same as the length of the second conductive type first terminal column 5 and the second conductive type second terminal column 6 along the second direction, thereby ensuring that the super junction column lengths of the cell area 2 and the terminal area 1 remain consistent, thereby not changing the normal production process flow and having little impact on the original process.

[0036] As another embodiment, the gate structure 11 also includes a shielding gate 114 arranged in the first trench 111. The shielding gate 114 is located below the gate 112, and the shielding gate 114 and the inner wall of the first trench 111 are also separated by the gate oxide layer 113. There is a gap between the shielding gate 114 and the gate 112 and they are also separated by the gate oxide layer 113. By setting the shielding gate 114, faster switching speed and lower switching loss can be achieved, further reducing the on-resistance and Miller capacitance, and improving the switching speed.

[0037] As a specific embodiment, it also includes an insulating dielectric layer 12, a front metal layer 13 and a back metal layer 14, wherein the insulating dielectric layer 12 is arranged on the front side of the second conductive type body region 9 and covers the entire second conductive type body region 9, and a plurality of metal contact holes 15 are opened in the insulating dielectric layer 12, and the metal contact holes 15 are arranged corresponding to the second conductive type columns 8 and penetrate into the second conductive type columns 8 to communicate with the second conductive type columns 8 and the first conductive type source region 10; the front metal layer 13 is arranged on the front side of the insulating dielectric layer 12, and the front metal layer 13 is located at the metal contact holes 15 and partially extends into the metal contact holes 15 until the metal contact holes 15 are filled. At this time, part of the front metal layer 13 in the metal contact holes 15 corresponding to the second conductive type columns 8 will contact the second conductive type columns 8 and the first conductive type source region 10; the back metal layer 14 is arranged on the back side of the first conductive type substrate 3 and covers the entire back side of the first conductive type substrate 3.

[0038] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0039] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A terminal structure of a semiconductor device, characterized in that: include: a first conductive type substrate; A first conductive type epitaxial layer is provided on the front surface of the first conductive type substrate; There are at least two first terminal pillars of the second conductivity type, which are arranged in sequence along the first direction and whose thickness increases gradually along the first direction; There are at least two second conductive type second terminal pillars, which are arranged on the side of the second conductive type first terminal pillar facing away from the semiconductor device cell area. The second conductive type second terminal pillars are arranged in sequence along the first direction and their thickness gradually decreases along the first direction.

2. The terminal structure of the semiconductor device according to claim 1, wherein: There are x second-conductivity-type first terminal pillars arranged in sequence along the first direction starting from the cell area close to the semiconductor device, wherein the thickness of the xth second-conductivity-type first terminal pillar along the first direction is not less than the thickness of the x-1th second-conductivity-type first terminal pillar along the first direction, and the thickness of the xth second-conductivity-type first terminal pillar is greater than the thickness of the 1st second-conductivity-type first terminal pillar.

3. The terminal structure of the semiconductor device according to claim 1, wherein: There are y second-conductivity-type second terminal pillars arranged in sequence along the first direction starting from the second-conductivity-type first terminal pillar, wherein the thickness of the yth second-conductivity-type second terminal pillar along the first direction is not greater than the thickness of the y-1th second-conductivity-type second terminal pillar along the first direction, and the thickness of the yth second-conductivity-type second terminal pillar is less than the thickness of the 1st second-conductivity-type second terminal pillar.

4. The terminal structure of the semiconductor device according to claim 1, wherein: The second conductive type first terminal pillar and the second conductive type second terminal pillar have the same length along the second direction.

5. The terminal structure of the semiconductor device according to claim 1, wherein: The number of the second conductive type first terminal pillars is less than the number of the second conductive type second terminal pillars.

6. The terminal structure of the semiconductor device according to claim 1, wherein: The first conductive type terminal pillars are set between two adjacent second conductive type first terminal pillars, between two adjacent second conductive type second terminal pillars, and between adjacent second conductive type first terminal pillars and second conductive type second terminal pillars; The ratio of the thickness of the second conductive type first terminal column to the adjacent first conductive type terminal column near the cell area along the first direction is the same as the ratio of the thickness of the second conductive type second terminal column to the adjacent first conductive type terminal column near the cell area along the first direction.

7. The terminal structure of the semiconductor device according to claim 1, wherein: A field oxide layer is provided on the front surface of the first conductive type epitaxial layer. The field oxide layer is provided on the first conductive type epitaxial layer in regions corresponding to the second conductive type first terminal pillar and the second conductive type second terminal pillar.

8. A semiconductor device, characterized in that: comprising a cell region and a terminal region, wherein the terminal region comprises the terminal structure of the semiconductor device according to any one of claims 1 to 7, and the cell region and the terminal region share the first conductive type substrate and the first conductive type epitaxial layer; The cellular region includes: At least two second conductive type columns are provided, extending from the front side to the back side of the first conductive type epitaxial layer; A second conductive type body region is provided on the front surface of the first conductive type epitaxial layer and is located within the first conductive type epitaxial layer; A first conductive type source region is disposed on the front side of the second conductive type body region and is located within the second conductive type body region; a gate structure, arranged between two adjacent second-conductivity-type main pillars and on the front surface of the second-conductivity-type epitaxial layer; an insulating dielectric layer, disposed on a front surface of the second conductive type body region, wherein a plurality of metal contact through-holes are formed in the insulating dielectric layer, the plurality of metal contact through-holes being disposed corresponding to the second conductive type pillars and communicating with the second conductive type pillars and the first conductive type source region; a front metal layer, disposed on the front surface of the insulating dielectric layer, wherein a portion of the front metal layer located at the metal contact through-hole extends into the metal contact through-hole until the metal contact through-hole is completely filled; The back metal layer is arranged on the back side of the first conductive type substrate.

9. The semiconductor device according to claim 8, wherein The thickness of the second conductive type column along the first direction is not greater than the thickness of the second conductive type first terminal column along the first direction.

10. The semiconductor device according to claim 8, wherein The gate structure includes a first trench opened on the front surface of the first conductive type epitaxial layer, a gate is arranged in the first trench, and a gate oxide layer is arranged between the gate and the inner wall of the first trench.

Images