Array substrate, preparation method thereof and display panel

Abstract

The invention discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate and a transistor, wherein the transistor comprises an insulating layer, a gate electrode, a source electrode, a drain electrode and an active layer; the gate electrode is located on the surface of one side of the substrate, the insulating layer covers the gate electrode and other areas in the surface of one side of the substrate, the source electrode, the drain electrode and the active layer are all located on the surface of the side, away from the substrate, of the insulating layer, and the active layer is in lap joint between the source electrode and the drain electrode; the source electrode and the drain electrode are made of light-transmitting conductive materials. Compared with a metal material, the surface of the source electrode and the surface of the drain electrode which are made of the light-transmitting conductive material are smoother, the thickness of the constructed source electrode and the constructed drain electrode is thinner than that of the metal electrode, when the active layer is in lap joint with the source electrode and the drain electrode, the active layer is not prone to breakage and is better attached to the source electrode and the drain electrode, and the service life of the active layer is prolonged. And the stability of the constructed transistor is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of display devices, and in particular relates to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] Liquid crystal display panels usually transmit electrical signals and control the display images through thin film transistors in an array substrate.

[0003] During the actual preparation process of the thin-film transistors in the array substrate, the metal electrode surface may be uneven and irregular. Due to the influence of the process, the minimum thickness of most metal electrodes is also relatively thick, which can easily lead to breakage and poor contact of the film layer overlapping the metal electrode, affecting the electrical properties of the thin-film transistor and thus affecting the display effect of the liquid crystal display panel. Summary of the Invention

[0004] The purpose of the present application is to provide an array substrate and a preparation method thereof, and a display panel, aiming to solve the problem of fracture and poor contact of the film layer overlapped on the metal electrode caused by the uneven surface of the metal electrode in the traditional solution.

[0005] A first aspect of an embodiment of the present application provides an array substrate, comprising: a substrate; a transistor located on the substrate, the transistor comprising an insulating layer, a gate electrode, a source electrode, a drain electrode and an active layer; the gate electrode is located on one side surface of the substrate, the insulating layer covers the gate electrode and other areas on one side surface of the substrate, the source electrode, the drain electrode and the active layer are all located on a side surface of the insulating layer away from the substrate, and the active layer is overlapped between the source electrode and the drain electrode; the source electrode and the drain electrode are both made of a light-transmitting conductive material.

[0006] In one embodiment, the array substrate further includes a common electrode and a pixel electrode, the common electrode is located on the surface of the insulating layer away from the substrate, the source electrode, the drain electrode and the common electrode are arranged in the same layer and material, the pixel electrode is located on the side of the common electrode away from the substrate, the pixel electrode is connected to the source electrode, or the pixel electrode is electrically connected to the drain electrode.

[0007] In one embodiment, a groove is provided on a surface of the insulating layer between the source electrode and the drain electrode, the surface being away from the substrate; and the active layer at least covers the groove.

[0008] In one embodiment, the transistor further includes a first external electrode and a second external electrode, and the array substrate further includes a third external electrode; the first external electrode is located on the source electrode, the second external electrode is located on the drain electrode; and the third external electrode is located on the common electrode.

[0009] In one embodiment, the active layer at least covers the surfaces of the first external electrode, the second external electrode, the third external electrode, the source electrode, and the drain electrode on a side away from the substrate.

[0010] In one embodiment, the array substrate further includes a passivation layer, and the passivation layer at least covers the transistor.

[0011] In one embodiment, the array substrate further includes a buffer layer and a metal trace, and the insulating layer further includes a connecting through-hole; the metal trace is located on a surface of the insulating layer away from the substrate, the gate electrode is connected to the metal trace through the connecting through-hole, the buffer layer is arranged between the metal trace and the insulating layer and between the metal trace and the gate electrode, and the material of the buffer layer is the light-transmitting conductive material.

[0012] A second aspect of an embodiment of the present application provides a method for preparing an array substrate, comprising: providing a substrate; forming a gate electrode and an insulating layer in sequence on one side of the substrate; the insulating layer covering at least the gate electrode and other areas of the substrate except the gate electrode; forming a transparent conductive film layer on the insulating layer, and etching the transparent conductive film layer to form a source electrode and a drain electrode; forming an active layer between the source electrode and the drain electrode; wherein the active layer is overlapped on the source electrode and the drain electrode, and the gate electrode, the source electrode, the drain electrode and the active layer are used to form a transistor.

[0013] In one embodiment, the forming of a transparent conductive film layer on the insulating layer and etching the transparent conductive film layer to form a source electrode and a drain electrode includes: sequentially forming a transparent conductive film layer and a metal film layer on the insulating layer; etching the metal film layer to form a first connecting electrode and a second connecting electrode; etching the transparent conductive film layer to form a source electrode and a drain electrode; and forming an active layer between the source electrode and the drain electrode includes: forming the active layer on the first external electrode, the second external electrode, the third external electrode, the surface of the source electrode and the drain electrode on one side away from the substrate, and between the source electrode and the drain electrode.

[0014] A third aspect of the embodiments of the present application provides a display panel, comprising the array substrate as described above.

[0015] The beneficial effects of the embodiments of the present application compared with the prior art are: compared with metal materials, the surfaces of the source electrode and the drain electrode made of transparent conductive material are smoother, and the thickness of the constructed source electrode and the drain electrode is also thinner than that of the metal electrode. When the active layer is overlapped on the source electrode and the drain electrode, the active layer is not easy to break and is more closely fitted to the source electrode and the drain electrode, thereby improving the stability of the constructed transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic cross-sectional view of an array substrate provided in one embodiment of the present application; Figure 2 Another cross-sectional schematic diagram of an array substrate provided in one embodiment of the present application; Figure 3 Another schematic cross-sectional view of an array substrate provided in one embodiment of the present application; Figure 4 A flowchart of a method for preparing an array substrate provided in one embodiment of the present application; Figure 5 Schematic diagram of the gate electrode and the insulating layer obtained by performing step S200; Figure 6 A schematic diagram of a source electrode and a drain electrode obtained by performing step S300; Figure 7 A schematic diagram of a display panel provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0018] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0019] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0021] It should be noted that in the fabrication process of thin-film transistors using a bottom-gate coplanar structure, the source and drain electrodes of the thin-film transistor are typically constructed first, followed by the active layer of the thin-film transistor. When the source and drain electrodes are made of metal materials (such as copper or aluminum), if the surfaces of the metal source and drain electrodes are typically uneven, and the thickness of the metal source and drain electrodes is typically much greater than that of the active layer, the active layer is prone to fracture, resulting in an increase in the on-resistance of the thin-film transistor and affecting its conductive performance.

[0022] At the same time, when the source electrode and the drain electrode of the thin film transistor are made of metal, the channel length of the thin film transistor is also relatively large, which affects the light transmittance of the display panel.

[0023] Figure 1 A cross-sectional schematic diagram of an array substrate provided in an embodiment of the present application is shown. For ease of description, only the portion related to this embodiment is shown, which is described in detail as follows: An array substrate 10 includes a substrate 100 and a transistor 200 .

[0024] The substrate 100 may be made of transparent materials such as glass and resin.

[0025] The transistor 200 is located on the substrate 100 , and includes an insulating layer 210 , a gate electrode 220 , a source electrode 230 , a drain electrode 240 , and an active layer 250 .

[0026] The gate electrode 220 is located on one side surface of the substrate 100 . The insulating layer 210 covers the gate electrode 220 and other areas of the one side surface of the substrate 100 . The source electrode 230 , the drain electrode 240 , and the active layer 250 are all located on the side surface of the insulating layer 210 away from the substrate 100 . The active layer 250 overlaps between the source electrode 230 and the drain electrode 240 . The source electrode 230 and the drain electrode 240 are both made of light-transmitting conductive materials.

[0027] Compared with metal materials, the surfaces of the source electrode 230 and the drain electrode 240 made of transparent conductive materials are smoother, and the thickness of the constructed source electrode 230 and the drain electrode 240 is also thinner than that of the metal electrodes. When the active layer 250 is overlapped on the source electrode 230 and the drain electrode 240, the active layer 250 is not easy to break and is more closely attached to the source electrode 230 and the drain electrode 240, thereby improving the stability of the constructed transistor 200.

[0028] It is understood that the array substrate 10 may include multiple transistors 200. The structure of each transistor 200 may be the same as the transistor 200 of this embodiment, or the structure of some transistors 200 may be different, depending on actual needs. The multiple transistors 200 each include multiple gate electrodes 220, source electrodes 230, drain electrodes 240, and active layers 250. The multiple transistors 200 may share the same insulating layer 210.

[0029] Specifically, the active layer 250 may be made of an oxide semiconductor material, for example, indium gallium zinc oxide (IGZO).

[0030] In one embodiment, the source electrode 230 and the drain electrode 240 are both made of indium tin oxide (ITO).

[0031] In one embodiment, if Figure 2 As shown, the array substrate 10 also includes a common electrode 310 and a pixel electrode 320. The common electrode 310 is located on the surface of the insulating layer 210 away from the substrate 100. The source electrode 230, the drain electrode 240 and the common electrode 310 are arranged in the same layer and the same material. The pixel electrode 320 is located on the side of the common electrode 310 away from the substrate 100, and the pixel electrode 320 is electrically connected to the source electrode 230 or the drain electrode 240.

[0032] It should be noted that, in an FFS (Fringe Field Switching) mode liquid crystal panel, it is usually necessary to form a fringe electric field through the common electrode 310 and the pixel electrode 320 to control the liquid crystal and achieve the purpose of displaying an image.

[0033] In this embodiment, by setting the source electrode 230, the drain electrode 240 and the common electrode 310 in the same layer and the same material, the source electrode 230, the drain electrode 240 and the common electrode 310 can be constructed simultaneously in the same process, thereby completing the construction of the source electrode 230 and the drain electrode 240 without adding additional processes.

[0034] In one embodiment, the distance between the source electrode 230 and the drain electrode 240 is less than or equal to 4 μm.

[0035] In some embodiments, the spacing between the source electrode 230 and the drain electrode 240 is equal to 3 μm.

[0036] It should be noted that the spacing between the source electrode 230 and the drain electrode 240 corresponds to the channel length of the transistor 200. Due to the limitations of the metal etching process, the machining accuracy of the metal electrodes is limited, making it difficult to shorten the spacing between the metal electrodes. However, indium tin oxide has higher etching accuracy, allowing the construction of a transistor 200 with a shorter channel length.

[0037] In one embodiment, if Figure 2 As shown, a groove 211 is provided on a surface of the insulating layer 210 between the source electrode 230 and the drain electrode 240 , which is away from the substrate 100 .

[0038] The depth of the groove 211 is greater than or equal to 10 nm, and the active layer 250 at least covers the groove 211 .

[0039] When the source electrode 230 and the drain electrode 240 are made of indium tin oxide and the active layer 250 is made of indium gallium zinc oxide, the etching liquid of the source electrode 230 and the drain electrode 240 will usually also affect the active layer 250. By etching a groove 211 on the insulating layer 210 between the source electrode 230 and the drain electrode 240, the etching liquid remaining between the source electrode 230 and the drain electrode 240 can be removed, thereby preventing the active layer 250 from being affected by the residual etching liquid and improving the product yield.

[0040] In one embodiment, if Figure 2 As shown, the transistor 200 further includes a first external electrode 260 and a second external electrode 270 , and the array substrate 10 further includes a third external electrode 330 .

[0041] The first external electrode 260 is located on the source electrode 230 , the second external electrode 270 is located on the drain electrode 240 , and the third external electrode 330 is located on the common electrode 310 .

[0042] It should be noted that the first external electrode 260 , the second external electrode 270 and the third external electrode 330 are used to connect with other wirings and the transistor 200 according to actual needs to form a required circuit.

[0043] The first external electrode 260 , the second external electrode 270 , the third external electrode 330 , the source electrode 230 , the drain electrode 240 , and the common electrode 310 can be manufactured in the same process by using a double photolithography process.

[0044] The first external electrode 260 , the second external electrode 270 and the third external electrode 330 may be conventional metal electrodes.

[0045] In one embodiment, if Figure 3 As shown, the active layer 250 also covers at least one surface of the first external electrode 260 , the second external electrode 270 , the third external electrode 330 , the source electrode 230 , and the drain electrode 240 away from the substrate 100 .

[0046] Specifically, the active layer 250 can be prepared by deposition and etching after the first external electrode 260 , the second external electrode 270 , the third external electrode 330 , the source electrode 230 and the drain electrode 240 are prepared.

[0047] Compared with metal materials, common passivation materials and insulating materials are more easily adhered to the active layer 250. By using the active layer 250 as a buffer between the first external electrode 260, the second external electrode 270, the third external electrode 330 and the passivation material and the insulating material, without adding additional preparation processes, only certain adjustments need to be made to the etching steps of the active layer 250 to reduce the separation of the deposited passivation material and insulating material from the transistor 200.

[0048] In one embodiment, if Figure 3 As shown, the array substrate 10 further includes a passivation layer 400 , and the passivation layer 400 at least covers the transistor 200 .

[0049] Specifically, the passivation layer 400 may simultaneously cover the common electrode 310, as well as the source electrode 230, the drain electrode 240, the active layer 250 of the transistor 200, and other areas of the surface of the insulating layer 210 away from the substrate 100. The pixel electrode 320 may be disposed on the surface of the passivation layer 400 away from the substrate 100 and connected to the corresponding electrode through a through hole in the passivation layer 400.

[0050] The passivation layer 400 is used to isolate and protect the transistor 200 .

[0051] It can be understood that when the active layer 250 also covers at least the surface of the first external electrode 260, the second external electrode 270, the third external electrode 330, the source electrode 230 and the drain electrode 240 on the side away from the substrate 100, the passivation layer 400 is mainly in contact with the insulating layer 210 and the active layer 250, thereby improving the stability of the passivation layer 400 and reducing the separation of the passivation layer 400 from the transistor 200.

[0052] In one embodiment, if Figure 3 As shown, the array substrate 10 further includes a buffer layer 500 and a metal trace 600 , and the insulating layer 210 further includes a connecting through hole 212 .

[0053] The metal trace 600 is located on the side surface of the insulating layer 210 away from the substrate 100, the gate electrode 220 is connected to the metal trace 600 through the connecting through hole 212, and the buffer layer 500 is arranged between the metal trace 600 and the insulating layer 210 and between the metal trace 600 and the gate electrode 220. The material of the buffer layer 500 is a light-transmitting conductive material.

[0054] It is understandable that the buffer layer 500 made of a light-transmitting conductive material can be constructed simultaneously with the source electrode 230 , the drain electrode 240 and the common electrode 310 , thereby reducing the number of preparation steps.

[0055] Figure 4 A flow chart of a method for preparing an array substrate 10 provided in an embodiment of the present application is shown. For ease of description, only the portion related to this embodiment is shown, which is described in detail as follows: A method for preparing an array substrate 10 includes steps S100 to S400.

[0056] Step S100: providing a substrate 100 .

[0057] Step S200: forming a gate electrode 220 and an insulating layer 210 in sequence on one side of the substrate 100. The insulating layer 210 at least covers the gate electrode 220 and other regions of the substrate 100 except the gate electrode 220.

[0058] The gate electrode 220 and the insulating layer 210 obtained by performing step S200 are as follows: Figure 5 As shown, it can be understood that the specific number, arrangement, size, shape and other parameters of the gate electrode 220 can be set according to actual needs, and this embodiment does not limit them. For example, multiple gate electrodes 220 can be constructed on the substrate 100 according to the number of transistors 200 to be constructed.

[0059] Before forming the insulating layer 210 , other wirings besides the gate electrode 220 may be constructed on the substrate 100 according to actual needs. For example, wirings for connecting part of the gate electrode 220 may be constructed to achieve synchronous control of the transistor 200 .

[0060] Step S300 : forming a transparent conductive film layer on the insulating layer 210 , and patterning the transparent conductive film layer to form a source electrode 230 and a drain electrode 240 .

[0061] The source electrode 230 and the drain electrode 240 obtained by performing step S300 are as follows: Figure 6 As shown, specifically, a transparent conductive film layer covering the surface of the insulating layer 210 can be formed by depositing an indium tin oxide material, and then etching is performed to obtain the required source electrode 230 and drain electrode 240 according to requirements.

[0062] It can be understood that the specific number, arrangement, size, shape and other parameters of the source electrode 230 and the drain electrode 240 can be set according to actual needs, and this embodiment does not limit them. For example, multiple source electrodes 230 and drain electrodes 240 can be constructed on the insulating layer 210 according to the number of transistors 200 to be constructed.

[0063] In some embodiments, step S300 may be: forming a transparent conductive film layer and a metal film layer in sequence on the insulating layer 210, and patterning the transparent conductive film layer and the metal film layer to form a source electrode 230 and a drain electrode 240, as well as a first external electrode 260 and a second external electrode 270 respectively located on the source electrode 230 and the drain electrode 240.

[0064] The specific processes and procedures used for the source electrode 230 , the drain electrode 240 , the first external electrode 260 , and the second external electrode 270 can be set according to actual needs, and are not limited in this embodiment.

[0065] Step S400 : forming an active layer 250 between the source electrode 230 and the drain electrode 240 . The active layer 250 overlaps the source electrode 230 and the drain electrode 240 . The gate electrode 220 , the source electrode 230 , the drain electrode 240 and the active layer 250 are used to form the transistor 200 .

[0066] The active layer 250 obtained by executing step S400 is as follows: Figure 1 As shown, specifically, an active layer 250 for connecting the source electrode 230 and the drain electrode 240 can be formed by depositing an oxide semiconductor material and performing patterned etching. The active layer 250 can cover the surface of the insulating layer 210 between the source electrode 230 and the drain electrode 240.

[0067] It is understood that when multiple transistors 200 need to be constructed, the active layers 250 of the respective transistors 200 can be constructed simultaneously.

[0068] In some embodiments, step S400 may include forming an active layer 250 on the surfaces of the first external electrode 260 , the second external electrode 270 , the third external electrode 330 , the source electrode 230 , and the drain electrode 240 away from the substrate 100 .

[0069] Figure 7 A schematic diagram of a display panel provided in an embodiment of the present application is shown. For ease of explanation, only the portion related to this embodiment is shown, which is described in detail as follows: A display panel 20 includes the array substrate 10 according to any one of the above embodiments.

[0070] Since the display panel 20 includes the array substrate 10 of any of the above embodiments, the display panel 20 has the beneficial effects of the array substrate 10 of any of the above embodiments, which will not be described in detail here.

[0071] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0072] Through the description of the above embodiments, those skilled in the art will understand that for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0073] It should be understood that the devices and methods disclosed in the several embodiments provided in this application can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device. In addition, some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0074] Units described as separate components may or may not be physically separate. Components shown as units may be one physical unit or multiple physical units. That is, they may be located in one place or distributed across multiple locations. Depending on actual needs, some or all of the units may be selected to achieve the objectives of this solution.

[0075] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit; may also exist physically separately; or some units may be integrated into a single unit, while some units may exist physically separately. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0076] It should be noted that all or part of the above-mentioned embodiments provided in this application (for example, part or all of any feature) can be arbitrarily combined or used in conjunction with each other.

[0077] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An array substrate, characterized in that: The array substrate includes: substrate; A transistor is located on the substrate, the transistor comprising an insulating layer, a gate electrode, a source electrode, a drain electrode and an active layer; The gate electrode is located on one side surface of the substrate, the insulating layer covers the gate electrode and other areas on one side surface of the substrate, the source electrode, the drain electrode and the active layer are all located on a side surface of the insulating layer away from the substrate, and the active layer is overlapped between the source electrode and the drain electrode; The source electrode and the drain electrode are both made of light-transmitting conductive materials.

2. The array substrate according to claim 1, wherein: The array substrate also includes a common electrode and a pixel electrode. The common electrode is located on the surface of the insulating layer away from the substrate. The source electrode, the drain electrode and the common electrode are arranged in the same layer and material. The pixel electrode is located on the side of the common electrode away from the substrate. The pixel electrode is connected to the source electrode, or the pixel electrode is electrically connected to the drain electrode.

3. The array substrate according to claim 1, wherein: A groove is provided on a surface of the insulating layer between the source electrode and the drain electrode, the surface being away from the substrate; and the active layer at least covers the groove.

4. The array substrate according to any one of claims 1 to 3, wherein: The transistor further includes a first external electrode and a second external electrode, and the array substrate further includes a third external electrode; The first external electrode is located on the source electrode, the second external electrode is located on the drain electrode; and the third external electrode is located on the common electrode.

5. The array substrate according to claim 4, wherein: The active layer at least covers surfaces of the first external electrode, the second external electrode, the third external electrode, the source electrode, and the drain electrode on a side away from the substrate.

6. The array substrate according to any one of claims 1 to 3, wherein: The array substrate further includes a passivation layer, and the passivation layer at least covers the transistor.

7. The array substrate according to any one of claims 1 to 3, wherein: The array substrate further includes a buffer layer and metal traces, and the insulating layer further includes connecting through holes; The metal trace is located on a surface of the insulating layer away from the substrate, the gate electrode is connected to the metal trace through the connecting through hole, the buffer layer is arranged between the metal trace and the insulating layer and between the metal trace and the gate electrode, and the material of the buffer layer is the light-transmitting conductive material.

8. A method for preparing an array substrate, characterized in that: include: providing a substrate; forming a gate electrode and an insulating layer in sequence on one side of the substrate; The insulating layer at least covers the gate electrode and other regions of the substrate except the gate electrode; forming a transparent conductive film layer on the insulating layer, and etching the transparent conductive film layer to form a source electrode and a drain electrode; An active layer is formed between the source electrode and the drain electrode; wherein the active layer overlaps the source electrode and the drain electrode, and the gate electrode, the source electrode, the drain electrode and the active layer are used to constitute a transistor.

9. The preparation method according to claim 8, wherein The step of forming a transparent conductive film layer on the insulating layer and etching the transparent conductive film layer to form a source electrode and a drain electrode comprises: forming a transparent conductive film layer and a metal film layer on the insulating layer in sequence; etching the metal film layer to form a first connecting electrode and a second connecting electrode; and etching the transparent conductive film layer to form a source electrode and a drain electrode; The forming of an active layer between the source electrode and the drain electrode comprises: The active layer is formed between the first external electrode, the second external electrode, surfaces of the source electrode and the drain electrode that are away from the substrate, and between the source electrode and the drain electrode.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 8.

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