Tunneling field effect transistor

Abstract

A tunneling field effect transistor is provided. The tunneling field effect transistor includes a semiconductor layer disposed on a substrate and having a first semiconductor region and a second semiconductor region. A band gap of the first semiconductor region is smaller than a band gap of the second semiconductor region, and a work function of the first semiconductor region is greater than a work function of the second semiconductor region. A gate overlapping the semiconductor layer is disposed over or under the semiconductor layer. A source and a drain are connected to the first semiconductor region and the second semiconductor region, respectively. The first semiconductor region has a first conductivity type source region in a region adjacent to the source and a first channel region overlapping the gate, and the second semiconductor region has a second conductivity type drain region in a region adjacent to the drain and a second channel region overlapping the gate. In the on state, the conduction band potential energy of the first channel region is equal to or higher than the conduction band potential energy of the second channel region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a tunneling field effect transistor. Background Art

[0002] Unlike conventional field-effect transistors, tunneling field-effect transistors (TFETs) operate using tunneling between the source, channel, and drain, rather than relying on depletion or inversion in the channel region. This enables them to achieve lower subthreshold swings, making them suitable for low-power devices.

[0003] However, TFETs have the disadvantage that their manufacturing process is somewhat complicated due to the need to dope the source and drain with different conductivity types, which requires additional measures to prevent alignment errors. In addition, since TFETs induce on-current through tunneling, ensuring high on-current characteristics can be challenging. Summary of the Invention

[0004] Technical issues

[0005] The technical problem to be solved by the present invention is to provide a tunneling field effect transistor which exhibits high on-current characteristics while maintaining a relatively simple manufacturing process.

[0006] The technical challenges solved by the present invention are not limited to those mentioned above. Those skilled in the art will clearly understand other unstated technical challenges from the following description.

[0007] Technical Solution

[0008] To solve the above problems, one aspect of the present invention provides a tunneling field-effect transistor. The tunneling field-effect transistor includes: a semiconductor layer disposed on a substrate; a gate disposed above or below the semiconductor layer and overlapping the semiconductor layer; and a source and a drain, respectively connected to at least two side surfaces of the semiconductor layer. The semiconductor layer includes a first semiconductor region connected to the source and a second semiconductor region connected to the drain. The band gap of the first semiconductor region is smaller than the band gap of the second semiconductor region. The first semiconductor region includes a source region of a first conductivity type and a first channel region other than the source region, wherein the source region of the first conductivity type is induced by a charge plasma of the first conductivity type in a region adjacent to the source. The second semiconductor region includes a drain region of a second conductivity type and a second channel region other than the drain region, wherein the drain region of the second conductivity type is induced by a charge plasma of the second conductivity type in a region adjacent to the drain.

[0009] The work function of the first semiconductor region may be greater than the work function of the second semiconductor region. The first semiconductor region and the second semiconductor region may be Si 1-x Ge x pattern (0 ≤ x ≤ 1), and the Si content of the second semiconductor region may be greater than the Si content of the first semiconductor region. The first semiconductor region may be Si 1- x Ge x pattern, wherein x is in the range of 0.5 to 1. The second semiconductor region may be Si 1-x Ge x A pattern wherein x is in the range of 0 to less than 0.5.

[0010] The gate may include a first gate region overlapping the first semiconductor region and a second gate region overlapping the second semiconductor region, and a metal pattern of the first gate region may have a work function greater than a work function of the metal pattern of the second gate region. The metal pattern of the first gate region may have a work function in the range of 4.4 eV to 4.7 eV, and the metal pattern of the second gate region may have a work function in the range of 4.1 eV to 4.4 eV.

[0011] The gate insulating layer may include a first gate insulating region overlapping the first semiconductor region and a second gate insulating region overlapping the second semiconductor region, and the first gate insulating region may include a dielectric material having a higher dielectric constant than the second gate insulating region. The first gate insulating region may include a high-k dielectric material having a higher dielectric constant than silicon oxide, and the second gate insulating region may include silicon oxide or a low-k dielectric material having a lower dielectric constant than silicon oxide.

[0012] The thickness of the first semiconductor region may be smaller than the thickness of the second semiconductor region.

[0013] In order to solve the above problems, one aspect of the present invention provides another embodiment of a tunneling field effect transistor. The tunneling field effect transistor includes a semiconductor layer, which is arranged on a substrate and includes a first semiconductor region and a second semiconductor region. The band gap of the first semiconductor region is smaller than the band gap of the second semiconductor region, and the work function of the first semiconductor region is greater than the work function of the second semiconductor region. The gate overlapping the semiconductor layer is arranged above or below the semiconductor layer. The source and the drain are connected to the first semiconductor region and the second semiconductor region, respectively. The first semiconductor region includes a first conductive type source region adjacent to the source and a first channel region overlapping the gate, and the second semiconductor region includes a second conductive type drain region adjacent to the drain and a second channel region overlapping the gate. In the on state, the conduction band potential energy of the first channel region is equal to or higher than the conduction band potential energy of the second channel region.

[0014] The gate may include a first gate region overlapping the first semiconductor region and a second gate region overlapping the second semiconductor region, and a work function of a metal pattern of the first gate region may be greater than a work function of a metal pattern of the second gate region.

[0015] The first semiconductor region and the second semiconductor region may be Si 1-x Ge x pattern (0 ≤ x ≤ 1), and the Si content of the second semiconductor region may be greater than the Si content of the first semiconductor region. The first semiconductor region may be Si 1-x Ge x pattern, wherein x is in the range of 0.5 to 1. The second semiconductor region is Si 1-x Ge x A pattern wherein x is in the range of 0 to less than 0.5.

[0016] The gate insulating layer may include a first gate insulating region overlapping the first semiconductor region and a second gate insulating region overlapping the second semiconductor region, and the first gate insulating region may include a dielectric material having a higher dielectric constant than the second gate insulating region. The first gate insulating region may include a high-k dielectric material having a higher dielectric constant than silicon oxide, and the second gate insulating region may include silicon oxide or a low-k dielectric material having a lower dielectric constant than silicon oxide.

[0017] Beneficial effects

[0018] As described above, according to one embodiment of the present invention, a tunneling field-effect transistor exhibiting high on-current characteristics while having a relatively simple manufacturing process can be provided.

[0019] However, the effects of the present invention are not limited to those mentioned above, and other effects that are not specifically described will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a cross-sectional view of a tunneling field-effect transistor according to an embodiment of the present invention.

[0021] Figure 2a and Figure 2b They are Figure 1 The energy band diagram of the semiconductor layer when the transistor is in the off state and the on state is shown in FIG.

[0022] Figure 3 is a perspective view showing a tunneling field effect transistor according to an embodiment of the present invention, and Figure 4 It is along Figure 1 A cross-sectional view taken along line II'.

[0023] Figure 5a and Figure 5b They are Figure 4 The energy band diagram of the semiconductor layer when the transistor is in the off state and the on state is shown in FIG.

[0024] Figure 6 is a cross-sectional view of a tunneling field-effect transistor according to an embodiment of the present invention.

[0025] Figure 7 is a cross-sectional view of a tunneling field-effect transistor according to an embodiment of the present invention.

[0026] Figures 8a to 8h The manufacturing reference is shown in sequence Figure 1 、 Figure 4 、 Figure 6 and Figure 7 A perspective view of a method for depositing a semiconductor layer according to an embodiment of the present invention is described. DETAILED DESCRIPTION

[0027] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings to provide a more specific understanding of the present invention. However, the present invention is not limited to the embodiments described herein and may be implemented in other forms. When a layer in a figure is referred to as being "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed between them. In these embodiments, "first," "second," or "third" is not intended to impose any limitations on components, but rather should be understood as terms used to distinguish components.

[0028] Figure 1 is a cross-sectional view of a tunneling field-effect transistor according to an embodiment of the present invention. Figure 2aand Figure 2b They are Figure 1 The energy band diagram of the semiconductor layer when the transistor is in the off state and the on state is shown in FIG.

[0029] refer to Figure 1 、 Figure 2a and Figure 2b , a substrate 100 may be provided. Substrate 100 may be a semiconductor substrate, a metal substrate, a glass substrate, or a flexible substrate. For example, the flexible substrate may be a polymer substrate, such as a polyethylene terephthalate (PET) or polyimide (PI) substrate. Devices for operating circuits, etc., may be formed on substrate 100. Furthermore, a protective layer 110, such as an insulating film covering the substrate or devices, may be formed. Protective layer 110 may be a silicon oxide film, a silicon nitride film, or a composite layer thereof.

[0030] The semiconductor layer 120 or the channel layer may be formed on the protective layer 110. The semiconductor layer 120 may include a first semiconductor region 121 and a second semiconductor region 123 having different band gaps. The first semiconductor region 121 and the second semiconductor region 123 may both be intrinsic semiconductor patterns.

[0031] The band gap of the first semiconductor region 121 may be smaller than the band gap of the second semiconductor region 123. In addition, the work function of the first semiconductor region 121 may be greater than the work function of the second semiconductor region 123. In this case, the conduction band potential energy of the second semiconductor region 123 may be higher than the conduction band potential energy of the first semiconductor region 121, which may result in a conduction band offset between the two regions.

[0032] The first semiconductor region 121 and the second semiconductor region 123 may be Si 1-x Ge x pattern (0 ≤ x ≤ 1), and the Si content of the second semiconductor region 123 may be greater than the Si content of the first semiconductor region 121. In addition, each of the first semiconductor region 121 and the second semiconductor region 123 may be a single crystal Si 1-x Ge x Pattern, polysilicon 1-x Ge x Patterned or amorphous Si 1-x Ge x pattern, and as an example, may be epitaxially grown single crystal Si 1-x Ge x pattern.

[0033] Specifically, the first semiconductor region 121 may be Si 1-x Ge xpattern, where x is 0.5 or greater; in other words, the Ge content may be greater than the Si content. In addition, x may range from 0.9 to 1. When x is 1, the first semiconductor region 121 may be a Ge pattern, specifically a single crystal Ge pattern, a polycrystalline Ge pattern, or an amorphous Ge pattern, and as an example, may be an epitaxially grown single crystal Ge pattern.

[0034] The second semiconductor region 123 may be Si 1-x Ge x Pattern, wherein x is less than 0.5; in other words, the Si content may be greater than the Ge content. In addition, x may range from 0 to 0.1. When x is 0, the second semiconductor region 123 may be a Si pattern, specifically a single crystal Si pattern, a polycrystalline Si pattern, or an amorphous Si pattern, and as an example, may be an epitaxially grown single crystal Si pattern.

[0035] The gate insulating film 130 may be provided on the semiconductor layer 120. The gate insulating film 130 may be a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or a composite film thereof.

[0036] The gate 140 may be formed on the gate insulating film 130, overlapping the semiconductor layer 120. The gate 140 may be a metal pattern selected from Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy including at least one of these metals.

[0037] An interlayer insulating film 150 may be formed on the gate 140. The interlayer insulating film 150 may be a silicon oxide film, a silicon nitride film, or a composite thereof. Contact holes may be formed in the interlayer insulating film 150 to expose at least two ends of the semiconductor layer 120, specifically, two side surfaces of the semiconductor layer 120 and adjacent portions thereof. The source electrode 161 and the drain electrode 163 may be formed in the contact holes, respectively. Thus, the source electrode 161 and the drain electrode 163 may be formed, each connected to at least two side surfaces of the semiconductor layer 120.

[0038] A contact hole may be formed in the interlayer insulating film 150 so that the distance between the gate 140 and the source 161 is smaller than the distance between the gate 140 and the drain 163. In this case, the on-current of the transistor may be increased, while the bipolar current may be reduced.

[0039] The source electrode 161 may be a metal electrode having a work function greater than that of the semiconductor layer 120 (particularly, the first semiconductor region 121) to which it is connected. When the first semiconductor region 121 is a Ge pattern, the source electrode 161 may include a metal having a work function greater than that of Ge, such as nickel (Ni), iridium (Ir), palladium (Pd), or platinum (Pt), each of which has a work function of 5 eV or greater. Due to the difference in work function between the first semiconductor region 121 and the source electrode 161, electrons in the first semiconductor region 121 adjacent to the source electrode 161 may migrate toward the source electrode 161. Consequently, a charge plasma of the first conductivity type (i.e., hole plasma) may form in the first semiconductor region 121 adjacent to the source electrode 161, thereby inducing a source region 121S of the first conductivity type (i.e., p-type). The area of the first semiconductor region 121 excluding the p-type source region 121S may be defined as a first channel region 121C. The first channel region 121C may overlap with the gate 140.

[0040] The drain electrode 163 may be a metal electrode having a work function lower than that of the semiconductor layer 120 (particularly, the second semiconductor region 123) to which it is connected. When the second semiconductor region 123 is a Si pattern, the drain electrode 163 may include a metal having a work function lower than that of Si, such as hafnium (Hf), indium (In), zirconium (Zr), or thallium (Tl), each of which has a work function of 4.2 eV or less. Due to the difference in work function between the second semiconductor region 123 and the drain electrode 163, electrons can move from the drain electrode 163 to the second semiconductor region 123. Consequently, a charge plasma of the second conductivity type (i.e., electron plasma) may form in the second semiconductor region 123 adjacent to the drain electrode 163, thereby inducing a drain region 123D of the second conductivity type (i.e., n-type). The area of the second semiconductor region 123 excluding the n-type drain region 123D may be defined as a second channel region 123C. The second channel region 123C may overlap with the gate 140.

[0041] As described above, the p-type source region 121S and the n-type drain region 123D can be induced to become conductive regions by forming a charged plasma, without the need for impurity doping (such as ion implantation). Although the source region 121S has been described as p-type and the drain region 123D as n-type, the present invention is not limited to this. By forming the source 161 and drain 163 using materials with appropriate work functions, the source region 121S can alternatively be formed as an n-type region, while the drain region 123D can be formed as a p-type region. Thus, the source region 121S can be defined as a region having a first conductivity type, while the drain region 123D can be defined as a region having a second conductivity type opposite to the first conductivity type.

[0042] Therefore, the source and drain regions are induced to be conductive regions by charge plasma formation caused by the work function difference between the electrodes 161 and 163 and the semiconductor regions 121 and 123, rather than impurity doping such as ion implantation, which can simplify the manufacturing process and suppress defect generation compared to conventional impurity doping technology.

[0043] exist Figure 1 In the embodiment of the present invention, gate electrode 140 is shown as being located above and overlapping semiconductor layer 120; however, the present invention is not limited thereto. Gate electrode 140 may alternatively be located below semiconductor layer 120 while still overlapping therewith. Furthermore, although source electrode 161 and drain electrode 163 are shown as being located above semiconductor layer 120, they may alternatively be located below semiconductor layer 120.

[0044] As described above, since the band gap of the first semiconductor region 121 is smaller than that of the second semiconductor region 123, when the transistor is in the on state, band-to-band tunneling (BTBT) from the valence band of the source region 121S to the conduction band of the first channel region 121C is more likely to occur. Consequently, the on-state current can be increased. On the other hand, since the band gap of the second semiconductor region 123 is relatively large, when the transistor is in the bipolar state, BTBT from the valence band of the second channel region 123C to the conduction band of the drain region 123D can be suppressed.

[0045] However, when the band gap of the first semiconductor region 121 is smaller than the band gap of the second semiconductor region 123, the work function of the first semiconductor region 121 may be greater than the work function of the second semiconductor region 123. In this case, as described above, the conduction band potential energy of the second channel region 123C is higher than the conduction band potential energy of the first channel region 121C, resulting in a conduction band offset between the two regions. This conduction band offset can serve as a diffusion barrier for the on-state current, thereby reducing the on-state current. This problem can be solved by other embodiments described later.

[0046] Figure 3 is a perspective view showing a tunneling field effect transistor according to an embodiment of the present invention, and Figure 4 It is along Figure 1 A cross-sectional view taken along line II'. Figure 5a and Figure 5b They are Figure 4 The energy band diagram of the semiconductor layer when the transistor is in the off state and the on state is shown in FIG. Figure 1 , Figure 2 and Figure 3 The described embodiments are essentially the same.

[0047] Reference Figure 3 、 Figure 4 、 Figure 5a and Figure 5b The gate 140 may include: a first gate region 141 overlapping with the first semiconductor region 121 (specifically, the first channel region 121C); and a second gate region 143 overlapping with the second semiconductor region 123 (specifically, the second channel region 123C). Specifically, the interface between the first semiconductor region 121 and the second semiconductor region 123 may be aligned with the interface between the first gate region 141 and the second gate region 143. In one embodiment, the interface between the first semiconductor region 121 and the second semiconductor region 123 and the interface between the first gate region 141 and the second gate region 143 may lie in the same plane.

[0048] Each metal pattern of the first gate region 141 and the second gate region 143 may be selected from Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy containing at least one of these metals, and may be selected to meet specific conditions as described below.

[0049] The work function of the metal pattern of the first gate region 141 may be greater than the work function of the metal pattern of the second gate region 143. In this case, due to the charge plasma formed in the first channel region 121C and the second channel region 123C by the first gate region 141 and the second gate region 143, respectively, the conduction band potential energy of the first channel region 121C may be equal to or higher than the conduction band potential energy of the second channel region 123C. Therefore, the conduction band offset ( Figure 3 offset in b).

[0050] As an example, the work function of the metal pattern of the first gate region 141 may be approximately 0.2 eV to 0.4 eV, specifically approximately 0.35 eV to 0.5 eV, or more specifically approximately 0.15 eV to 0.5 eV, less than the work function of the first semiconductor region 121. For example, when the first semiconductor region 121 is a Ge pattern having a work function of approximately 4.75 eV, the first gate region 141 may be a metal pattern having a work function of approximately 4.4 eV to 4.7 eV, such as a W pattern (work function: approximately 4.63 eV) or a Ru pattern (work function: approximately 4.7 eV).

[0051] The work function of the metal pattern in the second gate region 143 may be 0.2 to 0.6 eV, specifically about 0.23 eV to 0.55 eV, and more specifically 0.5 to 0.54 eV, smaller than the work function of the second semiconductor region 123. For example, if the second semiconductor region 123 is a Si pattern having a work function of about 4.63 eV, the second gate region 143 may be a metal pattern having a work function of about 4.1 eV to 4.4 eV, specifically an Al (work function: about 4.1 eV) pattern.

[0052] As described above, if the metal pattern of the first gate region 141 has a larger work function than the metal pattern of the second gate region 143, the conduction band offset generated between the first semiconductor region 121 and the second semiconductor region 123 can be alleviated or eliminated. Figure 3 b). Therefore, with reference Figure 1 Compared to the described embodiment, the on-state current can be increased.

[0053] Figure 6 is a cross-sectional view showing a tunneling field effect transistor according to an embodiment of the present invention. Figure 4 The embodiments described are essentially the same.

[0054] refer to Figure 6 , the thickness of the first semiconductor region 121 can be smaller than that of the second semiconductor region 123. In this case, not only can high-density charge plasma be generated in the first semiconductor region 121 (specifically, in the source region 121S) by the source electrode 161, but also the gate controllability of the first gate region 141 above the first channel region 121C (below the first gate region 141) can be enhanced. Figure 4 Compared to the described embodiment, the on-state current can be increased.

[0055] Figure 7 is a cross-sectional view showing a tunneling field effect transistor according to an embodiment of the present invention. Figure 1 The embodiments described are essentially the same.

[0056] refer to Figure 7, the gate dielectric layer 130 may include a first gate dielectric region 131 overlapping the first semiconductor region 121 and a second gate dielectric region 133 overlapping the second semiconductor region 123. Specifically, the interface where the first gate dielectric region 131 and the second gate dielectric region 133 contact each other may be aligned with respect to the interface where the first semiconductor region 121 and the second semiconductor region 123 contact each other. In one embodiment, the interface where the first semiconductor region 121 and the second semiconductor region 123 contact each other and the interface where the first gate dielectric region 131 and the second gate dielectric region 133 contact each other may be located in the same plane.

[0057] The first gate dielectric region 131 may be formed of a dielectric film having a higher dielectric constant than the second gate dielectric region 133. For example, the first gate dielectric region 131 may be a high-k dielectric film (i.e., a dielectric film having a higher dielectric constant than a silicon oxide film), such as Al2O3 or HfO2. The second gate dielectric region 133 may be a silicon oxide film or a dielectric film having a lower dielectric constant than a silicon oxide film, such as nanoporous silicon dioxide, fluorinated silicate, or an organic film (e.g., a polyimide or polymer film). In this case, when a voltage is applied to the gate 140 and the transistor is turned on, the conduction band potential energy of the second channel region 123C may be reduced more than the conduction band potential energy of the first channel region 121C. This may reduce or eliminate the conduction band offset ( Figure 3 b). Therefore, with reference Figure 4 Compared to the described embodiment, the on-state current can be increased.

[0058] Figures 8a to 8h The manufacturing reference is shown in sequence Figure 1 、 Figure 4 、 Figure 6 and Figure 7 A perspective view of a method for forming a semiconductor layer according to an embodiment of the present invention. Figure 1 The embodiments described are essentially the same.

[0059] Reference Figure 8a , a protective layer 110 may be provided on the substrate 100. On the protective layer 110, a primary semiconductor layer 127 may be formed. For example, the primary semiconductor layer 127 may be Si 1-x Ge x layer, which has Figure 1 Or the same composition as the second semiconductor region 123 described below. Specifically, the primary semiconductor layer 127 is Si 1-x Ge xLayer, where x is less than 0.5, means that the silicon content can be greater than the germanium content. In addition, x can range from 0 to 0.1. If x is 0, the primary semiconductor layer 127 is a Si layer, and this configuration can correspond to a silicon-on-insulator SOI substrate.

[0060] refer to Figure 8b , a mask layer 129 may be provided on the primary semiconductor layer 127. The mask layer 129 may be a silicon nitride film.

[0061] refer to Figure 8c , an opening 129 a exposing the preliminary semiconductor layer 127 may be formed in the mask layer 129 .

[0062] refer to Figure 8d , germanium Ge can be deposited on the primary semiconductor layer 127 in the opening 129a. Then, the primary semiconductor layer 127 exposed in the opening 129a can be converted into the primary first semiconductor region 121P using a Ge condensation method by heat treatment. The Ge condensation method is a technique in which a Si layer is deposited at 0 ≤ x < 0.5. 1-x Ge x Ge is deposited on the layer and heat treated, and Ge diffuses into the Si 1-x Ge x (0 ≤ x < 0.5) layer, a new Si is formed 1-x Ge x layer, where 0.5 ≤ x ≤ 1. By adjusting the Ge deposition thickness, heat treatment temperature and heat treatment time, the Si 1-x Ge x (0.5 ≤ x ≤ 1) Ge concentration and thickness of the layer. Therefore, the preliminary first semiconductor region 121P will be Si 1-x Ge x A layer, wherein x is 0.5 or greater, means that the Ge content may be higher than the Si content. In addition, x may be 0.9 or greater, up to 1. If x is 1, the preliminary first semiconductor region 121P may be a Ge layer.

[0063] refer to Figure 8e , the mask layer 129 may be removed to expose the primary semiconductor layer 127. In the figure, the thickness of the primary first semiconductor region 121P is shown to be smaller than the thickness of the primary semiconductor layer 127. This may correspond to the reference Figure 6 However, it is not limited thereto; by adjusting various parameters in the Ge condensation method, the thicknesses of the preliminary first semiconductor region 121P and the preliminary semiconductor layer 127 may also be the same.

[0064] refer to Figure 8f, a photoresist pattern PR may be formed on the preliminary first semiconductor region 121P and the preliminary semiconductor layer 127 .

[0065] Reference Figure 8g , using the photoresist pattern PR as a mask, the preliminary first semiconductor region 121P and the preliminary semiconductor layer 127 may be patterned to form a semiconductor layer 120 (eg Figure 1 、 Figure 4 、 Figure 6 and Figure 7 As shown), the semiconductor layer 120 is composed of a first semiconductor region 121 and a second semiconductor region 123.

[0066] refer to Figure 8h , the photoresist pattern PR may be removed. Subsequently (although not shown), the semiconductor layer 120 (eg Figure 1 、 Figure 4 、 Figure 6 and Figure 7 ) are sequentially formed on the gate dielectric layer 130 (as shown Figure 1 、 Figure 4 、 Figure 6 and Figure 7 As shown), gate 140 (as Figure 1 、 Figure 4 、 Figure 6 and Figure 7 As shown), the interlayer dielectric layer 150 (as shown Figure 1 、 Figure 4 、 Figure 6 and Figure 7 As shown), source 161 (as Figure 1 、 Figure 4 、 Figure 6 and Figure 7 As shown) and drain 163 (as Figure 1 、 Figure 4 、 6 and Figure 7 In this case, any components not specifically described may be formed using conventional semiconductor processes.

[0067] Although the present invention has been described in detail with reference to the preferred embodiments, the present invention is not limited to these embodiments. Those skilled in the art can make various modifications and changes within the technical spirit and scope of the present invention.

Claims

1. A tunneling field-effect transistor, comprising: a semiconductor layer disposed on a substrate; a gate electrode, which is disposed above or below the semiconductor layer and overlaps with the semiconductor layer; and A source electrode and a drain electrode are connected to at least two sides of the semiconductor layer, respectively. The semiconductor layer includes a first semiconductor region connected to the source and a second semiconductor region connected to the drain, and the band gap of the first semiconductor region is smaller than the band gap of the second semiconductor region. The first semiconductor region includes a source region of a first conductivity type and a first channel region excluding the source region, the source region of the first conductivity type being induced by a charge plasma of the first conductivity type in a region adjacent to the source. Furthermore, the second semiconductor region includes a drain region of the second conductivity type and a second channel region excluding the drain region, the drain region of the second conductivity type being induced by charge plasma of the second conductivity type in a region adjacent to the drain.

2. The tunneling field effect transistor according to claim 1, wherein A work function of the first semiconductor region is greater than a work function of the second semiconductor region.

3. The tunneling field effect transistor according to claim 1 or 2, wherein: The first semiconductor region and the second semiconductor region are Si 1-x Ge x pattern (0 ≤ x ≤ 1), and the Si content of the second semiconductor region is greater than the Si content of the first semiconductor region.

4. The tunneling field effect transistor according to claim 3, wherein: The first semiconductor region is Si 1-x Ge x pattern, where x is in the range of 0.5 to 1.

5. The tunneling field effect transistor according to claim 3, wherein The second semiconductor region is Si 1-x Ge x A pattern wherein x is in the range of 0 to less than 0.

5.

6. The tunneling field effect transistor according to claim 2, wherein: The gate includes a first gate region overlapping the first semiconductor region and a second gate region overlapping the second semiconductor region, Furthermore, a work function of the metal pattern in the first gate region is greater than a work function of the metal pattern in the second gate region.

7. The tunneling field effect transistor according to claim 6, wherein: The metal pattern of the first gate region has a work function in the range of 4.4 to 4.7 eV, and The metal pattern of the second gate region has a work function in the range of 4.1 to 4.4 eV.

8. The tunneling field effect transistor according to claim 2, wherein: The gate insulating layer includes a first gate insulating region overlapping the first semiconductor region and a second gate insulating region overlapping the second semiconductor region, and The first gate insulating region includes a dielectric material having a higher dielectric constant than the second gate insulating region.

9. The tunneling field effect transistor according to claim 8, wherein: The first gate insulating region comprises a high-k dielectric material having a higher dielectric constant than silicon oxide, Furthermore, the second gate insulating region includes silicon oxide or a low-k dielectric material having a lower dielectric constant than silicon oxide.

10. The tunneling field effect transistor according to claim 1, wherein The thickness of the first semiconductor region is smaller than that of the second semiconductor region.

11. A tunneling field-effect transistor, comprising: a semiconductor layer disposed on a substrate and comprising a first semiconductor region and a second semiconductor region, wherein a band gap of the first semiconductor region is smaller than a band gap of the second semiconductor region, and a work function of the first semiconductor region is larger than a work function of the second semiconductor region; a gate electrode, which is disposed above or below the semiconductor layer and overlaps with the semiconductor layer; a source electrode and a drain electrode, connected to the first semiconductor region and the second semiconductor region, respectively; The first semiconductor region includes a first conductive type source region adjacent to the source and a first channel region overlapping the gate, and the second semiconductor region includes a second conductive type drain region adjacent to the drain and a second channel region overlapping the gate, and Wherein, in the on state, the conduction band potential energy of the first channel region is equal to or higher than the conduction band potential energy of the second channel region.

12. The tunneling field effect transistor according to claim 11, wherein: The gate includes a first gate region overlapping the first semiconductor region and a second gate region overlapping the second semiconductor region, Furthermore, a work function of the metal pattern in the first gate region is greater than a work function of the metal pattern in the second gate region.

13. The tunneling field effect transistor according to claim 11 or 12, wherein: The first semiconductor region and the second semiconductor region are Si 1-x Ge x pattern (0 ≤ x ≤ 1), and the Si content of the second semiconductor region is greater than the Si content of the first semiconductor region.

14. The tunneling field effect transistor according to claim 13, wherein: The first semiconductor region is Si 1-x Ge x pattern, where x is in the range of 0.5 to 1.

15. The tunneling field effect transistor according to claim 13, wherein: The second semiconductor region is Si 1-x Ge x A pattern wherein x is in the range of 0 to less than 0.

5.

16. The tunneling field effect transistor according to claim 11, wherein The gate insulating layer includes a first gate insulating region overlapping the first semiconductor region and a second gate insulating region overlapping the second semiconductor region, and The first gate insulating region includes a dielectric material having a higher dielectric constant than the second gate insulating region.

17. The tunneling field effect transistor according to claim 16, wherein: The first gate insulating region comprises a high-k dielectric material having a higher dielectric constant than silicon oxide, and The second gate insulating region includes silicon oxide or a low-k dielectric material having a lower dielectric constant than silicon oxide.

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