Cache data management method and device and storage controller

Abstract

The invention relates to the technical field of memories, and discloses a cache data management method and device and a memory controller. The method comprises the following steps: when a target command of a host is detected, obtaining an access address corresponding to the target command; determining a target address conflicting with the access address in the cache unit; and when the target command is a write command, updating cache data corresponding to the target address in the cache unit into first data corresponding to the target address in the write command, and writing second data in the write command into the cache unit. When the target address with the conflict is detected, the cache data in the cache unit is updated, so that the data of the subsequent write command can be ensured to correctly fall into the memory, the data cached in sequence is prevented from being disordered in a data falling sequence, and the writing reliability of the data is improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a cache data management method, device, and storage controller. Background Art

[0002] Storage array systems utilize a write-terminate mechanism to improve command response speed. After data arrives at the storage array controller and undergoes integrity verification, the command execution result is submitted to the host. At this point, the data is only stored in the storage array controller's cache; the data is not yet flushed to disk within the storage array. Furthermore, to improve I / O efficiency and prevent hot data from being continuously read from disk, the array controller's cache is effectively a cache. Therefore, the host may attempt to read or write data that has not yet been flushed to disk.

[0003] For multiple write commands to the same data block, if the storage array cannot ensure that the cached data of the old command is refreshed with the latest command data before the data is written to the disk, it will cause the data of the successive write commands to be written to the disk multiple times, and even the timing sequence of the writes to the disk may be disordered, and the old data will not be refreshed by the new data, which will eventually reduce the reliability of data writing. Summary of the Invention

[0004] In view of this, the purpose of this application is to overcome the deficiencies in the prior art and provide a cache data management method, the method being applied to a storage controller in a storage system, the storage controller including a cache unit, the storage system also including a host and a storage array, the method comprising:

[0005] When a target command of the host is detected, obtaining an access address corresponding to the target command;

[0006] Searching the cache unit for a target address that conflicts with the access address;

[0007] When the target command is a write command, the cache data corresponding to the target address in the cache unit is updated to the first data corresponding to the target address in the write command, and the second data in the write command is written into the cache unit.

[0008] In one embodiment, the cache unit includes an index storage module, and the step of searching the cache unit for a target address that conflicts with the access address includes:

[0009] Determining a target index group according to an index namespace range of each index group in the index storage module and an access namespace corresponding to the access address;

[0010] An index address that overlaps with the access address is searched in the target index group, and is determined to be a target address that conflicts with the access address.

[0011] In one embodiment, updating the cache data corresponding to the target address in the cache unit to the first data corresponding to the target address in the write command, and writing the second data in the write command into the cache unit includes:

[0012] Determining a first cache sub-unit in the cache unit where cache data corresponding to the target address is stored;

[0013] storing first data corresponding to the target address in the write command into the first cache sub-unit;

[0014] A second cache sub-unit is determined according to the storage information of the cache unit, and the second data in the write command is stored in the second cache sub-unit.

[0015] In one embodiment, after the step of determining a target address in the cache unit that conflicts with the access address, the method further includes:

[0016] When the target command is a read command, third data corresponding to the target address in the cache unit and fourth data corresponding to the read command in the storage array are read and sent to the host.

[0017] In one embodiment, the step of reading the third data corresponding to the target address in the cache unit and the fourth data corresponding to the read command in the storage array includes:

[0018] Determine a third cache sub-unit corresponding to the target address in the cache unit, and read third data corresponding to the read command from the third cache sub-unit;

[0019] The fourth data corresponding to the read command is read from the storage array according to an access address of the fourth data corresponding to the read command.

[0020] In one embodiment, after storing the data in the cache unit, the method further includes:

[0021] A corresponding index is generated according to the access namespace, access address, cache subunit number and data length corresponding to the data stored in the cache unit.

[0022] In one embodiment, after the step of generating a corresponding index based on the access namespace, access address, cache subunit number, and data length corresponding to the data stored in the cache unit, the following steps are included:

[0023] sorting the indexes in the index group corresponding to the current cache sub-unit group based on the access namespace and access address corresponding to the indexes;

[0024] The sorted index group is stored in the index storage module in the cache unit.

[0025] In one embodiment, the method further comprises:

[0026] The data in the cache unit is written into the storage array according to the access namespace and the access address in the corresponding index.

[0027] The present application also provides a cache management device, the cache management device comprising:

[0028] an acquisition module, configured to acquire an access address corresponding to a target command when a target command of the host is detected;

[0029] A search module, configured to search the cache unit for a target address that conflicts with the access address;

[0030] An update module is used to update the cache data corresponding to the target address in the cache unit to the first data corresponding to the target address in the write command when the target command is a write command, and write the second data in the write command into the cache unit.

[0031] The present application also provides a storage controller, including a storage interface control module, a cache unit, a cache management device and a non-volatile storage control module; the cache management device is respectively connected to the storage interface control module, the non-volatile storage control module and the cache unit; the cache management device is used to execute the steps of the cache data management method.

[0032] The embodiments of the present application have the following beneficial effects:

[0033] When a target command from the host is detected, an access address corresponding to the target command is obtained; a target address in a cache unit that conflicts with the access address is determined; and when the target command is a write command, the cached data corresponding to the target address in the cache unit is updated to the first data corresponding to the target address in the write command, and the second data in the write command is written to the cache unit. By updating the cached data corresponding to the target address in the cache unit to the first data corresponding to the target address in the write command when a conflicting target address is detected, it is possible to ensure that the data of the subsequent write command can be written to the memory after the data is completed, avoiding the order of data of the successive write commands being written to the disk, and improving the reliability of data writing. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly illustrate the technical solution of this application, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of this application and should not be considered as limiting the scope of protection of this application. Those skilled in the art can also derive other relevant drawings based on these drawings without inventive effort.

[0035] Figure 1 This is a flow chart of the first embodiment provided by this application;

[0036] Figure 2 This is a flow chart of the second embodiment provided by this application;

[0037] Figure 3 This is a schematic diagram of the connection relationship between the host, storage controller and storage array provided by this application;

[0038] Figure 4 This is a schematic diagram of the internal structure of the cache unit provided by this application;

[0039] Figure 5 This is the cache subunit status representation provided by this application;

[0040] Figure 6 This is a flow chart of the third embodiment provided by this application;

[0041] Figure 7 This is a flowchart of the fourth embodiment provided by this application;

[0042] Figure 8 This is a flowchart of the fifth embodiment provided by this application;

[0043] Figure 9 This is a flow chart of the sixth embodiment provided by this application;

[0044] Figure 10 It is a structural diagram of the cache management device provided in this application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0046] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0047] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0048] Furthermore, the terms “first,” “second,” “third,” etc., are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0050] It is understandable that the method of the present application is applied to a storage controller in a storage system, the storage controller includes a cache unit, and the storage system also includes a host and a storage array.

[0051] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0052] Please refer to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the present application, the method includes:

[0053] Step S101: When a target command from a host is detected, an access address corresponding to the target command is obtained.

[0054] In this embodiment, when the storage controller detects a target command from the host, it obtains the access address of the target command. It should be noted that the target command may include a write command and a read command. The write command is when the host needs to write data to the storage array, and the read command is when the host needs to read the corresponding data from the storage array. Each target command will carry a corresponding access address, thereby clarifying which addresses of the storage array the target command acts on.

[0055] Step S102: searching the cache unit for a target address that conflicts with the access address.

[0056] In this embodiment, after obtaining the access address corresponding to the target command, the storage controller searches its cache units for a target address that conflicts with the access address. A conflict occurs when the access address of the target command overlaps or is identical to the address at which the data stored in the cache unit is to be stored in the storage array. It should be noted that, to improve write efficiency, a write termination mechanism is employed. After receiving a write command from the host and storing the data in the storage controller's cache units, the storage controller submits the command execution result to notify the host that the write command has been completed. When the data is stored in the cache units, an index is generated. The index includes the first address of the storage address range where the data is to be stored in the storage array and the data length. The storage controller then stores the data in the storage array based on the index. When the host sends a new command, the storage controller determines the storage address range corresponding to the index based on the first address and data length in each index in the cache units. The storage controller then compares the access address corresponding to the new command with the storage address range corresponding to each index. If the access address overlaps with the storage address range, the target address in the cache unit that conflicts with the access address is determined.

[0057] For example, the starting address in an index is LBA511, and the data length is 128, that is, the storage address range corresponding to the data stored therein is LBA511-LBA638; if the access address corresponding to the new command is LBA511-LBA600, then the access address corresponding to the new command overlaps with the storage address range given to the index, the overlapping part LBA511-LBA600, then the starting address LBA511 in the index is the target address. As another example, the starting address in one index is LBA511, and the data length is 128, that is, the storage address range corresponding to the data stored therein is LBA511-LBA638; the starting address in another index is LBA639, and the data length is 128, that is, the storage address range corresponding to the data stored therein is LBA639-LBA766; if the access address corresponding to the new command is LBA511-LBA700, then the access address corresponding to the new command overlaps with the storage address range given to the index, the overlapping part LBA511-LBA700, then the starting address LBA511 and the starting address LBA639 in the index are the target addresses.

[0058] Step S103 , when the target command is a write command, the cache data corresponding to the target address in the cache unit is updated to the first data corresponding to the target address in the write command, and the second data in the write command is written into the cache unit.

[0059] In this embodiment, after determining the target address, when the target command is a write command, the storage controller updates the cache data corresponding to the target address in the cache unit to the first data corresponding to the target address in the write command, and writes the remaining second data in the write command into the cache unit. It should be noted that the cache unit is divided into multiple sub-cache areas, each sub-cache area corresponds to multiple cache sub-units, and each cache sub-unit is numbered; when data is stored in a cache unit, an index is formed. In addition to the first address of the storage address range of the storage array in which the data is stored and the data length, the index also includes the number of the cache sub-unit storing the data; at this time, after determining the target address, the storage controller can determine the number of the cache sub-unit based on the target address and the index, and replace the data originally stored in the cache sub-unit with the first data corresponding to the target address in the write command.

[0060] For example, the first address in an index is LBA511, the data length is 128, and the cache sub-unit is numbered cell0, that is, the storage address range corresponding to the data stored therein is LBA511-LBA638; if the access address corresponding to the new command is LBA511-LBA600, then the access address corresponding to the new command overlaps with the storage address range of the index, the overlapping part LBA511-LBA600, then the first address LBA511 in the index is the target address; at this time, the storage controller replaces the data stored in cell0 with the data corresponding to the new command. As another example, the starting address in one index is LBA511, the data length is 128, and the cache sub-unit is numbered cell0, that is, the storage address range corresponding to the data stored therein is LBA511-LBA638; the starting address in another index is LBA639, the data length is 128, and the cache sub-unit is numbered cell1, that is, the storage address range corresponding to the data stored therein is LBA639-LBA766; if the access address corresponding to the new command is LBA511-LBA700, then the access address corresponding to the new command overlaps with the storage address range given to the index, the overlapping part is LBA511-LBA700, then the starting address LBA511 and the starting address LBA639 in the index are the target addresses; at this time, the storage controller replaces the data stored in cell0 with data corresponding to the new command in the storage address range of LBA511-LBA638, and replaces the data stored in cell1 with data corresponding to the new command in the storage address range of LBA639-LBA700.

[0061] In this embodiment, upon detecting a target command from a host, the storage controller obtains an access address corresponding to the target command; determines a target address in a cache unit that conflicts with the access address; and, if the target command is a write command, updates the cached data corresponding to the target address in the cache unit to the first data corresponding to the target address in the write command, and writes the second data in the write command to the cache unit. By updating the cached data corresponding to the target address in the cache unit to the first data corresponding to the target address in the write command upon detecting a conflicting target address, it ensures that the data of a subsequent write command can be written to the memory after the data is completed, preventing the order in which the data of successive write commands is written to the disk and improving the reliability of data writing.

[0062] Please refer to Figure 2 , Figure 2 This is a flow chart of the second embodiment of the present application. The difference between the second embodiment and the first embodiment is that the cache unit includes an index storage module, and the step of searching the cache unit for a target address that conflicts with the access address includes:

[0063] Step S201 : determining a target index group according to the index namespace range of each index group in the index storage module and the access namespace corresponding to the access address.

[0064] In this embodiment, the storage controller first determines the access namespace corresponding to the access address of the target command, and then compares the index namespace range of each index group in the index storage module with the access namespace corresponding to the access address to determine the target index group.

[0065] It is understandable that the index storage module stores indexes according to each sub-cache area of ​​the cache unit, and the indexes corresponding to each cache sub-unit in a sub-cache area form an index group. When each cache sub-unit in the sub-cache area is written, the storage controller sorts the indexes corresponding to the cache sub-unit in the index group according to the namespace and address in each index. After the data fills a sub-cache area in the cache unit, the sorted index group is stored in the index storage module. When the storage controller detects a new command, it compares the access namespace corresponding to the new command with the index namespace range corresponding to each index group in the index storage module. In this way, the target index group containing the access namespace can be filtered out from all index groups in the index storage module.

[0066] For example, the index namespace range of an index group in the index storage module is NameSpace1 to NameSpace3, and the access namespace corresponding to the new command is NameSpace1. At this time, it can be determined that this index group in the index storage module is the target index group.

[0067] Step S202 : searching the target index group for an index address that overlaps with the access address, and determining the target address that conflicts with the access address.

[0068] In this embodiment, after determining the target index group, the storage controller searches for an index address that overlaps with the access address in the target index group and determines it as the target address that conflicts with the access address. Optionally, to improve the efficiency of the search, the storage controller performs a binary search on the indexes in the target index group to determine the target address; for example, if the target index group has a total of 512 sorted indexes, the binary search conflict requires a maximum of 10 times, that is, (0) 512 -> (1) 256 -> (2) 128 -> (3) 64 -> (4) 32 -> (5) 16 -> (6) 8 -> (7) 4 -> (8) 2 -> (9) 1 -> (10) to complete.

[0069] It should be noted that in the specific implementation process, Figure 3As shown, the host is connected to the storage controller, the storage controller includes a cache unit, the storage array is connected to the storage controller, and the storage array is divided into multiple namespaces (NameSpace0-NameSpaceN, each namespace corresponds to multiple storage addresses). Figure 4 As shown, the cache unit is divided into multiple sub-cache areas (area 0-area n) and allocated and managed as cache sub-units (cell 0-cellk). When the storage controller receives a write command, it writes the data carried by the write command to the cache sub-unit in the cache unit and generates an index corresponding to the cache sub-unit. When the storage controller receives a read command, it reads the data to be read from the storage array to the cache sub-unit in the cache unit and generates an index corresponding to the cache sub-unit. The format of the index is:

[0070] NS_id+NS_sLBA+cell_id+block_num, where NS_id is the namespace (NameSpace) of the storage array accessed by the command, NS_sLBA is the starting address of the data stored in the cache subunit in the namespace of the storage array, cell_id is the number of the cache subunit, and block_num is the data length of the data stored in the cache subunit (one cache subunit can store data of 128 blocks in length). Based on the above, for example: the storage controller receives a write command, and the access address of the write command is storage addresses 511 to 959 (LBA511-LBA959) in namespace 1 (NameSpace 1) in the storage array. The storage controller stores the carried write data in cache subunit 0 to cache subunit 3 (cell0-cell 3) in the cache unit, thereby generating four corresponding indexes: NameSpace 1+LBA511+cell 0+128, NameSpace 1+LBA639+cell 1+128, and NameSpace 1+LBA767+cell 2+128, NameSpace 1+LBA895+cell 3+64.

[0071] After generating the index, the storage controller sorts the indexes corresponding to the cache sub-units in the same sub-cache area in the cache unit. After the data fills a sub-cache area in the cache unit, the index group is obtained and stored in the index storage module.

[0072] In addition, if Figure 5As shown, the storage controller also establishes a cache sub-unit status table to record the valid status of each cache sub-unit; when the status of the current cell is recorded as valid, the data stored in the current cell is valid data, that is, the current cell cannot be used to store new data; if the status of the current cell is recorded as invalid, the data in the current cell is invalid data, and the current cell can be released to store new data, that is, when a new command needs to store data in the cache unit, it can only be stored in the cache sub-unit in the invalid state. After the data is stored, the cache sub-unit is updated to the valid state.

[0073] In this embodiment, the storage controller first searches for the target index group based on the namespace, and then searches for the conflicting index address in the target index group based on the access address. This can quickly find the conflicting index address and improve search efficiency.

[0074] Please refer to Figure 6 , Figure 6 This is a flow chart of the third embodiment of the present application. The difference between the third embodiment and the first to second embodiments is that the cache data corresponding to the target address in the cache unit is updated to the first data corresponding to the target address in the write command, and the second data in the write command is written into the cache unit, including:

[0075] Step S301 : determining a first cache sub-unit in a cache unit where cache data corresponding to a target address is stored.

[0076] In this embodiment, after determining the target address, the storage controller can determine the first cache subunit where the cache data corresponding to the target address is stored based on the index corresponding to the target address. For example, an index is NameSpace1+LBA511+cell 0+128, and the access address corresponding to the new write command is LBA511-LBA600. The access address corresponding to the write command overlaps with the storage address range of the index, the overlapping portion being LBA511-LBA600. Therefore, the first address LBA511 in the index is the target address. At this point, based on the target address and the index, the first cache subunit can be determined to be cell 0.

[0077] Step S302: Store the first data corresponding to the target address in the write command into the first cache sub-unit.

[0078] In this embodiment, the storage controller stores the first data corresponding to the target address in the write command in the first cache subunit. For example, an index is NameSpace 1+LBA511+cell 0+128, and the access address corresponding to the new write command is LBA511-LBA600. The access address corresponding to the write command overlaps with the storage address range of the index, the overlapping portion being LBA511-LBA600. Therefore, the first address LBA511 in the index is the target address. Based on the target address and the index, the first cache subunit is determined to be cell 0, and the first data in the write command to be stored in LBA511-LBA600 is stored in the first cache subunit, cell 0. As another example, one index is NameSpace 1+LBA511+cell 0+128, and the other index is NameSpace 1+LBA639+cell 1+128. The access address corresponding to the new write command is LBA511-LBA700. The access address corresponding to the new write command overlaps with the storage address range of the index, the overlapping part is LBA511-LBA700, then the first address LBA511 and the first address LBA639 in the index are the target addresses; at this time, the first data in the write command that needs to be stored in LBA511-LBA600 is stored in the first cache sub-unit cell 0, and the first data in the write command that needs to be stored in LBA639-LBA700 is stored in the first cache sub-unit cell 1.

[0079] Step S303: Determine a second cache sub-unit according to the storage information of the cache unit, and store the second data in the write command in the second cache sub-unit.

[0080] In this embodiment, for the second data in the write command whose access address does not conflict, the storage control unit determines a second cache sub-unit based on the storage information of the cache unit and stores the second data in the write command in the second cache sub-unit. For example, the access address corresponding to the write command is LBA511-LBA959. At this time, there are only two indexes in the cache unit, one index is NameSpace 1+LBA511+cell 0+128, and the other index is NameSpace 1+LBA639+cell 1+128. In this case, the storage control unit can determine that the data at the access address LBA511-LBA766 in the write command is the first data, and the data at the access address LBA767-LBA959 is the second data. Cell 0 and cell 1 of the cache unit store the first data. Then, based on the storage information of the cache unit, the storage control unit determines that the second cache sub-units are cell 2 and cell 3. In accordance with the order, the second data at the access address LBA767-LBA894 is stored in cell 2, and the second data at the access address LBA895-LBA959 is stored in cell 3.

[0081] The storage controller in this embodiment, when detecting a conflicting target address, updates the cache data corresponding to the target address in the cache unit to the first data corresponding to the target address in the write command, and writes the second data in the write command that does not conflict to other cache sub-units. This ensures that the data of subsequent write commands can be correctly written to the disk, avoids confusion in the order of completing data writing of successive write commands, and improves the reliability of data writing.

[0082] Please refer to Figure 7 , Figure 7 This is a flow chart of the fourth embodiment of the present application. The fourth embodiment differs from the first to third embodiments in that, after the step of determining the target address in the cache unit that conflicts with the access address, the fourth embodiment further includes:

[0083] Step S401 , when the target command is a read command, read the third data corresponding to the target address in the cache unit and the fourth data corresponding to the read command in the storage array, and send them to the host.

[0084] In this embodiment, when the target command received by the storage controller is a read command, the storage controller determines that a target address in the cache unit conflicts with the access address of the read command, indicating that the data to be read by the read command is already stored in the cache unit. In this case, the storage controller reads third data corresponding to the target address in the cache unit and fourth data corresponding to the read command from the storage array, and sends them to the host. The third data is the data already stored in the cache unit among the data to be read by the read command, and the fourth data is the data not yet stored in the cache unit among the data to be read by the read command.

[0085] Specifically, the step of reading the third data corresponding to the target address in the cache unit and the fourth data corresponding to the read command in the storage array includes:

[0086] Step S4011 , determining a third cache sub-unit corresponding to the target address in the cache unit, and reading third data corresponding to the read command from the third cache sub-unit.

[0087] In this embodiment, when the storage controller determines that there is a target address in the cache unit that conflicts with the access address of the read command, it can determine the third cache sub-unit where the cache data corresponding to the target address is stored based on the index corresponding to the target address, and then read the third data corresponding to the read command from the third cache sub-unit.

[0088] For example, an index is NameSpace 1+LBA511+cell 0+128, and the access address corresponding to the read command is LBA511-LBA700. The access address corresponding to the read command overlaps with the storage address range of the index, and the overlapping part is LBA511-LBA638. Then the first address LBA511 in the index is the target address. At this time, based on the target address and the index, the third cache sub-unit can be determined to be cell 0, and the third data with the address LBA511-LBA638 can be read in cell0.

[0089] Step S4012: Read the fourth data corresponding to the read command from the storage array according to the access address of the fourth data corresponding to the read command.

[0090] In this embodiment, after determining that the third data among the data required to be read by the read command has been stored in the cache unit, the storage controller can determine that the other data required to be read by the read command is the fourth data, and then the storage controller reads the fourth data corresponding to the read command from the storage array according to the access address of the fourth data corresponding to the read command.

[0091] For example, an index is NameSpace 1+LBA511+cell 0+128, and the access address corresponding to the read command is LBA511-LBA700. The access address corresponding to the read command overlaps with the storage address range of the index, and the overlapping part is LBA511-LBA638. Then the data with the access address LBA511-LBA638 is the third data, and the data with the access address LBA639-LBA700 is the fourth data. The storage controller reads the data with the address LBA639-LBA700 in the storage array as the fourth data corresponding to the read command.

[0092] In this embodiment, when the target command received by the storage controller is a read command and it determines that a target address in the cache unit conflicts with the access address of the read command, the storage controller reads the third data with the conflict from the cache unit, reads the fourth data without the conflict from the storage array, and then combines the third and fourth data and sends them to the host. This eliminates the need to read data already stored in the cache unit by the read command from the storage array again, thereby improving data reading efficiency and avoiding damage to the storage array caused by repeated reads, thereby helping to extend the life of the storage array.

[0093] Please refer to Figure 8 , Figure 8 : is a flowchart of the fifth embodiment of the present application. The difference between the fifth embodiment and the first to fourth embodiments is that after storing the data in the cache unit, the method further includes:

[0094] Step S501 : Generate a corresponding index according to the access namespace, access address, cache subunit number and data length corresponding to the data stored in the cache unit.

[0095] In this embodiment, when the storage controller receives a target command, it stores the data corresponding to the target command in a cache unit and then generates a corresponding index based on the access namespace, access address, cache subunit number, and data length corresponding to the data stored in the cache unit. For example, if the target command's access namespace is NameSpace 1 and the access address is LBA511-LBA638, which corresponds to a data length of 128, and the storage controller allocates cache subunit 0 for this data, then an index is generated: NameSpace 1+LBA511+cell 0+128. For example, the access namespace of the target command is NameSpace 1, and the access address is LBA511-LBA700, that is, the corresponding data length is 190, and the cache sub-units allocated by the storage controller for these data are cell0 and cell1. At this time, the storage controller stores the data with a data length of 128 and an access address of LBA511-LBA638 in cell0, and can generate an index: NameSpace 1+LBA511+cell 0+128, and stores the data with a data length of 62 and an access address of LBA639-LBA700 in cell1, and can generate an index: NameSpace 1+LBA639+cell 1+62.

[0096] Step S502 : sorting the indexes in the index group corresponding to the current cache sub-unit group based on the access namespace and access address corresponding to the indexes.

[0097] In this embodiment, after storing data in a cache unit, the storage controller sorts the indexes corresponding to each cache sub-unit within each cache sub-unit group within the cache unit based on the access namespace and the access address, within the index group corresponding to the current cache sub-unit group. It is understood that a cache unit is divided into multiple sub-cache areas, each sub-cache area corresponds to a cache sub-unit group, and a cache sub-unit group includes multiple cache sub-units; the indexes corresponding to all cache sub-units within a cache sub-unit group constitute an index group.

[0098] Exemplarily, the storage controller receives a write command, and the access address of the write command is storage addresses 511 to 959 (LBA511-LBA959) in namespace 1 (NameSpace 1) in the storage array, and storage addresses 511 to 638 (LBA511-LBA638) in namespace 2 (NameSpace 2) in the access address storage array; the storage controller stores the carried write data in cache subunit 0 to cache subunit 4 (cell 0-cell 4) in the cache unit, and then generates 5 corresponding indexes, first performs a preliminary sorting based on the namespace, and the preliminary sorting rule is that the namespace number is smaller in the order, and then performs a secondary sorting on the storage addresses in each namespace, and the secondary sorting rule is that the storage address number is smaller in the order, and finally the order of the 5 indexes is: NameSpace 1+LBA511+cell 0+128, NameSpace 1+LBA639+cell 1+128, NameSpace 1+LBA767+cell 2+128, NameSpace 1+LBA895+cell 3+64, NameSpace 2+LBA511+cell 4+128. The index of NameSpace 1 is sorted before the index of NameSpace 2. In the index of NameSpace 1, the index with address LBA511 comes first, followed by the index of LBA639, the index of LBA767, and the index of LBA895.

[0099] Step S503: storing the sorted index group into the index storage module in the cache unit.

[0100] In this embodiment, after the storage controller completes sorting of an index group, it stores the sorted index group in the index storage module of the cache unit. For example, a sub-cache area in the cache unit includes cache sub-units cell0-cell511, i.e., 512 cache sub-units. Once all 512 cache sub-units in the sub-cache area have stored data and the storage controller has sorted the index corresponding to each cache sub-unit, the sorted index group can be stored in the index storage module of the cache unit.

[0101] In this embodiment, after storing the data corresponding to the command in the cache unit, the storage controller generates a corresponding index, sorts the index, and stores it in the index storage module, which helps to improve the efficiency of subsequent conflict detection.

[0102] Please refer to Figure 9 , Figure 9 This is a flow chart of the sixth embodiment of the present application. The difference between the sixth embodiment and the first to fifth embodiments is that the method further includes:

[0103] Step a: writing the data in the cache unit into the storage array according to the access namespace and access address in the corresponding index.

[0104] In this embodiment, after storing the data in the cache unit, the storage controller generates a corresponding index, sorts the index and stores it in the index storage module. According to the sorting of the index in the index storage module, the data in the cache unit is written into the storage array according to the access namespace and access address in each index, or the data in the cache unit is sent to the host.

[0105] The storage controller of this embodiment first stores the data corresponding to the command in a cache unit and generates an index. Then, based on the access namespace and access address in the index, the controller writes the data in the cache unit to the storage array or sends the data in the cache unit to the host. This improves the storage system's response efficiency to commands.

[0106] It is understandable that Figure 10 As shown, the present application also provides a cache data management device, the cache management device comprising:

[0107] The acquisition module 10 is used to acquire the access address corresponding to the target command when detecting the target command of the host;

[0108] A search module 20 is used to search for a target address in a cache unit that conflicts with an access address;

[0109] The update module 30 is configured to update the cache data corresponding to the target address in the cache unit to the first data corresponding to the target address in the write command, and write the second data in the write command into the cache unit when the target command is a write command.

[0110] The device of this embodiment corresponds to the cache data management method of the above embodiment. The options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0111] The present application also provides a storage controller comprising a storage interface control module, a cache unit, a cache management device, and a non-volatile storage control module; the cache management device is connected to the storage interface control module, the non-volatile storage control module, and the cache unit, respectively; and the cache management device is configured to execute a cache data management method. The optional features in the above embodiments also apply to this embodiment and are therefore not described again here.

[0112] The present application also provides a computer device. Exemplarily, the computer device includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program to enable the computer device to execute the functions of the various modules in the above-mentioned cache data management method or the above-mentioned cache data management device.

[0113] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU) and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0114] The memory may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0115] The present application also provides a computer storage medium for storing the computer program used in the above-mentioned computer device. The computer storage medium may be a readable storage medium, a non-volatile storage medium, or a volatile storage medium. For example, the computer storage medium may include, but is not limited to, various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0116] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0117] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0118] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0119] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A cache data management method, characterized in that: The method is applied to a storage controller in a storage system, wherein the storage controller includes a cache unit, and the storage system further includes a host and a storage array. The method includes: When a target command of the host is detected, obtaining an access address corresponding to the target command; Searching the cache unit for a target address that conflicts with the access address; When the target command is a write command, the cache data corresponding to the target address in the cache unit is updated to the first data corresponding to the target address in the write command, and the second data in the write command is written into the cache unit.

2. The cache data management method according to claim 1, wherein: The cache unit includes an index storage module, and the step of searching the cache unit for a target address that conflicts with the access address includes: Determining a target index group according to an index namespace range of each index group in the index storage module and an access namespace corresponding to the access address; An index address that overlaps with the access address is searched in the target index group, and is determined to be a target address that conflicts with the access address.

3. The cache data management method according to claim 1, wherein: The updating of the cache data corresponding to the target address in the cache unit to the first data corresponding to the target address in the write command, and writing the second data in the write command into the cache unit, comprises: Determining a first cache sub-unit in the cache unit where cache data corresponding to the target address is stored; storing first data corresponding to the target address in the write command into the first cache sub-unit; A second cache sub-unit is determined according to the storage information of the cache unit, and the second data in the write command is stored in the second cache sub-unit.

4. The cache data management method according to claim 1, wherein: After the step of searching the cache unit for a target address that conflicts with the access address, the method further includes: When the target command is a read command, third data corresponding to the target address in the cache unit and fourth data corresponding to the read command in the storage array are read and sent to the host.

5. The cache data management method according to claim 4, characterized in that: The step of reading the third data corresponding to the target address in the cache unit and the fourth data corresponding to the read command in the storage array includes: Determine a third cache sub-unit corresponding to the target address in the cache unit, and read third data corresponding to the read command from the third cache sub-unit; The fourth data corresponding to the read command is read from the storage array according to an access address of the fourth data corresponding to the read command.

6. The cache data management method according to claim 4, characterized in that: After storing the data in the cache unit, the method further includes: A corresponding index is generated according to the access namespace, access address, cache subunit number and data length corresponding to the data stored in the cache unit.

7. The cache data management method according to claim 6, characterized in that: After the step of generating a corresponding index according to the access namespace, access address, cache subunit number and data length corresponding to the data stored in the cache unit, the method further includes: sorting the indexes in the index group corresponding to the current cache sub-unit group based on the access namespace and access address corresponding to the indexes; The sorted index group is stored in the index storage module in the cache unit.

8. The cache data management method according to claim 1, wherein: The method further comprises: The data in the cache unit is written into the storage array according to the access namespace and the access address in the corresponding index.

9. A cache management device, characterized in that: The cache management device includes: An acquisition module, configured to acquire an access address corresponding to a target command when a target command from a host is detected; A search module, configured to search a cache unit for a target address that conflicts with the access address; An update module is used to update the cache data corresponding to the target address in the cache unit to the first data corresponding to the target address in the write command when the target command is a write command, and write the second data in the write command into the cache unit.

10. A storage controller, characterized in that: It includes a storage interface control module, a cache unit, a cache management device and a non-volatile storage control module; The cache management device is respectively connected to the storage interface control module, the non-volatile storage control module and the cache unit; The cache management device is used to implement the cache data management method according to any one of claims 1 to 8.

Images