Computer-implemented method of testing logic circuitry implementing cache functionality
By storing instructions or data sequences in cache logic circuits and using access counters to detect defects, the problems of high detection costs and data continuity in the prior art are solved, and efficient and reliable defect detection is achieved.
Patent Information
- Application Number
- CN202510182551.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-02-10
- Filing Date
- 2025-02-19
- Publication Date
- 2025-08-22
AI Technical Summary
In the prior art, defect detection of cache logic circuits requires expensive BIST systems or cache redundancy, and conventional software testing requires clearing of stored content, affecting the continuity of user data.
By storing instructions or data sequences in cache logic circuits, using access counters to detect defects, prevent unintended execution or reading, and using software methods to detect defects without clearing content.
This enables efficient and reliable detection of cache logic circuit defects without clearing the stored content, avoiding expensive hardware solutions.
Smart Images
Figure CN120523657A_ABST
Abstract
Description
Technical Field
[0001] Embodiments and implementations relate to apparatus for forming cache memory, particularly to logic circuits for implementing cache functionality of integrated circuits, and more particularly to testing of these logic circuits. Background Art
[0002] A cache memory is a storage space in an integrated circuit that is used to store instructions (in this case, we talk about instruction cache memory) or to store data (in this case, we talk about data cache memory). Cache memory can be formed from memory cells, such as "SRAM" or "DRAM" type memory cells. Logic circuits (also called "cache logic") can also implement cache functions, i.e., replicate the operations of the cache memory. Summary of the Invention
[0003] Over the life of an integrated circuit, such logic circuitry implementing cache functionality (hereinafter more simply referred to by the term "cache logic circuitry" or "cache logic") may exhibit hardware defects related to its wear.
[0004] When these logic circuits are used in the context of applications that comply with functional safety standards or utilize safety functions, they are periodically tested to detect these hardware defects, particularly permanent defects. These defects often lead to corruption of the data stored in the logic circuits and, consequently, to malfunctions of the integrated circuits.
[0005] Unlike memory cells, whose defects can be detected and possibly corrected, for example, by using parity bits or error correction codes, cache logic circuits may require other solutions that can detect their defects.
[0006] In particular, these other solutions may consist in the use of known “BIST” systems (acronym for “Built-in Self-Test”, which means “Integrated Automatic Test”) to enable detection of defects in cache memories and logic circuits, or in the implementation of cache redundancy in these logic circuits, or in tests based on the use of software.
[0007] However, the implementation of a "BIST" system and cache redundancy is a relatively expensive solution, so testing cache logic circuits through software remains an advantageous solution.
[0008] Conventional testing of cache logic circuits by software is usually performed before initialization of these logic circuits, which consists in, in particular, clearing the contents of the memory to allow the test to be performed in a "deterministic" manner.
[0009] In other words, tests performed on cache logic circuits after initialization of these logic circuits lead to results that allow determining whether the logic circuits have defects, in contrast to results obtained by tests performed on logic circuits whose contents have not been flushed.
[0010] This type of test therefore prevents the user from benefiting from the storage of such cache logic circuits after each test execution, since the contents of these circuits are cleared before each test and therefore instructions or data must be stored again at the end of each test.
[0011] Therefore, there is a need to provide a solution that allows detecting defects in cache logic circuits and that does not have the above-mentioned disadvantages.
[0012] The cache logic circuit may be used to store instructions. This logic circuit is then referred to as instruction cache logic circuit or more simply as "instruction cache logic."
[0013] The cache logic circuit may be used to store data. This logic circuit is then referred to as data cache logic circuit or more simply as "data cache logic."
[0014] According to one embodiment, a method for testing an instruction cache logic circuit of an integrated circuit is provided, comprising:
[0015] storing an instruction sequence comprising M instructions in the cache logic circuit,
[0016] Read the initial counter value of the cache access counter (hit counter)
[0017] The sequence of instructions is executed and for each instruction executed from the cache logic circuit, a current counter value of the cache access counter is incremented.
[0018] reading a final counter value of said cache access counter,
[0019] preventing unintended execution of instructions by the test during the time period from reading the initial counter value to reading the final counter value,
[0020] subtracting the initial counter value from the final counter value, and
[0021] The result of said subtraction is compared with the value M.
[0022] In various embodiments, the above methods may be implemented in an embedded electronic device including one or more processors, or implemented by a computing system or device.
[0023] Advantageously, the aforementioned prevention is performed by deactivating interrupts that may lead to the unintended execution of additional and / or different instructions. Unintended execution of these instructions may trigger additional counts of the cache access counter and thus may modify the test results. Thus, by deactivating these interrupts, modification of the test results by unintended execution of instructions is prevented, which therefore allows for increased reliability of the test.
[0024] This approach allows determining when a logic circuit is defective based on the value of a cache access counter ("hit counter").
[0025] Indeed, if the result of the subtraction is equal to the number of instructions M, the logic circuit can be considered free of defects. Conversely, if this result differs from M, the comparison allows indicating the presence of a defect in the logic circuit.
[0026] This method allows the testing of the logic circuitry implementing the cache functionality to be performed by software means without the need to clear the contents of the logic circuitry.
[0027] Thus, the method according to this aspect allows for the detection of defects in a logic circuit while allowing the continued use of instructions already stored in the logic circuit without having to store them again.
[0028] Furthermore, the method according to this aspect allows avoiding hardware solutions which may be expensive and have a complex design.
[0029] While the implementation of this aspect just mentioned provides a single execution of a sequence of M instructions, in another implementation it is possible to provide a loop processing, i.e., the sequence of M instructions is executed N times (in this case N is greater than 1, while in the previous implementation N is equal to 1), at the end of which the result of the aforementioned subtraction is compared with the value of the product N×M to determine the presence or absence of a defect in the instruction cache logic circuit.
[0030] According to an implementation of another aspect related to testing of data cache logic, there is provided a method for testing data cache logic circuitry of an integrated circuit, the integrated circuit including a first memory and a second memory, the method comprising:
[0031] storing at least one piece of data in at least one memory location of the second memory,
[0032] storing a sequence of instructions in the first memory, the sequence of instructions including at least one instruction for storing the address of the at least one memory location and corresponding data stored at the memory location in the data cache logic circuit, and at least one instruction for reading the address and data from the data cache logic circuit,
[0033] reading a first initial counter value of a cache access counter (“hit counter”), and / or a second initial counter value of a cache fault counter (“miss counter”), (the first initial counter value and the second initial counter value may be the same or different),
[0034] The instruction sequence is executed, and for each store instruction and each load instruction:
[0035] incrementing a current counter value of the cache access counter (“hit counter”) when one of the addresses read in the data cache logic circuit corresponds to an address of the at least one memory location of the second memory,
[0036] and / or incrementing a current counter value of the cache miss counter (“miss counter”) when none of the addresses read in the data cache logic circuit corresponds to the address of the at least one memory location of the second memory,
[0037] reading a first final counter value of the cache access counter and / or a second final counter value of the cache miss counter,
[0038] preventing unintended data reading by the test during a time period lasting from reading the first initial counter value and / or the second initial counter value to reading the first final counter value and / or the second final counter value,
[0039] subtracting the first initial counter value from the first final counter value to obtain a first result and / or subtracting the second initial counter value from the second final counter value to obtain a second result, and
[0040] The first result is compared with a value equal to the number of read instructions contained in the instruction sequence and / or the second result is compared with a value equal to zero.
[0041] In various embodiments, the above methods may be implemented in an embedded electronic device including one or more processors, or implemented by a computing system or device.
[0042] The prevention described herein is performed in a manner similar to that described for the instruction cache logic circuitry by deactivating interrupts that could result in unintended readings of data stored in the data cache logic circuitry during testing. Unintended readings of such data could trigger additional counts in the cache access counters ("hit counters") or cache failure counters ("miss counters") and thus potentially modify the test results. By deactivating these interrupts, modification of the test results due to unintended readings of data is prevented, thereby increasing the reliability of the test.
[0043] Similar to the foregoing, the method according to this aspect allows for determining when data cache logic circuitry is defective based on the values of the cache access counter and / or the cache fail counter.
[0044] Indeed, the data cache logic circuit may be considered to be functioning correctly if the first result is equal to the number of read instructions present in the instruction sequence and if the second result is equal to 0. Conversely, this comparison allows indicating the presence of a defect in the data cache logic circuit.
[0045] The other advantages described above in connection with the reliability of the test method and the test of an instruction cache logic circuit are also valid in the case of the method for testing a data cache logic circuit.
[0046] Furthermore, while the implementation of this other aspect just mentioned provides a single execution of the instruction sequence, in another implementation, it is possible to provide a loop processing of the instruction sequence, i.e., N (in this case N is greater than 1, while in the previous implementation N is equal to 1) executions, and finally comparing the result of the above subtraction with a value equal to N times the number of read instructions included in the instruction sequence to determine the presence or absence of a defect in the data cache logic circuit.
[0047] Advantageously, the method according to this further aspect may comprise interrupting the instruction sequence if the data read in the data cache logic circuit at the address is different from the data stored in the memory location of the second memory at the address.
[0048] Verification of data stored by the data cache logic during instruction execution allows for detection of defects in the cache logic before test results are determined from the initial and final counter values.
[0049] Therefore, the test duration of the data cache logic circuit can be shortened when a defect is detected by comparing a data segment stored by the logic circuit with a data segment stored in the second memory for the same address.
[0050] According to yet another aspect, a computer program product is provided that is configured to test (instruction or data) cache logic circuitry of an integrated circuit, the computer program product comprising instructions that, when the program is executed by a computer, cause the computer to implement a method for testing a previously defined instruction cache logic circuitry or a method for testing a previously defined data cache logic circuitry.
[0051] According to yet another aspect, there is provided a computer system comprising:
[0052] a memory comprising a computer program product as defined above,
[0053] A processing unit is configured to execute the computer program product. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] Other advantages and features of the present disclosure will become apparent upon review of the detailed description of non-limiting embodiments and implementations and from the accompanying drawings, in which:
[0055] Figure 1 、 Figure 2 、 Figure 3 and Figure 4 Implementations and embodiments of the present disclosure are schematically illustrated. DETAILED DESCRIPTION
[0056] Next, Figure 1 and Figure 3 Involves testing of instruction cache logic, and Figure 2 and Figure 4 The test involves the data cache logic, and also in the context of loop-free processing (N=1).
[0057] Figure 1 A computer system SYS including an integrated circuit IC according to an embodiment of the present disclosure is schematically shown.
[0058] The integrated circuit IC includes an instruction cache logic circuit LCacheA. The logic circuit LCacheA implements a cache function.
[0059] This logic circuit is well known to those skilled in the art and is called "Cache logic" in English. It allows for the storage of instructions. The structure and operation of this cache logic circuit LCacheA are understood to be common knowledge in the prior art and will not be described in detail in this application. For simplicity, the term "logic circuit LCacheA" will sometimes be used to refer to the instruction cache logic circuit LCacheA that implements the cache function.
[0060] The integrated circuit IC further comprises a first memory MEM1, for example a RAM memory (standing for “Random Access Memory”), and a processing unit UT, for example a processor.
[0061] The first memory MEM1 includes dedicated space for storing a computer program product (e.g., embedded system software) and dedicated space for storing an instruction sequence SW. For example, the instruction sequence SW includes several instructions denoted as InstA to InstB stored in memory locations at addresses AddA to AddB. The embedded system software is configured to test the logic circuit LCacheA, in particular by testing the logic circuit LCacheA due to the execution of the instruction sequence SW.
[0062] The processing unit is configured to execute the embedded software to implement the Figure 3 To this end, the processing unit UT is connected to a first memory MEM1.
[0063] The integrated circuit IC further includes a second memory MEM2, which may be, for example, a RAM memory, configured to store an instruction sequence different from the instruction sequence SW recorded in the first memory MEM1. For example, the instruction sequence stored in the second memory MEM2 includes M=3 instructions Inst00, Inst01, and Inst02.
[0064] In particular, each instruction of the instruction sequence is stored at an address of a memory location of the second memory MEM2. For example, the address Add00 of the memory location comprises the instruction Inst00.
[0065] The logic circuit LCacheA is configured to store an address of a memory location of the second memory MEM2 and an instruction stored in the second memory MEM2 at the memory location.
[0066] The processing unit UT is configured to execute instructions stored in the logic circuit LCacheA, for example, instruction Inst00 associated with the address Add00.
[0067] Furthermore, the integrated circuit IC includes a counter HCNT.
[0068] This counter HCNT is usually referred to as a “hit counter” or a “cache access counter” by those skilled in the art.
[0069] The counter HCNT is configured to increment the counter value ValCurr1 each time the processing unit UT executes an instruction stored in the logic circuit LCacheA.
[0070] The processing unit UT is further configured to read the counter value ValCurr1 of the counter HCNT.
[0071] Figure 3 Schematically shows an example of a method based on the use of a counter HCNT, the method being implemented by a computer, in particular by embedded software, for testing a reference before Figure 1 The logic circuit LCacheA of the integrated circuit IC is described. It is assumed that before the method is implemented, the initial counter value of the first counter HCNT is equal to 0, although this initial counter value may be different from 0.
[0072] The method comprises step S21 , ie preventing unintended execution of instructions by a test.
[0073] More specifically, an interrupt INTR ( Figure 1 ) may cause the processing unit UT to execute these instructions unexpectedly. The unexpected execution of these instructions may trigger additional counting of the counter HCNT and thus may modify the result of the test.
[0074] In this respect, the aforementioned blocking can be performed by deactivating the interrupt INTR by the processing unit UT.
[0075] Such deactivation is a conventional operation known per se.
[0076] This blocking, which allows the reliability of the test to be increased, is performed until the interrupted step S26 is reactivated.
[0077] The method comprises a step S22, in which the processing unit UT executes a sequence of instructions stored in the second memory MEM2.
[0078] In this example, the instruction sequence includes M=3 instructions Inst00, Inst01 and Inst02.
[0079] Step S22 further includes storing the instruction sequences Inst00 , Inst01 and Inst02 in the logic circuit LCacheA.
[0080] The method further includes a step S23 of reading an initial counter value ValInit1 of the first counter HCNT.
[0081] The initial counter value ValInit1 is read by the processing unit UT.
[0082] The method comprises a step S24 of executing the instruction sequence Inst00 , Inst01 and Inst02 .
[0083] During this step S24 , the instructions Inst00 , Inst01 and Inst02 are read from the logic circuit LchacheA and executed by the processing unit UT.
[0084] Step S24 comprises, each time an instruction is executed, incrementing the current counter value ValCurr1 of the counter HCNT when the executed instruction is an instruction stored in the logic circuit LCacheA.
[0085] However, in the event that the logic circuit LCacheA is defective, it may happen that the processing unit UT does not execute some or all instructions stored in the logic circuit LCache A. In this case, the current counter value ValCurr1 is not incremented.
[0086] The method then comprises a step S25 of reading the final counter value ValFnl1 of the counter HCNT. In the absence of any defect in the logic circuit LCacheA, the final counter value ValFnl1 amounts to 3 in this example.
[0087] The final counter value ValFnl1 is read by the processing unit UT.
[0088] Afterwards, the method comprises a step S26 (mentioned above) of activating interrupts INTR, in particular when these interrupts INTR were deactivated in step S21 .
[0089] The method comprises a step S27 of subtracting the initial counter value ValInit1 from the final counter value ValFnl1 . The result D1 of this subtraction is stored in a third variable and is therefore equal to 3 in this example in the absence of any defect in the logic circuit LCacheA.
[0090] Step S27 further comprises comparing the result D1 with the number of instructions M of the instruction sequence.
[0091] The result of this comparison allows to conclude that the logic circuit cache does not have any defects if D1 is equal to M, or to conclude that it is defective if D1 is different from M.
[0092] This method allows testing of a logic circuit's cache memory to be performed by software means without clearing the contents of the logic circuit. Thus, defects in the logic circuit can be detected while allowing instructions already stored in the logic circuit to continue to be used without having to store them again.
[0093] Thus, potentially expensive and complex hardware solutions are avoided.
[0094] Figure 2 A system SYS including an integrated circuit IC according to another embodiment of the present disclosure is schematically shown.
[0095] The integrated circuit IC comprises a data cache logic circuit LCacheB. This logic circuit implements a cache function. Again, such logic circuits are known to those skilled in the art as "Cache logic" in English and allow data to be stored. Although they may be identical to those previously referred to, Figure 1 The structure and operation of the described cache logic circuit LCacheA are different, but the structure and operation of this logic circuit LCacheB are classical and therefore will not be described in detail in this application.
[0096] In the following, for simplicity, the term “logic circuit LCacheB” will sometimes be simply used to refer to the data cache logic circuit LCacheB that implements the cache function.
[0097] The integrated circuit IC further comprises a first memory MEM1 and a processing unit UT such as a processor.
[0098] The processing unit UT and the first memory MEM1 can be referred to above Figure 1 The embedded system software (instruction sequence SW) stored in the first memory MEM1 is now configured to test the logic circuit LCacheB.
[0099] The processing unit UT is configured to execute the embedded software in order to implement the following reference Figure 4 Described method.
[0100] Furthermore, the integrated circuit IC comprises a second memory MEM2. The second memory MEM2 is configured to store a piece of data at an address of a memory location of the second memory MEM2. For example, the data segment Dat00 is stored at the memory location at the address Add03.
[0101] The logic circuit LCacheB is configured to store the address of a memory location of the second memory MEM2 and the data stored in the second memory MEM2 at the memory location. For example, in this case, it is assumed that the logic circuit LCacheB is defective and the data Dat01 stored in the logic circuit LCacheB is different from the data Dat00 stored at the corresponding address Add03 in the second memory MEM2.
[0102] The processing unit UT is configured to read data stored in the logic circuit LCacheB, for example, data Dat01 associated with the address Add03 .
[0103] The integrated circuit IC further includes a counter HCNT and a counter MCNT.
[0104] The counter HCNT, also referred to herein by the term “cache access counter” (“hit counter”), is configured to increment a counter value ValCurr1 each time the processing unit UT reads a piece of data stored in the logic circuit LCacheB.
[0105] The counter MCNT (often referred to as a "miss counter" or "cache fault counter" by those skilled in the art) is configured to increment a counter value ValCurr2 each time the processing unit UT reads a data segment stored in the second memory MEM2 and the data segment is not stored in the logic circuit LCacheB. The processing unit UT is also configured to read the counter value ValCurr1 of the counter HCNT and the counter value ValCurr2 of the counter MCNT.
[0106] Figure 4 Schematically shows an example of a method based on the use of a counter HCNT implemented by a computer, in particular an embedded software, for testing a previously referenced Figure 2 The logic circuit LCacheB of the integrated circuit IC is described.
[0107] It is assumed here that the initial counter value ValCurr1 of the counter HCNT is equal to 0, although the initial counter value may be different from 0.
[0108] The method comprises step S31 of preventing data from being read that is not intended by the test.
[0109] More specifically, through Figure 3 The interrupt INTR ( Figure 2 ) may cause the processing unit UT to read these data unintentionally. The unintended reading of these data may trigger an additional count of the counter HCNT and thus may modify the result of the test.
[0110] In this respect, the aforementioned blocking can be performed by deactivating the interrupt INTR by the processing unit UT.
[0111] Such deactivation is a conventional operation known per se.
[0112] This blocking, which allows the reliability of the test to be increased, is performed until the interrupted step S38 is reactivated.
[0113] The method comprises step S32 of storing at least one piece of data in at least one memory location of the second memory MEM2, for example, data Dat00 at a memory location at an address Add03 of the second memory MEM2.
[0114] Then, the method comprises a step S33 comprising reading, by the processing unit UT, data Dat00 from a memory location of the second memory MEM2 at address Add03 and storing, in the logic circuit LCacheB, the address Add03 of the memory location and the stored data Dat00 in the memory location of the second memory MEM2.
[0115] The method comprises a step S34 of reading an initial counter value ValInit2 of a counter HCNT of the integrated circuit IC.
[0116] An initial counter value ValInit2 is read by the processing unit UT and is equal to 1, for example, at this stage.
[0117] The method includes step S35 , which includes reading the address and data of the logic circuit LCacheB.
[0118] Step S35 includes incrementing the current counter value ValCurr1 of the counter HCNT when the processing unit UT reads a piece of data stored in the logic circuit LCacheB.
[0119] Nevertheless, a cache miss may occur if the logic circuit LCacheB is defective and the processing unit UT may read data stored at a memory location of the memory MEM2 which is not stored in the logic circuit LCacheB. In this case, the current counter value ValCurr1 is not incremented.
[0120] The method comprises a step S36 of interrupting the instruction sequence SW if the data at the address of the memory location of the second memory MEM2 read by the logic circuit LCacheB differs from the data stored in the memory location of the second memory MEM2 at that address. In practice, in the event of a defect, the data segment stored in the logic circuit LCacheB may be corrupted, so that the data segment does not correspond to the data segment stored at the corresponding address in the second memory MEM2.
[0121] More specifically, in Figure 2 and Figure 4 In the example shown, the data read from the logic circuit LCacheB at the address Add03 during the execution of the instruction sequence is data Dat01, which is different from the data Dat00 stored in the memory location of the second memory MEM2 located at the address Add03. Therefore, the execution of the instruction sequence SW by the processing unit UT is interrupted (step S36), and it is possible to indicate that a defect in the logic circuit LCacheB has been detected.
[0122] In the following, it will be considered that the execution of no instruction sequence is interrupted.
[0123] Then, the method comprises a step S37 of reading the final counter value ValFn12 of the counter HCNT.
[0124] The final counter value ValFn12 is read by the processing unit UT. In this example, in the absence of a cache miss, the final counter value ValFn12 is equal to 2, since the initial value is considered to be equal to 1.
[0125] The method includes the above reference Figure 3 The step S26 described similarly activates the interrupt INTR at step S38.
[0126] The method includes a combination similar to the previous Figure 3 Step S39 of step S27 described above. Step S39 consists of subtracting the initial counter value ValInit2 from the final counter value ValFnl2 to obtain a first result D1, here equal to 2-1=1. Step S39 consists of comparing the first result D1 with the number of read instructions contained in the instruction sequence SW.
[0127] Assuming that no execution of the instruction sequence was interrupted due to the first result D1 being equal to the expected value of 1, the result of this comparison allows to conclude that the logic circuit LCacheB is not defective.
[0128] The advantages of the method for testing the logic circuit LCacheB are similar to those of the above-described method for testing the logic circuit LCacheA.
[0129] Although the counter HCNT has been used to test the logic circuit LCacheB, the counter MCNT (“miss counter”) may also be used. The value of the counter MCNT is incremented each time the processing unit UT reads data Dat00 in the second memory MEM2 and the data is not stored in the logic circuit LCacheB.
[0130] By comparing the difference between the final counter value and the initial counter value of the counter MCNT with 0, it can be determined whether the logic circuit is defective.
[0131] A computer-implemented method for testing an instruction cache logic circuit (LCacheA) of an integrated circuit (IC) may include: storing an instruction sequence including M instructions (Inst00, Inst01, Inst02) in the cache logic circuit (LCacheA), reading an initial counter value (ValInit1) of a cache access counter (HCNT), executing the instruction sequence N times, where N is greater than or equal to 1, and for each instruction executed from the cache logic circuit (LCacheA), incrementing a current counter value (ValCurr) of the counter (HCNT), reading a final counter value (ValFn1) of the counter (HCNT), preventing unintended execution of instructions by the test during a time period lasting from reading the initial counter value (ValInt1) until reading the final counter value (ValFn1), subtracting the initial counter value (ValInit1) from the final counter value (ValFn1), and comparing a result of the subtraction (D1) with a value equal to a product N×M.
[0132] A computer-implemented method for testing a data cache logic circuit (LCacheB) of an integrated circuit (IC), the integrated circuit comprising a first memory (MEM1) and a second memory (MEM2), the method comprising: storing at least one piece of data (Dat00) in at least one memory location of the second memory, storing an instruction sequence (SW) in the first memory (MEM1), the instruction sequence comprising at least one instruction for storing an address (Add03) of the at least one memory location and corresponding data (Dat00) stored at the memory location in the cache logic circuit (LCacheB), and for reading the address and data of the data cache logic circuit (LCacheB), reading a first initial counter value of a cache access counter (HCNT) and / or a second initial counter value of a cache miss counter (MCNT), executing the instruction sequence (SW) N times, wherein N is greater than or equal to 1, and, for each store instruction and each read instruction: when one of the addresses read in the cache logic circuit (LCacheB) corresponds to the address of the at least one memory location of the second memory (MEM2), incrementing a current count of the cache access counter (HCNT) and / or when the address read in the cache logic circuit (LCacheB) does not correspond to the address of the at least one memory location of the second memory (MEM2), incrementing the current counter value (ValCurr2) of the cache miss counter (MCNT), reading a first final counter value (ValFnl2) of the cache access counter (HCNT) and / or a second final value of the cache miss counter (MCNT), and performing a series of operations from reading the first initial counter value and / or the second initial counter value until reading the first final counter value and / or the second final value of the cache miss counter (MCNT). The test apparatus comprises: a first cache access counter (HCNT) and a second cache fault counter (MCNT) configured to prevent unintended data reading during a period of time during which the test apparatus stores the first initial counter value (ValInit2) and / or subtract the first final counter value (ValFnl2) of the cache access counter (HCNT) from the first initial counter value (ValInit2) to obtain a first result (D1) and / or subtract the second initial counter value from the second final counter value of the cache fault counter (MCNT) to obtain a second result (D2), and comparing the first result (D1) with a value equal to N times the number of read instructions included in the instruction sequence (SW) and / or comparing the second result (D2) with a value equal to 0.
[0133] The method may include interrupting the instruction sequence (SW) if data (Dat01) read in the device forming the cache at the address is different from data (Dat00) stored in a memory cell of the second memory (MEM2) located at the address (Add03).
[0134] A computer program product configured to test a cache logic circuit (LCacheA, LCacheB) of an integrated circuit may include instructions that, when executed by a computer, cause the computer to implement one or more of the above methods.
[0135] A computer system may comprise: a memory (MEM1), (MEM1), a processing unit (UT) configured to execute said computer program product.
[0136] The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. If necessary, aspects of the embodiments can be modified to employ concepts from the various patents, applications, and publications to provide further embodiments.
[0137] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.
Claims
1. A computer-implemented method for testing an instruction cache logic circuit of an integrated circuit, the method comprising: Storing an instruction sequence comprising M instructions in the cache logic circuit; Read the initial counter value of the cache access counter; executing the instruction sequence N times, where N is greater than or equal to 1, and incrementing a current counter value of the counter for each instruction executed from the cache logic circuit; reading a final counter value of the counter; preventing unintended execution of instructions by the test during a time period lasting from reading the initial counter value to reading the final counter value; subtracting the initial counter value from the final counter value; as well as The result of the subtraction is compared to a value equal to the product of N and M.
2. A computer-implemented method for testing data cache logic circuitry of an integrated circuit, the integrated circuit comprising a first memory and a second memory, the method comprising: storing at least one piece of data in at least one memory location of the second memory; storing a sequence of instructions in the first memory, the sequence of instructions including at least one instruction for storing an address of the at least one memory location and corresponding data stored at the memory location in the cache logic circuitry, and at least one instruction for reading an address and data from the data cache logic circuitry; reading at least one of a first initial counter value of a cache access counter or a second initial counter value of a cache miss counter; Execute the instruction sequence N times, where N is greater than or equal to 1, and for each store instruction and each load instruction, perform at least one of the following: incrementing a current counter value of the cache access counter when one of the addresses read in the cache logic circuit corresponds to the address of the at least one memory location of the second memory; or incrementing a current counter value of the cache miss counter when none of the addresses read in the cache logic circuit corresponds to the address of the at least one memory location of the second memory; reading at least one of a first final counter value of the cache access counter or a second final value of the cache miss counter; preventing reading of data not intended by the test during a time period lasting from reading the first initial counter value or the second initial counter value to reading the first final counter value or the second final counter value, Do at least one of the following: subtracting the first initial counter value from the first final counter value of the cache access counter to obtain a first result; or subtracting the second initial counter value from the second final counter value of the cache miss counter to obtain a second result; as well as The first result is compared to at least one of a value equal to N times the number of read instructions included in the instruction sequence or the second result having a value equal to 0.
3. The method according to claim 2, comprising: The instruction sequence is interrupted if the data read at the address in the device forming the cache memory is different from the data stored in the memory location of the second memory located at the address.
4. A computer program product configured to test a cache logic circuit of an integrated circuit, the computer program product comprising instructions that, when executed by a computer, cause the computer to perform the method, the method comprising: Storing an instruction sequence comprising M instructions in the cache logic circuit; Read the initial counter value of the cache access counter; executing the instruction sequence N times, where N is greater than or equal to 1, and incrementing a current counter value of the counter for each instruction executed from the cache logic circuit; reading a final counter value of the counter; preventing unintended execution of instructions by the test during a time period lasting from reading the initial counter value to reading the final counter value; subtracting the initial counter value from the final counter value; as well as The result of the subtraction is compared to a value equal to the product of N and M.
5. A computer system comprising: a memory for storing content; as well as A processing unit configured to execute the contents to cause the system to perform a method for testing a data cache logic circuit of an integrated circuit, the integrated circuit comprising a first memory and a second memory, the method comprising: storing at least one piece of data in at least one memory location of the second memory; storing a sequence of instructions in the first memory, the sequence of instructions including at least one instruction for storing an address of the at least one memory location and corresponding data stored at the memory location in the cache logic circuitry, and at least one instruction for reading an address and data from the data cache logic circuitry; reading at least one of a first initial counter value of a cache access counter or a second initial counter value of a cache miss counter; Execute the instruction sequence N times, where N is greater than or equal to 1, and for each store instruction and each load instruction, perform at least one of the following: incrementing a current counter value of the cache access counter when one of the addresses read in the cache logic circuit corresponds to the address of the at least one memory location of the second memory; or incrementing a current counter value of the cache miss counter when none of the addresses read in the cache logic circuit corresponds to the address of the at least one memory location of the second memory; reading at least one of a first final counter value of the cache access counter or a second final value of the cache miss counter; preventing reading of data not intended by the test during a time period lasting from reading the first initial counter value or the second initial counter value to reading the first final counter value or the second final counter value, Do at least one of the following: subtracting the first initial counter value from the first final counter value of the cache access counter to obtain a first result; or subtracting the second initial counter value from the second final counter value of the cache miss counter to obtain a second result; and The first result is compared to at least one of a value equal to N times the number of read instructions included in the instruction sequence or the second result having a value equal to 0.
6. The system of claim 5, wherein the method comprises: The instruction sequence is interrupted if the data read at the address in the device forming the cache memory are different from the data stored in the memory location of the second memory at the address.