A method and system for key operation testing of an automotive chip

Abstract

The application relates to the technical field of chip testing, in particular to a key operation test method and system for an automotive chip. The system comprises a host computer, which sequentially applies different voltage disturbances to a tested chip; when each voltage disturbance is applied, the host computer sends a control instruction of an excitation signal to an external programmable logic chip; the external programmable logic chip sequentially sends an excitation signal of a key operation to the tested chip and receives an operation completion signal returned by the tested chip; the time difference of the excitation signal and the operation completion signal of each frequency, or the fact that the operation completion signal is not received, or the signal returned by the tested chip except the operation completion signal, is sent to the host computer; and the host computer judges whether the key operation of the tested chip is functionally failed under each voltage disturbance and the excitation signal of each frequency. The scheme provided in the application can eliminate the interference of voltage disturbance on the signal timing accuracy and guarantee the stability of second-level measurement.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and more specifically, to a key operation testing method and system for automotive-grade chips. Background Technology

[0002] With the trend of automotive electronics electrification, automotive-grade chips must maintain timing stability under complex voltage disturbances, and the stability of their critical operation execution time directly affects driving safety. Critical operation timing is a key indicator for automotive-grade chip certification, and performance consistency must be verified under extreme conditions such as overvoltage, undervoltage, and voltage dips.

[0003] The current testing method has the following problems:

[0004] 1. Internal timers or software timers are significantly affected by process / voltage / temperature drift, resulting in insufficient test accuracy in scenarios with multiple voltage disturbances;

[0005] 2. The lack of a high-precision external third-party testing system results in insufficient credibility of test results, failing to meet certification requirements;

[0006] 3. The testing process is complex, has poor compatibility, and is difficult to adapt to multiple chips and different interface protocols in an integrated manner;

[0007] 4. The inability to establish a quantitative relationship between voltage disturbance parameters and critical chip operation failures (such as timeouts or incorrect results) leads to an ambiguity in safety boundaries.

[0008] In view of the above, this application is hereby submitted. Summary of the Invention

[0009] The purpose of this application is to provide a key operation testing method and system for automotive-grade chips to solve the problems in the prior art.

[0010] To achieve the above objectives, this application adopts the following technical solution:

[0011] Firstly, this application provides a key operation testing system for automotive-grade chips, including:

[0012] The main control computer applies different voltage disturbances to the chip under test sequentially through a programmable power supply module; when each voltage disturbance is applied, the main control computer sends control commands of different frequencies of excitation signals to an external programmable logic chip.

[0013] The external programmable logic chip, in response to the control command, sequentially sends excitation signals of different frequencies for key operations to the chip under test, and receives the operation completion signal returned by the chip under test.

[0014] The external programmable logic chip sends the time difference between the excitation signal and the operation completion signal for each frequency, or the signal that the operation completion signal is not received, or the signal returned by the chip under test other than the operation completion signal, to the main control computer.

[0015] The main control computer determines, based on the received time difference or signal, whether the critical operation of the chip under test fails under each voltage disturbance and each frequency excitation signal.

[0016] Optionally, the system also includes a signal processing module, which processes the excitation signals of different frequencies from the external programmable logic chip and sends them to the chip under test, and processes the operation completion signal generated by the chip under test and sends it to the external programmable logic chip.

[0017] Optionally, the main control computer is equipped with testing software;

[0018] The test software sends control commands for excitation signals of different frequencies to an external programmable logic chip and control commands for voltage disturbances to a programmable power supply module, based on a set of pre-defined two-dimensional grid points.

[0019] Wherein, the horizontal axis of the two-dimensional grid point represents the voltage disturbance amplitude, and the vertical axis represents the frequency of the excitation signal.

[0020] Optionally, the external programmable logic chip integrates a time-to-digital converter module;

[0021] The time-to-digital converter module captures the edge T1 of the excitation signal and the edge T2 of the operation completion signal, and calculates the time difference between T1 and T2.

[0022] Optionally, if the main control computer determines that the time difference exceeds a specified time, it determines that the critical operation of the chip under test has timed out under the current voltage disturbance and the current frequency excitation signal; if it does not receive the operation completion signal or the chip under test returns a signal other than the operation completion signal, it determines that the critical operation of the chip under test has resulted in an execution error under the current voltage disturbance and the current frequency excitation signal.

[0023] Optionally, the main control computer statistically analyzes the failure type, failure frequency, and failure probability under each voltage disturbance and each frequency excitation signal; and plots a spectrum based on each voltage disturbance and each frequency excitation signal, as well as the failure probability, to fit the boundary line of the chip's functional safety operating area.

[0024] Optionally, the system may also include: an external high-precision stable clock, connected to an external programmable logic chip, used to provide time for the external programmable logic chip.

[0025] Secondly, this application provides a key operational testing method for automotive-grade chips, including:

[0026] The main control computer applies different voltage disturbances to the chip under test sequentially through a programmable power supply module; when each voltage disturbance is applied, the main control computer sends control commands of different frequency excitation signals to an external programmable logic chip.

[0027] In response to the control command, the external programmable logic chip sequentially sends excitation signals of different frequencies for key operations to the chip under test, and receives the operation completion signal returned by the chip under test.

[0028] The external programmable logic chip sends the time difference between the excitation signal and the operation completion signal for each frequency, or the operation completion signal not received, or signals other than the operation completion signal returned by the chip under test to the main control computer.

[0029] The main control computer determines, based on the received time difference or signal, whether the critical operation of the chip under test fails under each voltage disturbance and each frequency excitation signal.

[0030] Compared with the prior art, the beneficial effects of this application are as follows:

[0031] 1. A separate arrangement scheme is adopted. The chip under test is directly connected to the programmable power module to receive voltage disturbances, while the external programmable logic chip is independently placed in a low-noise environment. The operation completion signal emitted by the chip under test is collected through shielded leads, eliminating the interference of voltage disturbances on the signal timing accuracy and ensuring second-level measurement stability.

[0032] 2. The main control computer dynamically generates multi-dimensional disturbance waveforms such as overvoltage, undervoltage, and voltage drop through the bus with the programmable power module, and automatically traverses the two-dimensional grid points: voltage disturbance amplitude - frequency of excitation signal.

[0033] 3. Supports testing of various automotive-grade chip interfaces, possesses good compatibility and scalability, and is easy to promote and apply in the industry.

[0034] 4. This application supports the generation and analysis of automated failure maps, real-time determination of failure types (operation timeout or execution result error), automatic drawing of failure probability maps, and fitting of the boundary lines of the chip's functional safety working area; it can generate a visual failure analysis report that meets automotive-grade certification requirements with one click, replacing manual statistics and boundary calculation. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of a key operation testing system for automotive-grade chips provided in an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of the structure of another key operation testing system for automotive-grade chips provided in this application embodiment.

[0038] Figure 3 This is a schematic diagram of the two-dimensional spectrum provided in the embodiments of this application;

[0039] Figure 4 This is a flowchart of a key operation test method for an automotive-grade chip provided in an embodiment of this application. Detailed Implementation

[0040] The following description, in conjunction with the accompanying drawings, illustrates exemplary embodiments of this application, including various details to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0041] Figure 1 This is a schematic diagram of the structure of a key operation testing system for automotive-grade chips provided in an embodiment of this application. The system includes a main control computer, an external programmable logic chip, a programmable power supply module, and the chip under test; the modules and their connections are described below.

[0042] A master control computer is a core computer used for centralized management and control of other devices or subsystems, and is widely used in fields such as industrial automation, aerospace, traffic management, and energy systems. A master control computer can be an embedded master control computer, a server-level master control computer, or a real-time operating system master control computer. In this embodiment, the master control computer integrates testing software and has a first output interface and a second output interface. The first output interface is connected to a programmable power supply module, and the second output interface is connected to an external programmable logic chip.

[0043] A programmable power supply module is a power device whose output voltage, current, power, and other parameters can be controlled via software programming. In this embodiment, it primarily outputs voltage disturbances of varying amplitudes. The output terminal of the programmable power supply module is directly connected to the VDD (Voltage Drain-to-Drain) / GND (ground) pins of the chip under test (DUT), supporting dynamic adjustment of the voltage waveform. The VDD / GND pins are common power supply pins in electronic devices, used to provide power and ground to the chip. The VDD pin provides a positive voltage to the device, while the GND pin provides a reference potential, ensuring stable circuit operation. The output interface of the programmable power supply module is connected to the DUT to apply different voltage disturbances to it.

[0044] The chip under test is an automotive-grade chip, a semiconductor device specifically designed for automotive applications. This embodiment is applicable to interface testing of various automotive-grade chips, including but not limited to GPIO, SPI, I2C, LIN, CAN, and UART interfaces. GPIO (General Purpose Input / Output) is a general-purpose input / output interface used to expand the I / O ports of a microcontroller, providing additional control and monitoring functions. SPI (Serial Peripheral Interface) is a synchronous serial communication protocol, typically using four signal lines (clock, data output, data input, and chip select), supporting full-duplex communication and suitable for high-speed data transmission. I2C (Inter-Integrated Circuit) is a half-duplex synchronous communication protocol using two signal lines (clock and data lines), supporting multi-master and multi-slave communication, suitable for communication between low-speed devices. LIN (Local Interconnect Network) is a low-speed serial communication protocol typically used in automotive electronic systems as a lower-level network for the CAN bus, used for control and monitoring functions. CAN (Controller Area Network): A high-speed, reliable, and real-time serial communication protocol widely used in automotive, industrial control, and other fields, supporting multi-master device communication. UART (Universal Asynchronous Receiver / Transmitter): An asynchronous serial communication interface used to convert parallel data into serial data for transmission, suitable for long-distance communication.

[0045] An external programmable logic chip, such as a Field-Programmable Gate Array (FPGA), is a programmable logic device that allows users to configure its internal logic structure using a hardware description language (HDL) to implement customized digital circuit functions. Both the output and input interfaces of the external programmable logic chip are connected to the chip under test.

[0046] The main control computer applies different voltage disturbances to the chip under test (DUT) sequentially via a programmable power supply module. Optionally, these disturbances include normal voltage (rated value), overvoltage, undervoltage, and voltage dips. When applying each voltage disturbance, the main control computer sends control commands to an external programmable logic chip, specifying the frequency of the excitation signal. The excitation signal is an input signal actively applied to the DUT to stimulate its characteristics and acquire response data; its main functions include system identification, fault diagnosis, and performance verification. The excitation signal can be a deterministic signal (such as a step signal or a sinusoidal sweep signal), a random signal (such as white noise), or a transient signal (such as a pulse signal). This embodiment requires obtaining the frequency operating range of the excitation signal and selecting different frequency values ​​at equal intervals within this range to examine the DUT's response to excitation signals of different frequencies, such as high and low frequencies.

[0047] The external programmable logic chip responds to control commands based on excitation signals of different frequencies, parses the frequency of the excitation signal, sequentially sends excitation signals (Start signals) of different frequencies for key operations to the chip under test, and receives the operation completion signal (Stop signal) returned by the chip under test.

[0048] Specifically, for each combination of voltage disturbance (one voltage amplitude) and excitation signal at each frequency, an excitation signal is sent to the chip under test (DUT) to complete the test; then, another combination of excitation signals is sent, and the test is completed again, thus obtaining the test results for each combination of voltage disturbance and excitation signal at each frequency. Upon receiving the Start signal, the DUT triggers the execution of a critical operation. After completing the critical operation, it sends a Stop signal back to the external programmable logic chip. Normally, the DUT completes the critical operation within a specified time and immediately sends back a Stop signal. In some cases, the critical operation times out, resulting in a later Stop signal; in other cases, an internal error in the DUT may cause no Stop signal to be sent, or a signal other than a Stop signal may be sent, such as an error signal or an alarm signal.

[0049] An external programmable logic chip sends the time difference between the excitation signal and the operation completion signal for each frequency, or the signal that the operation completion signal is not received, or the signal returned by the chip under test other than the operation completion signal, to the main control computer.

[0050] The main control computer determines whether the critical operation of the chip under test (DUT) fails under each voltage disturbance and each frequency excitation signal based on the received time difference or signal. The types of functional failure include at least operation timeout and execution result error. Specifically, if the time difference exceeds a specified time, it is determined that the critical operation of the DUT has timed out under the current voltage disturbance and current frequency excitation signal; if no operation completion signal is received or the DUT returns a signal other than the operation completion signal, it is determined that the critical operation of the DUT has resulted in an execution result error under the current voltage disturbance and current frequency excitation signal.

[0051] Figure 2 This is a schematic diagram of the structure of another key operation testing system for automotive-grade chips provided in this application embodiment. Figure 1 The structure shown is based on the addition of a signal processing module and an external high-precision stable clock.

[0052] Specifically, the signal processing module has two sets of input / output interfaces. One set connects to the chip under test (DUT), and the other connects to the high-speed acquisition channel of an external programmable logic chip. The signal processing module receives excitation signals from the external programmable logic chip, processes them, and then sends them to the DUT. Furthermore, the signal processing module receives operation completion signals generated by the DUT, processes them, and then sends them to the external programmable logic chip. Signal processing includes, but is not limited to, filtering and level conversion. Signal filtering eliminates noise interference and improves signal integrity. Level conversion ensures voltage compatibility and improves the reliability of signal transmission.

[0053] An external high-precision stable clock can be a TCXO (Temperature Compensated Crystal Oscillator), which monitors and adjusts the frequency via sensors, requiring no preheating and suitable for applications with high startup time requirements; or an OCXO (Temperature Controlled Crystal Oscillator), which achieves extremely high frequency stability by placing the crystal in a temperature-controlled bath, suitable for scenarios with extremely high time accuracy requirements. The external high-precision stable clock connects to an external programmable logic chip to provide precise time, thereby accurately calculating the time difference between the excitation signal and the operation completion signal.

[0054] Optionally, the main control computer is equipped with testing software. Based on multiple pre-defined two-dimensional grid points, the testing software sends control commands for excitation signals of different frequencies to external programmable logic chips, and control commands for different voltage disturbances to programmable power supply modules. The horizontal axis of the two-dimensional grid points represents the voltage disturbance amplitude, and the vertical axis represents the frequency of the excitation signal. The testing software automatically traverses the two-dimensional grid points to achieve automatic testing under different operating conditions. If the chip under test or the testing function is changed, only the two-dimensional grid points and protocol configuration files in the testing software need to be updated; no changes to the hardware connections are required. Therefore, it is applicable to testing various chip types and various operating conditions.

[0055] Optionally, an external programmable logic chip integrates a time-to-digital converter (TDC) module. A TDC is a circuit used to convert time intervals into digital values, widely used in high-precision time measurement and synchronization control. Its core function is to accurately measure time intervals by detecting the edges (rising or falling edges) of signals and calculating their time differences. In this embodiment, the time-to-digital converter module captures the edge (rising or falling edge) T1 of the excitation signal, then starts timing based on an external high-precision stable clock, captures the edge (rising or falling edge) T2 of the operation completion signal, stops timing, and calculates the time difference between T1 and T2.

[0056] ΔT_ext = T2 - T1;

[0057] External programmable logic chips interact with the host computer in real time through appropriate interface protocols, exchanging data such as time zones and control commands. These interface protocols include, but are not limited to, UART, SPI, and Ethernet. UART stands for Universal Asynchronous Receiver / Transmitter, a serial asynchronous communication protocol commonly used for data transmission between devices. SPI stands for Serial Peripheral Interface, a synchronous serial communication protocol.

[0058] Optionally, the main control computer statistically analyzes the failure type, failure frequency, and failure probability under each voltage disturbance and each frequency excitation signal; based on each voltage disturbance and each frequency excitation signal, and the failure probability, it plots a spectrum and fits the boundary line of the chip's functional safety operating area. The failure probability can be calculated by dividing the number of failures over a period of time by the total number of two-dimensional test grid points. Figure 3This is a schematic diagram of a two-dimensional graph provided in an embodiment of this application. The horizontal axis represents voltage perturbation, the vertical axis represents the frequency of the excitation signal, and the color intensity indicates the probability of failure. The main control computer determines the boundary line of the chip's functionally safe operating area based on manually set failure criteria. For example... Figure 3 In the diagram, the redder the color, the higher the failure rate. The yellow ring represents the boundary line, and the area inside the yellow ring is the safe operating zone. Optionally, a three-dimensional map can be constructed based on different voltage disturbances, excitation signals of different frequencies, and failure probabilities to locate the voltage disturbances and excitation signals corresponding to the peak failure probability, ultimately outputting a stability assessment report that conforms to automotive-grade standards.

[0059] See Figure 4 This application also provides a critical operation testing method for automotive-grade chips, applicable to the critical operation testing system for automotive-grade chips provided in the above embodiments. The method includes:

[0060] S110. The main control computer applies different voltage disturbances to the chip under test sequentially through the programmable power supply module; when each voltage disturbance is applied, the main control computer sends control instructions for excitation signals of different frequencies to the external programmable logic chip.

[0061] S120. The external programmable logic chip responds to the control command by sequentially sending excitation signals of different frequencies for key operations to the chip under test, and receives the operation completion signal returned by the chip under test.

[0062] S130. The external programmable logic chip sends the time difference between the excitation signal and the operation completion signal for each frequency, or the signal that the operation completion signal is not received, or the signal returned by the chip under test other than the operation completion signal, to the main control computer.

[0063] S140. The main control computer determines, based on the received time difference or signal, whether the key operation of the chip under test fails under each voltage disturbance and each frequency excitation signal.

[0064] Compared with the prior art, the beneficial effects of this application are as follows:

[0065] 1. A separate arrangement scheme is adopted. The chip under test is directly connected to the programmable power module to receive voltage disturbances, while the external programmable logic chip is independently placed in a low-noise environment. The operation completion signal emitted by the chip under test is collected through shielded leads, eliminating the interference of voltage disturbances on the signal timing accuracy and ensuring second-level measurement stability.

[0066] 2. The main control computer dynamically generates multi-dimensional disturbance waveforms such as overvoltage, undervoltage, and voltage drop through the bus with the programmable power module, and automatically traverses the two-dimensional grid points: voltage disturbance amplitude - frequency of excitation signal.

[0067] 3. Supports testing of various automotive-grade chip interfaces, possesses good compatibility and scalability, and is easy to promote and apply in the industry.

[0068] 4. This application supports the generation and analysis of automated failure maps, real-time determination of failure types (operation timeout or execution result error), automatic drawing of failure probability maps, and fitting of the boundary lines of the chip's functional safety working area; it can generate a visual failure analysis report that meets automotive-grade certification requirements with one click, replacing manual statistics and boundary calculation.

[0069] 5. By scanning voltage disturbances and excitation signals, failure points are automatically marked, and two-dimensional / three-dimensional maps are generated to intuitively present the boundary of the chip's safe operating area.

[0070] 6. Picosecond-level high-precision measurement: The hardware timing method of using a time-to-digital converter module enables high-precision counting by an external counter under voltage disturbances.

[0071] 7. External independent verification capability: Avoids the susceptibility of internal timers and software timing to process / voltage / temperature drift, meeting the credibility requirements of automotive-grade certification;

[0072] 8. Multi-chip compatibility: Supports key operation tests of automotive-grade chips with different architectures and interface protocols, and has universality.

[0073] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired means, such as coaxial cable, optical fiber, digital subscriber line (DSL), or wireless means, such as infrared, wireless, microwave, etc. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium, or a semiconductor medium, etc. It is worth noting that the computer-readable storage medium mentioned in the embodiments of this application can be a non-volatile storage medium, in other words, it can be a non-transient storage medium.

[0074] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0075] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A key operation testing system for automotive-grade chips, characterized in that, include: The main control computer applies different voltage disturbances to the chip under test sequentially through a programmable power supply module; when each voltage disturbance is applied, the main control computer sends control commands of different frequencies of excitation signals to an external programmable logic chip. The main control computer is equipped with testing software. The test software sends control commands for excitation signals of different frequencies to an external programmable logic chip and control commands for voltage disturbances to a programmable power module, based on a set of pre-defined two-dimensional grid points. Wherein, the horizontal axis of the two-dimensional grid point represents the voltage disturbance amplitude, and the vertical axis represents the frequency of the excitation signal; The external programmable logic chip, in response to the control command, sequentially sends excitation signals of different frequencies for key operations to the chip under test, and receives the operation completion signal returned by the chip under test. The external programmable logic chip sends the time difference between the excitation signal and the operation completion signal for each frequency, or the signal that the operation completion signal is not received, or the signal returned by the chip under test other than the operation completion signal, to the main control computer. The main control computer determines, based on the received time difference or signal, whether the critical operation of the chip under test fails under each voltage disturbance and each frequency excitation signal.

2. The key operation testing system for automotive-grade chips according to claim 1, characterized in that, Also includes: The signal processing module processes the excitation signals of different frequencies from the external programmable logic chip and sends them to the chip under test. It also processes the operation completion signal generated by the chip under test and sends it to the external programmable logic chip.

3. The key operation testing system for automotive-grade chips according to claim 1, characterized in that, The external programmable logic chip integrates a time-to-digital converter module. The time-to-digital converter module captures the edge T1 of the excitation signal and the edge T2 of the operation completion signal, and calculates the time difference between T1 and T2.

4. The key operation testing system for automotive-grade chips according to claim 1, characterized in that, If the main control computer determines that the time difference exceeds a specified time, it determines that the critical operation of the chip under test has timed out under the current voltage disturbance and current frequency excitation signal; if it does not receive the operation completion signal or the chip under test returns a signal other than the operation completion signal, it determines that the critical operation of the chip under test has resulted in an execution error under the current voltage disturbance and current frequency excitation signal.

5. The key operation testing system for automotive-grade chips according to claim 4, characterized in that, The main control computer statistically analyzes the failure type, failure frequency, and failure probability under each voltage disturbance and each frequency excitation signal; it plots a spectrum based on each voltage disturbance and each frequency excitation signal, as well as the failure probability, and fits the boundary line of the chip's functional safety operating area.

6. The key operation testing system for automotive-grade chips according to claim 1, characterized in that, Also includes: An external high-precision stable clock is connected to an external programmable logic chip to provide time for the external programmable logic chip.

7. A key operation test method for automotive-grade chips, characterized in that, include: The main control computer applies different voltage disturbances to the chip under test sequentially through a programmable power supply module; when each voltage disturbance is applied, the main control computer sends control commands of different frequency excitation signals to an external programmable logic chip. The main control computer is equipped with testing software. The test software sends control commands for excitation signals of different frequencies to an external programmable logic chip and control commands for voltage disturbances to a programmable power module, based on a set of pre-defined two-dimensional grid points. Wherein, the horizontal axis of the two-dimensional grid point represents the voltage disturbance amplitude, and the vertical axis represents the frequency of the excitation signal; In response to the control command, the external programmable logic chip sequentially sends excitation signals of different frequencies for key operations to the chip under test, and receives the operation completion signal returned by the chip under test. The external programmable logic chip sends the time difference between the excitation signal and the operation completion signal for each frequency, or the operation completion signal not received, or signals other than the operation completion signal returned by the chip under test to the main control computer. The main control computer determines, based on the received time difference or signal, whether the critical operation of the chip under test fails under each voltage disturbance and each frequency excitation signal.

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