Memory order verification and acceleration method and system, computer device and storage medium

Abstract

The present application relates to a memory sequence verification and acceleration method, system, computer device and storage medium, the method of the present application is simplified to RISC-V processor core and system on chip, the scale of hardware simulation is reduced, and the simulation time of the verification case is shortened in the mode of converting the signal request sequence on the memory interface, at the same time, according to the FPGA platform, the top layer of the verification platform is compiled and tested, the effect of FPGA hardware acceleration can be maximized, so that the verification efficiency is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of processors, and particularly relates to a memory order verification and acceleration method and system, a computer device and a storage medium. BACKGROUND

[0002] At present, general multi-core processor structures are divided into three categories: homogeneous multi-core, homogeneous multi-light core and heterogeneous multi-core. The multi-core processor improves parallel processing and computing efficiency by integrating multiple cores, but faces key technical problems such as multi-core consistency and memory order. In the multi-core shared memory scenario, simultaneous access and modification of shared data by multiple cores can easily cause data consistency and memory order problems, resulting in data read-write order not meeting the program expectation.

[0003] In a reduced instruction set processor, the RISC-V (fifth generation reduced instruction set) manual specifies two memory order models: a weak consistency memory model (RVWMO) that only guarantees memory order in 13 specific cases, and the rest allows hardware to reorder to improve performance; and a total storage memory order model (RVTSO) that is more intuitive for software development. The difference in rules between different memory models brings challenges to the verification in the development of multi-core processors.

[0004] There are five general methods for multi-core memory order consistency and multi-core consistency verification:

[0005] 1. Simulation verification: simulate the running environment, execute business software and run performance tests (such as litmus tests) to verify data consistency.

[0006] 2. Random testing: randomly generate access operations to check data consistency based on simulation verification.

[0007] 3. Performance monitoring verification: monitor the running state of the processor to find potential consistency problems.

[0008] 4. Formal verification: model verification of the consistency protocol to ensure protocol correctness.

[0009] 5. FPGA emulator acceleration simulation: adapt the system-on-chip to the FPGA platform for acceleration, and compare the results with the software verification platform.

[0010] However, these methods have some shortcomings. Methods 1 and 2 rely on front-end simulation software, and the simulation time increases geometrically with the increase in the number of cores, and the complete verification time can be as long as several weeks or even months; method 3 relies on hardware performance counters, which cannot be read if the processor hangs due to consistency problems, and the software simulation takes a long time; method 4 solves the problem of slow simulation, but the modeling is difficult to completely match the hardware design; and method 5 accelerates the simulation and is close to the real hardware, but the software verification platform slows down the FPGA simulation acceleration effect.

[0011] Therefore, it is necessary to study a new memory order verification method for processor cores to solve the problems of long simulation time and weak acceleration effect. SUMMARY

[0012] The application provides a memory order verification and acceleration method, system and storage medium, and aims to solve the technical problems of long simulation time and weak acceleration effect of the existing RISC-V processor core consistency verification method.

[0013] To solve the above technical problems, in a first aspect, the application provides a memory order verification and acceleration method, comprising the following steps:

[0014] S101, simplifying a processor core to be subjected to memory order verification according to system functions to obtain a memory core module, connecting the memory core module with a network on chip to obtain a verification module, wherein the memory core module has a memory access interface;

[0015] S102, connecting a preset memory order verification component with the memory access interface of the verification module, connecting a preset monitoring component with the network on chip to obtain a verification platform top layer, the preset memory order verification component is used to send a signal request sequence containing a preset memory order verification case to the memory access interface, and the preset monitoring component is used to monitor a memory channel of the network on chip;

[0016] S103, compiling the verification platform top layer based on an FPGA platform to convert it into a runnable FPGA bit stream file, and simultaneously generating a memory order expected verification result corresponding to the verification module according to a memory order specification;

[0017] S104, burning the FPGA bit stream file into the FPGA platform for running, performing memory order verification testing, outputting a test waveform corresponding to the FPGA bit stream file through the FPGA platform, comparing the test waveform with the memory order expected verification result, and obtaining a processor core memory order verification result.

[0018] Further, the memory core module at least includes a memory unit and an LSU memory access unit of the processor core.

[0019] Further, the preset memory order verification component includes at least one of a memory access instruction generator, a reordering seed generator, a memory access emission scheduler, a memory access instruction submission verifier and a memory test result reporter.

[0020] Further, in step S101, the step of connecting the memory core module with the network on chip to obtain the verification module further comprises:

[0021] Connect a plurality of memory core modules corresponding to different processor cores to the same network on chip to obtain the to-be-verified module for memory order verification of a plurality of processor cores.

[0022] Further, the step S103 further includes:

[0023] The memory order result checking logic corresponding to the verification top-level platform is subjected to RTL file coding and syntax checking.

[0024] The memory order expected verification result is subjected to key waveform marking.

[0025] Further, the step S102 further includes:

[0026] Based on the preset memory order verification component, the preset memory order verification use case is converted into the signal request sequence.

[0027] Further, the preset memory order verification use case includes at least one of a sequential consistency verification use case, a data consistency verification use case and a network on chip delay characteristic verification use case.

[0028] In a second aspect, the application further provides a memory order verification and acceleration system, comprising:

[0029] A system building module is configured to simplify a processor core to be subjected to memory order verification according to system functions to obtain a memory core module, and connect the memory core module with a network on chip to obtain a to-be-verified module, wherein the memory core module has a memory access interface.

[0030] A use case conversion module is configured to connect a preset memory order verification component with the memory access interface of the to-be-verified module, and connect a preset monitoring component with the network on chip to obtain a verification platform top layer, wherein the preset memory order verification component is configured to send a signal request sequence containing a preset memory order verification use case to the memory access interface, and the preset monitoring component is configured to monitor a memory channel of the network on chip.

[0031] A compiling module is configured to compile the verification platform top layer based on an FPGA platform to convert it into a runnable FPGA bit stream file, and simultaneously generate a memory order expected verification result corresponding to the to-be-verified module according to a memory order specification.

[0032] A verification module is configured to burn the FPGA bit stream file into the FPGA platform for running and performing memory order verification testing, output a test waveform corresponding to the FPGA bit stream file through the FPGA platform, compare the test waveform with the memory order expected verification result, and obtain a processor core memory order verification result.

[0033] In a third aspect, the present application also provides a computer device, comprising a memory, a processor, and a memory order verification program of FPGA stored in the memory and executable on the processor, wherein the processor implements the steps of the memory order verification and acceleration method according to any one of the above embodiments when executing the memory order verification program of FPGA.

[0034] In a fourth aspect, the present application also provides a storage medium, wherein the storage medium stores a memory order verification program of FPGA, and the memory order verification program of FPGA implements the steps of the memory order verification and acceleration method according to any one of the above embodiments when executed by a processor.

[0035] The present application has the advantages that the memory order verification and acceleration method is proposed, the hardware simulation scale is reduced by appropriately simplifying the RISC-V processor core and the system on chip, the simulation time of the verification use case is shortened by converting the verification use case into a signal request sequence on the memory access interface, and the effect of FPGA hardware acceleration is maximized by compiling and testing the verification platform top layer according to the FPGA platform, so that the verification efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a step flowchart of the memory order verification and acceleration method provided by the embodiments of the present application;

[0037] Figure 2 is a hardware simplification diagram of a processor core provided by the embodiments of the present application;

[0038] Figure 3 is a memory core module diagram provided by the embodiments of the present application;

[0039] Figure 4 is a memory access interface diagram provided by the embodiments of the present application;

[0040] Figure 5 is a structure diagram of a preset memory order verification component and a preset monitoring component provided by the embodiments of the present application;

[0041] Figure 6 is a verification platform top layer diagram provided by the embodiments of the present application;

[0042] Figure 7 is a verification use case instruction conversion diagram provided by the embodiments of the present application;

[0043] Figure 8 is a data consistency verification data read-write diagram provided by the embodiments of the present application;

[0044] Figure 9is a structural schematic diagram of a memory order verification and acceleration system provided by an embodiment of the present application.

[0045] Figure 10 is a structural schematic diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0047] Please refer to Figure 1 , Figure 1 is a step flow schematic diagram of a memory order verification and acceleration method provided by an embodiment of the present application, and the memory order verification and acceleration method comprises the following steps:

[0048] S101, simplifying a processor core to be subjected to memory order verification according to system functions to obtain a memory core module, connecting the memory core module with a network on chip (NoC) to obtain a to-be-verified module, wherein the memory core module has a memory access interface.

[0049] The main purpose of step S101 is to reduce the scale of the hardware to be tested and build a multi-core processor system on chip. The main goal of the embodiment of the present application is to perform memory order verification, so in the process of hardware simplification, the memory core module at least includes a memory unit and an LSU memory access unit of the processor core. In a possible implementation manner, as shown in a processor core hardware simplification schematic diagram, Figure 2 all memory units (Cache, including L1D cache, L1I cache, L2 cache, etc.) in the processor core, LSU memory access units and related modules (such as memory management unit MMU, etc.) for memory access functions are extracted, and modules such as MMU, front-end module (FE), back-end module (BE) and vector module (VECTOR) in the processor are removed to form the memory core module.

[0050] In order to realize the verification of multiple processor cores, further, the step of connecting the memory core module with the network on chip to obtain the to-be-verified module in step S101 further comprises:

[0051] A plurality of memory core modules corresponding to different processor cores are connected to the same network on chip to obtain the to-be-verified module for memory order verification of multiple processor cores.

[0052] As shown in Figure 3 , Figure 3A memory core module corresponding to four processor cores is shown, wherein the DDR RAM component and the IO component are all component modules of the network on chip.

[0053] S102, the preset memory order verification component is connected with the memory access interface of the to-be-verified module, the preset monitoring component is connected with the network on chip, a verification platform top layer is obtained, the preset memory order verification component is used for sending a signal request sequence containing a preset memory order verification use case to the memory access interface, and the preset monitoring component is used for monitoring a memory channel of the network on chip.

[0054] In the embodiment of the application, for the designed memory access interface, as shown in Figure 4 , according to the interface function, it can be divided into a memory instruction request interface and a memory submission interface, wherein, as shown in Figure 4 , the data input channel interface, the data response channel interface, the write-back response channel interface and the request channel interface belong to the memory instruction request interface, and the cache interaction interface and the memory management module interface belong to the memory submission interface.

[0055] The preset memory order verification component includes at least one of a memory instruction generator, an out-of-order seed generator, a memory launch scheduler, a memory instruction submission verifier and a memory test result reporter. As shown in Figure 5 , Figure 5 is a structure diagram of the preset memory order verification component and the preset monitoring component provided by the embodiment of the application, in the implementation process, the preset memory order verification component is connected with the memory access interface of the to-be-verified module, specifically, various components are connected with their corresponding function interfaces (such as the data input channel interface, the data response channel interface, the write-back response channel interface and the like as shown in Figure 4 ), and when the preset monitoring component is connected with the network on chip, the AXI4 interface of the network on chip is used.

[0056] Further, step S102 further includes:

[0057] Based on the preset memory order verification component, the preset memory order verification use case is converted into the signal request sequence. The preset memory order verification use case includes at least one of a sequential consistency verification use case, a data consistency verification use case and a network on chip delay characteristic verification use case. As shown in Figure 6 , Figure 6 is a schematic diagram of the verification platform top layer provided by the embodiment of the application.

[0058] The preset memory order verification case mentioned in the embodiment of the present application refers to a program and input and output logic for verifying specific functions of a processor core. For example, a classical multi-core sequential consistency verification logic is performed for a dual-processor core, mainly testing characteristics such as a read buffer (Load Buffer), a write buffer (Store Buffer), message passing (Message Pass), independent write and independent read (Independent Write Independent Read), and a memory barrier instruction (Fence). This classical verification logic can perform memory consistency operations on a specified multi-core on a Linux operating system. However, in digital front-end simulation, the simulation of the Linux operating system takes a long time. In order to reduce the simulation time and speed up the verification of multi-core memory consistency, the embodiment of the present application converts these classical multi-core sequential consistency verification cases into a signal request sequence for an access interface of a to-be-verified module. As shown in Figure 7 For example, a Load, Store, or Fence instruction in the verification logic can be converted into a valid request on an access instruction request interface channel or valid data on an access submission interface.

[0059] However, as the design is continuously iterated and the scale is continuously increased, the use of classical cases alone cannot cover the verification of multi-core memory order of a processor system with more cores. Based on the design of the embodiment of the present application, a multi-core memory order verification case that conforms to the verification object can be derived, and related instruction operations can be converted into a signal request sequence.

[0060] S103, compiling the verification platform top layer based on an FPGA platform, converting it into a runnable FPGA bit stream file, and simultaneously generating a memory order expected verification result corresponding to the to-be-verified module according to a memory order specification.

[0061] The main purpose of step S103 is to generate memory order result checking logic corresponding to the verification top-level platform according to a specific memory order specification based on a formal memory order verification tool, and to code the memory order result checking logic into an RTL (Register Transfer Level) file and fix it to an FPGA (Field-Programmable Gate Array) platform. Further, step S103 further includes:

[0062] performing RTL file coding and syntax checking on the memory order result checking logic corresponding to the verification top-level platform;

[0063] performing key waveform marking on the memory order expected verification result.

[0064] The memory order result checking logic is used to monitor whether the memory order of the top layer of the verification platform conforms to the specification, and in the implementation process, this step is an important preparation work. For the processor core structure designed according to the specification, the correctness of the memory order is known, and therefore, the related memory order result checking logic can be derived through the formal memory order verification tool, the memory order result checking logic is converted into a hardware model of System: Verilog (a hardware description language) using a synthesizable grammar, and the multi-core memory order can be verified through the hardware model in an online and real-time manner whether it conforms to the rules, thereby improving the verification efficiency.

[0065] Further, the marking of the key waveforms facilitates subsequent waveform comparison and realizes more detailed functional verification. For example, the embodiment of the application provides a Litmus basic use case conversion schematic table as shown in Table 1, which illustrates the conversion mode of the Litmus basic use case and the checkpoint of the key waveform. As can be seen, after the verification use case is converted into a signal request queue, the waveforms have relatively obvious numerical characteristics, and therefore, the correct situation of the corresponding memory order can be quickly compared through the marking of the key waveforms.

[0066] Table 1: Litmus basic use case conversion schematic table

[0067]

[0068] Further, according to the obtained memory order expected verification result, the top layer of the verification platform can also be modified and optimized as needed in step S103, so that the resources consumed by the top layer of the verification platform are reduced, and the running clock thereof is improved, thereby reducing the design cycle.

[0069] S104, burn the FPGA bitstream file into the FPGA platform for running, and perform memory order verification test, output the test waveform corresponding to the FPGA bitstream file through the FPGA platform, compare the test waveform with the memory order expected verification result, and obtain the processor core memory order verification result.

[0070] The main purpose of the embodiment of the application for burning the FPGA bitstream file into the FPGA platform for running is to realize fast hardware simulation based on the characteristics of the FPGA. As mentioned in the above embodiment, through the pre-marked key waveforms, the differences from the test waveforms can be quickly analyzed, and the corresponding processor core memory order verification result is obtained.

[0071] For the convenience of understanding, for the verification of the data consistency of multiple processor cores, the waveform comparison method can refer to the data consistency verification data read-write schematic diagram shown in Figure 7 Figure 8 ​Fig. 2A shows the interaction of four cores sending write byte requests one time each, one core reading a byte request in sequence, Figure 8 Fig. 2B shows the interaction of eight cores sending write byte requests one time each, one core sending read byte requests two times in disorder. It can be seen that the verification of data consistency strictly regulates the data transmission order of different processor cores, so the design of the verification use case enables the test waveforms output by the FPGA platform to correspond to the FPGA bitstream file, and facilitates comparison.

[0072] For the on-chip network delay characteristic verification use case, it is mainly achieved by designing large flow use cases, boundary address use cases, hollow address use cases, etc., and judging the corresponding system response time from the test waveforms.

[0073] It can be understood that, compared with the existing memory order verification method of pure software simulation or FPGA platform simulation combined with software, the simulation based on the FPGA platform, the hardware language verification according to the syntax checking result, and the result comparison based on the output waveform have faster running speed and improved accuracy.

[0074] The present application has the beneficial effects that a memory order verification and acceleration method is proposed, which reduces the hardware simulation scale by appropriately simplifying the RISC-V processor core and the system on chip, shortens the simulation time of the verification use case by converting the verification use case into a signal request sequence on the memory interface, and maximizes the effect of FPGA hardware acceleration by compiling and testing the verification platform top layer based on the FPGA platform, so that the verification efficiency is improved.

[0075] The embodiment of the present application also provides a memory order verification and acceleration system 200, please refer to Figure 9 , Figure 9 Fig. 3 is a structural schematic diagram of the memory order verification and acceleration system provided by the embodiment of the present application, which comprises:

[0076] The system building module 201 is used for simplifying the processor core to be verified for memory order according to system functions to obtain a memory core module, connecting the memory core module with an on-chip network to obtain a to-be-verified module, wherein the memory core module has a memory interface;

[0077] The use case conversion module 202 is used for connecting a preset memory order verification component with the memory interface of the to-be-verified module, connecting a preset monitoring component with the on-chip network to obtain a verification platform top layer, the preset memory order verification component is used for sending a signal request sequence containing a preset memory order verification use case to the memory interface, and the preset monitoring component is used for monitoring a memory channel of the on-chip network.

[0078] The compiling module 203 is configured to compile the verification platform top layer based on the FPGA platform, convert the verification platform top layer into a runnable FPGA bit stream file, and generate a memory order expected verification result corresponding to the to-be-verified module according to a memory order specification.

[0079] The verification module 204 is configured to burn the FPGA bit stream file into the FPGA platform for running, perform a memory order verification test, output a test waveform corresponding to the FPGA bit stream file through the FPGA platform, compare the test waveform with the memory order expected verification result, and obtain a processor core memory order verification result.

[0080] The memory order verification and acceleration system 200 can implement the steps in the memory order verification and acceleration method in the above-described embodiments, and can achieve the same technical effects. Refer to the descriptions in the above-described embodiments, which will not be repeated here.

[0081] The embodiment of the present application further provides a computer device, please refer to Figure 10 , Figure 10 is a structural schematic diagram of the computer device provided by the embodiment of the present application, the computer device 300 comprises a memory 302, a processor 301 and a memory order verification program of FPGA stored in the memory 302 and capable of running on the processor 301.

[0082] The processor 301 invokes the memory order verification program of FPGA stored in the memory 302, and executes the steps in the memory order verification and acceleration method provided by the embodiment of the present application. Please refer to Figure 1 , which specifically comprises the following steps:

[0083] S101, simplifying a processor core to be subjected to memory order verification according to system functions to obtain a memory core module, connecting the memory core module with a network on chip to obtain a to-be-verified module, wherein the memory core module has a memory access interface.

[0084] The memory core module at least comprises a memory unit and an LSU memory access unit of the processor core.

[0085] Further, in step S101, the step of connecting the memory core module with the network on chip to obtain the to-be-verified module further comprises:

[0086] Connecting a plurality of memory core modules corresponding to different processor cores to the same network on chip to obtain the to-be-verified module for memory order verification of multiple processor cores.

[0087] S102, connect a preset memory order verification component with the memory access interface of the to-be-verified module, and connect a preset monitoring component with the network on a chip, to obtain a verification platform top layer, the preset memory order verification component is configured to send a signal request sequence containing a preset memory order verification case to the memory access interface, and the preset monitoring component is configured to monitor a memory channel of the network on a chip.

[0088] The preset memory order verification component comprises at least one of a memory access instruction generator, a reordering seed generator, a memory access launch scheduler, a memory access instruction submission verifier and a memory test result reporter.

[0089] Further, step S102 further comprises:

[0090] Based on the preset memory order verification component, the preset memory order verification case is converted into the signal request sequence. The preset memory order verification case comprises at least one of a sequential consistency verification case, a data consistency verification case and a network on a chip delay characteristic verification case.

[0091] S103, based on the FPGA platform, the verification platform top layer is compiled to be converted into a runnable FPGA bit stream file, and meanwhile, a memory order expected verification result corresponding to the to-be-verified module is generated according to a memory order specification.

[0092] Further, step S103 further comprises:

[0093] The memory order result checking logic corresponding to the verification top platform is subjected to RTL file coding and syntax checking;

[0094] The memory order expected verification result is subjected to key waveform marking.

[0095] S104, the FPGA bit stream file is burned into the FPGA platform to run, and a memory order verification test is performed, a test waveform corresponding to the FPGA bit stream file is output by the FPGA platform, the test waveform is compared with the memory order expected verification result, and a processor core memory order verification result is obtained.

[0096] The computer device 300 provided by the embodiment of the application can implement the steps in the memory order verification and acceleration method in the above-described embodiment, and can achieve the same technical effects. Refer to the description in the above-described embodiment, which will not be repeated here.

[0097] The embodiment of the application further provides a storage medium, wherein the storage medium stores a memory order verification program of an FPGA, and the memory order verification program of the FPGA, when executed by a processor, implements each process and step in the memory order verification and acceleration method provided by the embodiment of the application and can achieve the same technical effects. To avoid repetition, the same will not be repeated here.

[0098] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a memory sequence verification program of an FPGA instructing related hardware (which can be a mobile phone, a computer, a server, an air conditioner, a network device, etc.) to complete. The program can be stored in a computer readable storage medium, and when the program is executed, the processes of the above-mentioned embodiment methods can be included. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM), etc.

[0099] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusions, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or include elements inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0100] The embodiments of the present application are described above in conjunction with the drawings, and the disclosed are only the preferred embodiments of the present application, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the purpose of the present application and the scope protected by the claims under the inspiration of the present application, and all the changes belong to the protection of the present application.

Claims

1. A memory order verification and acceleration method, characterized in that, The method comprises the following steps: S101, simplifying a processor core to be subjected to memory order verification according to system functions to obtain a memory core module, connecting the memory core module with a network on chip to obtain a verification module, wherein the memory core module has a memory access interface, and the memory core module at least comprises a memory unit and an LSU memory access unit of the processor core; S102, connecting a preset memory order verification component with the memory access interface of the verification module, connecting a preset monitoring component with the network on chip to obtain a verification platform top layer, the preset memory order verification component is configured to send a signal request sequence comprising a preset memory order verification case to the memory access interface, and the preset monitoring component is configured to monitor a memory channel of the network on chip; S103, compiling the verification platform top layer based on an FPGA platform to convert it into a runnable FPGA bit stream file, and simultaneously generating a memory order expected verification result corresponding to the verification module according to a memory order specification; S104, burning the FPGA bit stream file into the FPGA platform for running and performing memory order verification testing, outputting a test waveform corresponding to the FPGA bit stream file through the FPGA platform, comparing the test waveform with the memory order expected verification result, and obtaining a processor core memory order verification result.

2. The memory order verification and acceleration method of claim 1, wherein, The preset memory order verification component comprises at least one of a memory access instruction generator, a reordering seed generator, a memory access emission scheduler, a memory access instruction submission verifier and a memory test result reporter.

3. The memory order verification and acceleration method of claim 1, wherein, In step S101, the step of connecting the memory core module with the network on chip to obtain the verification module further comprises: connecting a plurality of memory core modules corresponding to different processor cores to the same network on chip to obtain the verification module for memory order verification of multiple processor cores.

4. The memory order verification and acceleration method of claim 1, wherein, Step S103 further comprises: performing RTL file coding and syntax checking on memory order result checking logic corresponding to the verification platform top layer; performing key waveform marking on the memory order expected verification result.

5. The memory order verification and acceleration method of claim 1, wherein, Step S102 further comprises: based on the preset memory order verification component, converting the preset memory order verification case into the signal request sequence.

6. The memory order verification and acceleration method of claim 5, wherein, The preset memory order verification case comprises at least one of a sequential consistency verification case, a data consistency verification case and a network on chip delay characteristic verification case.

7. A memory order verification and acceleration system, comprising: comprises: a system building module configured to simplify a processor core to be subjected to memory order verification according to system functions to obtain a memory core module, connect the memory core module with a network on chip to obtain a verification module, wherein the memory core module has a memory access interface, and the memory core module at least comprises a memory unit and an LSU memory access unit of the processor core; A use case conversion module is configured to connect a preset memory order verification component with the memory access interface of the to-be-verified module and connect a preset monitoring component with the network on chip, to obtain a verification platform top layer, the preset memory order verification component is configured to send a signal request sequence containing a preset memory order verification use case to the memory access interface, and the preset monitoring component is configured to monitor a memory channel of the network on chip; A compiling module is configured to compile the verification platform top layer based on an FPGA platform, to convert it into a runnable FPGA bit stream file, and to generate a memory order expected verification result corresponding to the to-be-verified module according to a memory order specification; A verification module is configured to burn the FPGA bit stream file into the FPGA platform for running, to perform a memory order verification test, to output a test waveform corresponding to the FPGA bit stream file through the FPGA platform, to compare the test waveform with the memory order expected verification result, and to obtain a processor core memory order verification result.

8. A computer device, comprising: Comprise: a memory, a processor, and a memory order verification program of an FPGA stored on the memory and executable on the processor, and the processor implements the steps in the memory order verification and acceleration method according to any one of claims 1-6 when executing the memory order verification program of the FPGA.

9. A storage medium, characterized by The storage medium stores a memory order verification program of an FPGA, and the memory order verification program of the FPGA implements the steps in the memory order verification and acceleration method according to any one of claims 1-6 when executed by a processor.

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