RISC-V vector processor and memory access method
By introducing scalar cache, vector cache and data synchronization units into the RISC-V vector processor, the problems of insufficient bus bandwidth and cache consistency conflicts are solved, the memory access process is optimized, and the processor efficiency and performance are improved.
Patent Information
- Application Number
- CN202510582934.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-07
- Publication Date
- 2025-08-22
AI Technical Summary
The existing RISC-V vector processors cause data hunger and increased delay when the bus bandwidth is insufficient, and there is a conflict between the memory access operations of the scalar and vector processing modules, reducing processor efficiency.
Scalar cache unit, vector cache unit and data synchronization unit are introduced to maintain cache consistency through the data synchronization mechanism, reduce the number of bus accesses and delays, and optimize the memory access process.
Improves processor operation efficiency and overall performance, especially in parallel computing and data-intensive tasks, reducing cache coherence conflicts and bus latency.
Smart Images
Figure CN120523748A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and in particular to a RISC-V vector processor and a memory access method. Background Art
[0002] The RISC-V vector processor is a processor based on the RISC-V instruction set architecture (ISA) and is specifically designed to efficiently handle vector operations. RISC-V vector processors can process multiple data elements in parallel at once, making them suitable for applications requiring large-scale data processing, such as scientific computing, image processing, and machine learning.
[0003] Currently, the existing RISC-V vector processor architecture is as follows Figure 1 As shown in Figure 2, the architecture consists of a RISC-V scalar processing module with an instruction fetch unit and a scalar memory access unit, and a vector processing module with a vector memory access unit. The RISC-V scalar processing module is the processing unit that handles ordinary scalar requests. The instruction fetch unit is responsible for reading requests from memory, and the scalar memory access unit is responsible for accessing the storage unit for scalar data. The RISC-V vector processing module is the processing unit that handles vector requests, and the vector memory access unit is responsible for accessing the storage unit for vector data. The bus is the channel connecting these units, used to transmit data and requests.
[0004] The architecture's workflow is as follows: When processing a scalar request, the scalar processing module fetches instructions via the bus, decodes them, and then executes the request. When processing a vector request, the scalar processing module fetches instructions via the bus, decodes them, and sends the vector request and required operands to the vector processing module, which then executes the request. Furthermore, the scalar and vector processing modules in this architecture can operate simultaneously.
[0005] Figure 2 This is the architecture of the vector memory access unit provided in this background technology. The vector memory access unit is responsible for processing bus access requests from the vector processing module and includes a memory access queue, a write queue, a read queue, and an address queue. The memory access queue is used to record processor bus access requests, including load (read) and store (write) operations; the write queue is used to record requests and data written to the bus; the read queue is used to record requests to read from the bus; and the address queue is used to record the processor's access address to the bus.
[0006] comprehensive Figure 1 and Figure 2 , the workflow of the vector memory access unit architecture is:
[0007] 1. The vector execution unit sends a memory access request to the vector memory access unit;
[0008] 2. The vector memory access unit receives the request and records it in the memory access queue, address queue, read queue, and write queue in sequence.
[0009] 3. The memory access queue initiates requests to the bus in sequence.
[0010] However, because vector processors need to read large amounts of data from the bus for parallel processing, they place high demands on bus bandwidth. If the bus lacks sufficient bandwidth, the vector processor may suffer from data starvation and be unable to fully utilize its parallel processing capabilities. Therefore, existing architectures typically design high-bit-width buses to provide sufficient data throughput. However, high-bit-width buses increase bus latency and reduce processor speed.
[0011] At the same time, vector processors process multiple data elements at once (for example, a vector register can store multiple integers or floating-point numbers). This means that the vector memory access unit needs to access multiple sets of data for each request, increasing the number of memory access requests. The data throughput of the vector memory access unit of the vector processing module is much higher than that of the scalar processing module. In this scenario, the short-term bus throughput increases, the bus latency increases, and performance degrades.
[0012] Finally, the instruction fetch and scalar memory access operations of the scalar processing module conflict with the memory access operations of the vector processing module. When the vector and scalar processing modules access the bus simultaneously, data consistency conflicts may occur. For example, when a scalar processing module with a cache stores data to the bus, this data is temporarily stored in the scalar cache, and the vector processing module cannot access this recently stored data. These situations can cause the scalar processing module, the vector processing module, or even both, to enter a stalled state, reducing processor efficiency. Summary of the Invention
[0013] The object of the present invention is to provide a RISC-V vector processor and a memory access method to solve at least one technical problem raised in the background technology.
[0014] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a RISC-V vector processor, comprising a RISC-V scalar processing module having an instruction fetch unit and a scalar memory access unit and a RISC-V vector processing module having a vector memory access unit, and further comprising: a scalar cache unit, a vector cache unit and a data synchronization unit;
[0015] The scalar memory access unit is connected to the bus through the scalar cache unit;
[0016] The vector memory access unit is connected to the bus through the vector cache unit;
[0017] The scalar cache unit and the vector cache unit are both connected to the data synchronization unit; wherein,
[0018] The data synchronization unit is configured to update the shared data in the scalar cache unit or the vector cache unit according to a preset strategy, so that the shared data in the scalar cache unit and the shared data in the vector cache unit are updated synchronously, and the shared data is data shared between the scalar cache unit and the vector cache unit.
[0019] Furthermore, the data synchronization unit updates the shared data in the scalar cache unit or the vector cache unit according to a preset strategy, including:
[0020] If the shared data in the scalar cache unit is changed, the data synchronization unit sends the changed data to the vector cache unit to update the shared data in the vector cache unit;
[0021] If the shared data in the vector cache unit is changed, the data synchronization unit sends the changed data to the scalar cache unit to update the shared data in the scalar cache unit.
[0022] Furthermore, the situation where the shared data in the scalar cache unit is changed includes:
[0023] When executing a scalar memory access request, shared data in the scalar cache unit is modified;
[0024] When the RISC-V scalar processing module stores data in the scalar cache unit, the data belongs to the shared data in the vector cache unit.
[0025] Furthermore, the data synchronization unit determines that the data belongs to the shared data in the vector cache unit, including:
[0026] The data synchronization unit queries the vector cache unit whether the data belongs to a shared address segment, and if so, determines that the data belongs to shared data in the vector cache unit.
[0027] Furthermore, the data synchronization unit includes: a query queue subunit, an address queue subunit, a data queue subunit, a query interface subunit, a vector cache update subunit, and a scalar cache update subunit; the query queue subunit and the address queue subunit are connected to the query interface subunit, the query interface subunit is connected to the scalar cache update subunit and the vector cache update subunit; the data queue subunit is connected to the vector cache update subunit; wherein,
[0028] The query queue subunit is used to record the number of the cache scalar memory access request and storage load information, and initiate a query request to the vector cache unit;
[0029] The address queue subunit is used to record the address of the cache scalar memory access request;
[0030] The data queue subunit is used to record data of cache scalar memory access requests;
[0031] The query interface subunit is used to convert the information of the address queue of the query queue into an interface signal of the query vector cache and initiate a query request;
[0032] The vector cache update subunit is used to store data of a scalar memory access request and initiate a vector cache update request to the vector cache unit when the vector cache unit hits data;
[0033] The scalar cache update subunit is used to save the data returned when the vector cache unit hits, and initiate a scalar cache update request to the scalar cache unit.
[0034] Furthermore, the situation where the shared data in the vector cache unit is changed includes:
[0035] When executing a vector memory access request, shared data in the vector cache unit is modified.
[0036] In a second aspect, the present invention further provides a RISC-V vector processor memory access method, applicable to the RISC-V vector processor as described in the first aspect, the method comprising:
[0037] If the shared data in the scalar cache unit is changed, the data synchronization unit sends the changed data to the vector cache unit to update the shared data in the vector cache unit;
[0038] If the shared data in the vector cache unit is changed, the data synchronization unit sends the changed data to the scalar cache unit to update the shared data in the scalar cache unit;
[0039] The shared data is data shared between the scalar cache unit and the vector cache unit.
[0040] Optionally, the situation where the shared data in the scalar cache unit is changed includes:
[0041] When executing a scalar memory access request, shared data in the scalar cache unit is modified;
[0042] When the RISC-V scalar processing module stores data in the scalar cache unit, the data belongs to the shared data in the vector cache unit.
[0043] Optionally, the data synchronization unit determines that the data belongs to shared data in the vector cache unit, including:
[0044] The data synchronization unit queries the vector cache unit whether the data belongs to a shared address segment, and if so, determines that the data belongs to shared data in the vector cache unit.
[0045] Optionally, the situation where the shared data in the vector cache unit is changed includes:
[0046] When executing a vector memory access request, shared data in the vector cache unit is modified.
[0047] Technical effects:
[0048] (1) By adding a data synchronization unit to maintain the data consistency of the scalar cache and the vector cache, the data synchronization process is simplified, the processor stall caused by cache data consistency conflicts is reduced, and the processor operation efficiency is improved.
[0049] (2) Through the coordination of the vector cache unit, scalar cache unit, and data synchronization unit, and through effective data transfer and cache management mechanisms, the overall performance of the RISC-V vector processor system is significantly improved. In particular, the memory access process of the RISC-V vector processor is optimized, which significantly improves the processing efficiency of the RISC-V vector processor, especially in parallel computing and data-intensive tasks.
[0050] (3) By adding a vector cache unit, the number of times the RISC-V vector processing module accesses the bus is reduced, alleviating the RISC-V vector processing module's requirements for bus bandwidth and latency. At the same time, the vector cache unit reduces the latency of the RISC-V vector processing module accessing data in the main memory, reduces the latency of data transmission, and improves the efficiency of data transmission in the RISC-V vector processing module. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] Figure 1 The existing RISC-V vector processor architecture diagram provided as background technology for this application;
[0052] Figure 2 The architecture diagram of the vector memory access unit provided as background technology of this application;
[0053] Figure 3 An architectural diagram of the RISC-V vector processor provided in an embodiment of the present application;
[0054] Figure 4 This is an architectural diagram of a data synchronization unit provided in an embodiment of the present application;
[0055] Figure 5 A flowchart of a memory access method for a RISC-V vector processor provided in an embodiment of the present application;
[0056] Figure 6 A scalar memory access flow chart of the RISC-V vector processor provided in an embodiment of the present application;
[0057] Figure 7 A vector memory access flowchart for the RISC-V vector processor provided in an embodiment of the present application. DETAILED DESCRIPTION
[0058] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.
[0059] like Figure 3 As shown, an embodiment of the present invention provides an architectural diagram of a RISC-V vector processor. The RISC-V vector processor includes a RISC-V scalar processing module having an instruction fetch unit and a scalar memory access unit, a RISC-V vector processing module having a vector memory access unit, a scalar cache unit, a vector cache unit, and a data synchronization unit. The scalar memory access unit is connected to a bus via the scalar cache unit; the vector memory access unit is connected to the bus via the vector cache unit; and both the scalar cache unit and the vector cache unit are connected to the data synchronization unit.
[0060] The scalar cache unit and the vector cache unit cache shared data, and the shared data is data shared between the scalar cache unit and the vector cache unit.
[0061] In this embodiment, the main functions of the RISC-V scalar processing module are to read instructions from the bus, execute scalar memory access instructions, send vector instructions and data required for the instructions to the RISC-V vector processing module, and receive the execution results of the RISC-V vector processing module.
[0062] The main function of the RISC-V vector processing module is to execute vector non-memory access instructions and send vector memory access instructions to the vector memory access unit.
[0063] The scalar cache unit is a private cache for the RISC-V scalar processing module that is readable, writable, and updatable. It is used to accelerate data exchange between the RISC-V scalar processing module and the bus. Unlike existing caches, the scalar cache unit in this embodiment has a data synchronization unit interface to maintain the consistency of shared data between the vector cache unit and the scalar cache unit.
[0064] The vector cache unit is a private, readable, writable, and updatable cache for the RISC-V vector processing module, used to accelerate data exchange between the RISC-V vector processing module and the bus. Unlike existing caches, the vector cache unit in this embodiment includes a data synchronization unit interface to maintain the consistency of shared data between the vector cache unit and the scalar cache unit.
[0065] The data synchronization unit is configured to update the shared data in the scalar cache unit or the vector cache unit according to a preset strategy, so that the shared data in the scalar cache unit and the shared data in the vector cache unit are updated synchronously, specifically including:
[0066] If the shared data in the scalar cache unit is changed, the data synchronization unit sends the changed data to the vector cache unit to update the shared data in the vector cache unit;
[0067] If the shared data in the vector cache unit is changed, the data synchronization unit sends the changed data to the scalar cache unit to update the shared data in the scalar cache unit.
[0068] Specifically, the situations in which the shared data in the scalar cache unit is changed include the following two situations:
[0069] The first type: when executing a scalar memory access request, the shared data in the scalar cache unit is modified.
[0070] Specifically, when executing a scalar memory access request, if shared data in the scalar cache unit is modified, the address of the scalar memory access request and the modified data are sent to the vector cache unit to update invalid data in the vector cache unit.
[0071] The second type: when the RISC-V scalar processing module stores data in the scalar cache unit, the data belongs to the shared data in the vector cache unit.
[0072] Specifically, when the RISC-V scalar processing module stores data in the scalar cache unit, the data synchronization unit will query the vector cache unit whether the data belongs to the shared address segment. If so, it will determine that the data belongs to the shared data in the vector cache unit and control the vector cache to update the invalid data.
[0073] In this embodiment, the situation where the shared data in the vector cache unit is changed includes: the shared data in the vector cache unit is modified when a vector memory access request is executed.
[0074] Specifically, when executing a vector memory access request, if shared data in the vector cache unit is modified, the address of the vector memory access request and the modified data are sent to the scalar cache unit to update invalid data in the scalar cache unit.
[0075] The architecture diagram of the data synchronization unit provided in this embodiment is as follows Figure 4 As shown, the data synchronization unit includes: a query queue subunit, an address queue subunit, a data queue subunit, a query interface subunit, a vector cache update subunit and a scalar cache update subunit; the query queue subunit and the address queue subunit are connected to the query interface subunit, the query interface subunit is connected to the scalar cache update subunit and the vector cache update subunit; the data queue subunit is connected to the vector cache update subunit.
[0076] Wherein, the query queue subunit is used to record the number and storage load information of the cache scalar memory access request, and initiate a query request to the vector cache unit. The address queue subunit is used to record the address of the cache scalar memory access request. The data queue subunit is used to record the data of the cache scalar memory access request. The query interface subunit is used to convert the information of the address queue of the query queue into an interface signal for querying the vector cache, and initiate a query request. The vector cache update subunit is used to save the data of the scalar memory access request, and initiate an update vector cache request to the vector cache unit when the vector cache unit hits the data. The scalar cache update subunit is used to save the data returned when the vector access hits when the vector cache unit hits, and initiate an update scalar cache request to the scalar cache unit.
[0077] The data synchronization unit implements data transfer between the scalar cache unit and the vector cache unit, as well as consistency management between the scalar cache and the vector cache. After receiving a memory access request from the scalar processing module, the data synchronization unit records the address in the address queue subunit and the data in the data queue subunit. The query queue subunit records the request number and queries the vector cache unit in sequence. When the vector cache is hit, if the request is a scalar storage instruction, the data of the scalar memory access request is saved and the corresponding cache line in the vector cache unit is updated; if the request is a scalar load instruction, the data returned when the vector cache hits is saved and the corresponding cache line in the scalar cache unit is updated. When the vector cache is not hit, it indicates that the data does not belong to the data shared by the vector cache unit and the scalar cache unit, and there is no need to update the vector cache or the scalar cache.
[0078] Based on the same inventive concept, in the second aspect, Figure 5 As shown, an embodiment of the present invention further provides a flowchart of a memory access method for a RISC-V vector processor, which is applicable to the RISC-V vector processor as described in the first aspect. The method comprises the following steps:
[0079] Step S110 : If the shared data in the scalar cache unit is changed, the data synchronization unit sends the changed data to the vector cache unit to update the shared data in the vector cache unit.
[0080] Specifically, the situations in which the shared data in the scalar cache unit is changed include the following two situations:
[0081] The first type: when executing a scalar memory access request, the shared data in the scalar cache unit is modified.
[0082] Specifically, when executing a scalar memory access request, if shared data in the scalar cache unit is modified, the address of the scalar memory access request and the modified data are sent to the vector cache unit to update invalid data in the vector cache unit.
[0083] The second type: when the RISC-V scalar processing module stores data in the scalar cache unit, the data belongs to the shared data in the vector cache unit.
[0084] Specifically, when the RISC-V scalar processing module stores data in the scalar cache unit, the data synchronization unit will query the vector cache unit whether the data belongs to the shared address segment. If so, it will determine that the data belongs to the shared data in the vector cache unit and control the vector cache to update the invalid data.
[0085] Step S120: If the shared data in the vector cache unit is changed, the data synchronization unit sends the changed data to the scalar cache unit to update the shared data in the scalar cache unit.
[0086] In this embodiment, the situation where the shared data in the vector cache unit is changed includes: the shared data in the vector cache unit is modified when a vector memory access request is executed.
[0087] Specifically, when executing a vector memory access request, if shared data in the vector cache unit is modified, the address of the vector memory access request and the modified data are sent to the scalar cache unit to update invalid data in the scalar cache unit.
[0088] Furthermore, this embodiment also provides a flow chart of the RISC-V vector processor when executing scalar memory access and vector memory access, as shown in FIG. Figure 6 and Figure 7As shown. The memory access logic of the RISC-V vector processor also includes:
[0089] When the RISC-V vector processing module executes a vector store instruction, the RISC-V scalar processing module does not execute a scalar load instruction;
[0090] When the RISC-V vector processing module executes a vector load instruction, the RISC-V scalar processing module does not execute a scalar store instruction;
[0091] When the RISC-V scalar processing module executes a scalar store instruction, the RISC-V vector processing module does not execute any memory access instructions.
[0092] In summary, the RISC-V vector processor and memory access method provided in this embodiment have the following technical effects:
[0093] (1) By adding a data synchronization unit to maintain the data consistency of the scalar cache and the vector cache, the data synchronization process is simplified, the processor stall caused by cache data consistency conflicts is reduced, and the processor operation efficiency is improved.
[0094] (2) Through the coordination of the vector cache unit, scalar cache unit, and data synchronization unit, and through effective data transfer and cache management mechanisms, the overall performance of the RISC-V vector processor system is significantly improved. In particular, the memory access process of the RISC-V vector processor is optimized, which significantly improves the processing efficiency of the RISC-V vector processor, especially in parallel computing and data-intensive tasks.
[0095] (3) By adding a vector cache unit, the number of times the RISC-V vector processing module accesses the bus is reduced, alleviating the RISC-V vector processing module's requirements for bus bandwidth and latency. At the same time, the vector cache unit reduces the latency of the RISC-V vector processing module accessing data in the main memory, reduces the latency of data transmission, and improves the efficiency of data transmission in the RISC-V vector processing module.
[0096] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.
[0097] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.
[0098] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0099] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.
Claims
1. A RISC-V vector processor, comprising a RISC-V scalar processing module having an instruction fetch unit and a scalar memory access unit, and a RISC-V vector processing module having a vector memory access unit, characterized in that: Also includes: Scalar cache unit, vector cache unit and data synchronization unit; The scalar memory access unit is connected to the bus through the scalar cache unit; The vector memory access unit is connected to the bus through the vector cache unit; The scalar cache unit and the vector cache unit are both connected to the data synchronization unit; wherein, The data synchronization unit is configured to update the shared data in the scalar cache unit or the vector cache unit according to a preset strategy, so that the shared data in the scalar cache unit and the shared data in the vector cache unit are updated synchronously, and the shared data is data shared between the scalar cache unit and the vector cache unit.
2. A RISC-V vector processor according to claim 1, characterized in that: The data synchronization unit updates the shared data in the scalar cache unit or the vector cache unit according to a preset strategy, including: If the shared data in the scalar cache unit is changed, the data synchronization unit sends the changed data to the vector cache unit to update the shared data in the vector cache unit; If the shared data in the vector cache unit is changed, the data synchronization unit sends the changed data to the scalar cache unit to update the shared data in the scalar cache unit.
3. A RISC-V vector processor according to claim 2, characterized in that: The situation where the shared data in the scalar cache unit is changed includes: When executing a scalar memory access request, shared data in the scalar cache unit is modified; When the RISC-V scalar processing module stores data in the scalar cache unit, the data belongs to the shared data in the vector cache unit.
4. A RISC-V vector processor according to claim 3, characterized in that: The data synchronization unit determines that the data belongs to the shared data in the vector cache unit, including: The data synchronization unit queries the vector cache unit whether the data belongs to a shared address segment, and if so, determines that the data belongs to shared data in the vector cache unit.
5. A RISC-V vector processor according to claim 3, characterized in that: The data synchronization unit includes: a query queue subunit, an address queue subunit, a data queue subunit, a query interface subunit, a vector cache update subunit, and a scalar cache update subunit; the query queue subunit and the address queue subunit are connected to the query interface subunit, the query interface subunit is connected to the scalar cache update subunit and the vector cache update subunit; the data queue subunit is connected to the vector cache update subunit; wherein, The query queue subunit is used to record the number of the cache scalar memory access request and storage load information, and initiate a query request to the vector cache unit; The address queue subunit is used to record the address of the cache scalar memory access request; The data queue subunit is used to record data of cache scalar memory access requests; The query interface subunit is used to convert the information of the address queue of the query queue into an interface signal of the query vector cache and initiate a query request; The vector cache update subunit is used to store data of a scalar memory access request and initiate a vector cache update request to the vector cache unit when the vector cache unit hits data; The scalar cache update subunit is used to save the data returned when the vector cache unit hits, and initiate a scalar cache update request to the scalar cache unit.
6. A RISC-V vector processor according to claim 2, characterized in that: The situation where the shared data in the vector cache unit is changed includes: When executing a vector memory access request, shared data in the vector cache unit is modified.
7. A RISC-V vector processor memory access method, characterized in that: Applicable to the RISC-V vector processor according to any one of claims 1 to 5, the method comprising: If the shared data in the scalar cache unit is changed, the data synchronization unit sends the changed data to the vector cache unit to update the shared data in the vector cache unit; If the shared data in the vector cache unit is changed, the data synchronization unit sends the changed data to the scalar cache unit to update the shared data in the scalar cache unit; The shared data is data shared between the scalar cache unit and the vector cache unit.
8. A RISC-V vector processor memory access method according to claim 7, characterized in that: The situation where the shared data in the scalar cache unit is changed includes: When executing a scalar memory access request, shared data in the scalar cache unit is modified; When the RISC-V scalar processing module stores data in the scalar cache unit, the data belongs to the shared data in the vector cache unit.
9. A RISC-V vector processor memory access method according to claim 8, characterized in that: The data synchronization unit determines that the data belongs to the shared data in the vector cache unit, including: The data synchronization unit queries the vector cache unit whether the data belongs to a shared address segment, and if so, determines that the data belongs to shared data in the vector cache unit.
10. A RISC-V vector processor memory access method according to claim 7, characterized in that: The situation where the shared data in the vector cache unit is changed includes: When executing a vector memory access request, shared data in the vector cache unit is modified.