Active maintenance method and device for cache consistency, electronic equipment and storage medium

Abstract

Embodiments of the present application relate to the technical field of processor, and particularly relate to a cache consistency active maintenance method and device, electronic equipment and storage medium, comprising: in response to maintenance of cache consistency, invalidating a copy of a first cache block of a target processor core, and checking a consistency maintenance mode of the copy of the first cache block; in the case that the consistency maintenance mode is an active maintenance mode, after completing the invalidating, initiating an update command to update the copy of the first cache block to the latest data content; and after the update of the copy of the first cache block is completed, restoring the copy of the first cache block to an effective state. The application realizes convenient and selective use of the active maintenance method, and fully utilizes the existing hardware mechanism of passive maintenance of cache consistency on the CPU to reduce the hardware overhead of the active maintenance method.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of processor, and in particular, to a cache coherence proactively maintaining method and device, electronic equipment and storage medium. BACKGROUND

[0002] In order to accelerate the access to memory data, each processor core on a modern many-core CPU (Central Processing Unit) has a cache to improve the speed of data access and ensure the convenience of program writing. When running a parallel program, multiple threads of the same process read and write data in the same shared memory region, so that multiple cores may simultaneously save copies of the same cache block (cache line, usually 64 bytes). In order to ensure the correctness of the parallel program running, cache coherence between different processor cores of the same CPU and between different CPUs within the same computing node is required to keep the same data consistent among the caches of multiple processor cores within the same computing node.

[0003] The current method for maintaining cache coherence is a passive method, that is, when the cache block copy of processor core B is invalidated by processor A, B does not get the latest valid cache block copy, but has to wait until B accesses the cache block again to update the cache block copy in the cache miss processing mode. Although modern CPUs basically have the function of hardware data prefetching, it may happen that a cache block prefetched by one core is invalidated by another core, and cache miss occurs when the cache block is actually used.

[0004] Therefore, when a processor core wants to get the data produced by another processor core, it often has to pay the cost of cache miss and its large overhead. Especially in the producer-consumer parallel programming mode, the consumer thread constantly queries whether the producer thread has prepared the computing task, that is, the consumer thread constantly queries the signal data modified by the producer thread; whether the producer thread is in advance or lag, the consumer thread will occur cache miss when getting the updated signal data each time, that is, it needs to bear the synchronization overhead represented by cache miss overhead to get the new computing task, which will lead to the increase of the dynamic power consumption of the processor and the decrease of the overall throughput of the system. SUMMARY

[0005] The application aims to provide at least a cache consistency active maintenance method, which can at least solve the technical problem of passive cache consistency maintenance, resulting in cache block copy update by cache miss processing mode, causing dynamic power consumption increase of the processor and overall throughput decline of the system, and can at least achieve the effect of improving the need to bear synchronization overhead represented by cache miss overhead to obtain new computing tasks.

[0006] To solve the above technical problems, at least one embodiment of the application provides a cache consistency active maintenance method, comprising:

[0007] In response to cache consistency maintenance, invalidation operation is performed on the copy of the first cache block of the target processor core, and the consistency maintenance mode of the copy of the first cache block of the target processor core is checked, the consistency maintenance mode comprising an active maintenance mode;

[0008] In the case where the consistency maintenance mode is the active maintenance mode, after the invalidation operation is completed, an update command is initiated to update the copy of the first cache block to the latest data content; and

[0009] After the copy of the first cache block is updated, the copy of the first cache block is restored to an active state.

[0010] In some optional embodiments, before checking the consistency maintenance mode of the copy of the first cache block, the method further comprises:

[0011] In response to receiving a maintenance setting instruction corresponding to the copy of the first cache block, consistency maintenance setting information of the maintenance setting instruction is checked, wherein the consistency maintenance setting information is an active maintenance mode or a passive maintenance mode;

[0012] According to the consistency maintenance setting information, the consistency maintenance mode of the copy of the first cache block is set.

[0013] In some optional embodiments, setting the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information comprises:

[0014] The consistency maintenance setting information is stored in a preset storage space in the first cache block.

[0015] In some optional embodiments, setting the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information comprises:

[0016] Based on a directory protocol, the consistency maintenance setting information is stored in a table item corresponding to the first cache block in a directory structure.

[0017] In some optional embodiments, after the invalidation operation is completed, an update command is initiated to update the copy of the first cache block to the latest data content.

[0018] After the invalidation operation is completed, and after a preset waiting duration, an update command is initiated to update the copy of the first cache block to the latest data content.

[0019] In some optional embodiments, in the active maintenance mode, the size of the shared variable is aligned with the size of the first cache block.

[0020] In some optional embodiments, when the consistency maintenance mode of the copy of the first cache block is set to the active maintenance mode, the active maintenance mode is always maintained unchanged.

[0021] At least one embodiment of the present application further provides an active maintenance device for cache consistency, comprising:

[0022] An invalidation operation module is configured to perform an invalidation operation on a copy of a first cache block of a target processor core in response to maintenance of cache consistency.

[0023] A maintenance mode viewing module is configured to view a consistency maintenance mode of the copy of the first cache block in response to maintenance of cache consistency, wherein the consistency maintenance mode comprises an active maintenance mode.

[0024] A cache block copy updating module is configured to initiate an update command to update the copy of the first cache block to the latest data content after the invalidation operation is completed when the consistency maintenance mode is the active maintenance mode.

[0025] A recovery module is configured to recover the copy of the first cache block to an active state after the copy of the first cache block is updated.

[0026] At least one embodiment of the present application further provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the active maintenance method for cache consistency described above.

[0027] At least one embodiment of the present application further provides a computer readable storage medium storing a computer program, and the computer program is executed by a processor to implement the active maintenance method for cache consistency described above.

[0028] Embodiments of the present application provide a proactive cache consistency maintenance method, device, electronic equipment and storage medium. By introducing setting information of the consistency maintenance mode, the convenient selective use of the proactive maintenance method is achieved. When one processor core invalidates the cache block copy of another processor core, the content of the cache block copy of another processor core is immediately updated. If the invalidated cache block copy is not used subsequently, additional memory access of the cache and bandwidth pressure of program access memory will be increased. Therefore, the processor core can select to use the proactive maintenance or passive maintenance mode according to specific needs, thereby reducing unnecessary additional memory access and bandwidth pressure.

[0029] Specifically, when the processor core performs a maintenance operation (such as invalidating a cache block copy) on cache consistency, it will first check the consistency maintenance mode setting of the cache block copy. If the proactive maintenance mode is set, the processor core will actively initiate an update command of the cache block copy content after completing the invalidation operation, so that the latest data is obtained and the cache block copy is restored to a valid state. If the passive maintenance mode is set, only the invalidation operation is performed, and no update command is initiated. When it is necessary to ensure timely data update and avoid cache miss overhead, the processor core can select to use the proactive maintenance mode.

[0030] In addition, since modern CPUs usually have hardware mechanisms (such as cache consistency protocols and hardware data prefetching functions) that support the passive maintenance mode, the method can fully utilize these existing mechanisms to reduce the hardware overhead of the proactive maintenance method. For example, during the proactive maintenance process, the processor core can use the hardware prefetching function to obtain the latest data in advance, thereby reducing the delay caused by waiting for data update. At the same time, by finely controlling the switching time and conditions of the proactive maintenance and passive maintenance, the overall performance and resource utilization of the system can be further optimized.

[0031] In summary, the method of the present application introduces setting information of the consistency maintenance mode and uses the proactive maintenance and passive maintenance modes, thereby achieving the convenient selective use of the proactive maintenance method and fully utilizing the existing hardware mechanisms of the cache consistency passive maintenance on the CPU to reduce the hardware overhead of the proactive maintenance method. BRIEF DESCRIPTION OF DRAWINGS

[0032] One or more embodiments are illustrated by way of example in the accompanying drawings that are not intended to be limiting of the embodiments.

[0033] Figure 1 FIG. 1 is a flowchart of a proactive cache consistency maintenance method provided by an embodiment of the present application;

[0034] Figure 2 is a schematic diagram of the active maintenance device of cache coherency provided by another embodiment of the present application. DETAILED DESCRIPTION

[0035] To make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present application, and the embodiments can be combined and referenced with each other without contradiction.

[0036] To facilitate the understanding of the embodiments of the present application, the related content about cache coherency is introduced first.

[0037] Modern CPUs (central processing units) have tens or even hundreds of processor cores, providing huge computing power for accelerating program running. This requires upgrading the original serial program to a high-efficiency parallel program that can fully utilize the many-core CPU. Thread-level parallelization, which enables a process to have multiple threads that can work together simultaneously, is a basic means of developing parallel programs. The cooperation between threads often forms data dependency between them, that is, one thread uses the result data calculated by another thread. Since multiple threads of the same process share the entire memory space of the process, multiple threads can conveniently realize data dependency between them through shared variables.

[0038] To accelerate the access to memory data, each processor core on a modern many-core CPU has a cache to improve the speed of data access and ensure the convenience of program writing. When running a parallel program, multiple threads of the same process read and write data in the same shared memory region, so multiple cores may simultaneously save copies of the same cache block (cache line, usually 64 bytes). To ensure the correctness of the parallel program running, cache coherency between different processor cores of the same CPU and between different CPUs within the same computing node is required to keep the same data consistent between the caches of multiple processor cores within the same computing node.

[0039] There are two main ways to implement cache coherence protocol: a snooping-based coherence protocol (snooping protocol) and a directory-based coherence protocol (directory protocol). The snooping protocol relies on a bus or bus-like network connection; using this network, all requests from a private cache of a single processor core are broadcast to all other private caches of the system, and all access requests of the processors can be sequenced on this bus to meet the requirements of the cache coherence model and the memory consistency model for memory access order. In the directory protocol, the memory access request from the private cache of a processor core is first sent to the directory structure corresponding to the cache block, which records the sharing status of the current cache block. The directory structure controller will select a response to the request or forward the request to other private caches of the corresponding processor core according to the state of the current cache block. These two methods have advantages and disadvantages, so modern many-core CPUs usually use a hybrid of the two protocols.

[0040] In order to maintain cache coherence, processor core A will send an invalid command about a cache block to other processor cores when it first modifies the cache block; when processor core B has a valid copy of the cache block and receives the invalid command, it will invalidate its cache block copy and then respond to A; when B accesses the cache block again, a cache miss will occur, and the latest copy of the cache block will be obtained from A or the memory.

[0041] The above method of maintaining cache coherence can be called a passive method. When the cache block copy of processor core B is invalidated by processor A, B does not get the latest valid cache block copy, but has to wait until B accesses the cache block again to update the cache block copy through cache miss processing. Although modern CPUs basically have hardware data prefetching functions, it is possible that a cache block prefetched by one core is invalidated by another core, and a cache miss occurs when the cache block is actually used. Therefore, when a processor core wants to obtain data produced by another processor core, it often has to pay the cost of cache miss and its large overhead. In particular, in the producer-consumer parallel programming mode, the consumer thread constantly queries whether the producer thread has prepared the calculation task, i.e., the consumer thread constantly queries the signal data that the producer thread constantly modifies; regardless of whether the producer thread is in advance or lag, the consumer thread will have a cache miss when it obtains the updated signal data, i.e., it needs to bear the synchronization overhead represented by cache miss overhead to obtain new calculation tasks.

[0042] To solve the technical problems of the above-mentioned passive maintenance cache consistency, resulting in the cache block copy update being implemented in the cache miss processing mode, causing the dynamic power consumption of the processor to increase and the overall throughput of the system to decrease, the present application proposes an active maintenance method of cache consistency. The implementation details of the active maintenance method of cache consistency of the present embodiment will be described below. The following content is only provided for the implementation details for easy understanding, and is not necessary for implementing the present solution.

[0043] Embodiment one:

[0044] The active maintenance method of cache consistency of the present embodiment can be applied to electronic devices with communication, computing and data storage capabilities. The specific process can be as shown in Figure 1 , including:

[0045] Step 110, in response to the maintenance of cache consistency, invalidating the copy of the first cache block of the target processor core, and checking the consistency maintenance mode of the copy of the first cache block of the target processor core, the consistency maintenance mode including an active maintenance mode;

[0046] Step 120, in the case where the consistency maintenance mode is the active maintenance mode, after completing the invalidation operation, initiating an update command to update the copy of the first cache block to the latest data content;

[0047] Step 130, after the update of the copy of the first cache block is completed, restoring the copy of the first cache block to an active state.

[0048] In the present embodiment, when the processor core A (i.e. the target processor core) has an active copy of a cache block (i.e. the copy of the first cache block) and another processor core wants to modify the data of the cache block, the cache consistency protocol will initiate an invalidation operation of the copy of the first cache block to the target processor core, that is, initiate the maintenance of cache consistency. The system will record the current consistency maintenance mode of each cache block copy of each processor core, that is, any one of the active maintenance mode and the passive maintenance mode.

[0049] If it is determined that the copy of the first cache block adopts the active maintenance mode, in addition to marking the copy of the first cache block as invalid, an update command can also be actively initiated to obtain the latest data content from the data source (which can be the cache or main memory of another processor core).

[0050] The update command can include the specific address of the requested data, the request type (such as read, write), and the identity of the requester, and the like. These commands are sent to the processor core or memory controller responsible for maintaining the latest data through the system bus or a dedicated communication channel. Once the copy of the first cache block is successfully updated to the latest data content, it is re-labeled as valid state, ready for use by the processor core.

[0051] The cache coherency on modern many-core CPUs is passively maintained, i.e. only invalidation operation is performed. Active maintenance is different from passive maintenance, which updates the content of the cache block copy after completing the invalidation operation. There are multiple ways to implement this update. One easily thought of implementation method is that the cache coherency protocol hardware sends the latest data content to the cache block copy of a processor core at the same time when it initiates the invalidation operation. However, this method is difficult to implement because the processor core that needs to write data can only write data to the cache block after completing the invalidation operation on the corresponding cache block copy in other processor cores and confirming that it has acquired the exclusive ownership of the cache block. That is, invalidation operation and data update are performed sequentially, not simultaneously.

[0052] Another more practical method, which is also the method adopted in this embodiment, is to let the target processor core initiate the command to update the content of the copy of the first cache block after completing the invalidation operation on the target processor core. This update command can be essentially understood as a cache block data prefetch instruction. This implementation method can make full use of the existing functions of cache coherency on modern many-core CPUs, and therefore has good application prospects.

[0053] In an optional embodiment, when the coherency maintenance method is passive maintenance, only the invalidation operation is performed. If it is determined that the copy of the first cache block adopts passive maintenance, when the data of the copy is modified elsewhere, it only needs to be marked as invalid state. In this way, when the processor core accesses the data again, a cache miss will be triggered, and the latest data will be re-acquired from the main memory or other caches.

[0054] Active maintenance reduces the delay in data access and improves system performance by updating the cache in advance. However, active maintenance may increase the communication volume on the system bus, especially in high-concurrency access scenarios. Based on this, active maintenance should not be the default method or even the only method for maintaining cache coherency, because when the copy of the first cache block that has been invalidated is not used later, the active maintenance method will increase the additional access of the first cache block to the memory, increasing the bandwidth pressure of the program accessing the memory. Therefore, the active maintenance method of cache coherency in this embodiment focuses on solving the following two problems:

[0055] 1) how to achieve convenient and selective use of the active maintenance method;

[0056] 2) how to take full advantage of the existing hardware mechanism of cache coherency passive maintenance on the CPU to reduce the hardware overhead of the active maintenance method.

[0057] Specifically, the embodiment achieves convenient and selective use of the active maintenance method by introducing setting information of the consistency maintenance mode, allowing the processor core to select active maintenance or passive maintenance mode according to specific needs, thereby reducing unnecessary additional memory access and bandwidth pressure. When the processor core performs a maintenance operation on cache coherency (such as invalidating a cache block copy), it will first check the consistency maintenance mode setting of the cache block copy. If it is set to the active maintenance mode, the processor core will actively initiate an update command for the cache block copy content after completing the invalidation operation, so that it immediately obtains the latest data and recovers to the valid state. If it is set to the passive maintenance mode, only the invalidation operation is performed, and no update command is initiated. Therefore, when it is necessary to ensure timely data update and avoid cache miss overhead, the processor core can select to use the active maintenance mode.

[0058] In addition, since modern CPUs usually already have hardware mechanisms (such as cache coherency protocols and hardware data prefetching functions) that support passive maintenance mode, in this embodiment, these existing mechanisms are fully utilized to reduce the hardware overhead of the active maintenance method. For example, during active maintenance, the processor core can use the hardware prefetching function to obtain the latest data in advance (i.e., control the target processor core to initiate an update command), thereby reducing the delay caused by waiting for data update. At the same time, by finely controlling the switching time and conditions of active maintenance and passive maintenance, the overall performance and resource utilization of the system can be further optimized.

[0059] In summary, the active maintenance method of cache coherency of the embodiment achieves convenient and selective use of the active maintenance method by introducing setting information of the consistency maintenance mode and combining the use of active maintenance and passive maintenance modes, and fully utilizes the existing hardware mechanism of cache coherency passive maintenance on the CPU to reduce the hardware overhead of the active maintenance method.

[0060] In some optional embodiments, before the checking of the consistency maintenance mode of the copy of the first cache block, it further includes: in response to receiving a maintenance setting instruction corresponding to the copy of the first cache block, checking consistency maintenance setting information of the maintenance setting instruction, wherein the consistency maintenance setting information is an active maintenance mode or a passive maintenance mode; setting the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information.

[0061] In this embodiment, the target processor core, in response to execution of the maintenance setting instruction, views the consistency maintenance setting information of the maintenance setting instruction; if the consistency maintenance setting information is active maintenance setting, sets the consistency maintenance mode of the cache block copy corresponding to the maintenance setting instruction (i.e. the copy of the first cache block) to active maintenance mode; if the consistency maintenance setting information is passive maintenance setting, sets the consistency maintenance mode of the cache block copy corresponding to the maintenance setting instruction to passive maintenance mode.

[0062] In the background that the cache consistency of modern many-core CPUs all adopts passive maintenance mode, it can be considered that the consistency maintenance setting information during execution of existing memory access instructions is all passive maintenance setting. Therefore, the problem to be solved in this embodiment is: how to achieve convenient designation of active maintenance setting in the case of default passive maintenance setting.

[0063] There are at least two implementation manners to achieve convenient designation of active maintenance setting:

[0064] The first implementation manner extends the modality of active maintenance setting to various memory access instructions in the processor instruction set. The specific method can be to add a state marking bit about active maintenance setting in the operation code of existing memory access instructions (e.g. default passive maintenance setting, and active maintenance setting when marked). In other words, the maintenance setting instruction is a memory access instruction with a state marking bit, and the state marking bit contains the consistency maintenance setting information. The essence of this method is to add memory access instructions corresponding to active maintenance setting. Further, the definition of shared variables of active maintenance setting is supported in the programming language, and the compiler uses the memory access instruction of active maintenance setting modality to realize the access to the shared variables of active maintenance setting. The first implementation manner will cause great changes in the instruction set and decoding component, thereby bringing great hardware development cost.

[0065] In the second implementation, an instruction for changing the current consistency maintenance setting information (i.e., a maintenance setting instruction) is added, which can change the current consistency maintenance setting information from the passive maintenance setting to the active maintenance setting, or from the active maintenance setting to the passive maintenance setting. The second implementation is the implementation adopted in the present embodiment. Each maintenance setting instruction can query the current consistency maintenance setting information when executed. When the programming language supports the definition of the active maintenance setting shared variable, the compiler can add the instruction for changing the current consistency maintenance setting information before and after the maintenance setting instruction of the active maintenance setting shared variable; when the programming language does not support the definition of the active maintenance setting shared variable, the programmer can also add the instruction for changing the current consistency maintenance setting information in the program in the embedded assembly manner. This implementation is easy to implement and does not bring about large hardware development cost.

[0066] In some optional embodiments, the setting of the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information comprises storing the consistency maintenance setting information into a preset storage space in the first cache block.

[0067] In the present embodiment, an extra bit is used to record the current consistency maintenance mode in the first cache block. The hardware cost of this method is 1 / 512, where 512 represents that the size of a cache block is 64 bytes, i.e., 512 bits. The hardware cost is extremely low, which means that almost no burden is caused on the storage space, and this method is particularly suitable for resource-limited environments. Since the cost is extremely low, the method of the present embodiment has high cost-effectiveness in implementing cache consistency maintenance, and does not need to significantly increase the hardware cost for storing extra information.

[0068] In some optional embodiments, the setting of the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information comprises storing the consistency maintenance setting information into a preset storage space in the first cache block.

[0069] In the present embodiment, a bit is added to each table entry of the directory structure to record the current consistency maintenance mode of the corresponding cache block in combination with the directory protocol. In this way, the directory protocol issues the current consistency maintenance mode of the cache block at the same time of issuing the invalidation operation.

[0070] By issuing the current consistency maintenance mode of the cache block at the same time of issuing the invalidation operation through the directory protocol, the system can reduce the extra communication cost, because the system does not need to query or confirm the maintenance mode again in the subsequent operation, so that the system can respond to the consistency maintenance request more quickly, which helps to reduce the delay and improve the overall performance of the system.

[0071] In some alternative embodiments, the initiating an update command to update the copy of the first cache block to the latest data content after the invalidation operation is completed comprises: initiating an update command to update the copy of the first cache block to the latest data content after the invalidation operation is completed and after a preset waiting time period. In this embodiment, the update command can be initiated after the invalidation operation is completed and after a threshold number of CPU cycles, so as to appropriately relieve the working pressure of the cache consistency hardware. In some alternative embodiments, the update command can also be initiated immediately after the invalidation operation is completed. The specific implementation manner is selected based on actual needs, and is not limited herein.

[0072] In some alternative embodiments, in the active maintenance manner, the size of the shared variable is aligned with the size of the first cache block.

[0073] In this embodiment, when the consistency maintenance setting information of a memory access instruction is the active maintenance setting, the consistency maintenance manner of the copy of the first cache block is set to the active maintenance manner. If the consistency maintenance setting information of a memory access instruction is the passive maintenance setting, the consistency maintenance manner of the copy of the first cache block is set to the passive maintenance manner. An extreme case can occur: two memory access instructions executed in sequence correspond to the copy of the same first cache block, but their consistency maintenance setting information is different from each other, so that the current consistency maintenance manner of the copy of the first cache block is determined by the latest executed instruction, which can easily reduce the optimization effect of the cache consistency active maintenance method.

[0074] To solve the above problem, the size of the shared variable is aligned with the size of the cache block in the active maintenance manner, so as to avoid the occurrence of this case as much as possible. The specific reasons are as follows:

[0075] When the size of the shared variable is aligned with the size of the cache block, the storage positions of these variables in the cache are more likely to exclusively occupy a cache line. Since the cache line is the basic storage unit of the cache, and the processor accesses the cache in the unit of cache line, the alignment can ensure that the maintenance settings of different memory access instructions on the copy of the same cache block do not interfere with each other.

[0076] Through the alignment, even if two memory access instructions access the copy of the same cache block and their consistency maintenance setting information is different from each other, these settings will not cover each other in the same cache line. Since each setting is located in an independent cache line, the processor can correctly identify and execute the consistency maintenance operation required by each setting.

[0077] In summary, by aligning the size of the shared variable set by the active maintenance with the cache block size, the conflict caused by different memory access instructions with different maintenance settings on the same cache block copy can be avoided as much as possible, thereby improving the efficiency and accuracy of cache consistency maintenance.

[0078] In actual use, due to the limited capacity of the first cache block, the copy of the first cache block will be frequently swapped in and out. The newly swapped-in copy of the first cache block will be initialized to the passive maintenance mode. Therefore, when the copy of the first cache block in the active maintenance mode is swapped out to the memory, the active maintenance mode will be lost. However, the maintenance setting instruction of the active maintenance setting shared variable can change the cache block copy swapped in again to the active maintenance mode.

[0079] In some optional embodiments, when the consistency maintenance mode of the copy of the first cache block is set to the active maintenance mode, the active maintenance mode is always maintained unchanged.

[0080] In this embodiment, in order to improve the problem that two memory access instructions executed in sequence correspond to the same copy of the first cache block but have different consistency maintenance setting information, resulting in the optimization effect of the cache consistency active maintenance method being reduced, the priority of the active maintenance mode is set to be higher. That is, after a cache block copy is set to the active maintenance mode, it will not be set to the passive maintenance mode again.

[0081] Embodiment Two:

[0082] Another embodiment of the present application relates to a cache consistency active maintenance device. The implementation details of the cache consistency active maintenance device of this embodiment will be specifically described below. The following content is only provided for the implementation details for easy understanding, and is not necessary for implementing this solution. The schematic diagram of the cache consistency active maintenance device of this embodiment can be as shown in Figure 2 The cache consistency active maintenance device includes an invalidation operation module 210, a maintenance mode viewing module 220, a cache block copy updating module 230, and a recovery module 240.

[0083] The invalidation operation module 210 is configured to perform an invalidation operation on the copy of the first cache block of the target processor core in response to the maintenance of cache consistency.

[0084] The maintenance mode viewing module 220 is configured to view the consistency maintenance mode of the copy of the first cache block in response to the maintenance of cache consistency. The consistency maintenance mode includes an active maintenance mode.

[0085] The cache block copy updating module 230 is configured to, in the case that the consistency maintenance manner is the active maintenance manner, initiate an updating command to update the copy of the first cache block to the latest data content after the invalidation operation is completed.

[0086] The recovery module 240 is configured to recover the copy of the first cache block to the valid state after the updating of the copy of the first cache block is completed.

[0087] It is worth mentioning that each module involved in the embodiment is a logical module. In actual application, one logical unit can be one physical unit, or a part of one physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, units not closely related to solving the technical problems proposed in the present application are not introduced in the embodiment, but this does not mean that there are no other units in the embodiment.

[0088] In an optional embodiment, the method further comprises:

[0089] The maintenance manner viewing module is further configured to view consistency maintenance setting information of the maintenance setting instruction corresponding to the copy of the first cache block in response to receiving the maintenance setting instruction, wherein the consistency maintenance setting information is the active maintenance manner or the passive maintenance manner.

[0090] The maintenance manner setting module is configured to set the consistency maintenance manner of the copy of the first cache block according to the consistency maintenance setting information.

[0091] In some optional embodiments, the maintenance manner setting module comprises:

[0092] The first storage unit is configured to store the consistency maintenance setting information into a preset storage space in the first cache block.

[0093] In some optional embodiments, the maintenance manner setting module comprises:

[0094] The second storage unit is configured to store the consistency maintenance setting information into a table item corresponding to the first cache block in a directory structure based on a directory protocol.

[0095] In some optional embodiments, the cache block copy updating module comprises:

[0096] The first updating unit is configured to initiate an updating command to update the copy of the first cache block to the latest data content after the invalidation operation is completed and after a preset waiting duration.

[0097] In some optional embodiments, the maintenance mode setting module is further configured to keep the active maintenance mode unchanged when the consistency maintenance mode of the copy of the first cache block is set to the active maintenance mode.

[0098] Embodiment three:

[0099] Another embodiment of the present application relates to an electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the active maintenance method of cache consistency in each of the above embodiments.

[0100] The memory and the processor are connected in a bus mode, and the bus can include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripheral devices, voltage stabilizers and power management circuits together, which are well known in the art, and thus, further description will not be given herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements such as multiple receivers and transmitters, which provide units for communicating with various other devices on the transmission medium. The data processed by the processor is transmitted on the wireless medium through the antenna, and further, the antenna also receives data and transmits the data to the processor.

[0101] The processor is responsible for managing the bus and general processing, and can also provide various functions including timing, peripheral interface, voltage regulation, power management and other control functions. And the memory can be used to store the data used by the processor in the execution of the operation.

[0102] Embodiment four:

[0103] Another embodiment of the present application relates to a computer readable storage medium, which stores a computer program. The computer program is executed by the processor to implement the method embodiments.

[0104] That is, a person skilled in the art can understand that all or part of the steps in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a program stored in a storage medium, including a plurality of instructions for causing a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0105] A person of ordinary skill in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A proactive method for maintaining cache consistency, characterized in that, include: In response to maintaining cache consistency, an invalidation operation is performed on a copy of the first cache block of the target processor core, and the consistency maintenance method of the copy of the first cache block of the target processor core is examined, including an active maintenance method and a passive maintenance method. When the consistency maintenance method is active maintenance, after the invalidation operation is completed, an update command is initiated to update the copy of the first cache block with the latest data content; as well as After the copy of the first cache block is updated, the copy of the first cache block is restored to a valid state. In the case that the consistency maintenance method is the passive maintenance method, only the invalidation operation is performed and no update command is initiated. Before viewing the consistency maintenance method of the replica of the first cache block, the method further includes: In response to receiving a maintenance setting instruction corresponding to a copy of the first cache block, the consistency maintenance setting information of the maintenance setting instruction is viewed, wherein the consistency maintenance setting information is an active maintenance method or a passive maintenance method; Based on the consistency maintenance settings information, the consistency maintenance method for the replica of the first cache block is set.

2. The proactive maintenance method for cache consistency according to claim 1, characterized in that, The step of setting the consistency maintenance method for the replica of the first cache block according to the consistency maintenance setting information includes: The consistency maintenance settings information is stored in the preset storage space in the first cache block.

3. The proactive maintenance method for cache consistency according to claim 1, characterized in that, The step of setting the consistency maintenance method for the replica of the first cache block according to the consistency maintenance setting information includes: Based on the directory protocol, the consistency maintenance settings information is stored in the table entry in the directory structure corresponding to the first cache block.

4. The proactive maintenance method for cache consistency according to any one of claims 1-3, characterized in that, After completing the invalidation operation, initiating an update command to update the copy of the first cache block with the latest data content includes: After the invalidation operation is completed and after a preset waiting period, an update command is initiated to update the copy of the first cache block with the latest data content.

5. The proactive method for maintaining cache consistency according to any one of claims 1-3, characterized in that, In the active maintenance method, the size of the shared variable is set to be aligned with the size of the first cache block.

6. The proactive maintenance method for cache consistency according to any one of claims 1-3, characterized in that, Once the consistency maintenance mode of the first cache block replica is set to active maintenance mode, the active maintenance mode will remain unchanged.

7. A proactive cache consistency maintenance device, characterized in that, include: The invalidation operation module is used to invalidate a copy of the first cache block of the target processor core in response to the maintenance of cache consistency. The maintenance method viewing module is used to view the consistency maintenance method of the copy of the first cache block of the target processor core. The consistency maintenance method includes active maintenance method and passive maintenance method. The cache block replica update module is used to initiate an update command after the invalidation operation is completed when the consistency maintenance mode is active maintenance mode, so that the replica of the first cache block is updated to the latest data content; as well as The recovery module is used to restore the copy of the first cache block to a valid state after the copy of the first cache block is updated. When the consistency maintenance method is the passive maintenance method, it only performs the invalidation operation and does not initiate the update command. Also includes: The maintenance method viewing module is used to, in response to receiving a maintenance setting instruction corresponding to a copy of the first cache block, view the consistency maintenance setting information of the maintenance setting instruction before viewing the consistency maintenance method of the copy of the first cache block, wherein the consistency maintenance setting information is an active maintenance method or a passive maintenance method; The maintenance method setting module is used to set the consistency maintenance method of the replica of the first cache block according to the consistency maintenance setting information.

8. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the proactive cache coherency maintenance method as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the proactive maintenance method for cache coherency as described in any one of claims 1 to 6.

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