Weight-adjustable ultra-low power consumption superconducting neuron design method

Abstract

The invention relates to the technical field of neural networks, and provides a weight-adjustable ultra-low power consumption superconducting neuron design method, which comprises the following steps of: 1, designing a passive weight structure; an adjustable inductor is integrated in a transformer structure in an AQFP circuit, and the magnitude of output current is controlled by adjusting the magnitude of internal parameters of a passive weight structure circuit; 2, designing an activation circuit; an extra current source is placed in a threshold circuit of an AQFP circuit, an inductor couples an electric signal to a transformer circuit of a neuron, different thresholds are set by adjusting the amplitude and phase of current, and the magnitude of the signal flowing into an activation circuit is controlled; and 3, verifying the functionality of the multi-weight neurons. The invention has the advantages of flexible weight adjustment, efficient processing capability, high integration degree, low power consumption and small area.

Description

Technical Field

[0001] The present invention relates to the field of neural network technology, and in particular to a method for designing ultra-low power consumption superconducting neurons with adjustable weights. Background Art

[0002] Energy efficiency is a key factor constraining the future development of supercomputers. As supercomputers continue to expand, the amount of computation required is also rapidly increasing. However, existing processes consume significant energy, creating inevitable challenges. Therefore, further achieving low power consumption is a key research direction for the future development of high-performance computing systems.

[0003] With the rapid development of deep learning and artificial intelligence technologies, the demand for computing performance and efficiency in large-scale neural networks continues to rise, especially for complex calculations and data processing. Traditional semiconductor technology is gradually experiencing bottlenecks in improving processing speed and reducing power consumption, especially in scenarios where heat dissipation is a major issue, making it difficult to effectively support the further expansion of neural networks. If superconducting devices can be applied to neural networks, they can significantly reduce energy consumption and improve computing efficiency, making them particularly suitable for large-scale, complex data computing scenarios.

[0004] Researchers have proposed a binary neural network (BNN) design based on adiabatic quantum flux parametrizer (AQFP) logic. They combined in-memory computing, analog accumulation, and crossover architectures to apply the AQFP architecture to neural network design. Unlike traditional neural networks, this design effectively alleviates the memory bottleneck in superconducting digital circuits, achieving more efficient computation by reducing the memory usage of the von Neumann architecture. Researchers have investigated the stochastic behavior of AQFP devices and proposed a stochastic BNN acceleration framework, SupeRBNN, based on the AQFP architecture. However, BNNs suffer from unsatisfactory information processing accuracy, particularly due to a lack of flexible weight control, resulting in a significantly lower accuracy than convolutional neural network (CNN) models, which can adjust weights.

[0005] Some researchers have proposed a hybrid superconducting neuron design that combines fast single flux quantum (RSFQ) and quantum flux parametrizer (QFP) technologies. The RSFQ architecture enables fast signal processing, while the QFP is used to achieve low-power adjustment of synaptic weights, enabling neurons to achieve weighted responses based on input signals. Although this architecture implements eight different weights, the introduction of RSFQ circuits to achieve adjustable flux storage results in a significant increase in power consumption and area, which also affects the degree of integration and limits its application in large-scale neural network computing. In addition, the design uses three power switches to control flux storage to achieve weight adjustment, resulting in only eight discrete levels of weight adjustment. Further increasing the flexibility of weight adjustment will inevitably require the addition of a flux storage control unit, which will inevitably lead to further increases in power consumption and area. Summary of the Invention

[0006] The content of the present invention is to provide a method for designing ultra-low power superconducting neurons with adjustable weights. It designs a superconducting neuron that has the advantages of flexible weight adjustment, efficient processing capability, high degree of integration, low power consumption and small area, so as to further improve the applicability and energy efficiency of superconducting neural networks in large-scale computing.

[0007] According to the present invention, a method for designing an ultra-low power superconducting neuron with adjustable weights comprises the following steps:

[0008] Step 1: Passive weight structure design;

[0009] The two inductors L of the transformer structure in the AQFP circuit q and L out The middle integrated adjustable inductor L2, by adjusting the internal parameters L2, K of the passive weight structure circuit 12 , K 23 The size of the output current is controlled to achieve the adjustable function of the weight;

[0010] Step 2: Activate the circuit design;

[0011] Place an additional current source I in the threshold circuit of the AQFP circuit th , the inductor couples the electrical signal to the transformer circuit of the neuron by regulating the current I th Amplitude and phase set different thresholds to control the size of the signal flowing into the activation circuit;

[0012] Step 3: Functional verification of multi-weight neurons;

[0013] Functional verification of multi-weight neurons; determine the output current size when the weight is 1, and based on this, design and implement a synaptic circuit array with multiple weights; further integrate the constructed synaptic network into a single-layer 3-bit neuron model, and complete the functional verification of the invention through functional analysis of this neuron.

[0014] Preferably, in the AQFP circuit, the energy dissipation during a switching event is proportional to the operating frequency and inversely proportional to the Q value of the Josephson junction, and there is no minimum energy limit for the adiabatic switching operation.

[0015] As a preferred embodiment, in the AQFP circuit, the final state of the logic gate circuit is determined by the input I in The direction of I in When the input is positive, the single quantum flux Φ0 is stored in the right loop, and the circuit state is 1. in When it is a reverse input, Φ0 is stored in the left loop and the circuit state is 0; and q A large output current is generated in the q and L out The coupling between them is passed to the next level logic device;

[0016] Without considering the additional threshold signal, the electrical signal flowing out of the transformer circuit acts as I in =W1X1+W2X2+…+W n x n Flow into AQFP logic gates;

[0017]

[0018] I q The output current of the AQFP logic in the activation circuit;

[0019] The threshold circuit places an additional current source I th , the inductor couples the electrical signal to the transformer circuit of the neuron by regulating the current I th Amplitude and phase are set to different thresholds, and the signal flowing into the activation circuit becomes I in =W1X1+W2X2+…+W n X n +I th , the formula is rewritten as:

[0020]

[0021] This invention addresses the adjustable weight functionality of superconducting neural networks based on the AQFP architecture and proposes a low-power, multi-weight superconducting neuron design. To meet the diverse application needs of superconducting neural networks, a superconducting neuron is designed that combines flexible weight adjustment, efficient processing capabilities, high integration, low power consumption, and a small footprint, further enhancing the applicability and energy efficiency of superconducting neural networks in large-scale computing. Therefore, this invention provides new ideas and methods for achieving multi-weight and high-precision superconducting neural network systems, assisting the development of superconducting neural networks and possessing significant research significance and value for the development of quantum information technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A flowchart of a method for designing an extremely low-power superconducting neuron with adjustable weights;

[0023] Figure 2 This is the AQFP circuit schematic;

[0024] Figure 3 It is the circuit diagram of passive weight structure;

[0025] Figure 4 It is the structure diagram of the threshold circuit;

[0026] Figure 5 The diagram is a synaptic circuit with a gate circuit;

[0027] Figure 6 A simplified diagram of a synaptic circuit with a gate circuit.

[0028] Figure 7(a) is a synaptic circuit diagram of a single-layer 3-bit neuron model;

[0029] Figure 7(b) is the activation circuit diagram of a single-layer 3-bit neuron model;

[0030] Figure 8 This is a diagram of the circuit structure of a single-layer 3-bit neuron;

[0031] Figure 9 Schematic diagram of the readout results. DETAILED DESCRIPTION

[0032] In order to further understand the content of the present invention, the present invention is described in detail with reference to the accompanying drawings and embodiments. It should be understood that the embodiments are merely for explaining the present invention and are not intended to limit the present invention.

[0033] Example

[0034] like Figure 1 As shown, this embodiment provides a method for designing an ultra-low power superconducting neuron with adjustable weights, which includes the following steps:

[0035] Step 1: Passive weight structure design;

[0036] This example begins with the most basic logic based on adiabatic quantum flux parameter (AQFP). In AQFP logic, the energy dissipated during a switching event is proportional to the operating frequency and inversely proportional to the Q value of the Josephson junction. This indicates that in AQFP logic, there is no minimum energy limit for adiabatic switching operations. Furthermore, compared to RSFQ, AQFP offers simpler logic design, higher integration capabilities, and lower device power consumption. By implementing a multi-weight design, these superconducting neurons can achieve more complex learning capabilities and efficient signal processing capabilities through dynamic weight adjustment.

[0037] like Figure 2 As shown, the transformer structure in the AQFP circuit usually consists of two inductors L q and L out Composition. q The size is based on the research of relevant scholars on AQFP, and considering the influence of margin and dynamic power consumption, the normalized inductance value is set to β q =1.6. Combined with the Josephson junction critical current I specified by the superconducting process SIMITNb03P c =100μA, so the internal inductance parameters should satisfy the following relationship (where Φ0 represents the single quantum flux, which is 2.068×10 -15 Wb).

[0038]

[0039] like Figure 3 As shown in Figure 1, considering the characteristics of the AQFP circuit, a passive weight structure circuit diagram is designed according to actual needs. q =5.266pH remains unchanged. By adjusting the transformer's internal inductor L2, the output current I3 is changed. In the AQFP-based synaptic circuit, the output current amplitude directly reflects its weight. The larger the output current, the higher the corresponding weight, and vice versa. In this embodiment, L q and L out The middle integrated adjustable inductor L2 can be adjusted by adjusting the internal parameters L2 and K of the passive weight structure circuit. 12 , K 23 The size of the output current can be controlled to achieve the adjustable function of the weight.

[0040] Step 2: Activate the circuit design;

[0041] The final state of the AQFP logic gate circuit is determined by I in The direction of I inWhen it is a positive input, Φ0 is stored in the right loop. At this time, the circuit state is "1". in When it is a reverse input, Φ0 is stored in the left loop and the circuit state is "0"; and q A large output current is generated in the q and L out Based on this characteristic, AQFP naturally meets the requirements of the activation function. Without considering the additional threshold signal, the electrical signal flowing out of the transformer circuit acts as I in =W1X1+W2X2+…+W n X n Flow into AQFP logic gate. (I q (output current of the AQFP logic in the activation circuit)

[0042]

[0043] Threshold circuit such as Figure 4 、 Figure 5 and Figure 6 As shown, an additional current source I is placed in the threshold circuit th , the inductor couples the electrical signal to the transformer circuit of the neuron by regulating the current I th The amplitude and phase are set to different thresholds to control the size of the signal flowing into the activation circuit. At this time, the size of the signal flowing into the activation circuit becomes I in =W1X1+W2X2+…+W n X n +I th (If no additional current source is added, the threshold is considered to be 0), the above formula can be rewritten as:

[0044]

[0045] At this point, the weight and activation circuit design of the superconducting neurons based on the AQFP architecture has been completed.

[0046] Step 3: Functional verification of multi-weight neurons;

[0047] After determining the basic superconducting neuron structure, we start to realize neurons with different weights and determine the output current size when the weight is "1". out =11.25uA is regarded as weight "1", and all subsequent output currents are based on this, and the detailed current size is not specified.

[0048] According to the AQFP logic schematic, it is not difficult to find that the converter L q , L2 and L outThe coupling polarity between them will determine the output current polarity. q2 With K 2out When the same sign, L out The output current on the L has the same polarity as the input current; when they are of opposite signs, L out The output current on the MOSFET is opposite in polarity to the input current. Therefore, when designing the layout, the design of the negative weighted part can be based on the design of the positive weighted part, just by reversing the coupling method of the converter part.

[0049] In order to verify the design scheme, this embodiment constructs a single-layer 3-bit neuron model, whose circuit is shown in Figure 7(a) and Figure 7(b). In Figure 7(a), the input signals X1, X2 and X3 act on three parallel circuits respectively. In the design, the weight W1 is set to a value much larger than the other two weights, that is, W1>W2+W3. For the AQFP logic circuit, since the current on Lq is only related to the direction of the input current and has nothing to do with its amplitude, assuming that all input currents are positive, the current flowing through Lq remains constant even if there are significant differences in the input current amplitude. Under this condition, as long as the value of the first weight W1 is large enough to make it greater than the sum of the other two weights, that is, W1>W2+W3, the direction of the output current of the synaptic circuit will be determined only by the input signal X1.

[0050] The activation circuit in Figure 7(b) utilizes an AQFP buffer logic unit design with integrated weak current readout. The weighted current output from the synaptic circuit feeds the activation circuit, which then reads the phase of the weighted current to generate the final output signal. This design effectively separates the input signal weighting from the readout function, improving the integration density and readout accuracy of the neuron circuit.

[0051] like Figure 8 As shown, in order to realize the logical action of adiabatic superconductivity, an alternating current will pass. ac and DC bias current I ac Common incentives (i.e. I x =I ad +I dc ) introduces a magnetic flux of 0.25Φ0 respectively. The relevant parameters are: L q =5.266pH,L x =L d =7.4263pH, L1 =0.645pH. To improve the logic stability of the entire circuit and reduce errors caused by the clock, a buffer with the same number of bits as the multi-value weighted majority is placed in the adiabatic superconducting logic circuit.

[0052] When the input signals are X1, X2, and X3, after weighted operation and summation, the final current amplitude value is I=X1W1+X2W2+X3W3, where W1, W2, and W3 are the weights of the three neurons. In this embodiment, the weights are set to W1=1, W2=W3=0.333 respectively. When the weight is 1, the internal parameters of the transformer are K q2 =-4.442pH, K 2out =-6.805pH, L out =12.56pH, L2=28.3pH; when the weight is 0.333, the internal parameters of the transformer are: K q2 =-4.442pH, K 2out =-3.806pH, L out =12.56pH, L2=39.426pH.

[0053] like Figure 9 As shown, the three input signals are "11110000", "11001100" and "10101010", and the corresponding weights are 1, 0.333 and 0.333 respectively. The current amplitude value is I ∑ =X1+0.333X2+0.333X3. The final readout unit reads "11110000", which is consistent with the expected result. The results show that the correct logic is implemented and verify the effectiveness of the design.

[0054] The above is a schematic description of the present invention and its embodiments, which is not restrictive. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. Therefore, if a person skilled in the art is inspired by this and, without departing from the purpose of the present invention, designs a structure and embodiment similar to this technical solution without inventiveness, they shall fall within the scope of protection of the present invention.

Claims

1. A method for designing ultra-low power superconducting neurons with adjustable weights, characterized by: The following steps are involved: Step 1: Passive weight structure design; The two inductors L of the transformer structure in the AQFP circuit q and L out The middle integrated adjustable inductor L2, by adjusting the internal parameters L2, K of the passive weight structure circuit 12 , K 23 The size of the output current is controlled to achieve the adjustable function of the weight; Step 2: Activate the circuit design; Place an additional current source I in the threshold circuit of the AQFP circuit th , the inductor couples the electrical signal to the transformer circuit of the neuron by regulating the current I th Amplitude and phase set different thresholds to control the size of the signal flowing into the activation circuit; Step 3: Functional verification of multi-weight neurons; The output current size when the weight is 1 is determined, and based on this, a synaptic circuit array with multiple weights is designed and implemented; the constructed synaptic network is further integrated into a single-layer 3-bit neuron model, and the functional verification of this neuron is completed through functional analysis of this neuron.

2. The method for designing an ultra-low power superconducting neuron with adjustable weights according to claim 1, characterized in that: In the AQFP circuit, the energy dissipated during a switching event is proportional to the operating frequency and inversely proportional to the Q value of the Josephson junction. There is no minimum energy limit for adiabatic switching operation.

3. The method for designing an ultra-low power superconducting neuron with adjustable weights according to claim 2, characterized in that: In the AQFP circuit, the final state of the logic gate circuit is determined by the input I in The direction of I in When the input is positive, the single quantum flux Φ0 is stored in the right loop, and the circuit state is 1. in When it is a reverse input, Φ0 is stored in the left loop and the circuit state is 0; and q A large output current is generated in the q and L out The coupling between them is passed to the next level logic device; Without considering the additional threshold signal, the electrical signal flowing out of the transformer circuit acts as I in =W1X1+W2X2+…+W n X n Flow into AQFP logic gates; I q The output current of the AQFP logic in the activation circuit; The threshold circuit places an additional current source I th , the inductor couples the electrical signal to the transformer circuit of the neuron by regulating the current I th Amplitude and phase are set to different thresholds, and the signal flowing into the activation circuit becomes I in =W1X1+W2X2+…+W n X n +I th , the formula is rewritten as:

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