Design and manufacturing method for integrated chip adapter plate and adapter plate

Abstract

The invention discloses a design and manufacturing method for an integrated chip adapter plate and the adapter plate, and the design method comprises the steps: carrying out the electrical, heat transfer and mechanical analysis of a boron nitride adapter plate, and constructing a multi-physical field model; and carrying out design optimization on the boron nitride adapter plate according to the multi-physical field model to obtain optimized parameters. According to the method, the boron nitride adapter plate is designed and optimized by constructing the multi-physical field model, so that the breakthrough effects of reducing the high-frequency signal transmission loss of the boron nitride adapter plate and improving the heat dissipation efficiency are achieved. Based on precise control of optimized parameters and process parameters, the key technical problems of superhard material processing, high-density interconnection, thermal stress control and the like can be solved, and a high-reliability three-dimensional integration solution is provided for 5G communication, AI chips and high-performance calculation.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated semiconductor chips, and in particular to a design and manufacturing method for an integrated chip adapter board and the adapter board. Background Art

[0002] Integrated packaging technology plays a crucial role in the field of microelectronics. By efficiently integrating multiple functional modules into a single package, it significantly improves the performance of electronic devices. With the continuous advancement of semiconductor manufacturing technology, integrated packaging is moving towards higher density and higher performance, and has been widely used in various fields such as mobile terminals, data centers, and automotive electronics. However, the high-frequency and high-power operating conditions that accompany device miniaturization and increased functional integration have placed higher demands on the electrical, thermal, and mechanical reliability of packaging technology.

[0003] As the core carrier for high-density interconnection between chips, the material properties of the interposer directly impact the electrical and thermal reliability of the entire packaging system. Currently, mainstream silicon-based interposers (Through Silicon Via (TSV) and glass-based interposers (Through Glass Via (TGV)) face significant technical bottlenecks in meeting the requirements of high-frequency, high-speed signal transmission and high-power density heat dissipation. While three-dimensional integration technology based on through-silicon vias (TSVs) can significantly shorten interconnect lengths, improve system performance, and reduce power consumption, silicon's high dielectric constant and high conductivity make it susceptible to leakage current and signal crosstalk at high frequencies, impacting overall device reliability. On the other hand, glass, with its low thermal expansion coefficient and low dielectric constant, offers advantages in electrical insulation, making through-glass vias (TGVs) considered an alternative to TSVs. However, limitations in heat dissipation and processing make glass difficult to meet the requirements of high-power density heat dissipation, limiting its application in large-scale integrated circuits and RF devices.

[0004] In recent years, research on the application of wide-bandgap semiconductor materials in packaging has achieved breakthroughs. Cubic boron nitride (c-BN) has garnered significant attention due to its unique physical and chemical properties. Cubic boron nitride exhibits excellent in-plane thermal conductivity of 400-600 W / (m·K), a low dielectric constant of 5.1 (at 1 MHz), and a coefficient of thermal expansion of only 4.5 ppm / K. These combined performance metrics perfectly meet the stringent requirements of high-density packaging for heat dissipation efficiency, signal integrity, and mechanical reliability.

[0005] Boron nitride-based adapter plates can theoretically significantly improve the shortcomings of traditional adapter plates in high-frequency transmission and thermal management, and they have promising application prospects. However, the design and manufacturing methods of related adapter plates are currently lacking. Summary of the Invention

[0006] To overcome bottlenecks in existing technologies, such as heat dissipation and signal transmission, this invention aims to fully utilize the high thermal conductivity and low dielectric properties of boron nitride (BN) to fundamentally improve the electrothermal reliability and overall performance of the packaged module, thereby driving semiconductor integrated packaging technology toward higher density and performance. The structure of the BN adapter plate was optimized through electrical and thermodynamic analysis.

[0007] In order to achieve the above object, the present invention provides a design method of a surface-phase integrated chip adapter board, comprising: Conduct electrical, thermal, and mechanical analyses on the boron nitride adapter plate and construct a multi-physics model; The boron nitride adapter plate is designed and optimized based on the multi-physics field model to obtain the optimized parameters.

[0008] Furthermore, the multi-physics field model includes: Three-dimensional full-wave electromagnetic field simulation model, heat transfer simulation model with different orientations, heat dissipation simulation model of through-hole filling materials, and thermodynamic simulation model of boron nitride and filling materials.

[0009] Furthermore, the structure of the boron nitride adapter plate is designed and optimized according to the multi-physics field model, and the optimized parameters include: The parameters of the boron nitride adapter plate were preliminarily optimized in the preset frequency band based on the three-dimensional full-wave electromagnetic field simulation model, and the RLGC analytical model was established to verify the accuracy of the preliminarily optimized parameters and obtain the first parameters; The differences in multi-dimensional temperature distribution and equivalent thermal conductivity of the first parameter are analyzed based on heat transfer simulation models with different orientations and heat dissipation simulation models of through-hole filling materials, and the second parameter is optimized; According to the thermodynamic simulation model of boron nitride and the filling material, the thermal expansion coefficient of boron nitride and the thermal stress at the interface between the material in the through hole and the boron nitride are considered, and the second parameter is optimized to obtain the optimized parameter.

[0010] Furthermore, the optimized parameters include the crystal form of boron nitride, the material for through-hole filling, and the configuration of the through-hole.

[0011] The present invention also provides a method for manufacturing a surface-mount integrated chip adapter board. After the above-mentioned design method obtains the optimized parameters, the method further includes: The boron nitride substrate is processed to form a through hole inside, and a filling material is prepared in the through hole and then polished to obtain a preliminary product; Micro-bumps and a protective layer are prepared on the epitaxial side of the filling material in the preliminary product, and then a rewiring layer is prepared on the upper surface of the micro-bumps and the protective layer to obtain a surface-mount integrated chip adapter board.

[0012] Furthermore, the through hole is formed by laser etching; The filling material is obtained by growing a seed layer and then electroplating; The wiring layer is prepared by a Damascene process.

[0013] Preferably, the boron nitride substrate is also pretreated before processing, and the pretreatment includes using HNO3:HCl=3:1 mixed pickling to remove surface contaminants, followed by Ar / O2 plasma activation treatment (power 200-500W, duration 3-8min) to make the surface roughness Ra <10nm, the contact angle <5°, and the metal adhesion strength increased to 35MPa.

[0014] During the laser etching process, a through-hole structure meeting the design requirements is fabricated on a pretreated boron nitride substrate using a laser etching process. This process utilizes a high-energy pulsed laser beam to instantaneously melt and vaporize the material, thus avoiding the issues of etching stagnation and difficult morphology control encountered in traditional dry etching. Furthermore, thanks to boron nitride's excellent thermal stability and laser absorption properties, structural damage caused by thermal stress and microcracks is effectively avoided during the laser etching process, ensuring consistent through-hole depth and sidewall integrity.

[0015] Furthermore, the laser light source is a nanosecond laser with a power of 200-500W, a single pulse energy of 3-10mJ, a repetition frequency of 30-80kHz, and a scanning speed of 100-300mm / s, which realizes through-hole processing and ensures that the through-hole has high precision, regular morphology, high verticality and low heat-affected zone.

[0016] The process of growing the seed layer specifically includes sputtering the seed layer on the upper and lower surfaces of the through-hole, so that the seed layer is deposited simultaneously at the upper and lower entrances of the through-hole and gradually extends toward the middle, thereby improving the uniformity and continuity of the seed layer coating on the hole wall. This method is expected to improve the overall quality of the seed layer in high aspect ratio through-holes, and provide a good foundation for the subsequent stable and uniform electroplated copper filling. Preferably, a physical vapor deposition (PVD) process is used for sputtering deposition of the seed layer. Using a magnetron sputtering process, by adjusting the process parameters, the metal is uniformly deposited at the upper and lower entrances of the through-hole, and gradually extends toward the middle, thereby improving the uniformity and continuity of the seed layer coating on the hole wall. Exemplarily, the process is a substrate temperature of 10-30°C, a background vacuum of 3-8×10 -6Under 100-200 Torr conditions, the adhesion layer (power 100-300W, Ar flow rate 20-30sccm) and the conductive layer (power 250-500W, deposition rate 0.5-1.0μm / min) were sequentially deposited, achieving >95% coverage of the via inner wall. The resulting seed layer had a thickness of approximately 0.5-0.7μm at the entrance and 1.2-1.5μm in the middle of the via, providing an excellent foundation for subsequent stable and uniform electroplating fill.

[0017] Electroplating achieved void-free filling (void ratio <0.1%) at a constant current of 20-50 mA under 0.5-2 L / min airflow conditions and in pulsed reverse current (PRC) mode (forward 2-5 ASD / 10 ms, reverse 0.5-2 ASD / 1 ms), with a filling rate of 12-18 μm / h.

[0018] Furthermore, the thicknesses of the micro-bumps and the protective layer are 15±1 μm and 200±20 nm respectively.

[0019] The present invention also provides a surface-mount integrated chip adapter board, which is obtained by adopting the above-mentioned manufacturing method.

[0020] Furthermore, the material filled in the through hole includes at least one of solid metal, solid metal alloy, and carbon material; The configuration parameters of the through-holes include a taper of <1°, an edge chipping width of less than 2μm, a depth of 40-60μm, a spacing of 10-20μm, and a radius of 2-3μm.

[0021] The present invention also provides an application of the above-mentioned face-to-face integrated chip adapter board in chip integration, wherein the chip to be integrated is flipped and connected to the wiring layer.

[0022] Compared with the prior art, the present invention has the following beneficial effects: This invention optimizes the design of a boron nitride adapter plate by constructing a multi-physics model, achieving breakthrough results in reducing high-frequency signal transmission losses and improving heat dissipation efficiency. The invention's precise control of optimization and process parameters addresses key technical challenges such as superhard material processing, high-density interconnection, and thermal stress control, providing a highly reliable three-dimensional integrated solution for 5G communications, AI chips, and high-performance computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A flow chart showing a method for designing a surface-mount integrated chip adapter board according to Example 1 is shown; Figures 2(a)-2(d) show the return loss, insertion loss, reverse return loss, and reverse insertion loss results of adapter plates made of different materials, respectively. Figures 3(a)-3(c) show the return loss graphs of the c-BN adapter board with different thicknesses, different copper pillar spacings, and different copper pillar radii, respectively; Figures 4(a)-4(d) show the comparison between the HFSS simulation model and the ADS simulation results of the return loss, insertion loss, reverse return loss, and reverse insertion loss of the c-BN adapter board, respectively. Figures 5(a)-5(b) show the heat transfer analysis results of adapter plates made of different materials at different orientations; Figure 6 The basic architecture of the copper through-hole heat dissipation simulation model and the heat dissipation analysis results of chip integration built with adapter boards of different materials are shown; Figures 7(a) to 7(e) show the thermodynamic simulation results of adapter plates made of Si, glass, c-BN, h-BN, and w-BN, respectively; Figure 8 The application flow chart of the integrated chip adapter board of Example 2 is shown; Figure 9 A schematic diagram of the structure of a product prepared by the application process for an integrated chip adapter board is shown; Description of reference numerals: 1. Pre-treated substrate; 2. Through-hole structure; 3. Seed layer; 4. Electroplating layer; 5. Polished surface; 6. Protective layer; 7. Micro-bumps; 8. Dielectric layer; 9. Rewiring layer; 10. Chip. DETAILED DESCRIPTION

[0025] The endpoints of the ranges and any values ​​disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values ​​can be combined with each other to form one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed in the present invention.

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the specific embodiments of the present invention and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0027] Example 1 A design method for a surface-mount integrated chip adapter board, such as Figure 1 As shown, it includes the following steps, T1. Conduct electrical, heat transfer, and mechanical analyses on the boron nitride adapter plate and construct a multi-physics model. As a typical implementation method, the through-hole processing of the adapter plate adopts a laser process. In this embodiment, the cross-section of the through-hole is preset to a circle. At the same time, according to the currently mature and relatively cheap process, the filling material in the through-hole is preset to copper, that is, the through-hole contains a copper column. The subsequent analysis of this embodiment is carried out in accordance with these prerequisites. However, it should be noted that the specific cross-sectional shape of the through-hole and the filling material in the through-hole do not need to be limited. Based on certain specific conditions, the corresponding optimized parameters can be obtained based on the design concept of this embodiment. For example, the filling material in the through-hole is preset to gold, silver, graphene, etc., and the cross-section of the through-hole is set to a rectangle for simulation design.

[0028] For interposers made of different materials, the multiphysics models are constructed based on the same structural parameters: the thickness and through-hole structure of the interposer are identical; the through-holes are made of copper, forming copper pillars (copper vias), while the interposer materials vary. Interposer materials include silicon, glass, cubic boron nitride (c-BN), hexagonal boron nitride (h-BN), and wurtzite boron nitride (w-BN).

[0029] A three-dimensional full-wave electromagnetic field simulation model was constructed using ANSYS HFSS. An ANSYS Icepak simulation model for heat transfer in different orientations was established. The heat dissipation simulation model for the copper vias included the adapter plate and the copper pillars within it, the microbumps and protective layer on the epitaxial side of the copper pillars, the wiring layer above the microbumps, and the chip connected to the wiring layer. The thermodynamic simulation model for boron nitride and copper vias used structural parameters consistent with those used in the heat transfer simulation model in different orientations to ensure the accuracy and consistency of the calculation results.

[0030] T2. Optimize the design of the boron nitride adapter plate based on the multi-physics field model to obtain the optimized parameters Conduct electrical analysis based on the three-dimensional full-wave electromagnetic field simulation model (HFSS simulation model) in the preset frequency band 0GHz-100GHz, with the adapter plate thickness (H) of 40-60μm, the copper column spacing (P) of 10-20μm, and the copper column radius R Cu The reference structure is 2-3μm, the radiation boundary is set as a perfect matching layer, the metal surface is set as an ideal conductor, the excitation uses a wave port with a common-mode differential pair, and the grid division uses an equilateral triangle division method with dynamic surface resolution. The return loss (S11), insertion loss (S21), reverse return loss (S22), and reverse insertion loss (S12) of adapter plates made of different materials are analyzed. As shown in Figures 2 (a)-2 (d), the results show that at 0-100GHz, the return loss and reverse return loss of the c-BN adapter plate are both less than -20dB, the insertion loss and reverse insertion loss are both greater than -0.5dB, and the signal integrity can meet the requirements of signal transmission. Subsequently, the structural parameters of the c-BN adapter plate, including H, P and R Cu , the impact on the signal integrity of the copper through hole c-BN adapter board is analyzed, and preliminary optimization is performed, as shown in Figure 3 (a)-3 (c), and the parameters are obtained, and c-BN material is selected; the specific configuration of the copper through hole, the structural parameters with the best electrical performance parameters are H 40-50μm, P 15-18μm, and R Cu The RLGC equivalent circuit model is constructed by extracting the resistance (R), inductance (L), conductance (G), and capacitance (C) per unit length based on distributed transmission line theory. The DAC (Data Access Component) module in the Advanced Design System (ADS) is used to perform RLGC analysis to track frequency variations and further verify the effectiveness of the initially optimized parameters. A π-type equivalent circuit topology is employed, with the copper pillars equivalent to series RL branches and the dielectric layers equivalent to parallel GC networks, ultimately forming a multi-segment cascade model. The consistency of the initially optimized parameters with the equivalent circuit analysis results based on the RLGC analysis over a wide frequency range verifies the effectiveness of the established RLGC model in describing the parasitic effects of c-BN interposers with copper vias. Compared to finite element models, the RLGC analytical model simplifies high-frequency signal operations and reduces computational effort, while maintaining high accuracy within a certain frequency range. It is suitable for simulations of large-scale, complex integrated packages. As shown in Figures 4(a)-4(d), the simulation results of the three-dimensional full-wave electromagnetic field simulation model constructed in the 0-100 GHz frequency band verified by the RLGC analytical model have an error of less than 5%. In the later process optimization stage of packaging design, parameterized design can be implemented based on the RLGC equivalent circuit model to meet the loss tolerance requirements of different application scenarios, effectively reducing the amount of calculation while ensuring model accuracy.

[0031] The length and width of the heat transfer simulation model with different orientations are both 15μm, and the single copper pillar is further optimized. The H of the copper pillar is 40-60μm, and R Cu The 2-3 μm grid is refined by unstructured mesh (set to 0.1 μm in the horizontal direction and 0.2 μm in the vertical direction) and the ambient convection boundary (25 ° C, 10 W / (m 2 K)), simulate the horizontal (XY plane) and vertical (Z direction) heat flow paths, compare and analyze the heat distribution of different materials in the horizontal and vertical directions, and further calculate H for 40-60μm, R Cu As shown in Figure 5 (a) and Figure 5 (b), the results show that the c-BN adapter plate exhibits the best thermal conductivity efficiency in the horizontal and vertical directions, and can provide a more uniform temperature distribution. When H is 50μm, R Cu When the thickness is 2.5 μm, it exhibits strong heat transfer capabilities in both horizontal and vertical directions.

[0032] like Figure 6 The copper via heat dissipation simulation model shown in the figure is a design model for the interposer package. It is based on the interposer structure and the chip connected to it. The interposer structure consists of an interposer and a filler layer. The interposer contains an array of copper pillars, with microbumps attached to the epitaxial sides of the upper ends of the pillars. The microbumps are filled with a protective layer, and a wiring layer (not shown) is placed above the microbumps and the protective layer. The filler layer is connected to the interposer and contains microfluidic channels. The substrate measures 4 mm in length and width and is 50 μm thick. The chip itself measures 2 × 2 mm and is 100 μm thick. The microfluidic channels spanning the entire substrate are 30 μm wide and 25 μm high. Each microbump has a radius of 5 μm and corresponds to a copper via. During the simulation, the initial ambient temperature was set at 20°C, and the coolant flow rate in the microfluidic channels was 5 m / s. The thermal management performance of interposers made of different materials was evaluated under actual operating conditions. The results show that the c-BN interposer exhibits the best heat dissipation performance.

[0033] During the temperature rise process, the thermal expansion responses of different materials will differ due to their different thermal expansion coefficients and elastic properties, thus forming a thermal stress gradient at the interface or multi-material connection. According to the thermodynamic simulation model of different adapter plate materials and copper through-holes, the thermal expansion coefficients of different adapter plate materials, the thermal stress at the interface between the copper pillars in the through-holes and different adapter plate materials are considered, and the thermal stress and material mechanical properties are comprehensively considered according to the above structural parameters. By analyzing the temperature distribution and warping deformation under different working conditions, the structural reliability and stability are judged. If the expected results are not met, the structure is redesigned until the structure is reliable. If it meets the expectations, it will be prepared according to the structural parameters. It can be seen from Figure 7 (a) to Figure 7 (d) that the c-BN adapter plate has better stability under the same temperature field changes. At the same time, it is verified that the optimized configuration parameters of the heat transfer simulation model with different orientations meet the design requirements. Finally, the adapter plate material is selected as c-BN, H is 50μm, P is 15μm, and R is 15μm. Cu 2.5μm.

[0034] Example 2 The parameters obtained by the design method of Example 1 are used to manufacture an integrated chip adapter board, and applied in the field of chip integration, including the following steps: S101, cubic boron nitride (c-BN) substrate material pretreatment The surface contaminants of the c-BN substrate were removed by mixed pickling with HNO3:HCl=3:1, followed by Ar / O2 plasma activation treatment (power 300W, duration 5min), which reduced the surface roughness Ra to <10nm, the contact angle to <5°, and the metal adhesion strength to 35MPa.

[0035] S102: Using laser etching process to prepare through-hole structure on boron nitride substrate On the pretreated substrate 1, a laser etching process is used to create a through-hole structure 2 that meets the design requirements. This process utilizes a high-energy pulsed laser beam to instantaneously melt and vaporize the material, thus avoiding the issues of etching stagnation and difficult morphology control encountered in traditional dry etching. Furthermore, thanks to the excellent thermal stability and laser absorption properties of c-BN, structural damage caused by thermal stress and microcracks is effectively avoided during the laser etching process, ensuring consistent through-hole depth and sidewall integrity.

[0036] Furthermore, the laser light source is a 300W nanosecond laser with a single pulse energy of 5mJ, a repetition rate of 50kHz, and a scanning speed of 200mm / s. Through the instantaneous melting and vaporization of the high-energy pulsed laser, a microhole array with an H of 50±1μm, a P of 15±0.5μm, and an R of 2.5±0.2μm is processed on the substrate. The high thermal conductivity of the c-BN material is fully utilized to control the depth of the heat-affected zone to 0.42±0.08μm, the hole wall taper reaches 0.8°±0.2°, and the edge crack width is <1.7±0.3μm, which effectively improves the morphology accuracy compared to the traditional dry etching process. The depth consistency deviation is detected by white light interferometer, and the through-hole spacing accuracy is analyzed by optical microscope.

[0037] S103, depositing a seed layer by double-sided PVD process The seed layer 3 is deposited on both the upper and lower surfaces of the adapter plate through a sputtering process. This allows the seed layer 3 to be deposited simultaneously at the upper and lower entrances of the through-hole and gradually extends toward the center, improving the uniformity and continuity of the seed layer 3 coating on the hole walls. This method is expected to improve the overall quality of the seed layer 3 in high-aspect-ratio through-holes, providing a good foundation for subsequent stable and uniform electroplated copper filling.

[0038] Furthermore, a physical vapor deposition (PVD) process was used to sputter-deposit a metal seed layer on the upper and lower surfaces of the adapter plate and the inner wall of the through-hole. Using a magnetron sputtering process, by adjusting process parameters, the metal was uniformly deposited at the upper and lower entrances of the through-hole and gradually extended toward the middle, thereby improving the uniformity and continuity of the seed layer coating on the hole wall. The process was carried out at a substrate temperature of 20°C and a background vacuum of 5×10 -6 Under 10-100 Torr conditions, a 50nm Ti adhesion layer (power 200W, Ar flow rate 25sccm) and a 1.5μm Cu conductive layer (power 350W, deposition rate 0.8μm / min) were deposited in sequence, with the through-hole inner wall coverage >95%.

[0039] S104, through-hole plating filling Polyethylene glycol (PEG8000) was used as an inhibitor, sodium polydisulfide propanesulfonate (SPS) as an accelerator, and sodium thiazolinyl disulfide propanesulfonate (SH110) as a leveler. Electroplating was performed at room temperature with a constant current of 30 mA and an airflow of 1 L / min for 4 hours. Prior to plating, the Haring cell was rinsed with clean water for 5 minutes, then with deionized water. The equipment and test samples were rinsed with a well-mixed plating solution to ensure sample cleanliness. The plating solution ratio is CuSO4·5H2O (230g / L), NaCl (50g / L), H2SO4 (80g / L), SPS (3g / L), PEG8000 (200g / L) and SH110 (4g / L); under the pulsed reverse current (PRC) mode (forward 3ASD / 10ms, reverse 1ASD / 1ms), void-free filling (void ratio <0.1%) is achieved, and the filling rate reaches 15μm / h.

[0040] After this step, a copper column is formed in the through hole, and there is an excess electroplating layer 4 on the outside.

[0041] S105, Chemical Mechanical Polishing (CMP) and subsequent processing CMP was used to remove the excess electroplating layer 4. In the rough polishing stage, SiO2 abrasive (particle size 0.5 μm, pressure 3 psi) was used to achieve a removal rate of 800 nm / min. In the fine polishing stage, CeO2 abrasive (particle size 0.1 μm, pressure 1 psi) was used to reduce the surface roughness Ra to < 2 nm, resulting in a polished surface 5.

[0042] S106, preparing micro bumps and surface protection layer Microbumps 7 were formed by electroplating SnAgCu material on top of the copper vias. A photoresist mold (opening diameter 25±1μm) was used, with a plating current density of 4±0.5ASD, a temperature of 50±2°C, and a deposition rate of 12±1μm / h. The final height of microbumps 7 was 15±1μm. A 200±20nm thick protective layer 6 of silicon nitride was deposited on the non-functional areas using a PECVD process with a SiH4 / NH3 ratio of 1:3 and an RF power of 300W.

[0043] S107, build rewiring layer A 2.0±0.2μm thick SiO2 dielectric layer 8 is deposited (PECVD process, TEOS / O2=1:4), and a multi-layer copper redistribution layer 9 is formed by a dual damascene process, with a line width / spacing of 2±0.1μm / 2±0.1μm and a through-hole diameter of 10±0.5μm.

[0044] S108, Chip Integration The chip 10 is flipped and interconnected with the redistribution layer 9 by using a thermocompression bonding process (pressure 100±10 MPa, temperature 240±5° C., time 20±2 s).

[0045] After 1000 cycles of -55°C to 125°C thermal cycling testing, the chip integrated structure of this embodiment showed an interface shear strength retention rate of >95% and a contact resistance change rate of <2%, fully meeting the requirements of current packaging processes.

[0046] In summary, this invention introduces cubic boron nitride (c-BN) into the field of adapter board manufacturing for the first time, establishing a comprehensive "material-structure-process" technical solution. Leveraging c-BN's high thermal conductivity, low dielectric constant, and excellent thermal matching properties, combined with a through-hole array design and a laser-electroplating composite process, this breakthrough achieves reduced high-frequency signal transmission losses and improved heat dissipation efficiency. Through precise control of process parameters, this approach addresses key technical challenges such as ultrahard material processing, high-density interconnection, and thermal stress control, providing a highly reliable three-dimensional integrated solution for 5G communications, AI chips, and high-performance computing.

[0047] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A design method for a surface-mount integrated chip adapter board, characterized in that: include, Conduct electrical, thermal, and mechanical analyses on the boron nitride adapter plate and construct a multi-physics model; The boron nitride adapter plate is designed and optimized based on the multi-physics field model to obtain the optimized parameters.

2. The design method of the surface-integrated chip adapter board according to claim 1, characterized in that: The multi-physics model includes: Three-dimensional full-wave electromagnetic field simulation model, heat transfer simulation model with different orientations, heat dissipation simulation model of through-hole filling materials, and thermodynamic simulation model of boron nitride and filling materials.

3. The design method of the surface-phase integrated chip adapter board according to claim 2, characterized in that: The boron nitride adapter plate is designed and optimized according to the multi-physics field model, and the optimized parameters include: The parameters of the boron nitride adapter plate were preliminarily optimized in the preset frequency band based on the three-dimensional full-wave electromagnetic field simulation model, and the RLGC analytical model was established to verify the accuracy of the preliminarily optimized parameters and obtain the first parameters; The differences in multi-dimensional temperature distribution and equivalent thermal conductivity of the first parameter are analyzed based on heat transfer simulation models with different orientations and heat dissipation simulation models of through-hole filling materials, and the second parameter is optimized; According to the thermodynamic simulation model of boron nitride and the filling material, the thermal expansion coefficient of boron nitride and the thermal stress at the interface between the material in the through hole and the boron nitride are considered, and the second parameter is optimized to obtain the optimized parameter.

4. The method for designing a surface-integrated chip adapter board according to any one of claims 1 to 3, characterized in that: The optimized parameters include the crystal form of boron nitride, the material for through-hole filling, and the configuration of the through-hole.

5. A method for manufacturing a surface-mount integrated chip adapter board, characterized in that: After obtaining the optimized parameters according to the design method according to any one of claims 1 to 4, the method further comprises: The boron nitride substrate is processed to form a through hole inside, and a filling material is prepared in the through hole and then polished to obtain a preliminary product; Micro-bumps and a protective layer are prepared on the epitaxial side of the filling material in the preliminary product, and then a rewiring layer is prepared on the upper surface of the micro-bumps and the protective layer to obtain a surface-mount integrated chip adapter board.

6. The method for manufacturing a surface-integrated chip adapter board according to claim 5, characterized in that: The through hole is formed by laser etching; The filling material is obtained by growing a seed layer and then electroplating; The wiring layer is prepared by a Damascene process.

7. The method for manufacturing a surface-integrated chip adapter board according to claim 5, characterized in that: The thicknesses of the micro-bumps and the protective layer are 15±1 μm and 200±20 nm respectively.

8. A surface-mount integrated chip adapter board, characterized in that: The method is obtained by the manufacturing method according to any one of claims 5 to 7.

9. The surface-mount integrated chip adapter board according to claim 8, characterized in that: The material filled in the through hole includes at least one of a solid metal element, a solid metal alloy, and a carbon material; The configuration parameters of the through-holes include a taper of <1°, an edge chipping width of less than 2μm, a depth of 40-60μm, a spacing of 10-20μm, and a radius of 2-3μm.

10. An application of the surface-integrated chip adapter board according to claim 8 or 9 in chip integration, characterized in that: The chip to be integrated is flipped over and connected to the wiring layer.

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