Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the following steps: providing a substrate; forming a device structure on the substrate; etching the substrate at two sides of the device structure to form a groove extending into the substrate; forming an interlayer dielectric layer on the device structure, wherein the trench is filled with the interlayer dielectric layer; wherein the interlayer dielectric layer in the trench is of a shallow trench isolation structure. According to the technical scheme, the process period for manufacturing the semiconductor device is shortened.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Currently, the manufacturing method of a semiconductor device includes: forming a pad oxide layer and a hard mask layer on a substrate; forming a trench through the hard mask layer and the pad oxide layer and extending into the substrate through photolithography and etching processes; depositing an insulating material on the hard mask layer in the trench and on the periphery of the trench, and planarizing the insulating material to form a shallow trench isolation structure to define the active area; removing the hard mask layer and the pad oxide layer; forming a device structure in the active area; forming an etch stop layer to cover the shallow trench isolation structure and the device structure; forming an interlayer dielectric layer on the etch stop layer; and planarizing the interlayer dielectric layer. In the manufacturing process of the above-mentioned semiconductor device, the process of defining the active area is complex and time-consuming, resulting in an excessively long overall process cycle for manufacturing the semiconductor device. The above-mentioned semiconductor device is, for example, a CMOS device.

[0003] Therefore, how to improve the manufacturing process of semiconductor devices to reduce the process cycle is an issue that needs to be solved urgently. Summary of the Invention

[0004] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so that the process cycle of manufacturing the semiconductor device is reduced.

[0005] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] providing a substrate;

[0007] forming a device structure on the substrate;

[0008] Etching the substrate on both sides of the device structure to form trenches extending into the substrate;

[0009] forming an interlayer dielectric layer on the device structure, wherein the interlayer dielectric layer fills the trench;

[0010] Wherein, the interlayer dielectric layer in the trench is a shallow trench isolation structure.

[0011] Optionally, the step of forming the device structure on the substrate includes:

[0012] forming a well region in the substrate;

[0013] forming a gate structure on the well region;

[0014] forming a lightly doped source region and a lightly doped drain region in the well region on both sides of the gate structure, wherein the lightly doped source region and the lightly doped drain region both extend to below the gate structure;

[0015] forming a sidewall spacer on the sidewall of the gate structure;

[0016] forming a source region and a drain region in the well region on both sides of the gate structure, wherein the source region and the drain region both extend from the substrate outside the sidewall to below the sidewall;

[0017] A metal silicide layer is formed on the surfaces of the source region and the drain region.

[0018] Optionally, before etching the substrate on both sides of the device structure, the method for manufacturing the semiconductor device further includes:

[0019] forming an etch stop layer on the device structure and the substrate;

[0020] The etch stop layer and the substrate on both sides of the device structure are etched to form the trench.

[0021] Optionally, the method for manufacturing the semiconductor device further includes:

[0022] A first contact plug is formed, wherein the first contact plug penetrates the interlayer dielectric layer to be electrically connected to the device structure.

[0023] Optionally, the substrate is an SOI substrate, and the SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer; the method for manufacturing the semiconductor device further includes:

[0024] A second contact plug is formed penetrating the interlayer dielectric layer above and in the trench and the buried insulating layer below the trench, wherein the second contact plug is electrically connected to the underlying substrate.

[0025] Optionally, the substrate includes a seal ring region surrounding the device structure and the trench; before forming the device structure on the substrate, the method for manufacturing the semiconductor device further includes:

[0026] An alignment mark is formed in the substrate in the seal ring area.

[0027] The present invention also provides a semiconductor device, comprising:

[0028] substrate;

[0029] a device structure formed on the substrate;

[0030] trenches formed in the substrate on both sides of the device structure;

[0031] An interlayer dielectric layer is formed on the device structure, and the interlayer dielectric layer fills the trench, wherein the interlayer dielectric layer in the trench is a shallow trench isolation structure.

[0032] Optionally, the device structure includes:

[0033] a well region formed in the substrate;

[0034] a gate structure formed on the well region;

[0035] A lightly doped source region and a lightly doped drain region are formed in the well region on both sides of the gate structure, and both the lightly doped source region and the lightly doped drain region extend below the gate structure;

[0036] A sidewall spacer formed on a sidewall of the gate structure;

[0037] A source region and a drain region are formed in the well region on both sides of the gate structure, and both the source region and the drain region extend from the substrate outside the sidewall to below the sidewall;

[0038] A metal silicide layer is formed on the surfaces of the source region and the drain region.

[0039] Optionally, the semiconductor device further includes:

[0040] An etch stop layer is formed between the device structure and the interlayer dielectric layer, and the trench penetrates the etch stop layer.

[0041] Optionally, the semiconductor device further includes:

[0042] A first contact plug penetrates the interlayer dielectric layer to be electrically connected to the device structure.

[0043] Optionally, the substrate is an SOI substrate, and the SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer; the semiconductor device further includes:

[0044] A second contact plug penetrates the interlayer dielectric layer above and in the trench and the buried insulating layer below the trench, and is electrically connected to the underlying substrate.

[0045] Optionally, the substrate includes a seal ring area surrounding the device structure and the trench, and an alignment mark is formed in the substrate in the seal ring area.

[0046] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0047] 1. The method for manufacturing a semiconductor device of the present invention comprises: providing a substrate; forming a device structure on the substrate; etching the substrate on both sides of the device structure to form trenches extending into the substrate; forming an interlayer dielectric layer on the device structure, with the interlayer dielectric layer filling the trench; wherein the interlayer dielectric layer in the trench is a shallow trench isolation structure. This method reduces the process cycle for manufacturing the semiconductor device.

[0048] 2. The semiconductor device of the present invention comprises: a substrate; a device structure formed on the substrate; trenches formed in the substrate on both sides of the device structure; and an interlayer dielectric layer formed on the device structure, the interlayer dielectric layer filling the trenches, wherein the interlayer dielectric layer in the trenches is a shallow trench isolation structure. This reduces the process cycle for manufacturing the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0050] Figure 2a to Figure 2l yes Figure 1 Schematic diagram of a device in a method for manufacturing a semiconductor device shown.

[0051] Among them, Figures 1 to 21 The reference numerals are described as follows:

[0052] 10-substrate; 101-lower substrate; 102-buried insulating layer; 103-semiconductor layer; 111-first well region; 112-second well region; 1201-gate dielectric material layer; 1202-gate material layer; 121-first gate dielectric layer; 122-first gate layer; 123-second gate dielectric layer; 124-second gate layer; 131-first lightly doped source region; 132-first lightly doped drain region; 133-second lightly doped source region; 134-second lightly doped drain region; 14-sidewall; 151-first source region; 152-first drain region; 153-second source region; 154-second drain region; 16-metal silicide layer; 17-etching stop layer; 18-interlayer dielectric layer; 181-trench; 191-first contact plug; 192-second contact plug. DETAILED DESCRIPTION

[0053] To make the objects, advantages, and features of the present invention more apparent, the semiconductor device and its manufacturing method proposed by the present invention are further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the purpose of the embodiments of the present invention.

[0054] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 , Figure 1 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method for manufacturing a semiconductor device comprising:

[0055] Step S1, providing a substrate;

[0056] Step S2, forming a device structure on the substrate;

[0057] Step S3, etching the substrate on both sides of the device structure to form trenches extending into the substrate;

[0058] Step S4: forming an interlayer dielectric layer on the device structure, and the interlayer dielectric layer fills the trench; wherein the interlayer dielectric layer in the trench is a shallow trench isolation structure.

[0059] See below Figure 2a to Figure 2l The manufacturing method of the semiconductor device provided in this embodiment is introduced in more detail.

[0060] Follow step S1, refer to Figure 2a , providing a substrate 10.

[0061] The substrate 10 is a bulk substrate or a SOI (Semiconductor-On-Insulator) substrate.

[0062] exist Figure 2a to Figure 2l In the illustrated embodiment, the substrate 10 is an SOI substrate, which includes, from bottom to top, a lower substrate 101 , an insulating buried layer 102 , and a semiconductor layer 103 .

[0063] The bulk substrate, the lower substrate 101 and the semiconductor layer 103 may be made of any suitable semiconductor material, including but not limited to: Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors and other semiconductor materials, and the insulating buried layer 102 is, for example, a silicon oxide layer.

[0064] The substrate 10 may be a silicon substrate.

[0065] According to step S2 , a device structure is formed on the substrate 10 .

[0066] At least one device structure may be formed on the substrate 10. Figure 2a to Figure 2l In the illustrated embodiment, two device structures are formed on the substrate 10 .

[0067] The substrate 10 includes a seal ring region (not shown) surrounding the at least one device structure. The periphery of the seal ring region is a dicing street, and chips are cut along the dicing street.

[0068] Preferably, before forming the device structure on the substrate 10, the manufacturing method of the semiconductor device also includes: forming an alignment mark (not shown) in the substrate 10 in the sealing ring area, so that the alignment mark can be used for alignment when the device structure is subsequently manufactured, and the alignment mark is located in the sealing ring area to avoid affecting the pattern of the device structure.

[0069] In one embodiment, the step of forming the alignment mark includes: aligning with a notch at an edge of the substrate 10 , performing photolithography and etching processes to form a groove in the substrate 10 in the seal ring area as the alignment mark.

[0070] In one embodiment, the steps of forming the device structure on the substrate 10 include: forming a well region in the substrate 10; forming a gate structure on the well region; forming a lightly doped source region and a lightly doped drain region in the well region on both sides of the gate structure, with the lightly doped source region and the lightly doped drain region both extending below the gate structure; forming sidewalls on the sidewalls of the gate structure; forming a source region and a drain region in the well region on both sides of the gate structure, with the source region and the drain region both extending from the substrate outside the sidewalls to below the sidewalls; and forming a metal silicide layer on the surface of the source region and the drain region. The device structure is a MOS transistor. It should be noted that the composition of the device structure is not limited to the structure formed in the above steps.

[0071] In one embodiment, the device structure may include a gate stack structure or a SONOS structure, and the gate stack structure includes a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate.

[0072] In other embodiments, the metal silicide layer may also be formed on the surface of the gate structure.

[0073] The gate structure includes a gate dielectric layer and a gate layer stacked from bottom to top on the well region.

[0074] Taking the substrate 10 as an example in which two device structures are formed on the substrate 10 and the substrate 10 is an SOI substrate, the steps of forming the device structures on the substrate 10 may include: Figure 2b As shown, a photolithography process and an ion implantation process are performed to form a first well region 111 and a second well region 112 in the semiconductor layer 103. The first well region 111 and the second well region 112 may be located in a portion of the thickness of the semiconductor layer 103 or in the entire thickness. Figure 2cAs shown, a gate dielectric material layer 1201 and a gate material layer 1202 are sequentially formed and stacked on the semiconductor layer 103, and the gate dielectric material layer 1201 and the gate material layer 1202 cover the first well region 111 and the second well region 112; Figure 2d As shown, the gate material layer 1202 is etched to form a first gate layer 122 above the first well region 111, and a second gate layer 124 is formed above the second well region 112; Figure 2e As shown, a photolithography process and an ion implantation process are performed to form a first lightly doped source region 131 and a first lightly doped drain region 132 in the first well region 111 on both sides of the first gate layer 122, and a second lightly doped source region 133 and a second lightly doped drain region 134 in the second well region 112 on both sides of the second gate layer 124. The first lightly doped source region 131 and the first lightly doped drain region 132 both extend below the first gate layer 122, and the second lightly doped source region 133 and the second lightly doped drain region 134 both extend below the second gate layer 124. Figure 2f As shown, a deposition process and an etching process are performed to form sidewalls 14 on the sidewalls of the first gate layer 122 and the second gate layer 124, and the gate dielectric material layer 1201 is also etched to form a first gate dielectric layer 121 and a second gate dielectric layer 123. The first gate dielectric layer 121 extends from between the first gate layer 122 and the first well region 111 to between the sidewalls 14 on both sides and the first well region 111. The second gate dielectric layer 123 extends from between the second gate layer 124 and the second well region 112 to between the sidewalls 14 on both sides and the second well region 112. The first gate dielectric layer 121 and the first gate layer 122 constitute a first gate structure, and the second gate dielectric layer 123 and the second gate layer 124 constitute a second gate structure. Figure 2g As shown, a photolithography process and an ion implantation process are performed to form a first source region 151 and a first drain region 152 in the first well region 111 on both sides of the first gate structure, and a second source region 153 and a second drain region 154 are formed in the second well region 112 on both sides of the second gate structure. The first source region 151 and the first drain region 152 both extend from the first well region 111 outside the corresponding spacer 14 to below the spacer 10, and the second source region 153 and the second drain region 154 both extend from the second well region 112 outside the corresponding spacer 14 to below the spacer 10. The first source region 151, the first drain region 152, the second source region 153 and the second drain region 154 may be located in a partial thickness or the entire thickness of the semiconductor layer 103; as shown in FIG. Figure 2hAs shown, a metal silicide layer 16 is formed on the surfaces of the first source region 151 , the first drain region 152 , the second source region 153 and the second drain region 154 .

[0075] In one embodiment, the two device structures are two different MOS transistors, such as NMOS and PMOS, or one of the MOS transistors is used to make a low noise amplifier (LNA) and the other MOS transistor is used to make a radio frequency switch (RFSwitch).

[0076] In each of the device structures, the lightly doped source region, the lightly doped drain region, the source region and the drain region have the same doping type, the well region has a doping type opposite to that of the lightly doped source region, the doping concentrations of the lightly doped source region and the lightly doped drain region are lower than the doping concentrations of the source region and the drain region, and the depths of the lightly doped source region and the lightly doped drain region are less than the depths of the source region and the drain region.

[0077] like Figure 2i As shown, before subsequently etching the substrate 10 on both sides of the device structure, the method for manufacturing the semiconductor device further includes: forming an etch stop layer 17 on the device structure and the substrate 10 .

[0078] exist Figure 2i In the illustrated embodiment, the etch stop layer 17 covers the metal silicide layer 16 , the first gate dielectric layer 121 , the first gate layer 122 , the second gate dielectric layer 123 , the second gate layer 124 and the sidewall spacer 14 .

[0079] The etch stop layer 17 may be made of at least one insulating material selected from the group consisting of silicon oxynitride, silicon nitride, and nitrogen-doped carbon.

[0080] According to step S3, Figure 2j As shown, the substrate 10 on both sides of the device structure is etched to form trenches 181 extending into the substrate 10 .

[0081] The area surrounded by the trench 181 is the active area, and the seal ring area surrounds the trench 181 and the active area.

[0082] When the etch stop layer 17 is also formed on the device structure and the substrate 10, in the process of etching to form the groove 181, the etch stop layer 17 on both sides of the device structure is first etched, and then the substrate 10 is further etched using the etched etch stop layer 17 as a hard mask, that is, the etch stop layer 17 serves as a hard mask to define the active area.

[0083] In each of the device structures, the depth of the trench 181 is greater than or equal to the depths of the source region and the drain region.

[0084] When the substrate 10 is an SOI substrate, the trench 181 preferably penetrates the semiconductor layer 103 to expose the buried insulating layer 102 .

[0085] According to step S4, Figure 2k As shown, an interlayer dielectric layer 18 is formed on the device structure, and the interlayer dielectric layer 18 fills the trench 181 .

[0086] The interlayer dielectric layer 18 in the trench 181 can serve as a shallow trench isolation structure.

[0087] The interlayer dielectric layer 18 can be a single-layer structure or a multi-layer stacked structure.

[0088] The interlayer dielectric layer 18 may be made of at least one insulating material selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride, and nitrogen-doped carbon.

[0089] The method for manufacturing the semiconductor device further includes: planarizing the interlayer dielectric layer 18 .

[0090] Since the uneven device structure and the trench 18 are formed on the substrate 10 , the surface of the interlayer dielectric layer 18 is uneven. Therefore, a planarization process is performed on the surface of the interlayer dielectric layer 18 .

[0091] The interlayer dielectric layer 18 may be planarized by using a chemical mechanical polishing process.

[0092] like Figure 2l As shown, after planarizing the interlayer dielectric layer 18, the manufacturing method of the semiconductor device further includes: forming a first contact plug 191 in the interlayer dielectric layer 18 and the etch stop layer 17 on the device structure, that is, the first contact plug 191 penetrates the interlayer dielectric layer 18 and the etch stop layer 17 to be electrically connected to the device structure, so that voltage can be applied to the device structure through the first contact plug 191.

[0093] In which, the first contact plug 191 can be electrically connected to the metal silicide layer on the source region and the drain region in the device structure, respectively, or the first contact plug 191 can be electrically connected to the metal silicide layer on the source region, the drain region and the gate structure in the device structure, respectively.

[0094] When the substrate is an SOI substrate, Figure 2lAs shown, after planarizing the interlayer dielectric layer 18, the method for manufacturing the semiconductor device further includes: forming a second contact plug 192 that penetrates the interlayer dielectric layer 18 above and in the trench 181 and the insulating buried layer 102 below the trench 181, and the second contact plug 192 is electrically connected to the lower substrate 101.

[0095] In which, the lower substrate 101 may include a base (not shown) and a trap-rich layer (for example, a polysilicon layer, not shown) stacked from bottom to top, and the second contact plug 192 can be used to introduce stray charges in the interlayer dielectric layer 18 into the trap-rich layer (for example, the grain boundary structure of polysilicon can absorb stray charges) to reduce the interference of stray charges on the movement of electrons and thereby eliminate noise; and, a voltage can also be applied to the lower substrate 101 through the second contact plug 192 to control the potential of the lower substrate 101.

[0096] Preferably, the first contact plug 191 and the second contact plug 192 are formed simultaneously to simplify the process.

[0097] The method for manufacturing the semiconductor device further includes forming a sealing ring (not shown) in the sealing ring area, wherein the sealing ring penetrates the interlayer dielectric layer 18 in the sealing ring area and enters the substrate 10 , and the sealing ring surrounds the device structure and the shallow trench isolation structure.

[0098] The sealing ring is made of metal and is insulated from the substrate 10 .

[0099] The sealing ring is used to prevent cracks caused by mechanical vibration when cutting the cutting path from entering the chip; and the sealing ring can prevent water vapor from entering the chip and affecting reliability; and the sealing ring can conduct heat to promptly dissipate the heat in the chip; and the potential in the chip can be adjusted by applying voltage to the sealing ring.

[0100] As can be seen from the above, since the method for manufacturing the semiconductor device includes: forming the device structure on the substrate 10; etching the substrate 10 on both sides of the device structure to form the trench 181 for defining the active area; and forming an interlayer dielectric layer 18, wherein the interlayer dielectric layer 18 fills the trench 181, and the interlayer dielectric layer 18 in the trench 181 is a shallow trench isolation structure, then, compared with existing methods for manufacturing semiconductor devices, the method for manufacturing the semiconductor device of the present invention eliminates the steps of forming a pad oxide layer and a hard mask layer on the substrate, depositing an insulating material on the hard mask layer in the trench and around the trench, planarizing the insulating material, and removing the hard mask layer and pad oxide layer. Furthermore, the interlayer dielectric layer 18 is directly used to fill the trench 181 while forming the interlayer dielectric layer 18, that is, the formation of the interlayer dielectric layer 18 and the shallow trench isolation structure are combined into a single step. Therefore, the manufacturing method of the semiconductor device of the present invention moves the steps related to defining the active area from before forming the device structure to after forming the device structure, and integrates the steps related to defining the active area with multiple steps after forming the device structure, so that the process steps of manufacturing the semiconductor device are reduced, and the process cycle of manufacturing the semiconductor device is significantly reduced, thereby improving processing efficiency and saving process resources.

[0101] An embodiment of the present invention provides a semiconductor device, comprising: a substrate; a device structure formed on the substrate; trenches formed in the substrate on both sides of the device structure; an interlayer dielectric layer formed on the device structure, and the interlayer dielectric layer fills the trenches, wherein the interlayer dielectric layer in the trench is a shallow trench isolation structure.

[0102] In one embodiment, the semiconductor device is manufactured using the above-mentioned method for manufacturing a semiconductor device.

[0103] See below Figure 2l The semiconductor device provided by this embodiment is introduced in more detail.

[0104] The substrate 10 is a bulk substrate or a SOI (Semiconductor-On-Insulator) substrate. Figure 2l In the illustrated embodiment, the substrate 10 is an SOI substrate, which includes, from bottom to top, a lower substrate 101 , an insulating buried layer 102 , and a semiconductor layer 103 .

[0105] The bulk substrate, the lower substrate 101 and the semiconductor layer 103 may be made of any suitable semiconductor material, including but not limited to: Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors and other semiconductor materials, and the insulating buried layer 102 is, for example, a silicon oxide layer.

[0106] The substrate 10 may be a silicon substrate.

[0107] The device structure is formed on the substrate 10 .

[0108] At least one device structure may be formed on the substrate 10. Figure 2l In the illustrated embodiment, two device structures are formed on the substrate 10 .

[0109] In one embodiment, the device structure is a MOS transistor, and the device structure includes:

[0110] a well region formed in the substrate 10;

[0111] a gate structure formed on the well region;

[0112] A lightly doped source region and a lightly doped drain region are formed in the well region on both sides of the gate structure, and both the lightly doped source region and the lightly doped drain region extend below the gate structure;

[0113] A sidewall spacer formed on a sidewall of the gate structure;

[0114] A source region and a drain region are formed in the well region on both sides of the gate structure, and both the source region and the drain region extend from the substrate outside the sidewall to below the sidewall;

[0115] A metal silicide layer is formed on the surfaces of the source region and the drain region.

[0116] It should be noted that the composition of the device structure is not limited to the above structure.

[0117] In one embodiment, the device structure may include a gate stack structure or a SONOS structure, and the gate stack structure includes a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate.

[0118] In other embodiments, the metal silicide layer may also be formed on the surface of the gate structure.

[0119] The gate structure includes a gate dielectric layer and a gate layer stacked from bottom to top on the well region.

[0120] Take the substrate 10 as an example where two device structures are formed on the substrate 10 and the substrate 10 is an SOI substrate. Figure 2l As shown, the device structure may include:

[0121] A first well region 111 and a second well region 112 are formed in the semiconductor layer 103 . The first well region 111 and the second well region 112 may be located in a portion of the thickness of the semiconductor layer 103 or in the entire thickness of the semiconductor layer 103 .

[0122] a first gate structure and a second gate structure, wherein the first gate structure includes a first gate dielectric layer 121 and a first gate layer 122 stacked from bottom to top above the first well region 111, and the second gate structure includes a second gate dielectric layer 123 and a second gate layer 124 stacked from bottom to top above the second well region 112;

[0123] a first lightly doped source region 131, a first lightly doped drain region 132, a second lightly doped source region 133, and a second lightly doped drain region 134, wherein the first lightly doped source region 131 and the first lightly doped drain region 132 are formed in the first well region 111 on both sides of the first gate layer 122, and the second lightly doped source region 133 and the second lightly doped drain region 134 are formed in the second well region 112 on both sides of the second gate layer 124, and the first lightly doped source region 131 and the first lightly doped drain region 132 both extend below the first gate layer 122, and the second lightly doped source region 133 and the second lightly doped drain region 134 both extend below the second gate layer 124;

[0124] Spacers 14 are formed on the sidewalls of the first gate layer 122 and the second gate layer 124. The first gate dielectric layer 121 can extend from between the first gate layer 122 and the first well region 111 to between the spacers 14 and the first well region 111 on both sides. The second gate dielectric layer 123 can extend from between the second gate layer 124 and the second well region 112 to between the spacers 14 and the second well region 112 on both sides.

[0125] a first source region 151, a first drain region 152, a second source region 153, and a second drain region 154, wherein the first source region 151 and the first drain region 152 are formed in the first well region 111 on both sides of the first gate structure, and the second source region 153 and the second drain region 154 are formed in the second well region 112 on both sides of the second gate structure. The first source region 151 and the first drain region 152 both extend from the first well region 111 outside the corresponding spacer 14 to below the spacer 10, and the second source region 153 and the second drain region 154 both extend from the second well region 112 outside the corresponding spacer 14 to below the spacer 10. The first source region 151, the first drain region 152, the second source region 153, and the second drain region 154 may be located in a portion of the thickness of the semiconductor layer 103 or in the entire thickness;

[0126] The metal silicide layer 16 is formed on the surfaces of the first source region 151 , the first drain region 152 , the second source region 153 and the second drain region 154 .

[0127] In one embodiment, the two device structures are two different MOS transistors, such as NMOS and PMOS, or one of the MOS transistors is used to make a low noise amplifier (LNA) and the other MOS transistor is used to make a radio frequency switch (RFSwitch).

[0128] In each of the device structures, the lightly doped source region, the lightly doped drain region, the source region and the drain region have the same doping type, the well region has a doping type opposite to that of the lightly doped source region, the doping concentrations of the lightly doped source region and the lightly doped drain region are lower than the doping concentrations of the source region and the drain region, and the depths of the lightly doped source region and the lightly doped drain region are less than the depths of the source region and the drain region.

[0129] In one embodiment, the semiconductor device further includes an etch stop layer 17 formed on the device structure.

[0130] exist Figure 2l In the illustrated embodiment, the etch stop layer 17 covers the metal silicide layer 16 , the first gate dielectric layer 121 , the first gate layer 122 , the second gate dielectric layer 123 , the second gate layer 124 and the sidewall spacer 14 .

[0131] The etch stop layer 17 may be made of at least one insulating material selected from the group consisting of silicon oxynitride, silicon nitride, and nitrogen-doped carbon.

[0132] Grooves (i.e. Figure 2j The trenches 181 in are formed in the substrate 10 on both sides of the device structure.

[0133] An interlayer dielectric layer 18 is formed on the device structure, and the interlayer dielectric layer 18 fills the trench 181 , wherein the interlayer dielectric layer 18 in the trench 181 is a shallow trench isolation structure.

[0134] When the semiconductor device further includes the etch stop layer 17 , the etch stop layer 17 is formed between the device structure and the interlayer dielectric layer 18 , and the trench 181 penetrates the etch stop layer 17 .

[0135] The area surrounded by the shallow trench isolation structure is the active area, and the etch stop layer 17 can serve as a hard mask for defining the active area.

[0136] In each of the device structures, the depth of the shallow trench isolation structure is greater than or equal to the depth of the source region and the drain region.

[0137] When the substrate 10 is an SOI substrate, the shallow trench isolation structure preferably penetrates the semiconductor layer 103 to contact the buried insulating layer 102 .

[0138] The interlayer dielectric layer 18 can be a single-layer structure or a multi-layer stacked structure.

[0139] The interlayer dielectric layer 18 may be made of at least one insulating material selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride, and nitrogen-doped carbon.

[0140] The semiconductor device further includes a first contact plug 191 , which penetrates the interlayer dielectric layer 18 and the etch stop layer 17 to be electrically connected to the device structure, so that a voltage can be applied to the device structure through the first contact plug 191 .

[0141] In which, the first contact plug 191 can be electrically connected to the metal silicide layer on the source region and the drain region in the device structure, respectively, or the first contact plug 191 can be electrically connected to the metal silicide layer on the source region, the drain region and the gate structure in the device structure, respectively.

[0142] When the substrate is an SOI substrate, the semiconductor device may further include: a second contact plug 192, the second contact plug 192 penetrating the interlayer dielectric layer 18 above the shallow trench isolation structure, the shallow trench isolation structure and the insulating buried layer 102 below the shallow trench isolation structure, and the second contact plug 192 is electrically connected to the underlying substrate 101.

[0143] In which, the lower substrate 101 may include a base (not shown) and a trap-rich layer (for example, a polysilicon layer, not shown) stacked from bottom to top, and the second contact plug 192 can be used to introduce stray charges in the interlayer dielectric layer 18 into the trap-rich layer (for example, the grain boundary structure of polysilicon can absorb stray charges) to reduce the interference of stray charges on the movement of electrons and thereby eliminate noise; and, a voltage can also be applied to the lower substrate 101 through the second contact plug 192 to control the potential of the lower substrate 101.

[0144] The substrate 10 also includes a seal ring region (not shown) surrounding the at least one device structure and the shallow trench isolation structure. The seal ring region is surrounded by dicing lanes, along which chips are cut. Alignment marks (not shown) are formed in the substrate 10 within the seal ring region.

[0145] The semiconductor device further includes a seal ring (not shown) formed in the seal ring area. The seal ring penetrates the interlayer dielectric layer 18 in the seal ring area and enters the substrate 10. The seal ring surrounds the device structure and the shallow trench isolation structure.

[0146] The sealing ring is made of metal and is insulated from the substrate 10 .

[0147] The sealing ring is used to prevent cracks caused by mechanical vibration when cutting the cutting path from entering the chip; and the sealing ring can prevent water vapor from entering the chip and affecting reliability; and the sealing ring can conduct heat to promptly dissipate the heat in the chip; and the potential in the chip can be adjusted by applying voltage to the sealing ring.

[0148] As can be seen from the above, since the semiconductor device includes: a device structure formed on the substrate 10; trenches 181 formed in the substrate 10 on both sides of the device structure; and an interlayer dielectric layer 18 formed on the device structure, with the interlayer dielectric layer 18 filling the trenches 181, the interlayer dielectric layer 18 in the trenches 181 can function as a shallow trench isolation structure. Furthermore, since the interlayer dielectric layer 18 in the trenches 181 functions as a shallow trench isolation structure, the formation of the interlayer dielectric layer 18 and the shallow trench isolation structure can be combined into a single step. Therefore, the semiconductor device of the present invention enables the steps associated with defining the active region to be moved from before forming the device structure to after forming the device structure, and the steps associated with defining the active region are integrated with multiple steps after forming the device structure, thereby reducing the number of process steps in manufacturing the semiconductor device and significantly reducing the process cycle time for manufacturing the semiconductor device, improving processing efficiency, and conserving process resources.

[0149] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a device structure on the substrate; Etching the substrate on both sides of the device structure to form trenches extending into the substrate; forming an interlayer dielectric layer on the device structure, wherein the interlayer dielectric layer fills the trench; Wherein, the interlayer dielectric layer in the trench is a shallow trench isolation structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the device structure on the substrate includes: forming a well region in the substrate; forming a gate structure on the well region; forming a lightly doped source region and a lightly doped drain region in the well region on both sides of the gate structure, wherein the lightly doped source region and the lightly doped drain region both extend to below the gate structure; forming a sidewall spacer on the sidewall of the gate structure; forming a source region and a drain region in the well region on both sides of the gate structure, wherein the source region and the drain region both extend from the substrate outside the sidewall to below the sidewall; A metal silicide layer is formed on the surfaces of the source region and the drain region.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Before etching the substrate on both sides of the device structure, the method for manufacturing the semiconductor device further includes: forming an etch stop layer on the device structure and the substrate; The etch stop layer and the substrate on both sides of the device structure are etched to form the trench.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for manufacturing the semiconductor device further includes: A first contact plug is formed, wherein the first contact plug penetrates the interlayer dielectric layer to be electrically connected to the device structure.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The substrate is an SOI substrate, and the SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer; the method for manufacturing the semiconductor device further includes: A second contact plug is formed penetrating the interlayer dielectric layer above and in the trench and the buried insulating layer below the trench, wherein the second contact plug is electrically connected to the underlying substrate.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The substrate includes a seal ring area surrounding the device structure and the trench; before forming the device structure on the substrate, the method for manufacturing the semiconductor device further includes: An alignment mark is formed in the substrate in the seal ring area.

7. A semiconductor device, characterized in that: include: substrate; a device structure formed on the substrate; trenches formed in the substrate on both sides of the device structure; An interlayer dielectric layer is formed on the device structure, and the interlayer dielectric layer fills the trench, wherein the interlayer dielectric layer in the trench is a shallow trench isolation structure.

8. The semiconductor device according to claim 7, wherein The device structure includes: a well region formed in the substrate; a gate structure formed on the well region; A lightly doped source region and a lightly doped drain region are formed in the well region on both sides of the gate structure, and both the lightly doped source region and the lightly doped drain region extend below the gate structure; A sidewall spacer formed on a sidewall of the gate structure; A source region and a drain region are formed in the well region on both sides of the gate structure, and both the source region and the drain region extend from the substrate outside the sidewall to below the sidewall; A metal silicide layer is formed on the surfaces of the source region and the drain region.

9. The semiconductor device according to claim 7, wherein The semiconductor device further includes: An etch stop layer is formed between the device structure and the interlayer dielectric layer, and the trench penetrates the etch stop layer.

10. The semiconductor device according to claim 7, wherein The semiconductor device further includes: A first contact plug penetrates the interlayer dielectric layer to be electrically connected to the device structure.

11. The semiconductor device according to claim 7, wherein The substrate is an SOI substrate, and the SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer; the semiconductor device further includes: A second contact plug penetrates the interlayer dielectric layer above and in the trench and the buried insulating layer below the trench, and is electrically connected to the underlying substrate.

12. The semiconductor device according to claim 7, wherein The substrate includes a seal ring area surrounding the device structure and the trench, and an alignment mark is formed in the substrate in the seal ring area.

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