An anode phase sequence adaptive rectification method, system, device and medium

Abstract

The application discloses an anode phase sequence adaptive rectification method, system, device and medium, and belongs to the automatic control field.The method comprises the following steps: after receiving a starting command, delaying for a preset time and then outputting, collecting a synchronization signal during the delay, and judging an anode power supply phase sequence according to the synchronization signal; based on the phase sequence judgment result, selecting a corresponding preset pulse trigger sequence scheme; according to the selected pulse trigger sequence scheme and the synchronization signal, generating a silicon controlled rectifier trigger signal and outputting, so as to realize anode phase sequence adaptive rectification.The present application judges the anode power supply phase sequence according to the synchronization signal, and selects the silicon controlled rectifier trigger sequence of each bridge arm according to the judgment result, so that the anode power supply wiring can normally output no matter whether the wiring sequence is correct or reverse.

Description

Technical Field

[0001] The present invention relates to the field of automatic control, and in particular to an anode phase sequence adaptive rectification method, system, equipment and medium. Background Art

[0002] Three-phase rectification is a common rectification technology, such as Figure 1 As shown, the input amplitude is U in The three-phase anode power supply triggers the six thyristors A+, A-, B+, B-, C+, and C- (numbered 1, 4, 3, 6, 5, and 2 respectively) through the control device to control the DC output U out The amplitude of the phase-controlled rectifier bridge is generally called the anode voltage, and the output is the DC voltage Uout. The phase-controlled rectifier bridge actually connects the three-phase voltage to the positive or negative pole of the output terminal in a time-sharing manner. When the thyristor +A is turned on, the A phase voltage is connected to the + pole of the output terminal. When the thyristor -A is turned on, the A phase voltage is connected to the - pole of the output terminal. The same applies to phases B and C.

[0003] The relationship between the input voltage and output voltage of the phase-controlled rectifier bridge is as follows:

[0004] U out =1.35U in cosα;(1)

[0005] Where α is the control angle of the control device.

[0006] When the control angle is 60°, the output voltage waveform is as follows: Figure 2 shown.

[0007] Under normal conditions, the output of the phase-controlled rectifier bridge can change continuously as the control angle changes.

[0008] However, if the input anode power is connected in reverse order, the relationship between the output voltage and the angle will no longer satisfy Equation 1, and the output will become uncontrollable. Therefore, the input power phase sequence of the phase-controlled rectifier bridge is a key inspection item after the equipment is put into operation or overhauled.

[0009] From the principle of the phase-controlled rectifier bridge, the trigger pulse determines which phase of the voltage is output by the positive and negative poles of the output terminal. Even if the anode power supply is connected in reverse order, normal output can be achieved as long as the correct thyristor is turned on.

[0010] For example, if the anode power supply is normal, if the positive output terminal needs to output U A , negative output U C , just turn on thyristors 1 and 2, but when the anode power supply is input in reverse sequence, turning on thyristors 5 and 4 can achieve the same output effect, such as Figure 3 shown.

[0011] The synchronization signal is a key signal used by the control program to determine the zero-crossing point of the sine wave. The control angle uses the rising edge of the synchronization signal as the reference starting point of this cycle.

[0012] Figure 4 It is a typical synchronous shaping circuit that can shape the input sine wave into a synchronous square wave.

[0013] However, the rising edge of the synchronous square wave is determined by the flip level of the operational amplifier, which deviates from the actual zero-crossing point of the sine wave. Usually, a hardware compensation angle needs to be compensated by software to ensure that the output is consistent with the theoretical value. Figure 5 shown.

[0014] The rising edge of the three-phase synchronization signal can be used as the starting point of the cycle. Generally, phase A synchronization is used. The delay of the first pair of trigger pulses in this cycle is set in the MCU timer interrupt triggered by the rising edge of the phase A synchronization signal. The other two phases are used as redundant signals.

[0015] The time difference between the two rising edges or falling edges of each phase synchronization signal is the current signal period. The phase angle difference converted into an angle can be obtained by multiplying the ratio of the time difference of the two phase synchronization signals to the period by 360°.

[0016] Taking the A-phase synchronous interrupt as an example, the cycle calculation formula is as follows:

[0017] T=t A -t A_old (2)

[0018] t A is the moment of phase A synchronization interruption, read from the timer counter, t A_old It is the time of the last A-phase synchronous interruption, T is the period, and the unit is the timer count value.

[0019] Taking the calculation of the phase angle difference between A and B as an example, under normal circumstances, phase B lags behind phase A. The time difference between the two phases can be obtained by subtracting the current B phase synchronization interruption time from the A phase synchronization interruption time. One cycle is 360°. The ratio of the two-phase time difference to the cycle multiplied by 360° is the phase angle difference between the two phases.

[0020] α AB =(t B -t A ) / T×360(3)

[0021] where α AB is the phase angle difference between AB, in degrees, t A is the A phase synchronization interruption moment, t B is the moment of phase B synchronization interruption, and T is the period calculated by the test formula (2).

[0022] After obtaining the angle, you can refer to the reverse sequence judgment method of the patent "PT line break and PT three-phase reverse sequence fault judgment method and fault protection device" (publication number CN110412400A) to detect whether the current synchronization signal is reversed.

[0023] The relationship between synchronization and trigger pulse is shown in Figure 6 In the A-phase synchronous interrupt, a delay interrupt dT of the control angle α is set to trigger each thyristor in turn.

[0024] The calculation formula of the delay dT of the control angle α in units of MCU timer count value is as follows:

[0025] dT=α / 360×T(4)

[0026] Where T is the period obtained by formula (2), and α is the control angle.

[0027] After completing the +A and -C triggers, delay 60° to trigger +B and -C, then delay 60° to trigger -A and +B, then delay 60° to trigger -A and +C, then delay 60° to trigger -B and +C, and finally delay 60° to trigger +A and -B, completing 6 pulse triggers in one cycle.

[0028] Generally, only the rising edge of phase A in the three-phase synchronization signal is used as the reference starting point of this cycle to set the delay of each trigger pulse. Figure 7 As shown in (a), if the synchronous PT has a primary line failure, it will cause the phase of the two-phase synchronous signal to shift, as shown in Figure 7 As shown in (b) in the figure, the normal synchronization phase is selected based on the fault phenomenon. If the A phase synchronization signal is disconnected, the B phase synchronization signal is selected as the reference starting point for this cycle. However, because the B phase synchronization signal lags the A phase synchronization signal by 120°, the thyristor triggered for the first time in this cycle changes from +A, -C to -A, +B. If the B phase synchronization signal is disconnected, the C phase synchronization signal is selected as the reference starting point for this cycle. However, because the C phase synchronization signal lags the A phase synchronization signal by 240°, the thyristor triggered for the first time in this cycle changes from +A, -C to -B, +C. If the C phase synchronization signal is disconnected, the A phase synchronization signal is selected as the reference starting point for this cycle.

[0029] It should also be noted that the anode voltage is not always present. It may not be connected to the anode power supply until the start command is received. It is also possible that the initial amplitude of the anode voltage is extremely low and may not even reach the flip level of the operational amplifier. Figure 8The excitation system shown uses a self-shunt excitation connection and features an electrical braking function. Only when the electrical braking function is activated is the low-voltage switch S102 on the excitation transformer opened, and the high-voltage and low-voltage switches S105 and S104 on the brake transformer closed, connecting the auxiliary power supply as the anode power source. When excitation is activated to establish the generator voltage, switches S104 and S105 are opened, and the low-voltage switch S102 on the excitation transformer is closed. The anode power source comes from the generator terminal, and at this point, the residual voltage in the generator may be zero. When the start command is received, the controller does not even have a synchronization signal. The controller must close the primary excitation switch and apply primary excitation power to raise the generator terminal voltage and the anode voltage, thereby generating a synchronization signal.

[0030] Therefore, it is necessary to provide a new anode phase sequence adaptive rectification method, system, equipment and medium to solve the above technical problems. Summary of the Invention

[0031] The purpose of the present disclosure is to provide an anode phase sequence adaptive rectification method, system, device and medium in order to solve the above problems.

[0032] The present disclosure achieves the above objectives through the following technical solutions:

[0033] An anode phase sequence adaptive rectification method comprises the following steps:

[0034] After receiving the start command, it delays the output for a preset time, collects the synchronization signal during the delay period, and determines the anode power supply phase sequence according to the synchronization signal;

[0035] Based on the phase sequence judgment result, select the corresponding preset pulse trigger sequence scheme;

[0036] According to the selected pulse trigger sequence scheme and the synchronization signal, a thyristor trigger signal is generated and output to achieve anode phase sequence adaptive rectification.

[0037] As a further optimization solution of the present disclosure, based on the phase sequence judgment result, a corresponding preset pulse trigger sequence solution is selected, including:

[0038] If the phase sequence judgment result is sequential wiring, use the A phase synchronization signal to drive the trigger pulse;

[0039] If the phase sequence judgment result is reverse sequence wiring, use the C phase synchronization signal to drive the trigger pulse.

[0040] As a further optimization solution of the present disclosure, if the phase sequence judgment result is sequential wiring, the A-phase synchronization signal is used to drive the trigger pulse, including:

[0041] If the current anode power supply is wired sequentially, the rising edge of the A-phase synchronization signal is used as the cycle reference starting point, and the control angle α superimposed on the hardware compensation angle is used as the delay from the reference starting point to the rising edge of the first pair of trigger pulses +A and -C. Subsequently, +B and -C, -A and +B, -A and +C, -B and +C, +A and -B are output in sequence at preset angle intervals.

[0042] As a further optimization solution of the present disclosure, if the current anode power supply is connected in sequence, it is necessary to switch the synchronous phase when a synchronous disconnection fault occurs.

[0043] As a further optimization solution of the present disclosure, if the A-phase synchronization line is broken, the rising edge of the B-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes -A and +B, and then -A and +C, -B and +C, +A and -B, +B and -C, and +A and -C are output in sequence at preset angle intervals;

[0044] If the B-phase synchronization line is broken, the rising edge of the C-phase synchronization signal is used as the cycle reference starting point, the first pair of trigger pulses becomes -B and +C, and then +A and -B, +B and -C, +A and -C, +B and -C, +A and -C are output in sequence at preset angle intervals;

[0045] If the C-phase synchronization line is broken, the rising edge of the A-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +A and -C. Subsequently, +B and -C, -A and +B, -A and +C, -B and +C, +A and -B are output in sequence at preset angle intervals.

[0046] As a further optimization solution of the present disclosure, if the phase sequence judgment result is reverse sequence wiring, the C-phase synchronization signal is used to drive the trigger pulse, including:

[0047] If the current anode power supply is connected in reverse sequence, the rising edge of the C-phase synchronization signal is used as the cycle reference starting point, and the control angle α superimposed on the hardware compensation angle is used as the delay from the reference starting point to the rising edge of the first pair of trigger pulses -A and +C. Subsequently, -A and +B, +B and -C, +A and -C, +A and -B, -B and +C are output in sequence at preset angle intervals.

[0048] As a further optimization solution of the present disclosure, if the current anode power supply is connected in reverse order and the C phase synchronization is disconnected, the rising edge of the B phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +B and -C, and then +A and -C, +A and -B, -B and +C, -A and +C, -A and +B are output in sequence at preset angle intervals;

[0049] If the current anode power supply is connected in reverse order and the B phase synchronization is disconnected, the rising edge of the A phase synchronization signal is used as the cycle reference starting point, the first pair of trigger pulses becomes +A and -B, and then -B and +C, -A and +C, -A and +B, +B and -C, +A and -C are output in sequence at preset angle intervals;

[0050] If the current anode power supply is connected in reverse order and the A-phase synchronization is disconnected, the rising edge of the C-phase synchronization signal is used as the cycle reference starting point. The first pair of trigger pulses is -A and +C, and then -A and +B, +B and -C, +A and -C, +A and -B, -B and +C are output in sequence at preset angle intervals.

[0051] An anode phase sequence adaptive rectification system, comprising:

[0052] A judgment module is used to delay the output for a preset time after receiving the start command, collect the synchronization signal during the delay period, and judge the phase sequence of the anode power supply according to the synchronization signal;

[0053] A scheme selection module is used to select a corresponding preset pulse trigger sequence scheme based on the phase sequence judgment result;

[0054] The signal output module is used to generate and output a thyristor trigger signal according to the selected pulse trigger sequence scheme and the synchronization signal to achieve anode phase sequence adaptive rectification.

[0055] An electronic device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0056] Memory for storing computer programs;

[0057] The processor is used to execute the program stored in the memory to implement the anode phase sequence adaptive rectification method.

[0058] A computer-readable storage medium stores a computer program, which implements the anode phase sequence adaptive rectification method when executed by a processor.

[0059] The beneficial effects of the present disclosure are:

[0060] The present invention determines the phase sequence of the anode power supply according to the synchronization signal, and selects the triggering sequence of the thyristors of each bridge arm accordingly, so as to ensure that the anode power supply can be normally output regardless of whether it is connected in a forward or reverse sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 This is a topology diagram of a fully controlled rectifier bridge with an inductive load;

[0062] Figure 2This is a schematic diagram of the output waveform of the phase-controlled rectifier device when the control angle is 60°;

[0063] Figure 3 This is a three-phase fully controlled rectifier bridge topology diagram with the anode power supply connected in reverse sequence;

[0064] Figure 4 It is a synchronous shaping circuit diagram;

[0065] Figure 5 It is a schematic diagram of the sine wave zero crossing point and the rising edge of the synchronous square wave;

[0066] Figure 6 This is a schematic diagram of the sine wave zero crossing, the rising edge of the synchronization signal, and the thyristor trigger pulse;

[0067] Figure 7 (a) is the three-phase synchronous signal vector diagram in normal state. Figure 7 (b) is the three-phase synchronous signal vector diagram when the C-phase PT primary side is disconnected;

[0068] Figure 8 This is a schematic diagram of an excitation system with an electrical braking function and self-shunt excitation wiring;

[0069] Figure 9 is a flow chart of a method in an embodiment of the present disclosure;

[0070] Figure 10 is a system structure block diagram in an embodiment of the present disclosure;

[0071] Figure 11 It is a block diagram of the device structure in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0073] Reference Figure 9 One embodiment of the present invention provides an anode phase sequence adaptive rectification method, comprising the following steps:

[0074] After receiving the start command, it delays the output for a preset time, collects the synchronization signal during the delay period, and determines the anode power supply phase sequence according to the synchronization signal;

[0075] Based on the phase sequence judgment result, select the corresponding preset pulse trigger sequence scheme;

[0076] According to the selected pulse trigger sequence scheme and the synchronization signal, a thyristor trigger signal is generated and output to achieve anode phase sequence adaptive rectification.

[0077] Determining the anode power supply phase sequence according to the synchronization signal includes:

[0078] Calculate the time difference and period of the synchronization signals between each phase;

[0079] Calculate the phase angle difference based on the ratio of the time difference to the period;

[0080] If the phase angle difference matches the preset normal phase sequence difference, it is determined to be in order, otherwise it is in reverse order.

[0081] Calculating the time difference and period of each phase synchronization signal includes:

[0082] For the target synchronous phase A, obtain the timer counting moments of the two rising edges of the synchronization signal;

[0083] The period is calculated based on the difference in the timer counting time of the two rising edges of the synchronization signal. For the period of the target synchronization phase A, ,have:

[0084] ; (5)

[0085] Where, The timer counts the first rising edge of the synchronization signal. This is the timer counting moment of the second rising edge of the synchronization signal.

[0086] Calculating the phase angle difference according to the ratio of the time difference to the period includes:

[0087] Obtain the timer counting moment of the current rising edge of the synchronization signal of the target synchronization phase A and the adjacent synchronization phase B, and calculate the time difference;

[0088] The phase angle difference between the target synchronous phase A and the adjacent synchronous phase B is calculated using the time difference and the period of the target synchronous phase A. ,have:

[0089] ; (6)

[0090] Where, The timer count time of the current rising edge of the synchronization signal of the target synchronization phase A. The timer count time of the current rising edge of the synchronization signal of the target synchronization phase B.

[0091] The selecting from a plurality of preset trigger pulse sequences based on the phase sequence determination result includes:

[0092] If it is determined to be sequential, the A-phase synchronization signal is selected as the cycle starting point;

[0093] If it is determined to be in reverse order, the C-phase synchronization signal is selected as the cycle starting point.

[0094] The generating and outputting of the thyristor trigger signal according to the selected trigger pulse sequence and the synchronization signal comprises:

[0095] When the current synchronization signal fails, it switches to the backup synchronization signal as the cycle starting point;

[0096] In sequential mode, the standby priority order is phase B, phase C, and phase A;

[0097] In reverse order mode, the backup priority order is phase B, phase A, and phase C.

[0098] Generating a thyristor trigger signal comprises:

[0099] Calculate the timer delay of the trigger pulse, for the timer delay ,have:

[0100] ; (7)

[0101] Where, is the control angle, is the hardware compensation angle;

[0102] The rising edge of the synchronization signal triggers the timer, and the trigger pulse pair is output according to the time delay of the timer.

[0103] The hardware compensation angle is determined by the following steps:

[0104] Calculating the hardware compensation angle by the deviation between the rising edge of the synchronization signal and the actual zero-crossing point of the sine wave;

[0105] The hardware compensation angle is fixed in the controller parameters.

[0106] In this embodiment, the purpose of this method is to reduce the wiring requirements of the phase-controlled rectifier device so that the phase-controlled rectifier device can still output normally when the phase sequence of the anode power supply is wrong.

[0107] The anode power input terminals of conventional phase-controlled rectifiers are required to be connected in the order of A, B, and C. Once connected in reverse order, the relationship between the output voltage and the input voltage no longer follows formula (1), causing output loss of control. This problem usually requires readjusting the anode power supply wiring. This solution aims to provide a synchronous selection method and trigger pulse output sequence for reverse-sequence wiring, ensuring that the phase-controlled rectifier can also output normally when connected in reverse order.

[0108] like Figure 8As shown, the phase-controlled rectifier device may not have a synchronization signal before receiving a start command. Therefore, in a static state with no output, the probability of failure to determine the anode power supply wiring sequence based on the synchronization signal is high. Therefore, after receiving the start command, the phase-controlled rectifier device sets a 1-second output lockout delay, waiting 1 second after receiving the start command before outputting. During this waiting period, the current anode power supply phase sequence is detected with reference to the reverse sequence determination method described in Patent Publication No. CN110412400A, "PT Wire Break and PT Three-Phase Reverse Sequence Fault Detection Method and Fault Protection Device." Specifically, the phase angle differences of the AB phase, the BC phase, and the CA phase are all approximately 120 degrees under normal conditions, while the phase angle differences are approximately 240 degrees during reverse sequence. The presence of two phase angle differences greater than 200 degrees and lasting for more than 0.1 seconds indicates a three-phase reverse sequence.

[0109] If the current anode power supply is wired sequentially, the rising edge of the A-phase synchronization signal is used as the cycle reference starting point, and the control angle α superimposed on the hardware compensation angle is used as the delay from the reference starting point to the rising edge of the first pair of trigger pulses +A and -C. Subsequently, +B and -C, -A and +B, -A and +C, -B and +C, +A and -B are output in sequence at 60° intervals.

[0110] If the current anode power supply is wired sequentially, it is necessary to switch the synchronous phase when a synchronous disconnection fault occurs.

[0111] If the A-phase synchronization line is broken, the rising edge of the B-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes -A and +B, followed by -A and +C, -B and +C, +A and -B, +B and -C, and +A and -C at 60° intervals.

[0112] If the B-phase synchronization line is broken, the rising edge of the C-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes -B and +C, followed by +A and -B, +B and -C, +A and -C, +B and -C, and +A and -C at 60° intervals.

[0113] If the C-phase synchronization line is broken, the rising edge of the A-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +A and -C, followed by +B and -C, -A and +B, -A and +C, -B and +C, +A and -B at 60° intervals.

[0114] If the current anode power supply is connected in reverse sequence, the rising edge of the C-phase synchronization signal is used as the cycle reference starting point, and the control angle α superimposed on the hardware compensation angle is used as the delay from the reference starting point to the rising edge of the first pair of trigger pulses -A and +C. Subsequently, -A and +B, +B and -C, +A and -C, +A and -B, -B and +C are output in sequence at 60° intervals.

[0115] If the current anode power supply is connected in reverse order and the C phase synchronization is disconnected, the rising edge of the B phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +B and -C. Subsequently, +A and -C, +A and -B, -B and +C, -A and +C, -A and +B are output in sequence at 60° intervals.

[0116] If the current anode power supply is connected in reverse sequence and the B phase synchronization is disconnected, the rising edge of the A phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +A and -B, followed by -B and +C, -A and +C, -A and +B, +B and -C, and +A and -C at 60° intervals.

[0117] If the current anode power supply is connected in reverse order and the A phase synchronization is disconnected, the rising edge of the C phase synchronization signal is used as the cycle reference starting point. The first pair of trigger pulses is -A and +C, followed by -A and +B, +B and -C, +A and -C, +A and -B, -B and +C at 60° intervals.

[0118] like Figure 10 As shown, an embodiment of the present disclosure provides an anode phase sequence adaptive rectification system, comprising:

[0119] A judgment module is used to delay the output for a preset time after receiving the start command, collect the synchronization signal during the delay period, and judge the phase sequence of the anode power supply according to the synchronization signal;

[0120] A scheme selection module is used to select a corresponding preset pulse trigger sequence scheme based on the phase sequence judgment result;

[0121] The signal output module is used to generate and output a thyristor trigger signal according to the selected pulse trigger sequence scheme and the synchronization signal to achieve anode phase sequence adaptive rectification.

[0122] The implementation process of the functions and effects of each module in the above system is specifically described in the implementation process of the corresponding steps in the above method, which will not be repeated here.

[0123] For the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can be referred to the partial description of the method embodiment. The system embodiment described above is only schematic, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the disclosed solution. Those of ordinary skill in the art can understand and implement it without paying any creative work.

[0124] In the above embodiments, any number of all modules can be combined into one module for implementation, or any one of the modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. At least one of all modules can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or can be implemented in hardware or firmware by any other reasonable means of integrating or packaging the circuit, or can be implemented in any one of the three implementation methods of software, hardware, and firmware, or in an appropriate combination of any of them. Alternatively, at least one of all modules can be at least partially implemented as a computer program module, which can perform the corresponding function when the computer program module is executed.

[0125] See also Figure 11 The electronic device provided by an embodiment of the present disclosure includes a processor 1110, a communication interface 1120, a memory 1130 and a communication bus 1140, wherein the processor 1110, the communication interface 1120, and the memory 1130 communicate with each other through the communication bus 1140;

[0126] Memory 1130, for storing computer programs;

[0127] The processor 1110 is configured to implement the above-mentioned anode phase sequence adaptive rectification method when executing the program stored in the memory 1130 .

[0128] The communication bus 1140 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus 1140 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the figure shows only one thick line, but this does not mean that there is only one bus or only one type of bus.

[0129] The communication interface 1120 is used for communication between the electronic device and other devices.

[0130] The memory 1130 may include a random access memory (RAM) or a non-volatile memory, such as at least one disk storage. Alternatively, the memory 1130 may be at least one storage device located away from the processor 1110.

[0131] The above-mentioned processor 1110 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0132] The embodiments of the present disclosure further provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the anode phase sequence adaptive rectification method described above.

[0133] The computer-readable storage medium may be included in the device / apparatus described in the above embodiments, or may exist independently and not be incorporated into the device / apparatus. The computer-readable storage medium carries one or more programs that, when executed, implement the anode phase sequence adaptive rectification method according to the embodiments of the present disclosure.

[0134] According to embodiments of the present disclosure, a computer-readable storage medium may be a non-volatile computer-readable storage medium, such as, but not limited to, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0135] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present disclosure. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure.

Claims

1. An anode phase sequence adaptive rectification method, characterized in that: The following steps are involved: After receiving the start command, it delays the output for a preset time, collects the synchronization signal during the delay period, and determines the anode power supply phase sequence according to the synchronization signal; Based on the phase sequence judgment result, select the corresponding preset pulse trigger sequence scheme; If the current anode power supply is wired sequentially, it is necessary to switch the synchronous phase when a synchronous disconnection fault occurs; If the A-phase synchronization line is broken, the rising edge of the B-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes -A and +B, followed by -A and +C, -B and +C, +A and -B, +B and -C, +A and -C, and +A and -C, respectively, at a preset angle interval; if the B-phase synchronization line is broken, the rising edge of the C-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes -B and +C, followed by +A and -B, +B and -C, +A and -C, +B and -C, +A and -C, and +A and -C, respectively, at a preset angle interval; if the C-phase synchronization line is broken, the rising edge of the A-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +A and -C, followed by +B and -C, -A and +B, -A and +C, -B and +C, +A and -B, respectively, at a preset angle interval; According to the selected pulse trigger sequence scheme and the synchronization signal, a thyristor trigger signal is generated and output to achieve anode phase sequence adaptive rectification.

2. The anode phase sequence adaptive rectification method according to claim 1, characterized in that: Based on the phase sequence judgment result, the corresponding preset pulse trigger sequence scheme is selected, including: If the phase sequence judgment result is sequential wiring, use the A phase synchronization signal to drive the trigger pulse; If the phase sequence judgment result is reverse sequence wiring, use the C phase synchronization signal to drive the trigger pulse.

3. The anode phase sequence adaptive rectification method according to claim 2, characterized in that: If the phase sequence judgment result is sequential wiring, use the A-phase synchronization signal to drive the trigger pulse, including: If the current anode power supply is wired sequentially, the rising edge of the A-phase synchronization signal is used as the cycle reference starting point, and the control angle α superimposed on the hardware compensation angle is used as the delay from the reference starting point to the rising edge of the first pair of trigger pulses +A and -C. Subsequently, +B and -C, -A and +B, -A and +C, -B and +C, +A and -B are output in sequence at preset angle intervals.

4. The anode phase sequence adaptive rectification method according to claim 2, characterized in that: If the phase sequence judgment result is reverse sequence wiring, use the C phase synchronization signal to drive the trigger pulse, including: If the current anode power supply is connected in reverse sequence, the rising edge of the C-phase synchronization signal is used as the cycle reference starting point, and the control angle α superimposed on the hardware compensation angle is used as the delay from the reference starting point to the rising edge of the first pair of trigger pulses -A and +C. Subsequently, -A and +B, +B and -C, +A and -C, +A and -B, -B and +C are output in sequence at preset angle intervals.

5. An anode phase sequence adaptive rectification system, characterized in that: include: A judgment module is used to delay the output for a preset time after receiving the start command, collect the synchronization signal during the delay period, and judge the phase sequence of the anode power supply according to the synchronization signal; A scheme selection module is used to select a corresponding preset pulse trigger sequence scheme based on the phase sequence judgment result; If the current anode power supply is wired sequentially, it is necessary to switch the synchronous phase when a synchronous disconnection fault occurs; If the A-phase synchronization line is broken, the rising edge of the B-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes -A and +B, followed by -A and +C, -B and +C, +A and -B, +B and -C, +A and -C, and +A and -C, respectively, at a preset angle interval; if the B-phase synchronization line is broken, the rising edge of the C-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes -B and +C, followed by +A and -B, +B and -C, +A and -C, +B and -C, +A and -C, and +A and -C, respectively, at a preset angle interval; if the C-phase synchronization line is broken, the rising edge of the A-phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +A and -C, followed by +B and -C, -A and +B, -A and +C, -B and +C, +A and -B, respectively, at a preset angle interval; The signal output module is used to generate and output a thyristor trigger signal according to the selected pulse trigger sequence scheme and the synchronization signal to achieve anode phase sequence adaptive rectification.

6. An anode phase sequence adaptive rectification method, characterized in that: The following steps are involved: After receiving the start command, it delays the output for a preset time, collects the synchronization signal during the delay period, and determines the anode power supply phase sequence according to the synchronization signal; Based on the phase sequence judgment result, select the corresponding preset pulse trigger sequence scheme; If the current anode power supply is connected in reverse sequence and the C phase is disconnected synchronously, the rising edge of the B phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +B and -C, followed by +A and -C, +A and -B, -B and +C, -A and +C, -A and +B at preset angle intervals; If the current anode power supply is connected in reverse sequence and the B phase is disconnected synchronously, the rising edge of the A phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +A and -B, followed by -B and +C, -A and +C, -A and +B, +B and -C, +A and -C at preset angle intervals; If the current anode power supply is connected in reverse sequence and the A phase is disconnected synchronously, the rising edge of the C phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses is -A and +C, followed by -A and +B, +B and -C, +A and -C, +A and -B, -B and +C at preset angle intervals; According to the selected pulse trigger sequence scheme and the synchronization signal, a thyristor trigger signal is generated and output to achieve anode phase sequence adaptive rectification.

7. The anode phase sequence adaptive rectification method according to claim 6, characterized in that: Based on the phase sequence judgment result, the corresponding preset pulse trigger sequence scheme is selected, including: If the phase sequence judgment result is sequential wiring, use the A phase synchronization signal to drive the trigger pulse; If the phase sequence judgment result is reverse sequence wiring, use the C phase synchronization signal to drive the trigger pulse.

8. The anode phase sequence adaptive rectification method according to claim 7, characterized in that: If the phase sequence judgment result is sequential wiring, use the A-phase synchronization signal to drive the trigger pulse, including: If the current anode power supply is wired sequentially, the rising edge of the A-phase synchronization signal is used as the cycle reference starting point, and the control angle α superimposed on the hardware compensation angle is used as the delay from the reference starting point to the rising edge of the first pair of trigger pulses +A and -C. Subsequently, +B and -C, -A and +B, -A and +C, -B and +C, +A and -B are output in sequence at preset angle intervals.

9. The anode phase sequence adaptive rectification method according to claim 7, characterized in that: If the current anode power supply is wired sequentially, it is necessary to switch the synchronous phase when a synchronous disconnection fault occurs.

10. The anode phase sequence adaptive rectification method according to claim 7, characterized in that: If the phase sequence judgment result is reverse sequence wiring, use the C phase synchronization signal to drive the trigger pulse, including: If the current anode power supply is connected in reverse sequence, the rising edge of the C-phase synchronization signal is used as the cycle reference starting point, and the control angle α superimposed on the hardware compensation angle is used as the delay from the reference starting point to the rising edge of the first pair of trigger pulses -A and +C. Subsequently, -A and +B, +B and -C, +A and -C, +A and -B, -B and +C are output in sequence at preset angle intervals.

11. An anode phase sequence adaptive rectification system, characterized in that: include: A judgment module is used to delay the output for a preset time after receiving the start command, collect the synchronization signal during the delay period, and judge the phase sequence of the anode power supply according to the synchronization signal; A scheme selection module is used to select a corresponding preset pulse trigger sequence scheme based on the phase sequence judgment result; If the current anode power supply is connected in reverse sequence and the C phase is disconnected synchronously, the rising edge of the B phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +B and -C, followed by +A and -C, +A and -B, -B and +C, -A and +C, -A and +B at preset angle intervals; If the current anode power supply is connected in reverse sequence and the B phase is disconnected synchronously, the rising edge of the A phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses becomes +A and -B, followed by -B and +C, -A and +C, -A and +B, +B and -C, +A and -C at preset angle intervals; If the current anode power supply is connected in reverse sequence and the A phase is disconnected synchronously, the rising edge of the C phase synchronization signal is used as the cycle reference starting point, and the first pair of trigger pulses is -A and +C, followed by -A and +B, +B and -C, +A and -C, +A and -B, -B and +C at preset angle intervals; The signal output module is used to generate and output a thyristor trigger signal according to the selected pulse trigger sequence scheme and the synchronization signal to achieve anode phase sequence adaptive rectification.

12. An electronic device, characterized in that: The processor, the communication interface, the memory and the communication bus are connected to each other via the communication bus. Memory for storing computer programs; A processor is used to execute the program stored in the memory to implement the anode phase sequence adaptive rectification method described in any one of claims 1-4 and 6-10.

13. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the anode phase sequence adaptive rectification method according to any one of claims 1 to 4 and 6 to 10 is implemented.

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