Jitter for constant on-time control loop

Abstract

The invention relates to jitter for a constant on-time control loop. A pulse generator for generating a pulse setting an on-time for switching a DC-DC converter includes: a voltage divider having a tap generating a jitter reference voltage; a voltage-to-current converter device generating a charging current having a magnitude based on the jitter reference voltage; a timing capacitor charged by the charging current; a reset switch for timing the capacitor; and a comparator generating a pulse based on a comparison between a timing voltage stored on the timing capacitor and a reference voltage, in which a width of the pulse is set as a function of a rate at which the timing capacitor is charged by the charging current. The voltage divider is adjustable, and the resistance seen at the taps of the voltage divider is incrementally varied such that the dither reference voltage is modulated in a step triangle manner.

Description

Technical Field

[0001] The present invention relates to a pulse generator for generating on-time pulses for switching a DC-DC converter operated using a constant on-time control loop, and in particular to a pulse generator design that enables dithering of the switching frequency of the DC-DC converter. Background Art

[0002] Switching systems, such as DC-DC converters, are known sources of electromagnetic noise that can be harmful to other electronic devices in the same environment. These emissions typically have a discrete spectrum characterized by power peaks at harmonics of the switching frequency. To comply with electromagnetic compatibility (EMC) standards such as CISPR 22 / 25, these peaks must be aligned with specific threshold masks.

[0003] There are various methods to minimize the magnitude of these peaks from DC-DC converters. These techniques include shielding and filtering techniques, which help reduce emissions and radiated interference between the source (aggressor) and affected (victim) circuits.

[0004] One approach to improving compliance with EMC standards involves redistributing the emitted noise across a wider frequency range. This can be achieved by slightly varying the switching frequency. This maintains the overall emitted energy while reducing the intensity of individual peaks, making them less likely to interfere with nearby circuits. By doing so, the system can better coexist with other electronic equipment, reducing the potential for harmful electromagnetic interference.

[0005] However, existing implementations of this method have disadvantages. Figure 1 One such implementation is shown in FIG. 1 , which shows a method for generating the on-time T. ON The pulse generator 10 is used to switch the DC-DC converter using a constant on-time (COT) control loop. In particular, the pulse generator 10 generates a pulse for generating a set on-time T ON The fixed width pulse charging current I CHG In more detail, the pulse generator 10 includes a circuit connected to the input voltage node V IN and the top resistor R between node N1 TOP , and a bottom resistor R connected between node N1 and ground BOT The non-inverting input terminal of the amplifier 12 is connected to the node N1, the inverting input terminal thereof is connected to the node N2, and the output terminal thereof is connected to the gate of the n-channel transistor MN1. The drain of the n-channel transistor MN1 is connected to the node N3, and the source thereof is connected to the node N2. The resistor R RONConnected between node N2 and ground level, a voltage V is formed at node N2 PAR The source of the P-channel transistor MP1 is connected to the power supply voltage node V CC , its drain is connected to the node N3, and its gate is connected to the node N3. The source of the variable p-channel transistor MP2 is connected to the power supply voltage V CC The variable p-channel transistor MP2 is controlled by the control circuit 98 , and its drain is connected to the signal generator 13 , and its gate is connected to the node N3 .

[0006] The operation of the pulse generator 10 involves a perturbation for generating a set on-time T ON The pulse charging current I CHG , the purpose is to CHG In this design, the variable transistor MP2 is configured as a variable current source to generate the charging current I CHG A multi-branch current mirror wherein the currents provided by the branches of the current mirror are weighted by powers of 2. The branches are activated and deactivated sequentially.

[0007] The pulse generator 10 is used to generate T ON Pulse charging current I CHG The use of is effective in situations with a limited number of known switching frequencies. The charging current in this design depends on the input voltage V IN and external resistor R RON , the external resistor and the ratio of the converter’s output voltage to the switching frequency V OUT / F SW Using a wide range of V IN and R RON , I CHG It can vary from hundreds of nA to hundreds of μA.

[0008] Designing a current mirror that maintains correct biasing and high accuracy over the entire current range is challenging. Especially at the charging current I CHG The lower end of the current mirror branch corresponding to the less significant bits can have currents as low as a few nanoamperes, which becomes comparable to the noise level. Therefore, under different operating conditions, as the width, symmetry and average value are changed, the current applied to the switching frequency F SW The dithering effect can become unstable. This instability can undermine the effectiveness of dithering in spreading electromagnetic emissions across a wider spectrum, thereby maintaining EMC compliance.

[0009] In view of this, there is therefore a need to further develop techniques for redistributing emitted noise over a wider frequency range. Summary of the Invention

[0010] A pulse generator is disclosed herein for generating a pulse for setting an on-time T for switching a DC-DC converter. ON The pulse generator includes: a voltage divider coupled between an input voltage and ground, generating a dithered reference voltage at a tap of the voltage divider; a voltage-to-current converter device generating a charging current having a magnitude based on the dithered reference voltage; a timing capacitor configured to be charged by the charging current; a reset switch configured to selectively discharge the timing capacitor; and a comparator configured to generate a pulse based on a comparison between the timing voltage stored on the timing capacitor and a reference voltage, the pulse width being set as a function of the rate at which the timing capacitor is charged by the charging current; wherein the voltage divider is configured to incrementally change the resistance seen at the tap of the voltage divider such that the dithered reference voltage is modulated in a stepped triangular manner.

[0011] The voltage divider may include: a top resistor connected between the input voltage and the tap; a bottom resistor connected between the tap and a first switch, the first switch being configured to selectively couple the bottom resistor directly to a ground level or to couple the bottom resistor to the ground level through a second resistor; and an adjustable resistor connected between the tap and the second switch, the adjustable resistor being configured to selectively couple the adjustable resistor to the ground level or to allow the adjustable resistor to float, an incremental change in the resistance value of the adjustable resistor generating an incremental change in the resistance seen at the tap.

[0012] The variable resistor may include a plurality of resistors connected in series between a tap and a ground level, respective switches of the plurality of switches connected across respective ones of the plurality of resistors to selectively short-circuit different ones of the plurality of resistors.

[0013] The resistance of multiple resistors can vary by powers of 2.

[0014] The plurality of resistors may include: a first resistor connected between the tap and a first node; a second resistor connected between the first node and a second node; a third resistor connected between the second node and a third node; a fourth resistor connected between the third node and a fourth node; a fifth resistor connected between the fourth node and a fifth node; and a sixth resistor connected between the fifth node and a sixth node.

[0015] The plurality of switches may include: a third switch connected between the first node and the second node, the third switch being operated by a fourth bit of the dithering control word; a fourth switch connected between the second node and the third node, the fourth switch being operated by a third bit of the dithering control word; a fifth switch connected between the third node and the fourth node, the fifth switch being operated by a second bit of the dithering control word; a sixth switch connected between the fourth node and the fifth node, the sixth switch being operated by a first bit of the dithering control word; and a seventh switch connected between the fifth node and ground, the seventh switch being operated by a zeroth bit of the dithering control word. The second switch is connected between the sixth node and ground. The control circuit is configured to periodically increment the dithering control word from a first binary value to a second binary value, and, once the dithering control word has reached the second binary value, periodically decrement the dithering control word from the second binary value back to the first binary value.

[0016] The resistance of the second resistor may be equal to sixteen times the base resistance value, the resistance of the third resistor may be equal to eight times the base resistance value, the resistance of the fourth resistor may be equal to four times the base resistance value, the resistance of the fifth resistor may be equal to two times the base resistance value, and the resistance of the sixth resistor may be equal to the base resistance value.

[0017] The plurality of resistors may include: a first resistor connected between the tap and a first node; a second resistor connected between the first node and the second node; a third resistor connected between the second node and a third node; a fourth resistor connected between the third node and a fourth node; a fifth resistor connected between the fourth node and the fifth node; a sixth resistor connected between the fifth node and the sixth node; a seventh resistor connected between the sixth node and the seventh node; an eighth resistor connected between the seventh node and the eighth node; a ninth resistor connected between the eighth node and the ninth node; and a tenth resistor connected between the ninth node and the tenth node.

[0018] The plurality of switches may include: a third switch connected between the first node and the second node, the third switch being operated by a logic AND operation between the third bit and the fourth bit of the dithering control word; a fourth switch connected between the second node and the third node, the fourth switch being operated by a logic AND operation between the second bit and the fourth bit of the dithering control word; a fifth switch connected between the third node and the fourth node, the fifth switch being operated by a logic AND operation between the first bit and the fourth bit of the dithering control word; a sixth switch connected between the fourth node and the fifth node, the sixth switch being operated by a logic AND operation between the zeroth bit and the fourth bit of the dithering control word; and a sixth switch connected between the fifth node and the sixth node. A seventh switch connected between the sixth node and the seventh node, the seventh switch being operated by the fourth bit of the dithering control word; an eighth switch connected between the sixth node and the seventh node, the eighth switch being operated by a logical OR between the third bit and the fourth bit of the dithering control word; a ninth switch connected between the seventh node and the eighth node, the ninth switch being operated by a logical OR between the second bit and the fourth bit of the dithering control word; a tenth switch connected between the eighth node and the ninth node, the tenth switch being operated by a logical OR between the first bit and the fourth bit of the dithering control word; and an eleventh switch connected between the ninth node and the tenth node, the eleventh switch being operated by a logical OR between the zeroth bit and the fourth bit of the dithering control word. The second switch may be connected between the tenth node and ground. The control circuit may be configured to periodically increment the dithering control word from a first binary value to a second binary value, and, once the dithering control word has reached the second binary value, periodically decrement the dithering control word from the second binary value back to the first binary value.

[0019] The resistance of the second resistor may be equal to eight times the basic resistance value, the resistance of the third resistor may be equal to four times the basic resistance value, the resistance of the fourth resistor may be equal to two times the basic resistance value, the resistance of the fifth resistor may be equal to the basic resistance value, the resistance of the sixth resistor may be equal to four times the basic resistance value, the resistance of the seventh resistor may be equal to sixteen times the basic resistance value, the resistance of the eighth resistor may be equal to eight times the basic resistance value, the resistance of the ninth resistor may be equal to four times the basic resistance value, and the resistance of the tenth resistor may be equal to two times the basic resistance value.

[0020] The first transistor may be a first transistor having a first conduction terminal connected to the third node, a second conduction terminal connected to the second node, and a control terminal coupled to a gate drive voltage. The current mirror may include: a second transistor having a first conduction terminal coupled to a first given voltage, a second conduction terminal connected to the third node, and a control terminal connected to the third node; and a third transistor having a first conduction terminal coupled to the first given voltage, a second conduction terminal connected to the timing capacitor, and a control terminal connected to the third node.

[0021] The first amplifier may have a first input coupled to the tap to receive the dithered reference voltage, a second input coupled to the second node, and an output coupled to the control terminal of the first transistor.A sense resistor may be connected between the second node and a second given voltage.

[0022] The voltage-to-current converter device may include: a first transistor configured to generate a first current based on a gate drive voltage; a first amplifier configured to generate and modulate the gate drive voltage based on a comparison between the dithered reference voltage and a feedback voltage representative of the first current; and a current mirror configured to mirror the first current to generate the charging current.

[0023] Also disclosed herein is a method for generating pulses configured to switch the on-time of a DC-DC converter. The method includes: generating a dithered reference voltage by incrementally varying the resistance seen at the taps of a voltage divider such that the dithered reference voltage is modulated in a stepped triangular manner; generating a charging current having a magnitude based on the dithered reference voltage; receiving the charging current at a timing capacitor such that the charging current charges the timing capacitor; and comparing the voltage across the timing capacitor to a non-dithered reference voltage and asserting or deasserting a pulse based on the comparison, wherein the width of the pulse is set as a function of the rate at which the timing capacitor is charged by the charging current.

[0024] The resistance seen at a tap of the voltage divider can be incrementally changed by selectively shorting different ones of the plurality of resistors connected in series between the tap and ground by closing corresponding ones of the plurality of switches connected across corresponding ones of the plurality of resistors.

[0025] The resistance of multiple resistors can vary by powers of 2.

[0026] Each of the plurality of switches may be closed in response to assertion of a different bit of the dither control word.

[0027] Each switch in a first subset of the plurality of switches may be closed in response to a result of a logical AND operation between two different bits of the dithering control word, and each switch in a second subset of the plurality of switches may be closed in response to a result of a logical OR operation between two different bits of the dithering control word.

[0028] The remaining switches of the plurality of switches that are not in the first subset or the second subset may be closed in response to assertion of a bit of the dithering control word. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic block diagram of a known pulse generator for generating on-time pulses for switching a DC-DC converter operated using a constant on-time control loop.

[0030] Figure 2 is a schematic block diagram of a general form of a pulse generator disclosed herein for generating on-time pulses for switching a DC-DC converter operating using a constant on-time control loop.

[0031] Figure 3 is a schematic block diagram of a first pulse generator disclosed herein for generating pulses that set an on-time for switching a DC-DC converter operated using a constant on-time control loop.

[0032] Figure 4 Includes information showing the operation Figure 3 The input voltage and jitter reference voltage (V PAR ) is a series of graphs.

[0033] Figure 5 is a schematic block diagram of a second pulse generator disclosed herein for generating pulses that set an on-time for switching a DC-DC converter operated using a constant on-time control loop.

[0034] Figure 6 Includes information showing the operation Figure 5 The designed input voltage (V IN ) and the dither reference voltage (V PAR ) is a series of graphs.

[0035] Figure 7 Including showing Figure 5 The charging current (I CHG ) and the dither reference voltage (V PAR ) is a series of graphs.

[0036] Figure 8Is to show the use of Figure 5 Graph of the power spectrum of the input current of the DC-DC converter of the pulse generator of FIG. 1 with dithering activated and with dithering deactivated.

[0037] Figure 9 Is to show the use of Figure 5 Graphs of the power spectrum of the output voltage of the DC-DC converter of the pulse generator of FIG. 1 with dithering activated and with dithering deactivated.

[0038] Figure 10 is a schematic block diagram of a third pulse generator disclosed herein for generating pulses that set an on-time for switching a DC-DC converter operated using a constant on-time control loop. DETAILED DESCRIPTION

[0039] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure may be applied to embodiments and applications beyond those described above without departing from the spirit and scope of the disclosure. It is not intended to limit the present invention to the embodiments shown, but rather to accord the widest scope consistent with the principles and features disclosed or suggested herein.

[0040] Note that in the following description, unless otherwise specified, any resistor or resistance mentioned is a discrete device and is not simply an electrical lead between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than the lead between the two points, and such a resistor or resistance cannot be interpreted as a lead. Similarly, unless otherwise specified, any capacitor or capacitance mentioned is a discrete device and is not a parasitic element unless otherwise specified. In addition, unless otherwise specified, any inductor or inductance mentioned is a discrete device and is not a parasitic element unless otherwise specified.

[0041] Now refer to Figure 2 A pulse generator 10 ′ is described, which is used to generate a set on-time T ON The pulse generator 10' comprises a pulse connected to the input voltage node V IN and the top resistor R between node N1 TOP , and a bottom resistor R connected between node N1 and switch S1 BOT . Switch S1 selectively connects the bottom resistor R BOT Connect to ground or to resistor R connected between switch S1 and ground R The dither circuit 15 is composed of an adjustable resistor R connected between the node N1 and the node N5. ADJThe switch Sw is connected between the node N5 and the ground level. During operation, a jitter reference voltage V is formed at the node N1. PAR .

[0042] The non-inverting input terminal of the amplifier 12 is connected to the node N1, the inverting input terminal thereof is connected to the node N2, and the output terminal thereof is connected to the gate of the n-channel transistor MN1. The drain of the n-channel transistor MN1 is connected to the node N3, and the source thereof is connected to the node N2. The resistor R RON Connected between node N2 and ground level, a voltage V is formed at node N2 PAR ; Note that resistor R RON can be a discrete external component, and N2 can be the pin to which it is connected, allowing the resistor to be selected for matching the application, or resistor R RON The source of the P-channel transistor MP1 is connected to the power supply voltage node V CC , its drain is connected to the node N3, and its gate is connected to the node N3. The source of the p-channel transistor MP2 is connected to the power supply voltage node V CC , whose drain is connected to the signal generator 13, and whose gate is connected to the node N3.

[0043] The signal generator 13 includes a drain connected to the p-channel transistor MP2 to receive the charging current I CHG The timing capacitor Ct is connected between the node N4 and the ground level. The switch S2 is connected between the node N4 and the ground level. The comparator 14 has its non-inverting input terminal connected to the node N4 to receive the voltage across the timing capacitor Ct, and has its inverting input terminal coupled to the reference voltage V REF The output of the comparator 14 generates a defined on-time T ON End of pulse PULSE.

[0044] The control circuit 99 operates the switches S1, S2, Sw and adjusts the adjustable resistor R ADJ resistance.

[0045] In operation, the comparator 14 compares the voltage across Ct with the reference voltage V REF comparison, and when the voltage across the capacitor Ct is greater than the reference voltage V REF When the voltage across the capacitor Ct is less than the reference voltage V REF When the comparator 14 output PULSE is deasserted to logic low, the capacitor Ct is connected to the capacitor by the current I CHG Therefore, the current I CHGThe larger the value, the faster the capacitor Ct is charged, and the on-time T is set by the output PULSE of the comparator 14. ON The shorter the current I CHG The smaller the value, the slower the capacitor Ct is charged, and the on-time T is set by the output PULSE of the comparator 14. ON The longer.

[0046] The arrangement of the amplifier 12 acts as a voltage-current converter and drives the transistor MN1 so that the voltage at the node N2 is equal to the reference voltage V PAR ; Therefore, the dither reference voltage V PAR The magnitude of the drain current of MN1 is set, and the drain current of MN1 is mirrored by the current mirror arrangement of transistors MP1 and MP2 to generate a current I that charges the capacitor Ct. CHG Therefore, the current I CHG The magnitude of the dither reference voltage V PAR set up.

[0047] By periodically changing the top resistor R TOP , bottom resistor R BOT and adjustable resistor R ADJ The resistors of the voltage divider formed by the dither reference voltage V PAR To perform the dithering, the control circuit 99 sets the switch S1 to connect the bottom resistor R BOT Connected between node N1 and ground level, set the switch Sw to adjust the adjustable resistor R ADJ Connected between node N1 and ground level, and periodically adjusts the adjustable resistor R ADJ resistance, making the bottom resistor R BOT and adjustable resistor R ADJ The parallel combination of resistors results in a reference voltage V PAR The dither reference voltage V PAR It can be calculated as where R BOTTOM It is R BOT and R ADJ parallel combination.

[0048] V PAR about Figure 1 The advantage of the embodiment is that, depending on R BOT and R TOP The ratio of V IN The changes in V PAR However, if the voltage divider consists of R BOT and R TOP formed and sized correctly, the worst case variation is an order of magnitude, Figure 1The three orders of magnitude variation of the embodiment possible are opposite.

[0049] Switch S1 connects R BOT Connect to ground level and optionally depend on R BOT The size of the R R Easy to dither reference voltage V PAR When connected directly to ground during dithering, it forms the lowest possible resistance state in the voltage divider, generating the lowest reference point in the stepped voltage distribution. Conversely, when R BOT Leave floating (or connect to R R ), which effectively increases the resistance in the lower section of the voltage divider, thereby raising the voltage at node N1 to a higher step in the distribution.

[0050] Jitter reference voltage V PAR The staircase dithering disperses the spectral content of the noise emitted by the DC-DC converter employing the pulse generator 10 ′, thereby reducing the peak intensity of the noise emitted at any given frequency.

[0051] Now refer to Figure 3 A version of the pulse generator 10' is described in which a first embodiment of the dither circuit 15 is shown. Here, the dither control word (formed by bits b0, b1, b2, b3, b4) is generated by the control circuit 99. The dither circuit 15 comprises a resistor R connected between the node N1 and the node N5. FIX , a resistor R connected between node N5 and node N6 16R (having a resistance of 16RΩ), a resistor R connected between the node N6 and the node N7 8R (having a resistance of 8RΩ), a resistor R connected between the node N7 and the node N8 4R (having a resistance of 4RΩ), a resistor R connected between the node N8 and the node N9 2R (having a resistance of 2RΩ), a resistor RR (having a resistance of RΩ) connected between the node N9 and the node N10, and a switch S8 connected between the node N10 and the ground level. A switch S3 (controlled by bit b4 of the dithering control word) is connected between the nodes N5 and N6, a switch S4 (controlled by bit b3 of the dithering control word) is connected between the nodes N6 and N7, a switch S5 (controlled by bit b2 of the dithering control word) is connected between the nodes N7 and N8, a switch S6 (controlled by bit b1 of the dithering control word) is connected between the nodes N8 and N9, and a switch S7 (controlled by bit b0 of the dithering control word) is connected between the node N9 and the ground level.

[0052] In operation, the dither control word increments from binary 0 (b0000) to binary 15 (b1111) and then back to binary 0 from binary 15, selectively shorting resistor R 16R 、R 8R 、R 4R 、R 2R , part of RR, thus forming Figure 4 The reference voltage V PAR shape.

[0053] It can be seen that using Figure 3 The dither circuit 15 obtains the reference voltage V PAR The shape of is not a perfect stepped triangle, but more of a stepped inverted parabola. Thus, the spectral spreading of the noise content may not be sufficient for some applications (but perfectly sufficient for others).

[0054] For example, where a particular application requires a greater spectral spread of the noise content, it may be possible to utilize Figure 5 Example of . Figure 5 A version of the pulse generator 10' is shown in which a second embodiment of the dithering circuit 15' is shown. Here, the dithering circuit 15' comprises a resistor R connected between the node N1 and the node Nn1. FIX , a resistor R connected between the node Nn1 and the node Nn2 8R (having a resistance of 8RΩ), a resistor R connected between the node Nn2 and the node Nn3 4R (having a resistance of 4RΩ), a resistor R connected between the node Nn3 and the node Nn4 2R (having a resistance of 2RΩ), a resistor RR (having a resistance of RΩ) connected between the node Nn4 and the node Nn5, and a resistor R connected between the node Nn5 and the node Nn6. 4RR (having a resistance of 4RΩ), a resistor R connected between the node Nn6 and the node Nn7 16RR (having a resistance of 16RΩ), a resistor R connected between the node Nn7 and the node Nn8 8RR (having a resistance of 8RΩ), a resistor R connected between the node Nn8 and the node Nn9 4RR (having a resistance of 4RΩ), (a resistor R connected between the node Nn6 and the node Nn10 2RR (having a resistance of 2RΩ), the switch Sw10 is connected between the node Nn10 and the ground level.

[0055] The switch Sw1 (controlled by the logical AND of bits b3 and b4 of the dither control word) is connected between nodes Nn1 and Nn2, the switch Sw2 (controlled by the logical AND of bits b2 and b4 of the dither control word) is connected between nodes Nn2 and Nn3, the switch Sw3 (controlled by the logical AND of bits b1 and b4 of the dither control word) is connected between nodes Nn3 and Nn4, the switch Sw4 (controlled by the logical AND of bits b0 and b4 of the dither control word) is connected between nodes Nn4 and Nn5, and the switch Sw5 (controlled by bit b4 of the dither control word) is connected between nodes Nn6 and Nn7. ) is connected between node Nn5 and node Nn6, switch Sw6 (controlled by the logical OR of bit b3 and bit b4 of the dithering control word) is connected between nodes Nn6 and Nn7, switch Sw7 (controlled by the logical OR of bit b2 and bit b4 of the dithering control word) is connected between nodes Nn7 and Nn8, switch Sw8 (controlled by the logical OR of bit b1 and bit b4 of the dithering control word) is connected between nodes Nn8 and Nn9, and switch Sw9 (controlled by the logical OR of bit b0 and bit b4 of the dithering control word) is connected between nodes Nn9 and Nn10.

[0056] In operation here, in addition to the resistor (which is selectively shorted by assertion of bit b4 of the dither control word), resistor R 8R 、R 4R 、R 2R ,RR,R 16R 、R 8RR 、R 4RR , and R 2RR Some resistors in the circuit are selectively short-circuited by the logical combination of bits b0, b1, b2, b3, b4 of the dither control word. 8R By selectively short-circuiting the logic between bits b3 and b4, R 4R By selectively short-circuiting the bits b2 and b4, R 2R Selectively short-circuit by logical AND between bits b1 and b4, RR Selectively short-circuit by logical AND between bits b0 and b4, R 16R By selectively shorting between bits b3 and b4 through logical OR, R 8RR By selectively short-circuiting between bits b2 and b4 through logical OR, R 4RR Selectively short-circuit by logical OR between bits b1 and b4, and R 2RR Selectively short-circuited by logical OR between bits b0 and b4.

[0057] This formed Figure 6 The reference voltage shape is shown in the figure. It can be seen that the use of Figure 5 The reference voltage shape obtained by the dithering circuit 15' is closer to the perfect stepped triangle shape. In this way, the spectrum expansion of the noise content is relatively Figure 3The embodiments are improved and suitable for a wide range of applications. Figure 7 As shown, this embodiment also achieves a similar shape for the current. Figure 8 It shows how the power spectrum of the input current of the DC-DC converter using the pulse generator 10 ′ and the dithering circuit 15 ′ is reduced by approximately 10 dB due to the dithering. Figure 9 Figure 2 shows the effect of jitter on the output voltage of a DC-DC converter, i.e., the presence of a ripple with a frequency corresponding to the jitter modulation frequency.

[0058] Obviously, modifications and variations can be made to what is described and illustrated herein without departing from the scope of the present disclosure. For example, reference is now made to Figure 10 The pulse generator 10" is described for generating a set on-time T ON The on-time is used to switch the DC-DC converter which operates using a constant on-time (COT) control loop.

[0059] The pulse generator 10" includes a circuit connected to an input voltage node V IN and the top resistor R between node N1 TOP , and a bottom resistor R connected between node N1 and ground level BOT The non-inverting input terminal of the amplifier 12 is connected to the node N1, the inverting input terminal thereof is connected to the node N2, and the output terminal thereof is connected to the gate of the n-channel transistor MN1. The drain of the n-channel transistor MN1 is connected to the node N3, and the source thereof is connected to the node N2. The resistor R RON Connected between node N2 and ground level, a voltage V is formed at node N2 PAR The source of the P-channel transistor MP1 is connected to the power supply voltage node V CC , its drain is connected to the node N3, and its gate is connected to the node N3. The source of the p-channel transistor MP2 is connected to the power supply voltage node V CC , whose drain is connected to the signal generator 13, and whose gate is connected to the node N3.

[0060] The signal generator 13 includes a drain connected to the p-channel transistor MP2 to receive the charging current I CHG The timing capacitor Ct is connected between the node N4 and the ground level. The switch S2 is connected between the node N4 and the ground level. The comparator 14 has its non-inverting input terminal connected to the node N4 to receive the voltage across the timing capacitor Ct, and has its inverting input terminal coupled to the dither reference voltage V REF . Set the on time T ON A clock pulse PULSE is generated at the output of the comparator 14 .

[0061] Note that the dither reference voltage V used here isREF With the jitter reference voltage V PAR Instead, this is achieved using an analog multiplexer that sequentially selects the value of the voltage divider applied to the bandgap voltage. However, in the case of a dithered reference voltage, V REF Each time the value of φ changes, noise is injected through the comparator, which may generate undesirable effects.

[0062] It should be understood that Figure 2 -3 technique can also be applied by changing the resistor R TOP Example of a connection to perform dithering.

[0063] In summary, although the present disclosure has been described with a limited number of embodiments, those skilled in the art having benefit of this disclosure may conceive of other embodiments that do not depart from the scope of the disclosure. Furthermore, those skilled in the art may conceive of embodiments that represent various combinations of the embodiments disclosed herein made in various ways.

Claims

1. A pulse generator for generating a set on-time T ON The pulse generator comprises: a voltage divider coupled between the input voltage and ground, generating a dithered reference voltage at a tap of the voltage divider; a voltage-to-current converter device that generates a charging current having a magnitude based on the dithered reference voltage; a timing capacitor configured to be charged by the charging current; a reset switch configured to selectively discharge the timing capacitor; as well as a comparator configured to generate a pulse based on a comparison between a timing voltage stored on the timing capacitor and a reference voltage, the pulse having a width set as a function of a rate of charging of the timing capacitor by the charging current; wherein the voltage divider is configured to incrementally vary the resistance seen at the taps of the voltage divider such that the dithered reference voltage is modulated in a stepped triangular manner.

2. The pulse generator of claim 1 , wherein the voltage divider comprises: a top resistor connected between the input voltage and the tap; a bottom resistor connected between the tap and a first switch, the first switch being configured to selectively couple the bottom resistor directly to a ground level or to a ground level through a second resistor; as well as An adjustable resistor is connected between the tap and a second switch, the adjustable resistor being configured to selectively couple the adjustable resistor to ground or allow the adjustable resistor to float, an incremental change in the resistance value of the adjustable resistor generating the incremental change in the resistance seen at the tap.

3. The pulse generator according to claim 2, wherein the adjustable resistor comprises: A plurality of resistors are connected in series between the tap and a ground level, and corresponding switches of a plurality of switches are connected across corresponding resistors of the plurality of resistors to selectively short-circuit different ones of the plurality of resistors. The pulse generator of claim 2 , wherein the resistance of the plurality of resistors varies by a power of 2.

5. The pulse generator according to claim 2, wherein the plurality of resistors comprises: a first resistor connected between the tap and a first node; a second resistor connected between the first node and the second node; a third resistor connected between the second node and a third node; a fourth resistor connected between the third node and the fourth node; a fifth resistor connected between the fourth node and the fifth node; as well as a sixth resistor connected between the fifth node and the sixth node; The plurality of switches include: a third switch connected between the first node and the second node, the third switch being operated by a fourth bit of the dithering control word; a fourth switch connected between the second node and the third node, the fourth switch being operated by a third bit of the dithering control word; a fifth switch connected between the third node and the fourth node, the fifth switch being operated by the second bit of the dithering control word; a sixth switch connected between the fourth node and the fifth node, the sixth switch being operated by a first bit of the dithering control word; and a seventh switch connected between the fifth node and a ground level, the seventh switch being operated by a zeroth bit of the dithering control word; wherein the second switch is connected between the sixth node and the ground level; and further comprising a control circuit configured to periodically increment the dithering control word from a first binary value to a second binary value, and once the dithering control word has reached the second binary value, periodically decrement the dithering control word from the second binary value back to the first binary value.

6. The pulse generator of claim 5 , wherein the resistance of the second resistor is equal to sixteen times a base resistance value, the resistance of the third resistor is equal to eight times the base resistance value, the resistance of the fourth resistor is equal to four times the base resistance value, the resistance of the fifth resistor is equal to two times the base resistance value, and the resistance of the sixth resistor is equal to the base resistance value.

7. The pulse generator according to claim 2, wherein the plurality of resistors comprises: a first resistor connected between the tap and a first node; a second resistor connected between the first node and the second node; a third resistor connected between the second node and a third node; a fourth resistor connected between the third node and the fourth node; a fifth resistor connected between the fourth node and the fifth node; a sixth resistor connected between the fifth node and the sixth node; a seventh resistor connected between the sixth node and the seventh node; an eighth resistor connected between the seventh node and the eighth node; a ninth resistor connected between the eighth node and the ninth node; as well as a tenth resistor connected between the ninth node and the tenth node; The plurality of switches include: a third switch connected between the first node and the second node, the third switch being operated by a logical AND between a third bit and a fourth bit of the dither control word; a fourth switch connected between the second node and the third node, the fourth switch being operated by a logical AND between the second bit and the fourth bit of the dithering control word; a fifth switch connected between the third node and the fourth node, the fifth switch being operated by a logical AND between the first bit and the fourth bit of the dithering control word; a sixth switch connected between the fourth node and the fifth node, the sixth switch being operated by a logical AND between the zeroth bit and the fourth bit of the dithering control word; a seventh switch connected between the fifth node and the sixth node, the seventh switch being operated by the fourth bit of the dithering control word; an eighth switch connected between the sixth node and the seventh node, the eighth switch being operated by a logical OR between the third bit and the fourth bit of the dithering control word; a ninth switch connected between the seventh node and the eighth node, wherein the ninth switch is operated by a logical OR operation between the second bit and the fourth bit of the dithering control word; a tenth switch connected between the eighth node and the ninth node, the tenth switch being operated by a logical OR between the first bit and the fourth bit of the dithering control word; and an eleventh switch connected between the ninth node and the tenth node, the eleventh switch being operated by a logical OR between the zeroth bit and the fourth bit of the dithering control word; wherein the second switch is connected between the tenth node and the ground level; and further comprising a control circuit configured to periodically increment the dithering control word from a first binary value to a second binary value, and once the dithering control word has reached the second binary value, periodically decrement the dithering control word from the second binary value back to the first binary value.

8. The pulse generator according to claim 7, wherein the resistance of the second resistor is equal to eight times the basic resistance value, the resistance of the third resistor is equal to four times the basic resistance value, the resistance of the fourth resistor is equal to two times the basic resistance value, the resistance of the fifth resistor is equal to the basic resistance value, the resistance of the sixth resistor is equal to four times the basic resistance value, the resistance of the seventh resistor is equal to sixteen times the basic resistance value, the resistance of the eighth resistor is equal to eight times the basic resistance value, the resistance of the ninth resistor is equal to four times the basic resistance value, and the resistance of the tenth resistor is equal to two times the basic resistance value.

9. The pulse generator according to claim 1, wherein the first transistor comprises a first transistor having a first conduction terminal connected to the third node, a second conduction terminal connected to the second node, and a control terminal coupled to the gate drive voltage; as well as The current mirror comprises: a second transistor having a first conduction terminal coupled to a first given voltage, a second conduction terminal connected to the third node, and a control terminal connected to the third node; and a third transistor having a first conduction terminal coupled to the first given voltage, a second conduction terminal connected to the timing capacitor, and a control terminal connected to the third node.

10. The pulse generator according to claim 9, wherein the first amplifier has a first input coupled to the tap to receive the dithered reference voltage, a second input coupled to the second node, and an output coupled to a control terminal of the first transistor; and Also included is a sense resistor connected between the second node and a second given voltage.

11. The pulse generator of claim 1 , wherein the voltage-to-current converter means comprises: a first transistor configured to generate a first current based on a gate drive voltage; a first amplifier configured to generate and modulate the gate drive voltage based on a comparison between the dithered reference voltage and a feedback voltage representative of the first current; as well as A current mirror is configured to mirror the first current to generate the charging current.

12. A method for generating a pulse for setting an on-time for switching a DC-DC converter, the method comprising: generating a dithered reference voltage by incrementally varying the resistance seen at the taps of the voltage divider such that the dithered reference voltage is modulated in a stepped triangular fashion; generating a charging current having a magnitude based on the dithered reference voltage; receiving the charging current at a timing capacitor such that the charging current charges the timing capacitor; as well as The voltage across the timing capacitor is compared to a non-dithered reference voltage and a pulse is asserted or de-asserted based on the comparison, wherein a width of the pulse is set as a function of the rate at which the timing capacitor is charged by the charging current.

13. The method of claim 12 , wherein the resistance seen at the tap of the voltage divider is incrementally changed by: Different ones of the plurality of resistors connected in series between the tap and a ground level are selectively short-circuited by closing corresponding ones of the plurality of switches connected across corresponding ones of the plurality of resistors. The method of claim 13 , wherein the resistance of the plurality of resistors varies by powers of two.

15. The method of claim 13, wherein each switch of the plurality of switches is closed in response to assertion of a different bit of a dither control word.

16. The method of claim 13 , wherein each switch in a first subset of the plurality of switches is closed in response to a result of a logical AND operation between two different bits of a dithering control word, and wherein each switch in a second subset of the plurality of switches is closed in response to a result of a logical OR operation between two different bits of the dithering control word.

17. The method according to claim 16, wherein The remaining switches of the plurality of switches that are not in the first subset or the second subset are closed in response to assertion of one of the bits of the dither control word.

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