SCA hardware abstraction layer addressing method and device

Abstract

The invention relates to the technical field of software radio, and provides an SCA hardware abstraction layer addressing method and device, and the method comprises Ethernet bus logic address addressing and RapidIO bus logic address addressing. The device comprises a general purpose processor GPP, a digital signal processor DSP, a field programmable gate array FPGA, an Ethernet switching chip, a RapidIO switching chip and a memory EMMC. And the general processor GPP, the digital signal processor DSP and the field programmable gate array FPGA are respectively connected with the Ethernet exchange chip and the RapidIO exchange chip through an Ethernet bus and a RapidIO bus. According to the invention, a hardware abstraction layer logic address which can be used by a software radio station can be provided for transplantation and deployment of a software radio waveform component conforming to an SCA standard.

Description

Technical Field

[0001] The present invention relates to the technical field of software defined radio (SDR), and in particular to an SCA hardware abstraction layer (SCA) addressing method and device. Background Art

[0002] Software-defined radio (SDR) was first proposed by Dr. Joseph Mitola. The Joint Tactical Radio System (JTRS) Joint Program Office of the U.S. Department of Defense (DoD) spearheaded the development of the Software Communications Architecture (SCA) to support hardware and software independence across different SDR devices, enabling waveform interconnection, interoperability, and communication, thereby reducing the overall lifecycle cost of radio equipment. SCA, based on software technology, defines a series of standards that standardize the development environment for tactical wireless communication terminal hardware platforms and the development process for application waveforms. The latest standard is SCA version 4.1. Within the SCA series of standards, the SDR Modem Hardware Abstraction Layer (MHAL) application programming interface abstracts the modem interface from application software, providing software developers with an API for waveform-specific target platforms. However, MHAL only constrains the communication protocol interface (source and sink functions) between different computing units and does not mandate the number of computing units, the hardware architecture, or the transmission method.

[0003] The paper "Analysis of Hardware Abstraction Layer Application Programming Interface Based on SCA Specification" by Wang Yangang et al. analyzes the data structure and function interface of MHAL from the perspective of SCA standard specifications.

[0004] Chinese patent publication number CN107248867A provides a method for implementing MHAL on a DSP based on the SRIO bus, including MHAL initialization, implemented function interface, workflow, etc. However, it does not provide hardware abstraction layer addressing and devices for the GPP, DSP, and FPGA hybrid hardware structure, nor does it support multiple buses. Summary of the Invention

[0005] In view of the above problems, the present invention provides an SCA hardware abstraction layer addressing method and device.

[0006] The present invention provides an SCA hardware abstraction layer addressing method, comprising:

[0007] Ethernet bus logical addressing;

[0008] RapidIO bus logical addressing.

[0009] In some embodiments, the Ethernet bus logical addressing includes:

[0010] The logical address of the general purpose processor GPP is solidified in the configuration file XML;

[0011] The logical address of the digital signal processor DSP is solidified in the configuration file XML;

[0012] The logic address of the field programmable gate array FPGA is solidified in RAM;

[0013] Bind IP to each general purpose processor (GPP), digital signal processor (DSP), and field programmable gate array (FPGA) in the Ethernet switch chip;

[0014] Determine the Ethernet bus logical addressing format.

[0015] In some embodiments, the Ethernet bus logical address addressing format is specifically:

[0016] (1) The logical address length is 16 bits, in big endian order;

[0017] (2) Logical address Bit 15, used to indicate status;

[0018] (3) Logical address Bit 14-Bit 12, used to indicate the bus type of the encapsulated MHAL. 0b000 indicates an Ethernet bus, and 0b001 indicates a RapidIO bus.

[0019] (4) Logical address Bit11-Bit7, used to represent the IP number;

[0020] (5) Logical address Bit6-Bit4, used to indicate the channel number;

[0021] (6) Logical address Bit3-Bit1, used to indicate the message type;

[0022] (7) Logical address Bit 0 indicates spare and is used for function expansion.

[0023] In some embodiments, the last byte of the IP address of each processor is equal to the IP number in the Ethernet bus logical address format.

[0024] In some embodiments, the RapidIO bus logical addressing includes:

[0025] The general purpose processor GPP logical address is solidified in the configuration file XML;

[0026] The digital signal processor DSP logical address is solidified in the configuration file XML;

[0027] The logic address of the field programmable gate array FPGA is fixed in RAM;

[0028] The RapidIO switch chip allocates nodes for each general-purpose processor (GPP), digital signal processor (DSP), and field-programmable gate array (FPGA);

[0029] Determine the RapidIO bus logical address format.

[0030] In some embodiments, the RapidIO bus logical address format is specifically:

[0031] (1) The logical address length is 16 bits, in big endian order;

[0032] (2) Logical address Bit 15, used to indicate status;

[0033] (3) Logical address Bit 14-Bit 12, used to indicate the bus type of the encapsulated MHAL. 0b000 indicates an Ethernet bus, and 0b001 indicates a RapidIO bus.

[0034] (4) Logical address Bit11-Bit7, used to indicate the RapidIO node number;

[0035] (5) Logical address Bit6-Bit4, used to indicate the channel number;

[0036] (6) Logical address Bit3-Bit1, used to indicate the message type;

[0037] (7) Logical address Bit 0 indicates spare and is used for function expansion.

[0038] In some embodiments, the RapidIO node numbering rules are:

[0039] The GPP node number ranges from 0 to 11, and is numbered consecutively starting from 0. The number increases by 1 for each additional GPP.

[0040] The node number of the digital signal processor (DSP) ranges from 12 to 21, and is numbered consecutively starting from 12. The number increases by 1 for each additional digital signal processor (DSP).

[0041] The field programmable gate array (FPGA) node number ranges from 22 to 31, and is numbered consecutively starting from 22. The number increases by 1 for each additional field programmable gate array (FPGA).

[0042] The present invention also provides an SCA hardware abstraction layer addressing device using the above-mentioned SCA hardware abstraction layer addressing method, wherein the SCA hardware abstraction layer addressing device includes a general purpose processor GPP, a digital signal processor DSP, a field programmable gate array FPGA, an Ethernet switching chip, a RapidIO switching chip, and a memory EMMC;

[0043] The general purpose processor GPP, digital signal processor DSP and field programmable gate array FPGA are connected to the Ethernet switching chip and RapidIO switching chip respectively through the Ethernet bus and RapidIO bus; the general purpose processor GPP is deployed with an operating system OS and a common object request broker architecture CORBA; the general purpose processor GPP and digital signal processor DSP are respectively connected to external memory EMMC for storing programs and configuration files

[0044] In some embodiments, the Ethernet bus is a Gigabit Ethernet bus; and the RapidIO bus is a 4XRapidIO bus.

[0045] In some embodiments, the Common Object Request Broker Architecture (CORBA) should be compiled on an operating system (OS) into a library adapted to the current operating system (OS).

[0046] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0047] 1. The present invention uses Ethernet and RapidIO dual buses to implement the hardware portion of the MHAL and clarifies the addressing rules of the hardware abstraction layer. This allows for logical addressing based on the actual usage environment and provides hardware abstraction layer logical addresses that can be used by software radio stations, facilitating the transplantation and deployment of software radio waveform components that comply with the SCA standard.

[0048] 2. The present invention is designed according to the SCA series standards and provides an operational and implementable method.

[0049] 3. The present invention supports Gigabit Ethernet and 4X RapidIO communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 This is a schematic diagram of the message structure for the hardware abstraction layer.

[0051] Figure 2 Schematic diagram of the structure of the SCA hardware abstraction layer addressing device in an embodiment of the present invention.

[0052] Figure 3 Schematic diagram of the Ethernet bus logical address format in an embodiment of the present invention.

[0053] Figure 4Schematic diagram of the RapidIO bus logical address format in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0055] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0056] Example

[0057] In the SCA standard specification, the hardware abstraction layer message structure is defined as follows: Figure 1 As shown, it includes a 2-byte logical address (LD), a 2-byte hardware abstraction layer message length (Length, including the total length of LD, Length, and Payload), and a data payload (Payload) of Length-4 bytes.

[0058] SCA hardware abstraction layer device such as Figure 2 As shown, it includes a general-purpose processor (GPP), a digital signal processor (DSP), a field-programmable gate array (FPGA), an Ethernet switch chip, a RapidIO switch chip, and an EMMC memory. Specifically, in the SCA hardware abstraction layer device, the general-purpose processor (GPP), the digital signal processor (DSP), and the field-programmable gate array (FPGA) are connected to the Ethernet switch chip and the RapidIO switch chip via a Gigabit Ethernet bus and a 4x RapidIO bus, respectively, and deploy Gigabit Ethernet drivers and 4x RapidIO drivers, respectively. The general-purpose processor (GPP) deploys an operating system (OS) and a Common Object Request Broker Architecture (CORBA). The general-purpose processor (GPP) and the digital signal processor (DSP) are each connected to an external EMMC memory for storing programs and configuration files.

[0059] The Common Object Request Broker Architecture (CORBA) should be compiled on the operating system (OS) into a library adapted to the current operating system (OS).

[0060] An embodiment of the present invention provides an SCA hardware abstraction layer addressing method, including:

[0061] (1) Ethernet bus logical addressing;

[0062] (2) RapidIO bus logical addressing.

[0063] The Ethernet bus logical addressing includes:

[0064] The logical address of the general purpose processor GPP is solidified in the configuration file XML;

[0065] The logical address of the digital signal processor DSP is solidified in the configuration file XML;

[0066] The logic address of the field programmable gate array FPGA is solidified in RAM;

[0067] Bind IP to each general purpose processor (GPP), digital signal processor (DSP), and field programmable gate array (FPGA) in the Ethernet switch chip;

[0068] Determine the Ethernet bus logical addressing format.

[0069] In this embodiment, the Ethernet bus logical address format is as follows: Figure 3 As shown, specifically:

[0070] (1) The logical address length is 16 bits, in big endian order;

[0071] (2) Logical address Bit 15, used to indicate status, generally set to 0;

[0072] (3) Logical address Bit 14-Bit 12, used to indicate the bus type of the encapsulated MHAL. 0b000 indicates an Ethernet bus, and 0b001 indicates a RapidIO bus.

[0073] (4) Logical address Bit 11-Bit 7 is used to represent the IP number. The last byte of the IP address of each processor is equal to the IP number in the Ethernet bus logical address format.

[0074] (5) Logical address Bit6-Bit4, used to indicate the channel number. Channel number 1 is 0b001, channel 2 is 0b010, and so on.

[0075] (6) Logical address Bit3-Bit1, used to indicate the message type: 0b001 indicates a voice message, 0b010 indicates a data control message, and 0b011 indicates a data service message;

[0076] (7) Logical address Bit 0 indicates standby, used for function expansion, and is filled with 0 when in standby.

[0077] The RapidIO bus logical addressing includes:

[0078] The general purpose processor GPP logical address is solidified in the configuration file XML;

[0079] The digital signal processor DSP logical address is solidified in the configuration file XML;

[0080] The logic address of the field programmable gate array FPGA is fixed in RAM;

[0081] The RapidIO switch chip allocates nodes for each general-purpose processor (GPP), digital signal processor (DSP), and field-programmable gate array (FPGA);

[0082] Determine the RapidIO bus logical address format.

[0083] In this embodiment, the RapidIO bus logical address format is as follows: Figure 4 As shown, specifically:

[0084] (1) The logical address length is 16 bits, in big endian order;

[0085] (2) Logical address Bit 15, used to indicate status, generally set to 0;

[0086] (3) Logical address Bit 14-Bit 12, used to indicate the bus type of the encapsulated MHAL. 0b000 indicates an Ethernet bus, and 0b001 indicates a RapidIO bus.

[0087] (4) Logical address Bit 11-Bit 7 is used to represent the RapidIO node number. The RapidIO node numbering rule is as follows: the general purpose processor (GPP) node number ranges from 0 to 11, and is numbered consecutively starting from 0. The number increases by 1 for each additional general purpose processor (GPP); the digital signal processor (DSP) node number ranges from 12 to 21, and is numbered consecutively starting from 12. The number increases by 1 for each additional digital signal processor (DSP); the field programmable gate array (FPGA) node number ranges from 22 to 31, and is numbered consecutively starting from 22. The number increases by 1 for each additional field programmable gate array (FPGA);

[0088] (5) Logical address Bit6-Bit4, used to indicate the channel number. Channel number 1 is 0b001, channel 2 is 0b010, and so on.

[0089] (6) Logical address Bit3-Bit1, used to indicate the message type: 0b001 indicates a voice message, 0b010 indicates a data control message, and 0b011 indicates a data service message;

[0090] (7) Logical address Bit 0 indicates standby, used for function expansion, and is filled with 0 when in standby.

[0091] A set of logical addresses LD generated according to the above addressing rules is shown in Table 1.

[0092] Table 1 shows an example of a set of logical addresses LD generated according to the addressing rules:

[0093]

[0094] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A SCA hardware abstraction layer addressing method, characterized in that: include: Ethernet bus logical addressing; RapidIO bus logical addressing.

2. The SCA hardware abstraction layer addressing method according to claim 1, characterized in that: The Ethernet bus logical addressing includes: The logical address of the general purpose processor GPP is solidified in the configuration file XML; The logical address of the digital signal processor DSP is solidified in the configuration file XML; The logic address of the field programmable gate array FPGA is solidified in RAM; Bind IP to each general purpose processor (GPP), digital signal processor (DSP), and field programmable gate array (FPGA) in the Ethernet switch chip; Determine the Ethernet bus logical addressing format.

3. The SCA hardware abstraction layer addressing method according to claim 2, characterized in that: The Ethernet bus logical address addressing format is specifically: (1) The logical address length is 16 bits, in big endian order; (2) Logical address Bit 15, used to indicate status; (3) Logical address Bit 14-Bit 12, used to indicate the bus type of the encapsulated MHAL. 0b000 indicates an Ethernet bus, and 0b001 indicates a RapidIO bus. (4) Logical address Bit11-Bit7, used to represent the IP number; (5) Logical address Bit6-Bit4, used to indicate the channel number; (6) Logical address Bit3-Bit1, used to indicate the message type; (7) Logical address Bit 0 indicates spare and is used for function expansion.

4. The SCA hardware abstraction layer addressing method according to claim 3, characterized in that: The last byte of each processor's IP address is equal to the IP number in the Ethernet bus logical address compilation format.

5. The SCA hardware abstraction layer addressing method according to claim 1, characterized in that: The RapidIO bus logical addressing includes: The general purpose processor GPP logical address is solidified in the configuration file XML; The digital signal processor DSP logical address is solidified in the configuration file XML; The logic address of the field programmable gate array FPGA is fixed in RAM; The RapidIO switch chip allocates nodes for each general-purpose processor (GPP), digital signal processor (DSP), and field-programmable gate array (FPGA); Determine the RapidIO bus logical address format.

6. The SCA hardware abstraction layer addressing method according to claim 5, characterized in that: The RapidIO bus logical address format is specifically: (1) The logical address length is 16 bits, in big endian order; (2) Logical address Bit 15, used to indicate status; (3) Logical address Bit 14-Bit 12, used to indicate the bus type of the encapsulated MHAL. 0b000 indicates an Ethernet bus, and 0b001 indicates a RapidIO bus. (4) Logical address Bit11-Bit7, used to indicate the RapidIO node number; (5) Logical address Bit6-Bit4, used to indicate the channel number; (6) Logical address Bit3-Bit1, used to indicate the message type; (7) Logical address Bit 0 indicates spare and is used for function expansion.

7. The SCA hardware abstraction layer addressing method according to claim 6, characterized in that: The RapidIO node numbering rules are as follows: The GPP node number ranges from 0 to 11, and is numbered consecutively starting from 0. The number increases by 1 for each additional GPP. The node number of the digital signal processor (DSP) ranges from 12 to 21, and is numbered consecutively starting from 12. The number increases by 1 for each additional digital signal processor (DSP). The field programmable gate array (FPGA) node number ranges from 22 to 31, and is numbered consecutively starting from 22. The number increases by 1 for each additional field programmable gate array (FPGA).

8. An SCA hardware abstraction layer addressing device using the SCA hardware abstraction layer addressing method according to any one of claims 1 to 7, characterized in that: The SCA hardware abstraction layer addressing device includes a general purpose processor GPP, a digital signal processor DSP, a field programmable gate array FPGA, an Ethernet switching chip, a RapidIO switching chip and a memory EMMC; The general-purpose processor GPP, digital signal processor DSP and field programmable gate array FPGA are connected to the Ethernet switching chip and RapidIO switching chip respectively through the Ethernet bus and RapidIO bus; the general-purpose processor GPP is deployed with an operating system OS and a common object request broker architecture CORBA; the general-purpose processor GPP and digital signal processor DSP are respectively connected to external memory EMMC for storing programs and configuration files.

9. The SCA hardware abstraction layer addressing device according to claim 8, characterized in that: The Ethernet bus is a Gigabit Ethernet bus; the RapidIO bus is a 4X RapidIO bus.

10. The SCA hardware abstraction layer addressing device according to claim 8, characterized in that: The Common Object Request Broker Architecture (CORBA) should be compiled on the operating system (OS) into a library adapted to the current operating system (OS).

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