Signal processing method, device and storage medium based on distributed system

Abstract

The application discloses a signal processing method and device based on a distributed system and a storage medium, relates to the technical field of electric communication, and receives an original output signal of an ultra-high-definition signal source through a digital input interface, determines the resolution of a spliced display terminal and a target display area, performs stretching operation on the original output signal according to the resolution, performs area cutting on the stretched original output signal according to the target display area, determines a target signal, synchronizes the processed target signal to sub-distributed codec devices in the same group through a cascade architecture, and finally drives digital output interfaces of the sub-distributed codec devices to transmit the target signal to corresponding sub-screens of the spliced display terminal. The application processes the ultra-high-definition signal through multiple distributed codec devices in the distributed codec device and transmits the signal to corresponding sub-screens, so that the image display quality is improved and the image display delay is reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic communication technology, and in particular to a signal processing method, device, and storage medium based on a distributed system. Background Art

[0002] At present, mainstream distributed large-screen systems usually divide the source signal first, and then use multiple encoders to collect and encode it at a high compression rate, compressing the source signal into formats such as H.264 / H.265. The compressed code stream is then transmitted to the display end through the network, and finally received and decompressed by the corresponding decoder, and the decompressed image signal is output to the large screen for combined display. However, the above solution compresses the source signal into formats such as H.264 / H.265, which loses the quality and details of the original image. When the source signal needs to display fine content, the image displayed on the final large screen will be insufficient in clarity and lack of details, resulting in lower image display quality and increased image display delay.

[0003] The above content is only used to assist in understanding the technical solution of this application and does not constitute an admission that the above content is prior art. Summary of the Invention

[0004] The present application provides a signal processing method, device and storage medium based on a distributed system, aiming to solve the problems of low image display quality and increased image display delay in traditional solutions.

[0005] To achieve the above objectives, the present application provides a signal processing method based on a distributed system, which is applied to a distributed codec device, wherein the distributed codec device is composed of at least two sub-distributed codecs. The signal processing method based on the distributed system includes the following steps:

[0006] Receive the original output signal of the ultra-high resolution signal source through the digital input interface;

[0007] Determining the resolution and target display area of ​​the splicing display terminal, and performing a stretching operation on the original output signal according to the resolution;

[0008] Performing regional cropping on the stretched original output signal according to the target display area to determine a target signal;

[0009] Synchronizing the processed target signal to the sub-distributed codecs in the same group through a cascade architecture;

[0010] The digital output interface of each sub-distributed codec is driven to transmit the target signal to the sub-screen corresponding to the splicing display terminal, so that the display terminal splices and displays the target signal received by each sub-screen.

[0011] In one embodiment, the step of determining the resolution and target display area of ​​the splicing display terminal and performing a stretching operation on the original output signal according to the resolution includes:

[0012] Obtaining the resolution of the splicing display terminal and the target resolution of the ultra-high-resolution signal source;

[0013] Calculating horizontal and vertical stretching ratios according to the resolution and the target resolution;

[0014] An interpolation operation is performed on the original output signal based on the stretch ratio to generate an amplified signal that matches the resolution of the splicing display terminal.

[0015] In one embodiment, the step of performing region cropping on the stretched original output signal according to the target display area to determine the target signal includes:

[0016] acquiring the amplified signal after the stretching operation;

[0017] Calculating the overlapping range between the physical coordinates and the target display area according to the physical coordinates of the sub-screen of the splicing display terminal corresponding to each sub-distributed codec;

[0018] The amplified signal is subjected to the region cropping based on the overlapping range to generate the target signal.

[0019] In one embodiment, the step of synchronizing the processed target signal to the sub-distributed codecs in the same group through a cascade architecture includes:

[0020] Selecting at least one sub-distributed codec connected to a target display area corresponding to the ultra-high-resolution signal source as a master node;

[0021] Connecting the target signal to the sub-distributed codecs of the same group in series in a daisy-chain topology through the cascade output port of the master node;

[0022] During the concatenation process, the master node sends a control data packet containing the target signal to the sub-distributed codec.

[0023] In one embodiment, the step of sequentially connecting the target signal to the sub-distributed codecs of the same group in a daisy chain topology includes:

[0024] duplicating the target signal into multiple parallel signals through the master node;

[0025] Transmitting the multiple parallel signals to the corresponding sub-distributed codecs in a point-to-point direct connection manner through the cascade output port;

[0026] After receiving the multiple parallel signals, each sub-distributed codec determines redundant data in the multiple parallel signals that is not within the processing range of the node, and discards the redundant data.

[0027] In one embodiment, after the step of sequentially connecting the target signal to the sub-distributed codecs in the same group in a daisy-chain topology through the cascade output port of the master node, the method further includes:

[0028] Embedding a mapping relationship between a device identifier and sub-screen coordinates in the target signal through the master node;

[0029] After the sub-distributed codec receives the target signal, extracting a corresponding signal area according to the device identifier;

[0030] The phase of the target signal is adjusted according to the mapping relationship of the sub-screen coordinates and the signal area.

[0031] In one embodiment, after the step of receiving the original output signal of the ultra-high resolution signal source through the digital input interface, the method further includes:

[0032] Upon receiving the original output signal of the ultra-high resolution signal source, extracting a synchronization timestamp of the original output signal;

[0033] Generate system reference time through preset network clock protocol;

[0034] The synchronization timestamp is compensated for deviations from the system reference time to generate an original output signal with a unified timestamp.

[0035] In one embodiment, after the step of performing region cropping on the stretched original output signal according to the target display area and determining the target signal, the method further includes:

[0036] When the sub-screen corresponding to a single sub-distributed codec needs to display at least two sub-pictures, performing the stretching operation and the region cropping on each of the sub-pictures;

[0037] Splicing and synthesizing the cropped sub-images according to the layout of the target display area to generate a target image;

[0038] The processed target image is displayed on the sub-screen.

[0039] In addition, to achieve the above-mentioned purpose, the present application also provides a signal processing device based on a distributed system, and the signal processing device based on a distributed system includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the signal processing method based on the distributed system as described above.

[0040] In addition, to achieve the above-mentioned purpose, the present application also provides a storage medium, which is a computer-readable storage medium, and a computer program is stored on the computer-readable storage medium. When the computer program is executed by the processor, the steps of the signal processing method based on the distributed system as described above are implemented.

[0041] The present application provides a signal processing method based on a distributed system, a signal processing device based on a distributed system, and a storage medium. The method receives the original output signal of an ultra-high-resolution signal source through a digital input interface, and then determines the resolution and target display area of ​​the splicing display terminal, and stretches the original output signal according to the resolution. The stretched original output signal is then regionally cropped according to the target display area to determine the target signal. The processed target signal is then synchronized to the sub-distributed codecs of the same group through a cascade architecture, and finally the digital output interface of each sub-distributed codec is driven to transmit the target signal to the sub-screen corresponding to the splicing display terminal, so that the display terminal splices and displays the target signal received by each sub-screen. The present application processes the ultra-high-resolution signal through multiple distributed codecs in a distributed codec device, and transmits it to the corresponding sub-screen for display, thereby improving the display effect of the ultra-high-resolution signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 This is a flow chart of a first embodiment of the signal processing method based on a distributed system of the present application;

[0045] Figure 2 This is a schematic diagram of the overall architecture involved in the embodiment of this application;

[0046] Figure 3 This is a schematic diagram of the area involved in the embodiment of the present application;

[0047] Figure 4 This is a schematic diagram of the cascade architecture involved in the embodiment of the present application;

[0048] Figure 5This is a schematic diagram of the implementation process of the 2x3 splicing large screen involved in the embodiment of this application;

[0049] Figure 6 This is a flow chart of a second embodiment of the signal processing method based on a distributed system of the present application;

[0050] Figure 7 An example diagram designed for the embodiment of this application;

[0051] Figure 8 This is a flowchart of a third embodiment of the signal processing method based on a distributed system of the present application;

[0052] Figure 9 This is a schematic diagram of the architecture of the hardware operating environment of the signal processing device based on the distributed system involved in the embodiment of the present application.

[0053] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0054] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0055] To better understand the above technical solutions, exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0056] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0057] At present, mainstream distributed large-screen systems usually divide the source signal first, and then use multiple encoders to collect and encode it at a high compression rate, compressing the source signal into formats such as H.264 / H.265. The compressed code stream is then transmitted to the display end through the network, and finally received and decompressed by the corresponding decoder, and the decompressed image signal is output to the large screen for combined display. However, the above solution compresses the source signal into formats such as H.264 / H.265, which loses the quality and details of the original image. When the source signal needs to display fine content, the image displayed on the final large screen will be insufficient in clarity and lack of details, resulting in lower image display quality and increased image display delay.

[0058] This application processes ultra-high-resolution signals through multiple distributed codecs in a distributed coding and decoding device, and transmits them to the corresponding sub-screen display, thereby improving image display quality and reducing image display delay.

[0059] Example 1

[0060] Based on this, the embodiment of the present application provides a signal processing method based on a distributed system, referring to Figure 1 , Figure 1 This is a flow chart of a first embodiment of a signal processing method based on a distributed system of the present application. The signal processing method based on a distributed system includes steps S10 to S50:

[0061] Step S10: receiving the original output signal of the ultra-high resolution signal source through the digital input interface.

[0062] In this embodiment, the processing action is performed by a distributed codec device, which is composed of at least two sub-distributed codecs. The distributed codec device is in communication with the ultra-high-resolution signal source and is connected to the splicing display terminal via a cascade architecture. The digital input interface is an interface on the distributed codec device for receiving input from an external signal source, including an HDMI input interface. The original output signal of the ultra-high-resolution signal source refers to a video signal source with ultra-high resolution, such as a 1x2 ultra-high-resolution computer source with a resolution of 3840x1080, which directly outputs the original video signal without compression and processing.

[0063] Specifically, first connect the HDMI output port of the ultra-high-resolution signal source to the HDMI input interface of the distributed codec device via an HDMI cable. When the ultra-high-resolution signal source starts to output the video signal, the digital input interface of the distributed codec device will detect the signal input. Then, the interface circuit receives and preliminarily processes the input original output signal, including signal amplification, filtering and other operations. During this process, the distributed codec device will decode the input signal according to the HDMI protocol and parse out parameters such as the resolution, frame rate, and color space of the video signal. For example, for a 1x2 ultra-high-resolution computer source, the HDMI signal it outputs contains two independent video streams, corresponding to the two display areas of the computer source. The distributed codec device accurately receives these two signals through the digital input interface and identifies their key information such as resolution and refresh rate.

[0064] For example, Figure 2 As shown, Figure 2This is a schematic diagram of the overall architecture involved in the embodiment of this application. Taking a 2x2 spliced ​​display terminal as an example, the spliced ​​display terminal includes 2x2, that is, 4 sub-screens, and the four sub-screens are connected to four distributed codecs, that is, sub-distributed codecs via HDMI. A computer or workstation carrying an ultra-high-resolution signal source is connected to two of the sub-distributed codecs.

[0065] Step S20: determining the resolution of the splicing display terminal and the target display area, and performing a stretching operation on the original output signal according to the resolution.

[0066] In this embodiment, a spliced ​​display terminal refers to a large display device composed of multiple display units. The display units include LCD or LED screens with an overall display resolution for displaying the final spliced ​​image. The target display area refers to the specific area on the spliced ​​display terminal where the ultra-high-resolution signal source is to be displayed. The size and position of this area are determined based on the actual display requirements. The stretching operation is to enlarge or reduce the original output signal based on the proportional relationship between the resolution of the spliced ​​display terminal and the native resolution of the ultra-high-resolution signal source so that the image can fit the target display area.

[0067] Specifically, the device first obtains the total resolution of the video wall and the coordinates and dimensions of the target display area. Then, using an internal image processing algorithm, it calculates the stretch ratio between the original output signal and the target display area. Next, a digital signal processor (DSP) or graphics processing unit (GPU) performs pixel-level interpolation on the original output signal, adding or subtracting pixels to achieve image enlargement or reduction. To ensure image quality, high-quality interpolation algorithms (such as bicubic interpolation) can be used to minimize image distortion and aliasing. For example, if a 1x2 ultra-high-resolution computer source (3840x1080) is displayed full-screen on a 2x3 video wall (5760x2160), the device needs to stretch the computer source image by 1.5 times horizontally and 2 times vertically. During this operation, the position and color value of each pixel in the new image are calculated based on the stretch ratio, generating a stretched image that matches the resolution of the video wall.

[0068] Optionally, as an optional implementation, in this embodiment, step S20 further includes:

[0069] Obtaining the resolution of the splicing display terminal and the target resolution of the ultra-high-resolution signal source; calculating the horizontal and vertical stretch ratios according to the resolutions and the target resolutions; and performing an interpolation operation on the original output signal based on the stretch ratios to generate an amplified signal that matches the resolution of the splicing display terminal.

[0070] Specifically, in general, the resolution of the ultra-high-resolution computer source is equal to or lower than the resolution of the spliced ​​large screen. If the resolutions of the two are equal, the HDMI output of the ultra-high-resolution computer source can be directly connected one-to-one to the HDMI input of the distributed codec; if the resolution of the ultra-high-resolution computer source is lower than the resolution of the spliced ​​large screen, then the distributed codec corresponding to the spliced ​​large screen needs to be grouped according to the corresponding ratio (in order to ensure that the image is not distorted due to stretching, the ratio of the ultra-high-resolution computer source and the spliced ​​large screen is generally the same).

[0071] In this embodiment, the horizontal number of pixels of the spliced ​​display terminal is divided by the horizontal number of pixels of the target resolution of the ultra-high-resolution signal source to obtain the horizontal stretch ratio; similarly, the vertical number of pixels of the spliced ​​display terminal is divided by the vertical number of pixels of the target resolution of the ultra-high-resolution signal source to obtain the vertical stretch ratio. During the specific calculation, the device performs a division operation through an internal processor and stores the result in the memory for subsequent image stretching processing. According to the calculated horizontal and vertical stretch ratios, a suitable interpolation algorithm (such as a bicubic interpolation algorithm) is selected to process the original output signal. For the position of each new pixel point, the device calculates the color value and brightness value of the pixel point based on the values ​​of the surrounding known pixel points and the formula of the interpolation algorithm. Specifically, the color value and brightness value of the pixel point can be determined by the GPU of the device or a dedicated image processing chip through matrix operations and numerical calculations.

[0072] By acquiring the resolution information of the splicing display terminal and the ultra-high-resolution signal source, the horizontal and vertical stretch ratios are accurately calculated, ensuring that the image can be magnified in the correct proportion and avoiding problems such as image distortion. Finally, a high-quality interpolation method is used to generate the amplified signal, effectively improving the image resolution and display quality. This allows the image of the ultra-high-resolution signal source to better adapt to the splicing display terminal, enhancing the display effect of the distributed splicing system when processing ultra-high-resolution signal sources.

[0073] Step S30: performing region cropping on the stretched original output signal according to the target display area to determine a target signal.

[0074] In this embodiment, region cropping refers to the operation of extracting the display portion corresponding to each sub-distributed codec from the stretched image based on the specific location and size of the target display area on the spliced ​​display terminal. The target signal refers to the image signal that, after stretching and cropping, meets the display requirements of the sub-distributed codec connected to each sub-distributed codec.

[0075] Specifically, the corresponding cropping area is determined based on the position coordinates and size of the sub-screen connected to each sub-distributed codec on the video wall. Then, an image processing algorithm accurately extracts the image pixel information for this area from the stretched image data. Specifically, the coordinates of the top-left and bottom-right corners of the cropping area are determined. Within the two-dimensional pixel matrix of the image data, the corresponding pixels are extracted according to these coordinate ranges to form new image data as the target signal. To ensure cropping accuracy, the device employs high-precision image positioning and cropping technology to ensure that each sub-distributed codec captures the correct image portion. For example, for a sub-distributed codec distributed on a video wall, the corresponding sub-screen position is [1920, 0, 3840, 1080] (with the coordinates originating from the top-left corner of the video wall). The device then extracts the pixel data within this rectangular area from the stretched image to form the target signal for that sub-distributed codec.

[0076] Optionally, in this embodiment, step S30 includes:

[0077] Obtain the amplified signal after the stretching operation; calculate the overlapping range between the physical coordinates and the target display area according to the physical coordinates of the sub-screen of the spliced ​​display terminal corresponding to each sub-distributed codec; and perform the area cropping on the amplified signal based on the overlapping range to generate the target signal.

[0078] Specifically, the distributed codec device magnifies and crops the computer source image according to the display ratio and display position, and then outputs it for display. Figure 3 As shown, Figure 3 This is a schematic diagram of the area cropping involved in the embodiment of the present application. For a 1x2 ultra-high-resolution computer source to be displayed in full screen on a 2x3 spliced ​​large screen, it is necessary to zoom in horizontally by 3 / 2=1.5 times and vertically by 2 / 1=2 times. Then, the cropping coordinates of the amplified computer source screen are calculated based on the overlapping area of ​​the sub-screen coordinates corresponding to the distributed codec and the windowing coordinates of the computer source screen on the large screen. For example, the computer source screen 1 is on the distributed codec 2, and the sub-screen coordinates corresponding to the distributed codec 2 are [1920,0,3840,1080]. The windowing coordinates of the computer source screen 1 on the large screen are [0,0,2880,2160]. The overlapping area is [1920,0,2880,1080]. Subtracting the windowing starting position [0,0], the cropping coordinates of the amplified computer source screen are [1920,0,2880,1080]. The order of zooming in and out may be reversed, and the principle is similar.

[0079] Step S40: Synchronize the processed target signal to the sub-distributed codecs in the same group through a cascade architecture.

[0080] In this embodiment, a cascaded architecture refers to the interconnection and collaboration of multiple sub-distributed codecs through a specific connection method (such as HDMI cascading), enabling efficient signal transmission and synchronous processing between these devices. Sub-distributed codecs in the same group are responsible for processing the same ultra-high-resolution signal source for display in a specific area of ​​a spliced ​​display terminal in the cascaded architecture, requiring signal synchronization and sharing between them.

[0081] Specifically, the members and cascade order of the sub-distributed codecs in the same group are first determined. Then, the output interfaces and input interfaces of these devices are connected in sequence through HDMI cascade cables to form a signal transmission link. During the transmission process, the sub-distributed codec of the starting node sends the processed target signal to the next cascaded device through the HDMI output interface. After receiving the signal, each subsequent device briefly processes the signal and then forwards it to the next device until all sub-distributed codecs in the same group receive the target signal. In order to ensure the synchronization of the signal, precise clock synchronization technology is used between devices to ensure that each device maintains the same time reference when processing and transmitting signals, thereby achieving synchronization of the target signal among devices in the same group.

[0082] Alternatively, as Figure 4 As shown, Figure 4 This is a schematic diagram of the cascade architecture involved in the embodiment of the present application. In the cascade architecture, the sub-distributed codec 4 serves as the starting node, and is sequentially connected upward and to the right in series with other distributed codecs corresponding to the same display area. The target signal is then sent to the sub-distributed codec 5 cascaded thereto through the HDMI output interface. After receiving the signal, the sub-distributed codec 5 is adjusted by the signal processing circuit to ensure the timing and integrity of the signal, and then continues to send it to the next device, such as the sub-distributed codec 7, until all devices in the same group have obtained the signal. Similarly, the distributed codec 6 serves as the starting node and is sequentially connected upward and to the left. Devices that need to display multiple screens should be used as the end point of the series as much as possible, so that it is also convenient to connect according to a unified rule. Connecting in series in the above manner can ensure that each distributed codec can capture all computer source images to be displayed on the local HDMI input.

[0083] Furthermore, in this embodiment, after step S40, the following steps are further included:

[0084] When the sub-screen corresponding to a single sub-distributed codec needs to display at least two sub-pictures, the stretching operation and the area cropping are performed on each of the sub-pictures respectively; the cropped sub-pictures are spliced ​​and synthesized according to the layout of the target display area to generate a target picture; and the processed target picture is displayed in the sub-screen.

[0085] Specifically, when it is determined that the sub-screen of a certain sub-distributed codec needs to display at least two sub-pictures, the device first obtains the original resolution of each sub-picture and the coordinates and size of its target display area on the sub-screen. Then, for each sub-picture, its stretching ratio in the horizontal and vertical directions is calculated respectively, that is, the ratio of the width of the target display area to the width of the original sub-picture is used as the horizontal stretching ratio, and the ratio of the height is used as the vertical stretching ratio. Each sub-picture is stretched using an interpolation algorithm to increase or decrease the number of pixels to achieve image enlargement or reduction. Next, according to the coordinates of the target display area of ​​each sub-picture on the sub-screen, the pixel positions of the upper left and lower right corners of the cropping area are determined, and the pixel data in the area is cut out in the stretched sub-picture to obtain the cropped sub-picture.

[0086] Based on the pre-set layout of the target display area, the position coordinates and arrangement order of each cropped sub-image within the target image are determined. Then, using an image synthesis algorithm, these sub-images are sequentially written into the corresponding areas of the target image according to their coordinate positions. Specifically, the pixel data of each sub-image is copied to the corresponding position on the target image, forming a unified pixel matrix. During this process, the device must ensure that there are no noticeable gaps or overlaps between the spliced ​​sub-images, and that parameters such as color and brightness remain consistent.

[0087] By stretching and cropping each sub-image individually, each one is ensured to accurately fit its target display area on the sub-screen. Multiple sub-images are then combined into a complete target image through splicing and synthesis, meeting the diverse content display requirements on the sub-screens. Leveraging the advantages of a distributed splicing system, the system's flexibility and adaptability in handling complex display scenarios are enhanced, enabling ultra-high-resolution signal sources to be presented in a richer, higher-quality format on spliced ​​display terminals. This further enhances the practicality and competitiveness of the distributed splicing system in various application scenarios, particularly in scenarios requiring the simultaneous display of multiple different sources or types of image content, providing users with a superior visual experience.

[0088] Step S50: driving the digital output interface of each sub-distributed codec to transmit the target signal to the sub-screen corresponding to the splicing display terminal, so that the display terminal splices and displays the target signal received by each sub-screen.

[0089] In this embodiment, a digital output interface refers to the interface on the sub-distributed codec used to output the processed image signal to the display terminal, a common example being an HDMI output interface. The sub-screens corresponding to the spliced ​​display terminal are independent display units driven by each sub-distributed codec within the spliced ​​display terminal. Each sub-screen is responsible for displaying a specific area within the entire spliced ​​image. Spliced ​​display combines the image portions displayed by multiple sub-screens into a complete, large image according to a set of rules and sequences.

[0090] Specifically, after receiving the synchronized target signal, each sub-distributed codec performs final signal processing and conversion via its internal digital output interface driver circuitry. This includes signal level conversion, clock adjustment, and color space conversion, ensuring accurate recognition and display by the sub-screen. The digital output interface then transmits the processed signal to the corresponding sub-screen via an HDMI cable. Upon receiving the signal, the sub-screen illuminates and controls the color of its pixels based on the image data contained in the signal, displaying the corresponding portion of the image. Within the video wall, all sub-screens simultaneously display their respective image portions, and splicing control technology is used to stitch together the sub-images corresponding to each sub-screen. For example, when outputting the signal, the sub-distributed codec performs precise pixel mapping and signal modulation based on the sub-screen's resolution and display characteristics. This ensures that the sub-screen correctly displays its assigned image area and maintains color and brightness consistency with adjacent sub-screens, thereby ensuring image integrity and uniformity across the entire video wall.

[0091] For example, Figure 5 As shown, Figure 5 This is a schematic diagram of the implementation process of the 2x3 spliced ​​large screen involved in the embodiment of the present application. Taking the resolution of the 2x3 spliced ​​large screen as 5760x2160 as an example, the target display area is the entire spliced ​​large screen. For the input 1x2 ultra-high-resolution computer source signal (3840x1080), the device calculates the horizontal stretching ratio as 5760 / 3840=1.5 and the vertical stretching ratio as 2160 / 1080=2. Then, the image processing chip performs row-by-row and column-by-column interpolation operations on the image data of the computer source, expands the width of the image by 1.5 times and the height by 2 times, and generates new stretched image data. The resolution of the stretched image is 5760x2160. Assume that the position of the sub-screen corresponding to a sub-distributed codec on the spliced ​​large screen is horizontally from the 1920th pixel column to the 3840th pixel column, and vertically from the 0th pixel row to the 1080th pixel row. Based on these coordinate parameters, the device extracts the corresponding area from the stretched image data, namely the pixel data from columns 1920 to 3840 and rows 0 to 1080, to form the target signal for that sub-distributed codec. In this way, each sub-distributed codec obtains the image portion corresponding to its own sub-screen position.

[0092] The sub-distributed codecs responsible for displaying the left area of ​​the 1x2 ultra-high-resolution computer source form a group. Assume that the group members include sub-distributed codecs 1, 2, and 3, which are cascaded in order from top to bottom. The HDMI output interface of sub-distributed codec 1 is connected to the HDMI input interface of sub-distributed codec 2, and the output interface of sub-distributed codec 2 is connected to the input interface of sub-distributed codec 3. The processed target signal starts from sub-distributed codec 1 and is transmitted to sub-distributed codecs 2 and 3 through the cascade link in turn. During the transmission process, each device adjusts the signal according to the clock synchronization signal to ensure that all devices in the same group finally receive the target signal synchronously. Similarly, if Figure 4 The 3x3 splicing large screen is the same as the above implementation method, and a new group of sub-distributed codecs are added to process the image signal. The specific implementation process will not be repeated here.

[0093] In the technical solution provided in this embodiment, the original output signal of the ultra-high-resolution signal source is received through a digital input interface, and then the resolution and target display area of ​​the splicing display terminal are determined, and the original output signal is stretched according to the resolution, and then the stretched original output signal is regionally cropped according to the target display area to determine the target signal, and then the processed target signal is synchronized to the sub-distributed codecs of the same group through a cascade architecture, and finally the digital output interface of each sub-distributed codec is driven to transmit the target signal to the sub-screen corresponding to the splicing display terminal, so that the display terminal splices and displays the target signal received by each sub-screen. This example solution processes the ultra-high-resolution signal through multiple distributed codecs in the distributed codec device and transmits it to the corresponding sub-screen for display, thereby improving the image display quality and reducing the image display delay.

[0094] In addition, the original output signal of the ultra-high-resolution signal source is stably received through the digital input interface, ensuring the integrity and quality of the signal source; then, precise stretching and cropping operations are performed according to the resolution of the splicing display terminal and the target display area, so that the image can perfectly adapt to the various sub-screens of the spliced ​​large screen; then, the cascade architecture is used to achieve synchronous signal transmission between the same group of sub-distributed codecs, ensuring the consistency of image display; finally, the processed target signal is accurately transmitted to the corresponding sub-screen through the digital output interface to realize splicing display. The whole process reduces display delay and improves picture quality, effectively overcoming the picture quality loss and delay problems existing in traditional distributed splicing systems when processing ultra-high-resolution signal sources.

[0095] Example 2

[0096] Based on this, the present application also provides a second embodiment, referring to Figure 6 , Figure 6 This is a flow chart of the second embodiment of the signal processing method based on a distributed system of the present application, wherein step S40 includes steps S41 to S43:

[0097] Step S41: selecting at least one sub-distributed codec connected to the target display area corresponding to the super-high-resolution signal source as a master node.

[0098] Step S42: connecting the target signal to the sub-distributed codecs of the same group in series in a daisy-chain topology through the cascade output port of the master node.

[0099] Step S43: During the concatenation process, the master node sends a control data packet containing the target signal to the sub-distributed codec.

[0100] In this embodiment, the master node refers to a sub-distributed codec that is directly connected to the ultra-high-resolution signal source in the cascade architecture composed of distributed codec devices. The cascade output port refers to the interface on the master node sub-distributed codec that is used to output the processed target signal to the next sub-distributed codec. Daisy chain topology is a network connection method in which devices are connected in sequence to form a link. The signal passes through each device in sequence from the starting device. After each device receives the signal, it forwards it to the next device until the end of the link. In distributed codec devices, the use of daisy chain topology can achieve efficient signal transmission and synchronous processing, reducing signal transmission delay and distortion.

[0101] A control packet is a data unit sent by the master node to the distributed codecs in the same group, containing target signal information and control instructions. It includes target signal parameters, display control information such as the coordinates of the target display area and the display order, as well as instructions required for device synchronization and coordination.

[0102] Specifically, first determine the location and range of the target display area on the spliced ​​display terminal where the ultra-high-resolution signal source is to be displayed. Then, find the sub-distributed codecs directly connected to the target display area. These sub-distributed codecs are usually located at the starting position or key position of the target display area. According to the selection rules, one of them is selected as the master node. Specifically, the sub-distributed codec in the upper left corner of the display area or the device with a lighter load can be given priority. After the master node is selected, it is configured accordingly, including setting it as the starting point for signal transmission and granting it the authority to control and coordinate devices in the same group. For example, when a 1x2 ultra-high-resolution computer source is displayed on a 2x2 spliced ​​large screen, the target display area covers the two sub-screens on the left side of the spliced ​​large screen. Then, among the sub-distributed codecs corresponding to the two sub-screens on the left, the sub-distributed codec located in the upper left corner can be selected as the master node. It will be responsible for receiving the signal from the ultra-high-resolution signal source and distributing it to other devices in the same group.

[0103] Next, the master node's cascade output port is connected to the input port of the next sub-distributed codec via an HDMI cable. After receiving the target signal, the master node transmits it through the cascade output port. The next sub-distributed codec receives the signal and processes it accordingly, sending it to the next device through its own cascade output port. This continues until all sub-distributed codecs in the same group have received the target signal. During this process, each device needs to properly buffer and synchronize the signal to ensure stability and synchronization during transmission. For example, when the master node sends a signal to the next device, it waits for the device to confirm receipt before continuing to send subsequent data, thus ensuring complete signal transmission. Furthermore, precise clock synchronization technology is used between devices to ensure that each device maintains the same time reference when processing and forwarding signals, achieving synchronous signal transmission.

[0104] When the master node transmits the target signal through the cascade output port, it generates a control packet. The control packet generation process includes collecting relevant parameters of the target signal, setting display control information, and writing device synchronization instructions. The master node sends the control packet along with the target signal to the next sub-distributed codec using a dedicated communication protocol, such as a custom protocol based on TCP / IP or an HDMI extension. Upon receiving the control packet, the next device parses it, extracts the parameters and instructions, and processes the target signal accordingly, adjusting its own display parameters and synchronization status. This device then forwards the control packet to the next sub-distributed codec until all devices in the group have received and processed the control packet. Specifically, the control packet may include information such as the target signal resolution (3840x2160), the frame rate (60Hz), the coordinate range of the target display area, and instructions for specific cropping and splicing operations upon receiving the signal. Based on this information, the devices in the group accurately process the target signal to ensure the desired display quality.

[0105] Optionally, in this embodiment, the step of sequentially connecting the target signal to the sub-distributed codecs of the same group in a daisy chain topology includes:

[0106] The target signal is copied into multiple parallel signals through the master node; the multiple parallel signals are transmitted to the corresponding sub-distributed codecs in a point-to-point direct connection manner through the cascade output port; after each sub-distributed codec receives the multiple parallel signals, the redundant data in the multiple parallel signals that is not within the processing range of the node is determined, and the redundant data is discarded.

[0107] Specifically, after receiving the target signal and performing preliminary processing, the master node inputs it into the signal replication module. The signal replication module contains multiple signal replication units, each responsible for replicating one signal path. These units replicate the target signal using high-speed signal processing circuits, such as FPGAs or ASICs, ensuring that each replicated signal remains highly consistent with the original signal in terms of timing and content. For example, the master node needs to replicate the target signal into three parallel signals, each transmitted to three sub-distributed codecs. After receiving the target signal, the signal replication module simultaneously replicates the signal through the three signal replication units, with each replica generating a signal identical to the original.

[0108] Then each cascade output port of the master node is connected to the input port of a specific sub-distributed codec via HDMI. During the transmission process, the signal control unit of the master node distributes the copied multi-channel parallel signals to each cascade output port. Each output port encodes and modulates the signal according to the preset communication protocol, and then sends the signal to the corresponding sub-distributed codec through a cable. After receiving the multi-channel parallel signal, each sub-distributed codec first parses the signal through the signal parsing module to extract the data packet and control information in the signal. Then, based on the device's own processing range, including the coordinates of the target display area, the position of the sub-screen, etc. and preset rules, it determines which data belongs to the range that needs to be processed by this node and which data is redundant data. For redundant data, the device discards it through the data discarding module.

[0109] The target signal is copied into multiple parallel signals through the master node to improve the transmission efficiency and synchronization of the signal, ensuring that multiple sub-distributed codecs can receive the same signal at the same time; secondly, the multiple parallel signals are transmitted in a point-to-point direct connection mode, which reduces the interference and delay of the signal during the transmission process, improves the signal quality and system stability; in addition, by discarding redundant data at the sub-distributed codec end, the processing burden of the device is reduced, thereby improving the efficiency and response speed of the device.

[0110] Furthermore, in this embodiment, after the step of sequentially connecting the target signal to the sub-distributed codecs of the same group in a daisy-chain topology through the cascade output port of the master node, the method further includes:

[0111] The mapping relationship between the device identifier and the sub-screen coordinates is embedded in the target signal through the main node; after the sub-distributed codec receives the target signal, the corresponding signal area is extracted according to the device identifier; and the phase of the target signal is adjusted according to the mapping relationship of the sub-screen coordinates and the signal area.

[0112] Specifically, device identifier extraction refers to the process by which the sub-distributed codec identifies and reads the device identifier from the received target signal. The signal region to be processed refers to the portion of the target signal image that the sub-distributed codec determines it needs to process, based on the mapping between the device identifier and the sub-screen coordinates.

[0113] After the sub-distributed codec receives the target signal, it first parses the signal through the signal parsing module. The signal parsing module searches the metadata portion of the signal and extracts the device identifier and the sub-screen coordinate mapping relationship. The device then compares the extracted device identifier with its own device identifier. If they match, the device determines the signal area it needs to process based on the sub-screen coordinate mapping relationship. After determining the signal area to be processed, the sub-distributed codec calculates its own position on the splicing display terminal and its relative position to other sub-screens based on the sub-screen coordinate mapping relationship. The device then adjusts the phase of the target signal through the phase adjustment module. The phase adjustment module fine-tunes the signal clock signal based on the relative position of the device and the preset synchronization parameters.

[0114] It should be noted that by embedding the mapping relationship between device identifiers and sub-screen coordinates in the target signal, processing guidance is provided to the sub-distributed codec, ensuring that each device can accurately identify and process its own signal portion. The sub-distributed codec extracts the corresponding signal area based on the device identifier, improving system processing efficiency and accuracy, avoiding unnecessary signal processing and resource waste. Finally, the phase of the target signal is adjusted based on the sub-screen coordinate mapping relationship to ensure that the sub-screen images are correctly aligned and displayed synchronously, improving the overall display quality of the video wall.

[0115] For example, Figure 7 As shown, Figure 7 The example diagram designed for the embodiment of this application is combined with Figure 5 Consider a 3x3 large video wall, with the target display area consisting of the three central sub-screens (positions (2,2), (2,3), and (3,2)). Three sub-distributed codecs are directly connected to the target display area, corresponding to these three sub-screens. Based on the selection rule, the sub-distributed codec at position (2,2) is preferentially selected as the master node. This device is configured in master node mode, enabling it to receive signals from ultra-high-resolution signal sources and begin distributing the signals to other devices in the same group.

[0116] In the technical solution provided in this embodiment, cascade transmission of signals is performed through a daisy chain topology, which improves the efficiency and synchronization of signal transmission and ensures the synchronous display of images on the spliced ​​display terminal; by sending control data packets containing target signals, the sub-distributed codecs in the same group can accurately receive and process signals, ensuring the consistency and stability of the display effect.

[0117] Example 3

[0118] Based on this, the present application also provides a third embodiment, referring to Figure 8 , Figure 8This is a flow chart of the third embodiment of the signal processing method based on a distributed system of the present application. After step S10, steps S60 to S80 are also included:

[0119] Step S60: upon receiving the original output signal of the ultra-high resolution signal source, extracting the synchronization timestamp of the original output signal.

[0120] Step S70: Generate system reference time through a preset network clock protocol.

[0121] Step S80: performing offset compensation on the synchronization timestamp and the system reference time to generate an original output signal with a unified timestamp.

[0122] In this embodiment, a synchronization timestamp refers to a set of time information embedded in the original output signal generated by the ultra-high-resolution signal source. This time information is typically generated by the signal source's clock system and is used to identify the specific time point corresponding to the signal content. Extracting the synchronization timestamp is the process of identifying and obtaining this time information from the received original output signal. The preset network clock protocol is a preconfigured protocol used to synchronize the clocks of various devices in the distributed splicing system. Network clock protocols include the Network Time Protocol (NTP) and the Precision Time Protocol (PTP). These protocols broadcast or multicast time synchronization information within the local area network, enabling all devices in the network to adjust their clocks to a common time base. Generating the system reference time refers to running the preset network clock protocol to generate a standard time signal that serves as a time reference for the entire system. This reference time serves as the basis for time synchronization for all devices in the system. Deviation compensation is the process of adjusting the difference between the extracted synchronization timestamp and the system reference time. Since the local clock of the ultra-high-resolution signal source and the network clock of the distributed splicing system may not be completely consistent, clock drift and initial time deviation may occur. Therefore, deviation compensation is required to eliminate these differences.

[0123] Specifically, when the distributed codec receives the raw output signal from the ultra-high-resolution signal source via its digital input interface, the signal processing module immediately begins parsing the signal. It searches the packet header within the metadata portion of the signal for the storage location of the synchronization timestamp. Using predefined parsing rules, the synchronization timestamp data can be extracted based on the standard format embedded in the HDMI signal's timestamps.

[0124] As an optional implementation, for signals transmitted using the HDMI 2.0 protocol, the synchronization timestamp is located in the ancillary data segment at the beginning of each video frame. By reading the data at these locations, the device obtains the time information recorded by the signal source when generating the signal. This time information is typically a relative time value referenced to a starting point of the signal source's local clock, such as the number of microseconds or milliseconds that have elapsed since the signal source started.

[0125] Optionally, a network clock server is configured within the distributed splicing system network, and a device can be designated as a time master. This server, or master, runs a pre-defined network clock protocol. Other distributed codec devices in the network act as slaves, communicating with the time master through a network interface. The time master sends time synchronization information to the slaves at a specified interval, including the current precise time value, clock offset, and network delay compensation parameters. Upon receiving this information, the slaves adjust their local clocks according to the network clock protocol algorithm to align them with the master. After a period of synchronization, all devices in the system maintain high-precision synchronization with the time master, generating a unified system reference time.

[0126] Next, the time synchronization algorithm module runs in the distributed codec device. This module first obtains the extracted synchronization timestamp (denoted as T_source) and the generated system reference time (denoted as T_system). It then calculates the time offset ΔT = T_source - T_system between the two. Based on this time offset, the timestamps of the original output signal are adjusted. Specifically, ΔT can be added or subtracted from the timestamps of the original signal to convert them to timestamps based on the system reference time. For example, if T_source is 100 microseconds later than T_system, then for each timestamp value t in the original signal, the new timestamp t' = t - 100 microseconds. After the offset compensation, the timestamps of the original output signal are unified to the system reference time coordinate system.

[0127] In the technical solution provided in this embodiment, a preset network clock protocol is used to generate a system reference time, thereby ensuring the time consistency of all devices in the distributed splicing system. Through deviation compensation, the timestamps of different signal sources are unified to the system reference time, eliminating the time difference between the signal source and the system, and ensuring seamless splicing and synchronous update of the image on the splicing display terminal.

[0128] The present application provides a signal processing device based on a distributed system, and the signal processing device based on a distributed system includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the signal processing method based on the distributed system in the above-mentioned embodiment one.

[0129] Reference below Figure 9 , which shows a schematic diagram of the structure of a distributed system-based signal processing device suitable for implementing the embodiments of the present application. The distributed system-based signal processing device in the embodiments of the present application may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 9 The signal processing device based on the distributed system shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0130] like Figure 9As shown, the distributed system-based signal processing device may include a processing device 1001 (e.g., a core processor, graphics processor, etc.), which can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 1002 or programs loaded from a storage device 1003 into a random access memory (RAM) 1004. RAM 1004 also stores various programs and data required for the operation of the distributed system-based signal processing device. Processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to I / O interface 1006: input device 1007 including, for example, a touch screen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output device 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage device 1003 including, for example, a magnetic tape, hard disk, etc.; and communication device 1009. Communication device 1009 may allow the distributed system-based signal processing device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a distributed system-based signal processing device with various systems, it should be understood that implementation or presence of all the illustrated systems is not required. More or fewer systems may alternatively be implemented or present.

[0131] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program comprising program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device 1003, or installed from a read-only memory 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are performed.

[0132] The distributed system-based signal processing device provided by this application, using the distributed system-based signal processing method in the above-mentioned embodiment, can solve the technical problems of how to improve image display quality and reduce image display delay. Compared with the prior art, the beneficial effects of the distributed system-based signal processing device provided by this application are the same as the beneficial effects of the distributed system-based signal processing method provided by the above-mentioned embodiment, and the other technical features of the distributed system-based signal processing device are the same as those disclosed in the method of the previous embodiment, and are not further described here.

[0133] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0134] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0135] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, a computer program) stored thereon, wherein the computer-readable program instructions are used to execute the signal processing method based on a distributed system in the above-mentioned embodiment.

[0136] The computer-readable storage medium provided herein may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including, but not limited to, wires, optical cables, radio frequency (RF), etc., or any suitable combination thereof.

[0137] The computer-readable storage medium may be included in a signal processing device based on a distributed system; or may exist independently without being assembled into a signal processing device based on a distributed system.

[0138] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by a signal processing device based on a distributed system, the signal processing device based on the distributed system: receives the original output signal of the ultra-high-resolution signal source through a digital input interface; determines the resolution and target display area of ​​the splicing display terminal, and stretches the original output signal according to the resolution; performs regional cropping on the stretched original output signal according to the target display area to determine the target signal; synchronizes the processed target signal to the sub-distributed codecs in the same group through a cascade architecture; drives the digital output interface of each sub-distributed codec to transmit the target signal to the sub-screen corresponding to the splicing display terminal, so that the display terminal splices the target signal received by each sub-screen for display. The computer program code for performing the operations of the present application can be written in one or more programming languages ​​or a combination thereof. The programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0139] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of code, and the module, program segment or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or can be implemented using a combination of dedicated hardware and computer instructions.

[0140] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0141] The computer-readable storage medium provided in this application stores computer-readable program instructions (i.e., a computer program) for executing the aforementioned distributed system-based signal processing method. This computer-readable storage medium can address the technical issues of improving image display quality and reducing image display latency. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided in this application are similar to those of the distributed system-based signal processing method provided in the aforementioned embodiments, and are not further elaborated here.

[0142] An embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the above-mentioned signal processing method based on a distributed system.

[0143] The computer program product provided in this application can solve the technical problems of how to improve image display quality and reduce image display latency. Compared with the prior art, the beneficial effects of the computer program product provided in the embodiments of this application are the same as the beneficial effects of the signal processing method based on a distributed system provided in the above embodiments, and will not be repeated here.

[0144] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent processing scope of the present application.

Claims

1. A signal processing method based on a distributed system, characterized in that: Applied to a distributed codec device, the distributed codec device is composed of at least two sub-distributed codecs, and the signal processing method based on the distributed system includes the following steps: Receive the original output signal of the ultra-high resolution signal source through the digital input interface; Determining the resolution and target display area of ​​the splicing display terminal, and performing a stretching operation on the original output signal according to the resolution; obtaining an amplified signal after the stretching operation; Calculating the overlapping range between the physical coordinates and the target display area according to the physical coordinates of the sub-screen of the splicing display terminal corresponding to each sub-distributed codec; Performing regional cropping on the amplified signal based on the overlapping range to generate a target signal; Selecting at least one sub-distributed codec connected to a target display area corresponding to the ultra-high-resolution signal source as a master node; duplicating the target signal into multiple parallel signals via the master node through the cascade output port of the master node; Transmitting the multiple parallel signals to the corresponding sub-distributed codecs in a point-to-point direct connection manner through the cascade output port; After each of the sub-distributed codecs receives the multiple parallel signals, determining redundant data in the multiple parallel signals that is not within the processing range of the node, and discarding the redundant data; During the concatenation process, the master node sends a control data packet containing the target signal to the sub-distributed codec; The digital output interface of each sub-distributed codec is driven to transmit the target signal to the sub-screen corresponding to the splicing display terminal, so that the display terminal splices and displays the target signal received by each sub-screen.

2. The method according to claim 1, wherein The step of determining the resolution and target display area of ​​the splicing display terminal and performing a stretching operation on the original output signal according to the resolution includes: Obtaining the resolution of the splicing display terminal and the target resolution of the ultra-high-resolution signal source; Calculating horizontal and vertical stretching ratios according to the resolution and the target resolution; An interpolation operation is performed on the original output signal based on the stretch ratio to generate an amplified signal that matches the resolution of the splicing display terminal.

3. The method according to claim 1, wherein After each of the sub-distributed codecs receives the multiple parallel signals, determining redundant data in the multiple parallel signals that is not within the processing range of the node, and discarding the redundant data, the method further includes: Embedding a mapping relationship between a device identifier and sub-screen coordinates in the target signal through the master node; After the sub-distributed codec receives the target signal, extracting a corresponding signal area according to the device identifier; The phase of the target signal is adjusted according to the mapping relationship of the sub-screen coordinates and the signal area.

4. The method according to claim 1, wherein After the step of receiving the original output signal of the ultra-high resolution signal source through the digital input interface, the method further includes: Upon receiving the original output signal of the ultra-high resolution signal source, extracting a synchronization timestamp of the original output signal; Generate system reference time through preset network clock protocol; The synchronization timestamp is compensated for deviations from the system reference time to generate an original output signal with a unified timestamp.

5. The method according to claim 1, wherein After the step of performing regional cropping on the amplified signal based on the overlapping range to generate a target signal, the method further includes: When the sub-screen corresponding to a single sub-distributed codec needs to display at least two sub-pictures, performing the stretching operation and the region cropping on each of the sub-pictures; Splicing and synthesizing the cropped sub-images according to the layout of the target display area to generate a target image; The processed target image is displayed on the sub-screen.

6. A signal processing device based on a distributed system, characterized in that: The signal processing device based on a distributed system includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the signal processing method based on a distributed system according to any one of claims 1 to 5.

7. A storage medium, characterized in that: The storage medium is a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the signal processing method based on a distributed system according to any one of claims 1 to 5 are implemented.

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