Wiring circuit board, electrical element mounting board, electronic component, and method for manufacturing wiring circuit board

Abstract

The invention provides a printed circuit board, an electrical element mounting board, an electronic component, and a method of manufacturing the printed circuit board, in which a conductor layer including a plurality of terminal portions is formed on a first insulating layer. A second insulating layer is formed on the first insulating layer so as to cover a part of the conductor layer. The plurality of terminal parts are two-dimensionally arranged so as to be repeatedly arranged in a preset arrangement pattern. The second insulating layer includes a unit structure (US) protruding upward corresponding to each terminal portion. Each unit structure includes: an opening portion that overlaps a central portion of a corresponding terminal portion when viewed in a stacking direction of the wired circuit board so as to expose the central portion of the terminal portion; a first annular portion that overlaps an outer portion surrounding the central portion of the corresponding terminal portion when viewed in the lamination direction; and a second annular portion that surrounds the first annular portion when viewed in the stacking direction and is formed so as to be recessed further away from an outer edge of the first annular portion.

Description

Technical Field

[0001] The present invention relates to a wiring circuit board, an electric component mounting board, an electronic component, and a method for manufacturing the wiring circuit board. Background Art

[0002] In electronic devices, a printed circuit board is used to transmit and receive electrical signals between a plurality of electronic components. Electronic components such as semiconductor chips are mounted on the printed circuit board.

[0003] In a wired circuit board, the surface on which electronic components are mounted is formed with an insulating covering layer, such as solder resist. For example, in the semiconductor component package (wired circuit board) described in Japanese Patent Application Laid-Open No. 2001-274034, a covering layer composed of solder resist is formed on one side and the other side of a multilayer structure comprising a core material, multiple wiring layers, and multiple insulating layers. The covering layer has an opening formed therein to expose a portion of the wiring layer as a terminal portion. Summary of the Invention

[0004] When mounting electronic components on a wiring circuit board, the terminal portions of the electronic components are joined to the terminal portions of the wiring circuit board exposed on the mounting surface of the wiring circuit board, for example, using solder. During this mounting, an underfill is also provided to fill the gap formed between the mounting surface of the wiring circuit board and the electronic components. The underfill improves the adhesion between the mounting surface of the wiring circuit board and the electronic components, thereby increasing the reliability of the connection between the wiring circuit board and the electronic components. However, depending on the state of the mounting surface of the wiring circuit board, sufficient adhesion may not be achieved even with the use of an underfill. If sufficient adhesion cannot be achieved between the mounting surface of the wiring circuit board and the electronic components, there is a possibility that the electronic components may peel off the wiring circuit board.

[0005] The object of the present invention is to provide a wiring circuit substrate capable of preventing electrical elements from being peeled off after being mounted, an electrical element mounting substrate including the wiring circuit substrate, an electronic component including the wiring circuit substrate, and a method for manufacturing the wiring circuit substrate.

[0006] According to one aspect of the present invention, a wiring circuit substrate comprises: a first insulating layer having a first surface; a conductor layer having a plurality of terminal portions and formed on the first surface of the first insulating layer; and a second insulating layer formed on the first surface of the first insulating layer in a manner covering a portion of the conductor layer, the plurality of terminal portions being two-dimensionally arranged on the first surface in a manner repeatedly arranged in a predetermined configuration pattern, the second insulating layer including a plurality of mounting reinforcement portions, the plurality of mounting reinforcement portions corresponding to the plurality of terminal portions, respectively, and respectively protruding in a direction toward which the first surface faces, each of the plurality of mounting reinforcement portions including: an opening portion, which overlaps with the central portion of the corresponding terminal portion when viewed in the stacking direction of the first insulating layer and the second insulating layer in a manner exposing the central portion of the corresponding terminal portion; a first annular portion, which overlaps with the outer portion of the corresponding terminal portion surrounding the central portion when viewed in the stacking direction; and a second annular portion, which surrounds the first annular portion when viewed in the stacking direction and is formed in a manner recessed as it moves away from the outer edge of the first annular portion.

[0007] According to another aspect of the present invention, an electrical component mounting substrate comprises: the above-mentioned wiring circuit substrate; and an electrical component having a plurality of electrical contacts, wherein the electrical component is mounted on the wiring circuit substrate by connecting the plurality of electrical contacts to the plurality of terminal portions of the wiring circuit substrate using solder, and a bottom filler is filled between the electrical component and the wiring circuit substrate.

[0008] An electronic component according to still another aspect of the present invention includes the above-mentioned electric component mounting substrate.

[0009] According to another aspect of the present invention, a method for manufacturing a wiring circuit substrate includes: a process of preparing a first insulating layer having a first surface; a process of forming a conductor layer having a plurality of terminal portions on the first surface of the first insulating layer; and a process of forming a second insulating layer on the first surface of the first insulating layer in a manner covering a portion of the conductor layer, wherein the process of forming the conductor layer includes a process of two-dimensionally arranging the plurality of terminal portions on the first surface in a manner repeatedly arranged in a predetermined arrangement pattern, and the process of forming the second insulating layer includes a coating process of coating the plurality of terminal portions on the first surface of the first insulating layer in a manner covering the plurality of terminal portions. A varnish of a thermosetting resin or thermoplastic resin containing a solvent is applied; a pressing process, after the coating process, a pressing member having a flat pressing surface is prepared, and the exposed surface of the varnish is flattened by bringing the pressing surface of the pressing member into contact with the exposed surface of the varnish; a heat treatment process, after the pressing process, the varnish is cured by heating the varnish to volatilize the solvent contained in the varnish; and a process of forming a plurality of openings in the cured varnish after the heat treatment process in such a manner that the central portion of each terminal portion is exposed and the outer portion of each terminal portion surrounding the central portion is covered by the varnish.

[0010] According to another aspect of the present invention, a method for manufacturing a wiring circuit substrate includes: a process of preparing a first insulating layer having a first surface; a process of forming a conductor layer having a plurality of terminal portions on the first surface of the first insulating layer; and a process of forming a second insulating layer on the first surface of the first insulating layer in a manner covering a portion of the conductor layer, wherein the process of forming the conductor layer includes a process of two-dimensionally arranging the plurality of terminal portions on the first surface in a manner of repeatedly arranging them in a predetermined arrangement pattern, and the process of forming the second insulating layer includes a pasting process of pasting a package in a semi-cured state on the first surface of the first insulating layer in a manner covering the plurality of terminal portions. A sheet-like member containing a thermosetting resin or a thermoplastic resin; a pressing step, after the pasting step, preparing a pressing member having a flat pressing surface, and flattening the exposed surface of the sheet-like member by bringing the pressing surface of the pressing member into contact with the exposed surface of the sheet-like member; a heat treatment step, after the pressing step, heating the sheet-like member to volatilize a solvent contained in the sheet-like member and solidify the sheet-like member; and a step, after the heat treatment step, forming a plurality of openings in the solidified sheet-like member in such a manner that the central portion of each terminal portion is exposed and the outer portion of each terminal portion surrounding the central portion is covered by the sheet-like member.

[0011] According to the present invention, it is possible to prevent the electric component from being separated from the wired circuit board after the electric component is mounted on the wired circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a plan view of the wired circuit board according to the first embodiment. Figure 2 is included Figure 1 A top view of a mounting substrate of a wiring circuit substrate. Figure 3 Observed from the direction of the hollow arrow A Figure 2 Side view of the mounting substrate. Figure 4 yes Figure 1 An enlarged top view of a portion of a wiring circuit substrate indicated by a dotted frame. Figure 5 yes Figure 4 Cross-sectional view at line BB. Figure 6 yes Figure 1 A perspective view of a portion of a wiring circuit substrate shown by a dotted frame. Figure 7 This is a schematic side view showing an example of a roll-to-roll device used in the manufacturing process of a wired circuit board. Figure 8 Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 9 Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 10 Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 11 Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 12 Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 13 Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 14 Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 15 Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 16 Is used to illustrate Figure 1A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 17 Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 18 Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 19 Is used to illustrate Figure 1 A cross-sectional view of another example of a method for manufacturing a wired circuit board. Figure 20 Is used to illustrate Figure 1 A cross-sectional view of another example of a method for manufacturing a wired circuit board. Figure 21 Is used to illustrate Figure 1 A cross-sectional view of another example of a method for manufacturing a wired circuit board. Figure 22 It is a cross-sectional view of a wired circuit board according to a second embodiment. Figure 23 Is used to illustrate Figure 22 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 24 Is used to illustrate Figure 22 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 25 Is used to illustrate Figure 22 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 26 Is used to illustrate Figure 22 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 27 Is used to illustrate Figure 22 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 28 Is used to illustrate Figure 22 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 29 Is used to illustrate Figure 22 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 30 Is used to illustrate Figure 22 A cross-sectional view of an example of a method for manufacturing a wired circuit board. Figure 31 It is a cross-sectional view of a wired circuit board according to a third embodiment. DETAILED DESCRIPTION [Description of Preferred Embodiments]

[0013] 1. First Implementation Hereinafter, a printed circuit board, an electric component mounted substrate, an electronic component, and a method for manufacturing the printed circuit board according to a first embodiment will be described with reference to the drawings.

[0014] <1> Overview of the structure of a printed circuit board, an electrical component mounting board, and electronic components Figure 1 It is a plan view of the wired circuit board according to the first embodiment. Figure 2 is included Figure 1 FIG1 is a plan view of a semiconductor chip mounting substrate (hereinafter referred to as a mounting substrate) of a wired circuit substrate 1. ... Figure 3 Observed from the direction of the hollow arrow A Figure 2 3 is a side view of the mounting substrate 3.

[0015] The wired circuit board 1 according to this embodiment is formed by laminating multiple layers (described later) Figure 5 The metal support 10, the first insulating layer 20, the conductor layer 30 and the second insulating layer 40 are formed. Figure 1 As shown, the majority of the upper surface of the wired circuit board 1 is formed by the second insulating layer 40. A plurality (25 in this example) of openings 49 are formed in the second insulating layer 40. Terminal portions 31 are provided at the bottom of each of the plurality of openings 49 so as to be exposed upward from the wired circuit board 1 through the opening 49.

[0016] In a plan view, the plurality of (25 in this example) terminal portions 31 provided on the wired circuit board 1 are arranged two-dimensionally in a manner that a predetermined arrangement pattern is repeatedly arranged. Figure 1 In the example shown in FIG. 1 , the plurality of terminal portions 31 are arranged at equal intervals in a matrix shape when the wired circuit board 1 is viewed from above.

[0017] like Figure 2 As shown, in Figure 1 A plurality of (in this example, four) semiconductor chips 2 are mounted on the upper surface of the wiring circuit substrate 1. The mounting substrate 3 is manufactured by mounting a predetermined number of semiconductor chips 2 on the wiring circuit substrate 1. Figure 2 and Figure 3 As shown by the dot-dash line, the manufactured mounting substrate 3 is assembled on an electronic component 4 such as a portable terminal.

[0018] Each semiconductor chip 2 has a mounting surface that faces the wired circuit board 1 when assembled on the mounting substrate 3. A plurality of terminal portions corresponding to any of the plurality of terminal portions 31 of the wired circuit board 1 are formed on this mounting surface. In the following description, each terminal portion of the semiconductor chip 2 is referred to as a chip terminal portion.

[0019] When mounting multiple semiconductor chips 2 on a wired circuit board 1, each semiconductor chip 2 is positioned so that its multiple chip terminals face corresponding terminals 31 of the wired circuit board 1. Furthermore, each chip terminal of the semiconductor chip 2 is connected to its corresponding terminal 31 of the wired circuit board 1 using solder 5. At this point, a gap is created between the upper surface of the wired circuit board 1 and each semiconductor chip 2. This gap is filled with underfill 6.

[0020] In the wired circuit board 1 according to this embodiment, the shape of the upper surface of the mounting substrate 3 manufactured as described above is improved to improve the adhesion between the upper surface of the wired circuit board 1 and the semiconductor chip 2. The structure of the wired circuit board 1 will be described in detail below.

[0021] <2> Structure of the Wired Circuit Board 1 Figure 1 The wiring circuit board 1 has a rectangular shape when viewed from above. Figure 1 The direction parallel to one of the four sides of the wiring circuit board 1 extending in the horizontal direction (left and right direction on the paper) is called the first direction D1. Figure 1 The direction parallel to the other side extending in the longitudinal direction (the vertical direction on the paper) of the wiring circuit board 1 is called the second direction D2. The first direction D1 and the second direction D2 are orthogonal to each other in a plane. Moreover, the direction orthogonal to the first direction D1 and the second direction D2 (the direction intersecting the paper) is called the third direction D3. In addition, the third direction D3 is described later. Figure 5 The stacking direction of the metal support 10, the first insulating layer 20, the conductive layer 30, and the second insulating layer 40 is shown in FIG. In given figures described later, the first direction D1, the second direction D2, and the third direction D3 are indicated by arrows as appropriate.

[0022] Figure 4 yes Figure 1 FIG. 1 is an enlarged plan view of a portion of the wired circuit board 1 indicated by a dotted-line frame. Figure 5 yes Figure 4 Cross-sectional view at line BB. Figure 6 yes Figure 1 1 is a perspective view of a portion of the wired circuit board 1 indicated by a dotted frame.

[0023] exist Figure 4 In, as Figure 1 The portion within the dotted line frame is a top view of a portion of the wiring circuit board 1 including nine terminal portions 31. Figure 4 In the top view, the nine terminal portions 31 are arranged at equal intervals in a matrix of three rows and three columns.

[0024] First, based on Figure 5 The cross-sectional view of FIG1 illustrates the structure of the wiring circuit substrate 1. Figure 5 The upper part indicates Figure 4 In addition, a part of the cross-sectional view of the upper half is enlarged and shown in the lead-out frame of the lower half. Figure 5 As shown in the upper and lower halves of FIG, the wired circuit board 1 includes a metal support 10, a first insulating layer 20, a conductor layer 30, and a second insulating layer 40.

[0025] The metal support 10 is a plate-shaped member made of metal, for example, stainless steel. Alternatively, the metal support 10 may be made of copper, a copper alloy, aluminum, titanium, or an alloy containing iron and nickel. The metal support 10 has higher rigidity than the first insulating layer 20 and the second insulating layer 40. Furthermore, the metal support 10 has an upper surface 11 and a lower surface 12 that face opposite directions in the third direction D3. The thickness of the metal support 10 is not less than 10 μm and not more than 30 μm.

[0026] The first insulating layer 20 includes a photosensitive resin and is laminated on the upper surface 11 of the metal support 10. As the photosensitive resin constituting the first insulating layer 20, for example, photosensitive polyimide is used. Instead of photosensitive polyimide, the first insulating layer 20 can also be formed by other photosensitive resins (other photosensitive resins such as acrylic resin, epoxy resin, polyamide resin, polybenzoxazole resin or polyvinyl chloride resin). The first insulating layer 20 covers the upper surface 11 of the metal support 10. In addition, the first insulating layer 20 has an upper surface 21 and a lower surface 22 facing in opposite directions to each other in the third direction D3. The thickness of the first insulating layer 20 is greater than 1 μm and less than 10 μm. In addition, the first insulating layer 20 can also be composed of a non-photosensitive resin. Therefore, the first insulating layer 20 can also be composed of a thermoplastic resin or a thermosetting resin like the second insulating layer 40 described later.

[0027] In addition to the above examples, the first insulating layer 20 may also have a structure in which multiple different resins are laminated. For example, the first insulating layer 20 may have a structure in which a thermoplastic resin layer and a thermosetting resin layer are laminated. More specifically, the first insulating layer 20 may have a structure in which two or more layers are laminated, each of which is made of two or more materials selected from thermoplastic polyimide, thermosetting polyimide, thermoplastic epoxy resin, thermosetting epoxy resin, thermoplastic acrylic, and thermosetting acrylic.

[0028] The conductor layer 30 includes a plurality of terminal portions 31 and a plurality of wiring portions 32 ( Figure 4), and are formed on the upper surface 21 of the first insulating layer 20 in a predetermined pattern. Specifically, the plurality of terminal portions 31 are arranged in a matrix at equal intervals on the upper surface 21 of the first insulating layer 20. On the other hand, the plurality of wiring portions 32 correspond to the plurality of terminal portions 31, respectively. Figure 4 As indicated by the thick dashed line, each wiring portion 32 is formed to extend from the corresponding terminal portion 31 .

[0029] The conductor layer 30 is formed by growing a plated layer on the seed layer using an electroplating method. A specific example of this formation method will be described later. The seed layer forming the conductor layer 30 may, for example, include a chromium thin film and a copper thin film. Alternatively, the seed layer may include a titanium thin film and a copper thin film. Alternatively, the seed layer may include a copper thin film. On the other hand, the plated layer may be formed from a metal or alloy including one or more of copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, and ruthenium. In this embodiment, the plated layer is copper.

[0030] The thickness of the conductor layer 30 in the third direction D3 (the stacking direction of the wiring circuit substrate 1) is not less than 1 μm and not more than 20 μm. In addition, in the wiring circuit substrate 1 involved in this embodiment, the plurality of terminal portions 31 in the conductor layer 30 each have a circular shape when viewed from above. The outer diameter (diameter) of each terminal portion 31 when viewed from above is not less than 5 μm and not more than 400 μm. Furthermore, in the wiring circuit substrate 1 involved in this embodiment, the distance d1 ( Figure 4 ) is 5 μm or more and 500 μm or less. In addition, the distance d2 ( Figure 4 ) is also 5 μm or more and 500 μm or less. In addition, the distances d1 and d2 may be the same length or different lengths from each other.

[0031] The second insulating layer 40 includes a thermoplastic resin or a thermosetting resin and is formed on the upper surface 21 of the first insulating layer 20 in a manner covering a portion of the plurality of terminal portions 31 and the plurality of wiring portions 32. As the thermoplastic resin or thermosetting resin constituting the second insulating layer 40, for example, thermoplastic polyimide or thermosetting polyimide is used. Instead of thermoplastic polyimide or thermosetting polyimide, the second insulating layer 40 may be formed of other thermoplastic resins (other thermoplastic resins such as acrylic resin, epoxy resin, polyamide resin, polybenzoxazole resin, or polyvinyl chloride resin), or may be formed of other thermosetting resins (other thermosetting resins such as acrylic resin, epoxy resin, polyamide resin, or polyvinyl chloride resin). The second insulating layer 40 has an upper surface 40a and a lower surface 40b ( Figure 5 ).

[0032] In addition to the above examples, the second insulating layer 40 may also have a structure in which multiple different resins are laminated. For example, the second insulating layer 40 may have a structure in which a thermoplastic resin layer and a thermosetting resin layer are laminated. More specifically, the second insulating layer 40 may have a structure in which two or more layers are laminated, each of which is made of two or more materials selected from thermoplastic polyimide, thermosetting polyimide, thermoplastic epoxy resin, thermosetting epoxy resin, thermoplastic acrylic, and thermosetting acrylic.

[0033] like Figure 4 and Figure 5 As shown, the second insulating layer 40 has a plurality of openings 49 corresponding to the plurality of terminal portions 31. Each of the plurality of openings 49 has a circular shape when viewed from above and is formed so as to overlap with the corresponding terminal portion 31. When viewed from above, the inner diameter of each opening 49 is smaller than the outer diameter (diameter) of the corresponding terminal portion 31 and is 2 μm or more and 300 μm or less.

[0034] The plurality of openings 49 overlap the plurality of terminal portions 31, respectively, so that the center portion of each terminal portion 31 is exposed to the space above the wired circuit board 1 through the corresponding opening 49. On the other hand, the outer portion of each terminal portion 31 surrounding the center portion of the terminal portion 31 in a plan view is covered by the second insulating layer 40.

[0035] In the following description, the portion of the second insulating layer 40 that covers the outer portion of each terminal portion 31 when viewed from above, that is, the portion that covers the outer portion of each terminal portion 31 when viewed along the third direction D3, is referred to as the first annular portion 41. Furthermore, the portion of the second insulating layer 40 that surrounds each of the plurality of first annular portions 41 when viewed from above, that is, the portion that surrounds each of the plurality of first annular portions 41 when viewed from the third direction D3, is referred to as the second annular portion 42.

[0036] exist Figure 4 In order to clearly distinguish the first annular portion 41 from the second annular portion 42 in the second insulating layer 40 , the first annular portion 41 is marked with a dark dot pattern, and the second annular portion 42 is marked with a light dot pattern.

[0037] according to Figure 4 As can be seen, the wired circuit board 1 has a plurality of unit structures US including a first annular portion 41 and a second annular portion 42 corresponding to one terminal portion 31 in plan view. Furthermore, these unit structures US are continuously arranged in the first direction D1 and the second direction D2, similarly to the plurality of terminal portions 31.

[0038] exist Figure 5The lower half of the lead frame shows an enlarged representation of a unit structure US including a terminal portion 31 and the corresponding first annular portion 41 and second annular portion 42. Here, assuming that the upper surface 21 of the first insulating layer 20 is a reference plane orthogonal to the third direction D3, the distance between the reference plane and the upper surface 40a of the second insulating layer 40 in the third direction D3 varies between the multiple portions. Specifically, the distance between the reference plane and the upper surface 40a in the second annular portion 42 is smaller than the distance between the reference plane and the upper surface 40a in the first annular portion 41. Furthermore, in the unit structure US, the second annular portion 42 is formed so as to become recessed as it moves away from the outer edge of the first annular portion 41.

[0039] Thus, in the unit structure US corresponding to each terminal portion 31 , the second insulating layer 40 protrudes upward from a position outside the terminal portion 31 to the center 31 c of the terminal portion 31 on the upper surface 21 of the first insulating layer 20 .

[0040] exist Figure 6 In the perspective view of FIG, in order to easily understand the shape of the upper surface 40a of the second insulating layer 40, the shortest path on the upper surface 40a connecting the two adjacent first annular portions 41 is indicated by a dotted line. Figure 6 As shown, on the first insulating layer 20 , the plurality of unit structures US of the second insulating layer 40 protrude upward, so that a plurality of concave and convex portions corresponding to the plurality of terminal portions 31 are formed in a matrix on the upper surface of the wired circuit board 1 .

[0041] According to the above structure, Figure 1 When multiple semiconductor chips 2 are mounted on a wiring circuit substrate 1, a gap, consisting of a mixture of narrow and wide spaces, is formed between the wiring circuit substrate 1 and each semiconductor chip 2. Furthermore, this gap is filled with an underfill 6. In this case, if the underfill 6 contacts the concave and convex portions of the multiple unit structures US within the aforementioned gap and solidifies, the adhesion between the wiring circuit substrate 1 and each semiconductor chip 2 after mounting is strengthened by the anchoring effect. As a result, in the manufactured mounting substrate 3, each semiconductor chip 2 can be prevented from peeling off from the wiring circuit substrate 1.

[0042] <3> Preferred shape of the second insulating layer 40 (a) In the above-described wired circuit board 1, the total area of ​​the second insulating layer 40 in a plan view (when viewed along the third direction D3) is defined as a first area value S1. Furthermore, the total area of ​​the openings 49 (opening area) included in the plurality of unit structures US is defined as a second area value S2. In this case, the second insulating layer 40 is preferably formed so that the value (S2 / S1) obtained by dividing the second area value S2 by the first area value S1 is not less than 0.01 and not more than 0.5.

[0043] By setting the value (S2 / S1) to 0.01 or greater, semiconductor chip 2 can be mounted on wired circuit board 1 using solder more easily than when the value (S2 / S1) is less than 0.01. Furthermore, the reliability of the electrical connection between the mounted semiconductor chip 2 and wired circuit board 1 is improved. On the other hand, by setting the value (S2 / S1) to 0.5 or less, a larger contact area of ​​underfill 6 at second insulating layer 40 can be ensured than when the value (S2 / S1) is greater than 0.5. Consequently, the adhesion between wired circuit board 1 and each semiconductor chip 2 after mounting can be improved.

[0044] (b) If Figure 5 As shown in the lead-out box of , the maximum value of the distance between the reference plane in the third direction D3 (the upper surface 21 of the first insulating layer 20) and the upper surface 40a of the second insulating layer 40 is set to the first thickness value T1. In addition, the minimum value of the distance between the reference plane in the third direction D3 and the upper surface 40a of the second insulating layer 40 is set to the second thickness value T2. In this case, the second insulating layer 40 is preferably formed so that the value (T2 / T1) obtained by dividing the second thickness value T2 by the first thickness value T1 is greater than 0.3 and less than 1. In addition, in the second insulating layer 40, the value (T2 / T1) is more preferably greater than 0.5 and less than 1, further preferably greater than 0.75 and less than 1, and even more preferably greater than 0.8 and less than 1.

[0045] When the value (T2 / T1) is greater than 0.3, no significant unevenness is formed on the upper surface 40a of the second insulating layer 40. This prevents poor filling of the underfill 6 due to the underfill 6 being unable to follow the uneven shape. Furthermore, since no significant unevenness is formed on the upper surface 40a of the second insulating layer 40, the overall thickness of the second insulating layer 40 can be reduced. This allows for a thinner wired circuit board 1.

[0046] (c) The difference (T1-T2) between the first thickness value T1 and the second thickness value T2 can be regarded as the depth of the recess formed in the upper surface 40a of the second insulating layer 40. This difference (T1-T2) is greater than 0 μm and less than 10 μm, preferably greater than 0 μm and less than 5 μm.

[0047] (d) Furthermore, when the first thickness value T1 is defined as described above, the first thickness value T1 is preferably less than 25 μm. Furthermore, when the second thickness value T2 is defined as described above, the second thickness value T2 is preferably less than 20 μm. In these cases, the thickness of the wired circuit board 1 can be reduced.

[0048] (e) In the aforementioned wired circuit board 1, the distance between the upper surface 21 of the first insulating layer 20 and the upper end surface of each first annular portion 41 in the third direction D3 is referred to as the reinforcement portion height. The reinforcement portion heights of the multiple first annular portions 41 formed on a single wired circuit board 1 may vary. The maximum of the multiple reinforcement portion heights corresponding to the multiple first annular portions 41 is referred to as the reinforcement portion maximum height Hmax, and the minimum of the multiple reinforcement portion heights is referred to as the reinforcement portion minimum height Hmin.

[0049] In this case, the second insulating layer 40 is preferably formed so that the value (Hmin / Hmax) of the minimum height Hmin of the reinforcement portion divided by the maximum height Hmax of the reinforcement portion is greater than 0.7. Thus, when the value (Hmin / Hmax) is greater than 0.7, the amount of underfill 6 filled between multiple portions of the wiring circuit board 1 and the semiconductor chip 2 when the semiconductor chip 2 is mounted on the wiring circuit board 1 is more uniform, compared to when the value (Hmin / Hmax) is less than 0.7. Therefore, a decrease in adhesion caused by a localized lack of underfill 6 between the wiring circuit board 1 and the semiconductor chip 2 after mounting can be suppressed.

[0050] <4> Example of a method for manufacturing the wired circuit board 1 In the present embodiment, the wired circuit board 1 is manufactured by, for example, a roll-to-roll method. Figure 7 This is a schematic side view showing an example of a roll-to-roll device used in the manufacturing process of the wired circuit board 1 .

[0051] like Figure 7 As shown, the roll-to-roll device 500 includes a roll-out unit 501 , a winding unit 502 , and a plurality of processing units ( 510 , 520 , etc. ) First, a roll (unwinding roll) R1 with a long metal support 10 wound thereon is prepared and placed in the roll-to-roll device 500 .

[0052] The metal support 10 is unwound from the prepared unwound roll R1. Figure 7 As indicated by the dotted arrow, the tube is wound around another roller (winding roller) R2 provided in the winding section 502 .

[0053] In the roll-to-roll device 500, multiple processing units (510, 520, ...) are arranged between two rollers (R1, R2) along the direction of movement of the metal support 10. Each of the multiple processing units (510, 520, ...) forms the aforementioned first insulating layer 20, conductive layer 30, and second insulating layer 40 on the elongated metal support 10 as it moves between the two rollers (R1, R2). Consequently, multiple wired circuit boards 1 are formed on the metal support 10 wound around the winding roller R2. An example method for manufacturing the wired circuit board 1 will be described in detail below.

[0054] Figures 8 to 18 Is used to illustrate Figure 1 A cross-sectional view showing an example of a method for manufacturing the wired circuit board 1. Figures 8 to 18 The cross-sectional view shown is Figure 1 The wiring circuit substrate 1 Figure 5 The upper part of the figure corresponds to the cross-sectional view of the part shown.

[0055] As described above, the unwinding roll R1 ( Figure 7 ), and the metal support 10 is released from the release roller R1. Figure 8 A cross-sectional view of the metal support 10 fed out from the feed roll R1 is shown in FIG. The metal support 10 has an upper surface 11 and a lower surface 12 facing in opposite directions to each other.

[0056] Then, if Figure 9 As shown, a first insulating layer 20 is formed on the upper surface 11 of the metal support 10. Specifically, the first insulating layer 20 is formed as follows. First, a varnish of a photosensitive resin is applied to the upper surface 11 of the metal support 10 in such a manner as to cover the entire upper surface 11 of the metal support 10. In this example, a varnish of a photosensitive polyimide is used as the varnish of the photosensitive resin. Then, the applied varnish of the photosensitive polyimide is sequentially subjected to a drying process, an exposure process, a development process, and a curing process. Thus, the first insulating layer 20 is formed on the upper surface 11 of the metal support 10. The first insulating layer 20 has an upper surface 21 and a lower surface 22 facing in opposite directions to each other.

[0057] Alternatively, instead of applying a photosensitive polyimide varnish to the upper surface 11 of the metal support 10, the first insulating layer 20 may be formed by attaching a sheet-like member (film) containing photosensitive polyimide. Alternatively, instead of applying a photosensitive polyimide varnish to the upper surface 11 of the metal support 10, the first insulating layer 20 may be formed by attaching a sheet-like member (film) containing photosensitive epoxy resin. Alternatively, the first insulating layer 20 may be formed by attaching a laminate of a sheet-like member (film) containing photosensitive polyimide and a sheet-like member (film) containing photosensitive epoxy resin to the upper surface 11 of the metal support 10.

[0058] Then, if Figure 10 As shown by the thick solid line, a seed layer 39 is formed on the exposed upper surface 21 of the first insulating layer 20. Figure 11 As shown, a plating resist 51 having openings in a predetermined pattern is formed on the upper surface 11 of the first insulating layer 20. Specifically, the plating resist 51 is formed, for example, as follows.

[0059] First, a varnish of a positive photosensitive resin is applied to the upper surface 11 of the first insulating layer 20. After the varnish has spread over the entire upper surface 11 of the first insulating layer 20, the varnish is dried. As a result, the varnish is cured to form a layer of photosensitive resin. Next, a portion of the formed photosensitive resin layer is irradiated with exposure light corresponding to the photosensitive resin in a given pattern. The given pattern is equivalent to the pattern of the conductor layer 30 formed in the subsequent process. Then, the layer of photosensitive resin is developed. The photosensitive resin in this example is a positive photosensitive resin. In this case, the exposed portion dissolves in the developer. Thus, a resist layer 51 having an opening of a given pattern is formed. At this time, a portion of the seed layer 39 is exposed upward through the opening of the resist layer 51.

[0060] Next, electroplating is performed using the exposed portion of the seed layer 39. Figure 12 As shown, a conductor (copper in this example) is filled in the opening of the plating resist 51 to form the plating layer 38 .

[0061] Then, if Figure 13 As shown, the plating resist 51 is removed. The plating resist 51 is removed by, for example, exposing and developing the plating resist 51 remaining on the upper surface 21 of the first insulating layer 20. Figure 14 As shown in FIG. 1 , the portion of the seed layer 39 where the plating layer 38 is not formed is removed by etching. Thus, the conductor layer 30 is formed by a stack of the seed layer 39 and the plating layer 38. Figures 13 to 18In FIG, three terminal portions 31 in the conductor layer 30 are shown. At this time, on the upper surface 21 of the first insulating layer 20, a portion of the conductor layer 30 is arranged two-dimensionally as a plurality of terminal portions 31 in a repeated arrangement in a predetermined configuration pattern. Figures 15 to 18 In the figure, the seed layer 39 is omitted.

[0062] Next, a varnish 60 of a thermoplastic resin or a thermosetting resin is applied to the upper surface 21 of the first insulating layer 20 so as to cover the entire exposed portion of the conductive layer 30. In this example, a varnish of a thermoplastic polyimide or a thermosetting polyimide is used as the varnish 60 of the thermoplastic resin or the thermosetting resin. Figure 15 As shown in FIG. 1 , a layer of liquid varnish 60 is formed on the first insulating layer 20. Figures 15 to 18 In FIG. 5 , the varnish 60 is marked with a dot pattern.

[0063] Varnish 60 contains a volatile solvent. At the time of application, varnish 60 has high fluidity. Consequently, the upper surface of the varnish 60 layer is flat. Furthermore, the thickness of the varnish 60 layer is smaller in the portion overlapping with the conductor layer 30 (hereinafter referred to as the conductor overlapping portion) and larger in the portion not overlapping with the conductor layer 30 (hereinafter referred to as the non-conductor overlapping portion).

[0064] Next, a drying process is performed to volatilize the solvent in the varnish 60 to a degree that does not lose fluidity. This drying process is performed by heating the laminate including the varnish 60. At this time, the upper surface 60a of the varnish 60 layer deforms according to the thickness of each part of the varnish 60 due to the volatilization of the solvent contained in the varnish 60.

[0065] Specifically, the amount of solvent volatilized from the thinner conductor overlap portion is less than the amount of solvent volatilized from the thicker non-conductor overlap portion. Therefore, the conductor overlap portion shrinks at a smaller ratio than the non-conductor overlap portion. In other words, the non-conductor overlap portion shrinks more than the conductor overlap portion. Figure 16 As shown, the upper surface 60a of the dried varnish 60 layer protrudes upward in the conductor overlapping portion (the portion overlapping the terminal portion 31) and is recessed in the non-conductor overlapping portion (the portion not overlapping the terminal portion 31).

[0066] Next, a pressing member (not shown) having a flat pressing surface is prepared. In addition, the pressing surface of the pressing member is brought into contact with the upper surface 60a of the varnish 60 layer, thereby pressing the upper surface 60a of the varnish 60. At the time of this pressing, the varnish 60 has fluidity. Thus, as shown in FIG. Figure 17 As shown, the upper surface 60a of the layer of varnish 60 is flattened. In this case, the thickness of the layer of varnish 60 becomes smaller in the conductor overlapping portion and becomes larger in the non-conductor overlapping portion.

[0067] After that, the varnish 60 is cured. This curing process is a heat treatment that volatilizes the solvent contained in the varnish 60 and cures the varnish 60. During this heat treatment, as in the above-mentioned drying process, the amount of solvent volatilized from the conductor overlapping portion is different from the amount of solvent volatilized from the thicker non-conductor overlapping portion. Figure 18 As shown, the upper surface 60 a of the cured varnish 60 layer protrudes upward in the conductor overlapping portion (the portion overlapping the terminal portion 31 ) and is recessed in the non-conductor overlapping portion (the portion not overlapping the terminal portion 31 ).

[0068] Furthermore, the size of the concavities and convexities ( Figure 18 ) is larger than the size of the concavo-convexity formed on the upper surface 60a of the layer of the varnish 60 after the above-mentioned drying process ( Figure 16 This difference in the size of the concave and convex is considered to be because the total amount of solvent volatilized from the varnish 60 during the curing process is smaller than the total amount of solvent volatilized from the varnish 60 during the drying process.

[0069] Finally, a plurality of openings are formed in the varnish 60 layer so that the central portion of each of the plurality of terminal portions 31 is exposed upward and the outer portion of the terminal portion 31 is covered with the cured varnish 60. The formation of the plurality of openings can be performed, for example, by laser processing, drilling processing, or exposure and development based on photolithography. Figure 5 As shown, the second insulating layer 40 including a plurality of openings 49 is formed on the first insulating layer 20, thereby completing the wired circuit board 1. The completed wired circuit board 1 is wound around a winding roll R2.

[0070] Alternatively, instead of applying the varnish 60 to the upper surface 21 of the first insulating layer 20, the second insulating layer 40 may be formed by attaching a sheet-like member (film) made of photosensitive polyimide. Alternatively, instead of applying the varnish 60 to the upper surface 21 of the first insulating layer 20, the second insulating layer 40 may be formed by attaching a sheet-like member (film) made of photosensitive epoxy resin. Alternatively, the second insulating layer 40 may be formed by attaching a laminate of a sheet-like member (film) made of photosensitive polyimide and a sheet-like member (film) made of photosensitive epoxy resin to the upper surface 21 of the first insulating layer 20.

[0071] The wired circuit board 1 wound by the winding roll R2 is cut into pieces according to predetermined design dimensions, for example, based on the dimensions of the mounting substrate 3 to be produced and the electronic components 4 to be assembled on the mounting substrate 3. This allows for the production of multiple wired circuit boards 1 having sizes appropriate for the intended use.

[0072] In this case, as described above, the second insulating layer 40 of each wired circuit board 1 is preferably formed as Figure 5 The second thickness value T2 is divided by Figure 5 The value (T2 / T1) obtained by dividing the first thickness value T1 is greater than 0.3 and less than 1. In addition, the second insulating layer 40 is preferably formed so that the value (Hmin / Hmax) obtained by dividing the minimum height Hmin of the reinforcement portion by the maximum height Hmax of the reinforcement portion is greater than 0.7.

[0073] <5> Another Example of the Method for Manufacturing the Wired Circuit Board 1 Regarding another example of the method for manufacturing the wired circuit board 1 , differences from the example of the method for manufacturing the wired circuit board 1 described above will be described. Figures 19 to 21 Is used to illustrate Figure 1 sectional view of another example of the method for manufacturing the wired circuit board 1. Figures 19 to 21 The cross-sectional view shown is Figure 1 The wiring circuit substrate 1 Figure 5 The upper part of the figure corresponds to the cross-sectional view of the part shown.

[0074] In the manufacturing method of the wiring circuit board 1 of this embodiment, first, according to the above Figures 8 to 14 In the method shown, the first insulating layer 20 is formed on the metal support 10, and the conductive layer 30 is formed on the first insulating layer 20. In addition, unnecessary portions of the seed layer 39 are removed.

[0075] Afterwards, cover Figure 14 A sheet-like member 60s made of a thermoplastic resin or a thermosetting resin is attached to the upper surface 21 of the first insulating layer 20 so as to completely cover the exposed conductor layer 30 in the laminated body. Here, the sheet-like member 60s is a sheet-like member in which the varnish 60 of the thermoplastic resin or the thermosetting resin has been so-called B-staged. More specifically, the sheet-like member 60s is a member in which the varnish 60 of the thermoplastic resin or the thermosetting resin has been formed into a sheet in a semi-cured state that is non-sticky and appears to be cured. Thus, as Figure 19 As shown in FIG. 1 , a layer of sheet-like member 60s is formed on the first insulating layer 20. Figures 19 to 21 In order to clearly distinguish the method used in one example of the method for manufacturing the wired circuit board 1, Figures 15 to 18 The varnish 60 and the sheet-like member 60s are shown, and the sheet-like member 60s is hatched.

[0076] When the sheet member 60s is attached, the sheet member 60s deforms to follow the outer shapes of the upper surface 21 of the first insulating layer 20 and the conductive layer 30. As a result, the upper surface 60a of the sheet member 60s attached to the first insulating layer 20 forms projections and depressions corresponding to the pattern of the conductive layer 30 formed on the first insulating layer 20.

[0077] Next, a pressing member (not shown) having a flat pressing surface is prepared. In addition, the pressing surface of the pressing member is brought into contact with the upper surface 60a of the sheet member 60s, so that the upper surface 60a of the sheet member 60s is pressed. At this pressing time point, the sheet member 60s in a semi-cured state is deformed. As a result, Figure 20 As shown, the upper surface 60a of the sheet-like member 60s is flattened.

[0078] After that, the sheet member 60s is cured. This curing treatment is a heat treatment that volatilizes the solvent contained in the semi-cured sheet member 60s and cures the sheet member 60s. During this heat treatment, the sheet member 60s is cured as in the example of the varnish 60 described above ( Figure 18 Similarly, the amount of solvent volatilized in the plurality of portions of the sheet member 60s is different. Figure 21 As shown, the upper surface 60 a of the layer of the sheet-like member 60 s protrudes upward in a portion overlapping with the terminal portion 31 , and is recessed in a portion not overlapping with the terminal portion 31 .

[0079] Finally, multiple openings are formed in the layer of sheet member 60s, so that the central portion of each of the multiple terminals 31 is exposed upward and the outer portions of the terminal portions 31 are covered by the cured sheet member 60s. This completes the wired circuit board 1. The completed wired circuit board 1 is wound onto winding roll R2.

[0080] In another example of the method for manufacturing the wired circuit board 1, as described above, the sheet member 60s is used to form the second insulating layer 40. Therefore, the method including the step of applying the varnish 60 on the first insulating layer 20 and the step of drying the varnish 60 to evaporate the solvent to a degree that does not lose fluidity is not achieved. Figures 15 to 18 Compared with the manufacturing method, the number of steps is reduced.

[0081] <6> Effects of the First Embodiment (a) As described above, in the wired circuit board 1 , the second insulating layer 40 forming the mounting surface of the plurality of semiconductor chips 2 has a plurality of unit structures US protruding upward corresponding to the plurality of terminal portions 31 .

[0082] The plurality of unit structures US, together with the plurality of terminal portions 31, are arranged at equal intervals in a matrix shape when the wiring circuit substrate 1 is viewed from above. Thus, when the plurality of semiconductor chips 2 are mounted on the wiring circuit substrate 1, a gap is formed between the wiring circuit substrate 1 and the semiconductor chips 2, in which a mixture of narrow spaces and wide spaces exists. The gap is filled with a bottom filler 6, which contacts the surface of the unit structure US and solidifies. In this case, the anchoring effect is utilized to strengthen the adhesion between the wiring circuit substrate 1 and the plurality of semiconductor chips 2 after mounting. As a result, in the mounting substrate 3, the plurality of semiconductor chips 2 can be prevented from peeling off from the wiring circuit substrate 1.

[0083] (b) The thickness of the conductor layer 30 is 1 μm or more and 20 μm or less. This size range is relatively narrow as the thickness range of the conductor layer 30 used in the wired circuit board 1. Therefore, the wired circuit board 1 can be made thinner and flatter.

[0084] (c) The wired circuit board 1 described above includes a metal support 10. The metal support 10 supports the first insulating layer 20, the conductive layer 30, and the second insulating layer 40. The metal support 10 has relatively high rigidity. Therefore, deformation such as warping in the wired circuit board 1 can be suppressed, and the handleability of the wired circuit board 1 can be improved.

[0085] (d) As described above, photosensitive polyimide is used as the photosensitive resin constituting the first insulating layer 20 , and thermoplastic polyimide or thermosetting polyimide is used as the thermoplastic resin or thermosetting resin constituting the second insulating layer 40 .

[0086] In this case, due to the relatively low dielectric constant of polyimide, a wired circuit board 1 suitable for high-frequency signal transmission can be achieved. Furthermore, polyimide has high dimensional stability and high heat resistance. Furthermore, the thermal expansion coefficients of polyimide and the conductor layer 30 used in the wired circuit board 1 are easily matched. Therefore, as described above, when polyimide is used as the material for the first insulating layer 20 and the second insulating layer 40, deformation such as warping of the wired circuit board 1 can be suppressed. As a result, the reliability of the wired circuit board 1 is improved.

[0087] As mentioned above, epoxy resin can also be used as the material for first insulating layer 20. Epoxy resin, like polyimide, has high dimensional stability and high heat resistance. Furthermore, it is relatively easy to match the thermal expansion coefficient between epoxy resin and the conductor layer 30 used in the wired circuit board 1. Therefore, when epoxy resin is used as the material for first insulating layer 20 and second insulating layer 40, deformation such as warping of the wired circuit board 1 can be suppressed.

[0088] 2. Second Implementation Hereinafter, the wired circuit board and the method for manufacturing the wired circuit board according to the second embodiment will be described with respect to differences from the wired circuit board and the method for manufacturing the wired circuit board according to the first embodiment.

[0089] The wired circuit board 1 according to the second embodiment basically has the same appearance as the wired circuit board 1 according to the first embodiment. However, the structure of the plurality of terminal portions 31 of the wired circuit board 1 according to the second embodiment differs from that of the first embodiment.

[0090] <1> Structure of the Wired Circuit Board 1 Figure 22 It is a cross-sectional view of a wired circuit board 1 according to the second embodiment. Figure 22 The cross-sectional view is equivalent to Figure 5 This is a cross-sectional view of a wired circuit board 1 according to the first embodiment. Figure 22 In, also with Figure 5 Similarly, in the upper part of the example Figure 4 In addition, a portion of the cross-sectional view of the upper half is enlarged and shown in the lead-out frame of the lower half.

[0091] like Figure 22 As shown, in the wiring circuit board 1 according to this embodiment, the plurality of terminal portions 31 in the conductor layer 30 are respectively composed of two layers, namely, a lower conductor layer 31a and an upper conductor layer 31b stacked in the third direction D3. Specifically, the terminal portion 31 in this example is composed of a lower conductor layer 31a formed directly on the upper surface 21 of the first insulating layer 20 and an upper conductor layer 31b formed on the lower conductor layer 31a. On the other hand, in this embodiment, the plurality of wiring portions 32 (see FIG. 1 ) in the conductor layer 30 are respectively composed of two layers, namely, a lower conductor layer 31a and an upper conductor layer 31b stacked in the third direction D3. Figure 4 The plurality of wiring portions 32 indicated by the thick dashed lines are formed of a single layer of the lower conductor layer 31a.

[0092] With this structure, the positions of the exposed portions of the plurality of terminal portions 31 (the height positions of the terminal portions 31) can be made different from the positions of the wiring portions 32 formed in the third direction D3 (the height positions of the wiring portions 32). This increases the degree of freedom in the layout of the plurality of wiring portions 32 and the plurality of terminal portions 31 in the wired circuit board 1.

[0093] Here, the thickness of the lower conductive layer 31a in the third direction D3 (the stacking direction of the wired circuit board 1) is between 1 μm and 10 μm. Therefore, the thickness of the plurality of wiring portions 32 is between 1 μm and 10 μm. Furthermore, the thickness of the upper conductive layer 31b in the third direction D3 (the stacking direction of the wired circuit board 1) is between 1 μm and 20 μm. These dimensions are relatively narrow for the thickness of the conductive layer 30 used in the wired circuit board 1. Consequently, the wired circuit board 1 can be made thinner and flatter.

[0094] Furthermore, the thickness of the plurality of terminal portions 31 in the third direction D3 (the stacking direction of the wired circuit board 1) is less than the second thickness value T2 of the second insulating layer 40 in the third direction D3. In this case, it is possible to prevent undesirable portions of the plurality of terminal portions 31 other than the central portion from being exposed in the space above the second insulating layer 40.

[0095] As described above, in this embodiment, each terminal portion 31 is formed of a lower conductive layer 31a and an upper conductive layer 31b. The lower conductive layer 31a constituting each terminal portion 31 has a circular shape when viewed from above, and its outer diameter (diameter) is greater than 5 μm and less than 400 μm. On the other hand, the upper conductive layer 31b constituting each terminal portion 31 has a circular shape when viewed from above, and its outer diameter (diameter) is greater than 2 μm and less than 300 μm.

[0096] In this embodiment, the second insulating layer 40 is also preferably formed so that the value (T2 / T1) obtained by dividing the second thickness value T2 by the first thickness value T1 is greater than 0.3 and less than 1. In the second insulating layer 40, the value (T2 / T1) is more preferably greater than 0.5 and less than 1, further preferably greater than 0.75 and less than 1, and even more preferably greater than 0.8 and less than 1.

[0097] By setting the value (T2 / T1) to be greater than 0.3, it is possible to suppress poor filling of the underfill 6 due to the underfill 6 not being able to follow the uneven shape. In addition, by preventing significantly large unevenness from being formed on the upper surface 40a of the second insulating layer 40, the thickness of the wired circuit board 1 can be reduced.

[0098] With the above structure Figure 22 The wired circuit board 1 of the embodiment can be used as a component of the mounting substrate 3 in the same manner as the wired circuit board 1 of the first embodiment. Figure 22 The mounting substrate 3 of the wired circuit board 1 can be used as one component of the electronic component 4 .

[0099] <2> Method for manufacturing the wired circuit board 1 A method for manufacturing the wired circuit board 1 according to the second embodiment will be described. The wired circuit board 1 according to this embodiment is similar to the first embodiment, using, for example, Figure 7 The roll-to-roll device 500 is manufactured by a roll-to-roll method. Figures 23 to 30 Is used to illustrate Figure 22 A cross-sectional view showing an example of a method for manufacturing the wired circuit board 1. Figures 23 to 30 The cross-sectional view shown is Figure 22 The upper part of the figure corresponds to the cross-sectional view of the part shown.

[0100] In the method for manufacturing the wired circuit board 1 according to the present embodiment, first, the method described in the first embodiment is performed. Figures 8 to 13 The method shown in FIG. 1 is used to produce a laminate (a portion of the wiring circuit board 1). At this point in time, the laminate in the process of being produced has a structure in which a plurality of plating layers 38 are formed on one side (the upper surface 21 of the first insulating layer 20) of the laminate of the metal support 10 and the first insulating layer 20 via a seed layer 39.

[0101] Then, if Figure 23 As shown in FIG. 1 , a resist layer 52 having openings of a given pattern is formed on the upper surface 11 of the first insulating layer 20. The resist layer 52 is formed by Figure 11 The plating resist 51 is formed in the same manner as described above.

[0102] The plating resist 52 is formed to cover the plurality of wiring portions 32 ( Figure 4 ) is formed on the first insulating layer 20. In addition, the plating resist 52 has a plurality of openings in the portion of the plating layer 38 where the plurality of terminal portions 31 are to be formed. Thus, a portion of the plating layer 38 is exposed upward through the plurality of openings.

[0103] Next, electroplating is performed using the portions of the plating layer 38 exposed through the plurality of openings in the plating resist 52. Figure 24 As shown, a conductor (copper in this example) is filled in the opening of the plating resist 52 to form a new plating layer. Figure 22 The upper conductor layer 31b.

[0104] Then, if Figure 25 As shown, the plating resist 52 is removed. Figure 26 As shown, the exposed portion of the seed layer 39 is removed by etching. Thus, a stack of the seed layer 39 and the plating layer 38 is formed. Figure 22 The conductor layer 30 is formed by a laminate of the lower conductor layer 31a and the upper conductor layer 31b.

[0105] More specifically, as a part of the conductor layer 30, a plurality of terminal portions 31 including a lower conductor layer 31a and an upper conductor layer 31b are formed. In addition, as the other part of the conductor layer 30, a plurality of wiring portions 32 ( Figure 4 At this time, on the upper surface 21 of the first insulating layer 20, a portion of the conductive layer 30 is arranged two-dimensionally as a plurality of terminal portions 31 in a repeated arrangement in a predetermined configuration pattern. Figures 26 to 30 In FIG, three terminal portions 31 in the conductor layer 30 are shown. Figures 27 to 30 In the figure, the seed layer 39 is omitted.

[0106] Next, according to the first embodiment described Figures 15 to 18 According to the method shown, the second insulating layer 40 is formed on the upper surface 21 of the first insulating layer 20 .

[0107] Specifically, if Figure 27 As shown in FIG. 1 , a layer of a liquid varnish 60 of thermoplastic polyimide or thermosetting polyimide is formed on the first insulating layer 20. Then, a drying process is performed to evaporate the solvent of the varnish 60 to a degree that does not lose fluidity. Figure 28 As shown, the upper surface 60a of the varnish 60 layer after the drying process has unevenness formed.

[0108] Next, a pressing member (not shown) having a flat pressing surface is prepared, and the pressing member is used to press the upper surface 60a of the layer of varnish 60. Figure 29 As shown, the upper surface 60a of the layer of varnish 60 is planarized.

[0109] After that, the varnish 60 is cured. Figure 30 As shown, the upper surface 60a of the varnish 60 layer after the curing process is again formed with unevenness. Finally, a plurality of openings are formed in the varnish 60 layer in such a way that the central portion of each of the plurality of terminal portions 31 is exposed upward and the outer portion of the terminal portion 31 is covered by the cured varnish 60. Thus, the varnish 60 layer is completed. Figure 22 The finished wired circuit board 1 is wound on a winding roll R2. The wired circuit board 1 wound on the winding roll R2 is cut, for example, according to a predetermined design size. This allows for the production of multiple wired circuit boards 1 having sizes appropriate for the intended use.

[0110] In addition, the wired circuit board 1 according to this embodiment is not limited to Figures 27 to 30 For example, it is also possible to follow the example described in the first embodiment. Figures 19 to 21 The second insulating layer 40 can be formed by the method shown in FIG. That is, the sheet member 60s ( Figure 19), pressing the sheet member 60s and performing a curing process to form the second insulating layer 40.

[0111] 3. Third Implementation Hereinafter, differences between the wired circuit board according to the third embodiment and the wired circuit board according to the second embodiment will be described.

[0112] Figure 31 It is a cross-sectional view of a wired circuit board 1 according to the third embodiment. Figure 31 The cross-sectional view is equivalent to Figure 22 A cross-sectional view of a wiring circuit board 1 according to a second embodiment of the present invention. Figure 31 As shown, the wired circuit board 1 according to the third embodiment has a structure in which an additional wiring circuit structure is provided on the lower surface 12 of the metal support 10 in the wired circuit board 1 according to the second embodiment. Furthermore, the wired circuit board 1 according to the third embodiment has a structure in which the wiring circuit structure on the upper surface 11 of the metal support 10 and the additional wiring circuit structure on the lower surface 12 of the metal support 10 are electrically connected by through-holes 91 passing through through-holes 19 formed in the metal support 10.

[0113] Specifically, in the wired circuit board 1 according to this embodiment, the metal support 10 is provided with a through hole 19 extending from the upper surface 11 to the lower surface 12. The first insulating layer 20 is formed to cover the upper surface 11 of the metal support 10 and the inner peripheral surface of the through hole 19.

[0114] As in the second embodiment, a conductive layer 30 is formed in a predetermined pattern on the upper surface 21 of the first insulating layer 20. Furthermore, as in the second embodiment, a second insulating layer 40 having a plurality of openings 49 is formed on the upper surface 21 of the first insulating layer 20 to partially cover the conductive layer 30. The second insulating layer 40 includes a plurality of unit structures US that have the plurality of openings 49 and protrude upward.

[0115] A third insulating layer 70 is formed on the lower surface 12 of the metal support 10. The third insulating layer 70 has an upper surface 71 and a lower surface 72 that face opposite directions in a third direction D3. The upper surface 71 of the third insulating layer 70 contacts the lower surface 12 of the metal support 10. A conductive layer 90 is formed in a predetermined pattern on the lower surface 72 of the third insulating layer 70. Furthermore, a fourth insulating layer 80 is formed on the lower surface 72 of the third insulating layer 70 to cover the conductive layer 90.

[0116] Through-holes 99 are formed in the first insulating layer 20 and the third insulating layer 70, extending through the interior of the through-hole 19 of the metal support 10 in the third direction D3. Through-holes 99 are formed within the interior of the through-holes 99. Through-holes 91 are electrically connected to a portion of the conductive layer 30 on the upper surface 21 of the first insulating layer 20. Furthermore, through-holes 91 are electrically connected to a portion of the conductive layer 90 on the lower surface 72 of the third insulating layer 70.

[0117] 4. Other Implementation Methods (a) The wired circuit board 1 according to the first to third embodiments includes the metal support 10, but the present invention is not limited thereto. The metal support 10 may not be provided on the wired circuit board 1. In this case, the wired circuit board 1 can be made thinner.

[0118] (b) While the wired circuit board 1 according to the first and second embodiments is manufactured using a roll-to-roll process and thus possesses flexibility, the present invention is not limited thereto. The wired circuit board 1 may also be manufactured using methods other than the roll-to-roll process. For example, it may be manufactured using a single-sheet process in which a single sheet is processed sequentially. In this case, the wired circuit board 1 may also be a rigid substrate that lacks flexibility.

[0119] (c) In the wired circuit board 1 according to the first to third embodiments, two insulating layers (insulating layer 20 and insulating layer 40) are stacked on the upper surface 11 of the metal support 10, with the conductive layer 30 formed between these layers. However, the present invention is not limited to this. The wired circuit board 1 may also have a structure in which three or more insulating layers are stacked on the upper surface 11 of the metal support 10, and the conductive layer 30 is formed within these insulating layers.

[0120] (d) In the wired circuit boards 1 according to the first to third embodiments, the plurality of terminal portions 31 are arranged in a matrix when viewed from above along the third direction D3 , but the present invention is not limited thereto. The plurality of terminal portions 31 may also be arranged in a staggered pattern.

[0121] (e) In the wired circuit boards 1 according to the first to third embodiments, the plurality of openings 49 formed in the second insulating layer 40 each have a circular shape in plan view. However, the present invention is not limited to this. The plurality of openings 49 may each have an elliptical shape in plan view, or may have a polygonal shape such as a triangle or a quadrilateral.

[0122] (f) In one example of the method for manufacturing the wired circuit board 1 according to the first embodiment, after the varnish 60 is applied to the first insulating layer 20, a drying process is performed to evaporate the solvent in the varnish 60 to a degree that does not lose fluidity. However, the present invention is not limited to this. The drying process described above may not be performed. In this case, the varnish 60 may be cured directly after application.

[0123] 5. Correspondence between each part of the embodiment and each structural element of the scope of the patent claim Hereinafter, examples of correspondence between the components of the claimed scope and the components of the embodiments will be described. As the components of the claimed scope, various other components having the structures or functions described in the claimed scope may also be used.

[0124] In the above-mentioned embodiment, the wiring circuit substrate 1 is an example of a wiring circuit substrate, the upper surface 21 of the first insulating layer 20 is an example of a first surface, the first insulating layer 20 is an example of a first insulating layer, the terminal portion 31 is an example of a terminal portion, the conductor layer 30 is an example of a conductor layer, and the second insulating layer 40 is an example of a second insulating layer.

[0125] In addition, the unit structure US is an example of an installation reinforcement portion, the opening portion 49 is an example of an opening portion, the first annular portion 41 is an example of a first annular portion, the second annular portion 42 is an example of a second annular portion, the upper surface 40a of the second insulating layer 40 is an example of a second surface, and the metal support body 10 is an example of a metal support body.

[0126] In addition, the lower conductor layer 31a is an example of a first conductor layer, the upper conductor layer 31b is an example of a second conductor layer, the semiconductor chip 2 is an example of an electrical component, the solder 5 is an example of solder, the underfill 6 is an example of an underfill, the mounting substrate 3 is an example of an electrical component mounting substrate, the electronic component 4 is an example of an electronic component, and the sheet member 60s is an example of a sheet member.

[0127] 6. Summary of implementation methods (Item 1) The wiring circuit substrate involved in the first item comprises: a first insulating layer having a first surface; a conductor layer having a plurality of terminal portions and formed on the first surface of the first insulating layer; and a second insulating layer formed on the first surface of the first insulating layer in a manner covering a portion of the conductor layer, the plurality of terminal portions being two-dimensionally arranged on the first surface in a manner repeatedly arranged in a predetermined configuration pattern, the second insulating layer including a plurality of mounting reinforcement portions, the plurality of mounting reinforcement portions corresponding to the plurality of terminal portions, respectively, and respectively protruding in a direction toward which the first surface faces, each of the plurality of mounting reinforcement portions including: an opening portion, which exposes a central portion of the corresponding terminal portion and overlaps with the central portion of the terminal portion when viewed in the stacking direction of the first insulating layer and the second insulating layer; a first annular portion, which overlaps with an outer portion of the corresponding terminal portion surrounding the central portion when viewed in the stacking direction; and a second annular portion, which surrounds the first annular portion when viewed in the stacking direction and is formed in a manner that is recessed as it moves away from the outer edge of the first annular portion.

[0128] In this wired circuit board, multiple mounting reinforcement sections are provided corresponding to the multiple terminal sections. Each mounting reinforcement section has an opening that exposes the center portion of the corresponding terminal section. Furthermore, the mounting reinforcement section covers the outer portion of the terminal section. Thus, when mounting an electrical component on the wired circuit board, the multiple electrical contacts of the electrical component can be soldered to the multiple terminal sections through the multiple openings in the second insulating layer.

[0129] When mounting electrical components on a wired circuit board, an underfill is placed between the wired circuit board and the electrical components. According to the above structure, the multiple mounting reinforcement portions correspond to the multiple terminal portions, respectively. Therefore, the multiple mounting reinforcement portions are arranged two-dimensionally on the first surface in a repetitive pattern according to a predetermined arrangement. Consequently, a regular pattern of irregularities is created between the electronic component and the wired circuit board by the two-dimensional arrangement of the multiple mounting reinforcement portions on the second insulating layer.

[0130] When the underfill material between the electronic component and the wired circuit board contacts the uneven portions of the second insulating layer and cures, the adhesion between the wired circuit board and the electronic component after mounting is strengthened due to the anchoring effect. This prevents the electronic component from peeling off from the wired circuit board after mounting.

[0131] (Second item) In the wiring circuit substrate involved in the first item, the second insulating layer can be formed so that, when the total area of ​​the second insulating layer observed along the stacking direction is set to a first area value S1 and the total area of ​​the opening portions of the multiple mounting reinforcement portions is set to a second area value S2, the value (S2 / S1) obtained by dividing the second area value S2 by the first area value S1 is greater than 0.01 and less than 0.5.

[0132] In this case, by setting the value (S2 / S1) to be greater than 0.01, it is easier to install electrical components on the wiring circuit board using solder, compared to a case where the value (S2 / S1) is less than 0.01. In addition, the reliability of the electrical connection between the installed electrical components and the wiring circuit board is improved. On the other hand, by setting the value (S2 / S1) to be less than 0.5, the contact area of ​​the underfill at the second insulating layer can be ensured to be greater than a case where the value (S2 / S1) is greater than 0.5. Therefore, the adhesion between the wiring circuit board and the electronic component after installation can be improved.

[0133] (Item 3) In the wiring circuit substrate involved in the first or second item, the second insulating layer may have a second surface exposed in the same direction as the first surface, and when the maximum value of the distance between the first surface and the second surface in the stacking direction is set to the first thickness value T1 and the minimum value of the distance between the first surface and the second surface in the stacking direction is set to the second thickness value T2, the second insulating layer may be formed so that the value (T2 / T1) obtained by dividing the second thickness value T2 by the first thickness value T1 is greater than 0.3 and less than 1.

[0134] In this case, no significant unevenness is formed on the second surface of the second insulating layer. This prevents underfill defects caused by the underfill's inability to follow the uneven shape. Furthermore, since no significant unevenness is formed on the second surface, the overall thickness of the second insulating layer can be reduced. This allows for a thinner wired circuit board.

[0135] (Item 4) In the wired circuit board according to any one of Items 1 to 3, the thickness of the conductor layer in the stacking direction may be 1 μm or more and 20 μm or less.

[0136] The aforementioned size range is relatively narrow as the thickness range of the conductor layer used in the wired circuit board, so that the wired circuit board can be made thinner and flatter.

[0137] (Item 5) In the wired circuit board according to any one of Items 1 to 4, the wired circuit board may further include a metal support, and the first insulating layer may be formed on the metal support.

[0138] In this case, the first insulating layer, the conductive layer, and the second insulating layer are each supported by a metal support. The metal support has high rigidity. Therefore, deformation such as warping in the wired circuit board can be suppressed, and the handleability of the wired circuit board is improved.

[0139] (Item 6) In the wired circuit board according to any one of Items 1 to 5, at least one of the first insulating layer and the second insulating layer may contain a resin including at least one of polyimide and epoxy resin.

[0140] In this case, since polyimide and epoxy resin have relatively low dielectric constants, a wiring circuit substrate suitable for the transmission of high-frequency signals can be achieved. Furthermore, polyimide and epoxy resin have high dimensional stability and high heat resistance. Furthermore, it is relatively easy to match the thermal expansion coefficients of polyimide and epoxy resin with the conductor layers used in the wiring circuit substrate. Therefore, the above-mentioned structure can suppress deformations such as warping. As a result, the reliability of the wiring circuit substrate is improved.

[0141] (Item 7) In the wiring circuit substrate involved in any one of items 1 to 6, the conductor layer may include: a first conductor layer, which is directly formed on the first insulating layer; and a plurality of second conductor layers, which are respectively stacked on a plurality of parts of the first conductor layer, and the plurality of terminal portions may be composed of a plurality of parts of the first conductor layer and the plurality of second conductor layers.

[0142] In this case, the first conductor layer can be used to form wiring sections connected to multiple terminal sections. This allows the exposed portions of the multiple terminal sections to be positioned differently from the positions of the wiring sections in the stacking direction. This increases the degree of freedom in the layout of the wiring sections and terminal sections within the wired circuit board.

[0143] (Item 8) In the wired circuit board according to Item 7, the thickness of the second conductor layer in the stacking direction may be 1 μm or more and 20 μm or less.

[0144] The aforementioned size range is relatively narrow as the thickness range of the conductor layer used in the wired circuit board, so that the wired circuit board can be made thinner and flatter.

[0145] (Item 9) In the wired circuit board according to any one of Items 1 to 8, the thickness of the plurality of terminal portions in the stacking direction may be smaller than a minimum value of the thickness of the second insulating layer in the stacking direction.

[0146] According to the above configuration, it is possible to prevent undesired portions of the plurality of terminal portions other than the central portion from being exposed in the space above the second insulating layer.

[0147] (Item 10) In the wiring circuit substrate involved in any one of items 1 to 9, when the distance between the first surface in the stacking direction and the upper end surface of the first annular portion of each mounting reinforcement portion is set as the reinforcement portion height, the maximum height of the multiple reinforcement portion heights corresponding to the multiple mounting reinforcement portions is set as the reinforcement portion maximum height Hmax, and the minimum height of the multiple reinforcement portion heights is set as the reinforcement portion minimum height Hmin, the value obtained by dividing the reinforcement portion minimum height Hmin by the reinforcement portion maximum height Hmax (Hmin / Hmax) can be greater than 0.7.

[0148] In this case, compared to a case where the value (Hmin / Hmax) is 0.7 or less, the amount of underfill filled between multiple portions of the wired circuit board and the electronic components when mounting the electronic components on the wired circuit board becomes more uniform. This prevents a decrease in adhesion caused by localized underfill shortages between the wired circuit board and the electronic components after mounting.

[0149] (Item 11) The electrical component mounting substrate involved in Item 11 comprises: a wiring circuit substrate described in any one of Items 1 to 10; and an electrical component having a plurality of electrical contacts, wherein the electrical component is mounted on the wiring circuit substrate by connecting the plurality of electrical contacts to the plurality of terminal portions of the wiring circuit substrate using solder, and a bottom filler is filled between the electrical component and the wiring circuit substrate.

[0150] The electric component mounting substrate includes the above-mentioned wired circuit substrate, thereby making it difficult for the electric component to be peeled off from the wired circuit substrate.

[0151] (Item 12) The electronic component according to Item 12 includes the electric component mounting substrate according to Item 11.

[0152] This electronic component includes the above-mentioned electric component mounting substrate and therefore has high reliability.

[0153] (Item 13) The method for manufacturing a wiring circuit substrate involved in Item 13 includes: a process of preparing a first insulating layer having a first surface; a process of forming a conductor layer having a plurality of terminal portions on the first surface of the first insulating layer; and a process of forming a second insulating layer on the first surface of the first insulating layer in a manner covering a portion of the conductor layer, the process of forming the conductor layer including a process of two-dimensionally arranging the plurality of terminal portions in a manner of repeatedly arranging them in a predetermined arrangement pattern on the first surface, and the process of forming the second insulating layer including a coating process of coating the plurality of terminal portions on the first surface of the first insulating layer in a manner covering the plurality of terminal portions. A varnish of a thermosetting resin or a thermoplastic resin containing a solvent is coated on the varnish; a pressing process, after the coating process, preparing a pressing member having a flat pressing surface, and flattening the exposed surface of the varnish by bringing the pressing surface of the pressing member into contact with the exposed surface of the varnish; a heat treatment process, after the pressing process, heating the varnish to volatilize the solvent contained in the varnish and solidify the varnish; and a process of forming a plurality of openings in the solidified varnish after the heat treatment process in such a way that the central portion of each terminal portion is exposed and the outer portion of each terminal portion surrounding the central portion is covered by the varnish.

[0154] In this method for manufacturing a wired circuit board, when forming the second insulating layer, the exposed surface of the fluidized varnish is flattened during a pressing step. At this time, the thickness of the varnish layer formed on the first surface decreases in the portion overlapping with the plurality of terminals (hereinafter referred to as the terminal overlapping portion) and increases in the portion not overlapping with the plurality of terminals (hereinafter referred to as the non-terminal overlapping portion).

[0155] Then, the solvent contained in the varnish evaporates during the heat treatment process. The amount of solvent evaporated from the terminal overlapping portion of the varnish layer is less than the amount of solvent evaporated from the non-terminal overlapping portion of the varnish layer. Therefore, the terminal overlapping portion shrinks at a smaller ratio than the non-terminal overlapping portion. In other words, during the heat treatment process, the non-terminal overlapping portion shrinks significantly compared to the terminal overlapping portion. As a result, the non-terminal overlapping portion after heat treatment is formed to be recessed relative to the terminal overlapping portion. After the heat treatment process, a plurality of openings are formed in such a way that the central portion of each of the plurality of terminal portions is exposed.

[0156] When mounting an electric component on the wired circuit board completed as described above, the electric contacts of the electric component can be soldered to the terminal portions through the openings of the second insulating layer.

[0157] When mounting an electrical component on a wiring circuit board, an underfill is filled between the wiring circuit board and the electrical component. In the wiring circuit board, a plurality of terminal overlapping portions and a plurality of non-terminal overlapping portions surrounding each terminal overlapping portion are formed to protrude in a direction toward which the first surface of the first insulating layer faces.

[0158] Each terminal overlapping portion and the non-terminal overlapping portion surrounding it are referred to as a mounting reinforcement portion. In this case, multiple mounting reinforcement portions correspond to multiple terminal portions, and are therefore arranged two-dimensionally on the first surface in a repetitive pattern according to a predetermined arrangement. Consequently, a regular pattern of irregularities is created between the electronic component and the printed circuit board by the two-dimensional arrangement of the multiple mounting reinforcement portions on the second insulating layer.

[0159] When the underfill material between the electronic component and the wired circuit board contacts the uneven portions of the second insulating layer and cures, the adhesion between the wired circuit board and the electronic component after mounting is strengthened due to the anchoring effect. This prevents the electronic component from peeling off from the wired circuit board after mounting.

[0160] (Item 14) The method for manufacturing a wiring circuit substrate involved in Item 14 includes: a process of preparing a first insulating layer having a first surface; a process of forming a conductor layer having a plurality of terminal portions on the first surface of the first insulating layer; and a process of forming a second insulating layer on the first surface of the first insulating layer in a manner covering a portion of the conductor layer, the process of forming the conductor layer includes a process of two-dimensionally arranging the plurality of terminal portions in a manner of repeatedly arranging them in a predetermined configuration pattern on the first surface, and the process of forming the second insulating layer includes a pasting process of pasting a semi-cured film on the first surface of the first insulating layer in a manner covering the plurality of terminal portions. a sheet-like member containing a thermosetting resin or a thermoplastic resin in a state; a pressing process, after the pasting process, preparing a pressing member having a flat pressing surface, and flattening the exposed surface of the sheet-like member by bringing the pressing surface of the pressing member into contact with the exposed surface of the sheet-like member; a heat treatment process, after the pressing process, heating the sheet-like member to volatilize the solvent contained in the sheet-like member and solidify the sheet-like member, and after the heat treatment process, forming a plurality of openings in the solidified sheet-like member in a manner such that the central portion of each terminal portion is exposed and the outer portion of each terminal portion surrounding the central portion is covered by the sheet-like member.

[0161] In this method for manufacturing a wired circuit board, when forming the second insulating layer, the exposed surface of the semi-cured sheet member is flattened during a pressing step. At this time, the thickness of the sheet member layer formed on the first surface decreases in the portion overlapping with the plurality of terminal portions (hereinafter referred to as the terminal overlapping portion) and increases in the portion not overlapping with the plurality of terminal portions (hereinafter referred to as the non-terminal overlapping portion).

[0162] Then, during the heat treatment process, the solvent contained in the sheet-like component evaporates. The amount of solvent evaporated from the terminal overlapping portion of the sheet-like component layer is less than the amount of solvent evaporated from the non-terminal overlapping portion of the sheet-like component layer. Therefore, the terminal overlapping portion shrinks at a smaller ratio than the non-terminal overlapping portion. In other words, during the heat treatment process, the non-terminal overlapping portion shrinks significantly compared to the terminal overlapping portion. As a result, the non-terminal overlapping portion after heat treatment is formed to be recessed relative to the terminal overlapping portion. After the heat treatment process, multiple openings are formed in a manner such that the central portion of each of the multiple terminal portions is exposed.

[0163] When mounting an electric component on the wired circuit board completed as described above, the electric contacts of the electric component can be soldered to the terminal portions through the openings of the second insulating layer.

[0164] When mounting an electrical component on a wiring circuit board, an underfill is filled between the wiring circuit board and the electrical component. In the wiring circuit board, a plurality of terminal overlapping portions and a plurality of non-terminal overlapping portions surrounding each terminal overlapping portion are formed to protrude in a direction toward which the first surface of the first insulating layer faces.

[0165] Each terminal overlapping portion and the non-terminal overlapping portion surrounding it are referred to as a mounting reinforcement portion. In this case, multiple mounting reinforcement portions correspond to multiple terminal portions, and are therefore arranged two-dimensionally on the first surface in a repetitive pattern according to a predetermined arrangement. Consequently, a regular pattern of irregularities is created between the electronic component and the printed circuit board by the two-dimensional arrangement of the multiple mounting reinforcement portions on the second insulating layer.

[0166] When the underfill material between the electronic component and the wired circuit board contacts the uneven portions of the second insulating layer and cures, the adhesion between the wired circuit board and the electronic component after mounting is strengthened due to the anchoring effect. This prevents the electronic component from peeling off from the wired circuit board after mounting.

Claims

1. A wiring circuit substrate comprising: a first insulating layer having a first surface; a conductor layer having a plurality of terminal portions and formed on the first surface of the first insulating layer; as well as a second insulating layer formed on the first surface of the first insulating layer so as to cover a portion of the conductive layer; The plurality of terminal portions are two-dimensionally arranged on the first surface in a manner of being repeatedly arranged in a predetermined arrangement pattern. The second insulating layer includes a plurality of mounting reinforcement portions, each corresponding to the plurality of terminal portions and protruding in a direction toward which the first surface faces. Each of the plurality of mounting reinforcement portions comprises: an opening portion that exposes a central portion of a corresponding terminal portion and overlaps with the central portion of the terminal portion when viewed along a stacking direction of the first insulating layer and the second insulating layer; a first annular portion that overlaps with an outer portion of the corresponding terminal portion surrounding the central portion when viewed in the stacking direction; and The second annular portion surrounds the first annular portion when viewed in the stacking direction and is formed so as to be recessed as it moves away from an outer edge of the first annular portion.

2. The wired circuit substrate according to claim 1, wherein The second insulating layer is formed so that, when the total area of ​​the second insulating layer observed along the stacking direction is set to a first area value S1 and the total area of ​​the opening portions of the multiple mounting reinforcement portions is set to a second area value S2, a value S2 / S1 obtained by dividing the second area value S2 by the first area value S1 is greater than 0.01 and less than 0.

5.

3. The wired circuit substrate according to claim 1 or 2, wherein: The second insulating layer has a second surface exposed in the same direction as the first surface, When the maximum value of the distance between the first surface and the second surface in the stacking direction is set to the first thickness value T1 and the minimum value of the distance between the first surface and the second surface in the stacking direction is set to the second thickness value T2, the second insulating layer is formed as follows: the value T2 / T1 obtained by dividing the second thickness value T2 by the first thickness value T1 is greater than 0.3 and less than 1.

4. The wired circuit board according to any one of claims 1 to 3, wherein The thickness of the conductor layer in the stacking direction is 1 μm or more and 20 μm or less.

5. The wired circuit board according to any one of claims 1 to 4, wherein The wiring circuit substrate further includes a metal support. The first insulating layer is formed on the metal support.

6. The wired circuit board according to any one of claims 1 to 5, wherein At least one of the first insulating layer and the second insulating layer includes a resin including at least one of polyimide and epoxy resin.

7. The wired circuit board according to any one of claims 1 to 6, wherein The conductor layer includes: a first conductor layer formed directly on the first insulating layer; and a plurality of second conductor layers, each of which is stacked on a plurality of portions of the first conductor layer; The plurality of terminal portions are constituted by a plurality of portions of the first conductor layer and the plurality of second conductor layers.

8. The wired circuit substrate according to claim 7, wherein The thickness of the second conductive layer in the stacking direction is greater than or equal to 1 μm and less than or equal to 20 μm.

9. The wired circuit board according to any one of claims 1 to 8, wherein The thickness of the plurality of terminal portions in the stacking direction is smaller than a minimum value of the thickness of the second insulating layer in the stacking direction.

10. The wired circuit board according to any one of claims 1 to 9, wherein When the distance between the first surface in the stacking direction and the upper end surface of the first annular portion of each mounting reinforcement portion is set as the reinforcement portion height, the maximum height of the multiple reinforcement portion heights corresponding to the multiple mounting reinforcement portions is set as the reinforcement portion maximum height Hmax, and the minimum height of the multiple reinforcement portion heights is set as the reinforcement portion minimum height Hmin, the value Hmin / Hmax obtained by dividing the reinforcement portion minimum height Hmin by the reinforcement portion maximum height Hmax is greater than 0.

7.

11. An electrical component mounting substrate comprising: The wired circuit substrate according to claim 1 or 2; and an electrical element having a plurality of electrical contacts, The electrical element is mounted on the wired circuit board by connecting the plurality of electrical contacts to the plurality of terminal portions of the wired circuit board using solder. An underfill is filled between the electrical component and the wired circuit board.

12. An electronic component comprising: The electric component mounting substrate according to claim 11.

13. A method for manufacturing a wiring circuit substrate, comprising: a step of preparing a first insulating layer having a first surface; forming a conductive layer having a plurality of terminal portions on the first surface of the first insulating layer; as well as forming a second insulating layer on the first surface of the first insulating layer so as to cover a portion of the conductive layer; The step of forming the conductive layer includes the step of two-dimensionally arranging the plurality of terminal portions in a manner of being repeatedly arranged in a predetermined arrangement pattern on the first surface. The process of forming the second insulating layer includes: a coating step of coating a varnish of a thermosetting resin or a thermoplastic resin containing a solvent on the first surface of the first insulating layer in a manner covering the plurality of terminal portions; a pressing step of preparing a pressing member having a flat pressing surface after the coating step, and flattening the exposed surface of the varnish by bringing the pressing surface of the pressing member into contact with the exposed surface of the varnish; a heat treatment step of heating the varnish after the pressing step to volatilize the solvent contained in the varnish and solidify the varnish; and After the heat treatment step, a step of forming a plurality of openings in the cured varnish such that a central portion of each terminal is exposed and an outer portion of each terminal surrounding the central portion is covered with the varnish.

14. A method for manufacturing a wiring circuit substrate, comprising: a step of preparing a first insulating layer having a first surface; forming a conductive layer having a plurality of terminal portions on the first surface of the first insulating layer; as well as forming a second insulating layer on the first surface of the first insulating layer so as to cover a portion of the conductive layer; The step of forming the conductive layer includes the step of two-dimensionally arranging the plurality of terminal portions in a manner of being repeatedly arranged in a predetermined arrangement pattern on the first surface. The process of forming the second insulating layer includes: a pasting step of pasting a sheet-like member containing a thermosetting resin or a thermoplastic resin in a semi-cured state on the first surface of the first insulating layer so as to cover the plurality of terminal portions; a pressing step of preparing a pressing member having a flat pressing surface after the pasting step, and flattening the exposed surface of the sheet member by bringing the pressing surface of the pressing member into contact with the exposed surface of the sheet member; a heat treatment step of heating the sheet-like member after the pressing step to volatilize a solvent contained in the sheet-like member and solidify the sheet-like member; and After the heat treatment step, a step of forming a plurality of openings in the cured sheet member such that a central portion of each terminal is exposed and an outer portion of each terminal surrounding the central portion is covered by the sheet member.

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