Memory device, manufacturing method of memory device and transistor

Abstract

The invention discloses a memory device, a manufacturing method of the memory device and a transistor, and the memory device comprises a semiconductor substrate which is divided into a memory region; a plurality of first grooves are formed in the semiconductor substrate; the gate insulating layer and the semi-floating gate are formed in the first groove; the plurality of second grooves are formed in the semiconductor substrate, each second groove is located above the plurality of first grooves, and each second groove is communicated with the plurality of first grooves in the same row in the first direction; the inter-gate dielectric layer and the control gate are formed in the second groove of the storage region; the second isolation layer is formed in the second groove, the second isolation layer is located on the control gate, and the top surface of the control gate is lower than the top surface of the semiconductor substrate; the second isolation layer is formed on the control gate, so that the top surface of the control gate is lower than the top surface of the semiconductor substrate, the distance between the control gate and the source / drain electrode is ensured, electric leakage and breakdown between the control gate and the source / drain electrode can be effectively reduced, and the performance of the memory device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory device, a method for manufacturing a memory device, and a transistor. Background Art

[0002] In the application process of integrated circuits, the performance of various semiconductor devices will be affected by the thickness of different material layers, which in turn affects the performance of storage devices.

[0003] During actual operation, the researchers of this application found that in the current memory device manufacturing process, the thickness of different material layers may not meet another performance requirement while meeting a certain performance requirement, thereby affecting the overall performance of the memory device. Summary of the Invention

[0004] The technical solution to the technical problem mainly solved by the present invention is: to provide a memory device, a method for manufacturing a memory device and a transistor, by forming a second isolation layer on the control gate so that the top surface of the control gate is lower than the top surface of the semiconductor substrate, thereby ensuring the distance between the control gate and the source / drain of the gate structure, which can effectively reduce leakage and breakdown between the control gate and the source / drain, and improve the performance of the memory device.

[0005] To solve the above technical problems, a technical solution adopted in the present application is: to provide a memory device, comprising: a semiconductor substrate, wherein the semiconductor substrate is divided into a storage area; a plurality of first trenches are formed in the semiconductor substrate; a gate insulating layer and a semi-floating gate are formed in the first trenches; a plurality of second trenches are formed in the semiconductor substrate, each of the second trenches is located above the plurality of first trenches, and each of the second trenches is connected to the plurality of first trenches in the same row in a first direction; an inter-gate dielectric layer and a control gate are formed in the second trenches of the storage area; a second isolation layer is formed in the second trench, and the second isolation layer is located above the control gate, wherein the top surface of the control gate is lower than the top surface of the semiconductor substrate.

[0006] In one embodiment of the present application, the semiconductor substrate is further divided into a lead-out area, and the gate insulation layer and the semi-floating gate are formed in the first trench of the lead-out area; an inter-gate dielectric layer and a lead-out line are formed in the second trench of the lead-out area, wherein the top surface of the lead-out line is higher than the top surface of the semiconductor substrate of the storage area, and the lead-out line is connected to multiple control gates in the same row in the first direction.

[0007] In one embodiment of the present application, the device further includes: a first sub-dielectric layer, the first sub-dielectric layer being formed on the semiconductor substrate on both sides of the lead wire, and the top surface of the first sub-dielectric layer and the top surface of the lead wire being located in the same plane, wherein the plurality of lead wires in the second direction are separated by the first sub-dielectric layer.

[0008] In one embodiment of the present application, it further includes: a first isolation layer, wherein the first isolation layer is located on the sidewall of the second trench.

[0009] In an embodiment of the present application, a plurality of isolation structures are formed in the semiconductor substrate, wherein the plurality of isolation structures extend along the second direction to divide the semiconductor substrate into a plurality of active regions.

[0010] In one embodiment of the present application, a plurality of the half-floating gates in the same row in the first direction are isolated by an isolation structure in the first trench, wherein a top surface of the half-floating gate is higher than a top surface of the isolation structure in the first trench.

[0011] In one embodiment of the present application, the semi-floating gate includes a first gate and a second gate; the first gate is isolated from the semiconductor substrate by the gate insulation layer, and the second gate is in contact with the semiconductor substrate, wherein in the second direction, the width of the second gate is greater than the width of the first gate.

[0012] In one embodiment of the present application, it further includes: a plurality of source / drain electrodes, wherein the plurality of source / drain electrodes are formed in the semiconductor substrate on both sides of the first trench in the second direction.

[0013] To solve the above technical problems, another technical solution adopted in the present application is: providing a method for manufacturing a semiconductor transistor, comprising: providing a semiconductor substrate, wherein a plurality of first trenches and a plurality of second trenches are located in the semiconductor substrate, each second trench is located above the plurality of first trenches, and each second trench is connected to the plurality of first trenches in the same row in the first direction; forming a gate insulation layer and a semi-floating gate in each first trench; forming an inter-gate dielectric layer and a control gate in each second trench; and forming a second isolation layer above the control gate of the second trench, wherein the top surface of the control gate is lower than the top surface of the semiconductor substrate.

[0014] In one embodiment of the present application, the forming of multiple first trenches and multiple second trenches includes: forming multiple third trenches, multiple third trenches are formed in the semiconductor substrate, and forming an isolation structure in each of the third trenches, wherein the multiple third trenches extend along the second direction; removing at least part of the isolation structure and the semiconductor substrate to form a plurality of second trenches and a plurality of first trenches, wherein the multiple first trenches in the same row in the first direction are isolated by the isolation structure.

[0015] In one embodiment of the present application, the forming of a gate insulating layer and a semi-floating gate in each of the first trenches includes: forming the gate insulating layer on the sidewalls of each of the first trenches; forming a first gate material in the first trench where the gate insulating layer is formed; removing at least a portion of the first gate material and at least a portion of the gate insulating layer to form a contact window, and forming a second gate material above the contact window; removing at least a portion of the first gate material and the second gate material to form the semi-floating gate, with the remaining first gate material serving as the first gate and the remaining second gate material serving as the second gate, and the semi-floating gate including the first gate and the second gate.

[0016] In one embodiment of the present application, when forming the semi-floating gate, it also includes: removing at least a portion of the isolation structure exposed by the second trench so that the top surface of the semi-floating gate is higher than the top surface of the isolation structure exposed by the second trench, wherein in the first direction, the width of the isolation structure exposed by the second trench is smaller than the width of the isolation structure in the semiconductor substrate, so that the width of the second gate formed in the first trench is greater than the width of the first gate.

[0017] In one embodiment of the present application, the forming of an intergate dielectric layer and a control gate in each of the second trenches includes: forming an intergate dielectric layer, the intergate dielectric layer being in contact with the semi-floating gate; forming a third gate material covering the intergate dielectric layer; and lowering the height of the third gate material in the storage area to form the control gate.

[0018] In one embodiment of the present application, the semiconductor substrate is further divided into a lead-out area, and the gate insulation layer and the semi-floating gate are formed in the first trench of the lead-out area; an inter-gate dielectric layer and a lead-out line are formed in the second trench of the lead-out area, wherein the top surface of the lead-out line is higher than the top surface of the semiconductor substrate of the storage area, and the lead-out line is connected to multiple control gates in the same row in the first direction.

[0019] In one embodiment of the present application, source / drain electrodes are formed in the semiconductor substrate on both sides of the first trench in the second direction.

[0020] In one embodiment of the present application, before forming the inter-gate dielectric layer, a first isolation layer is formed on the sidewalls of the second trench.

[0021] To solve the above technical problems, another technical solution adopted in the present application is: providing a transistor, comprising: a semiconductor substrate; a gate insulation layer and a semi-floating gate formed in the semiconductor substrate; an intergate dielectric layer and a control gate formed in the semiconductor substrate and located above the semi-floating gate, wherein the control gate is isolated from the semi-floating gate by the intergate dielectric layer; a second isolation layer is formed above the control gate; wherein the top surface of the control gate is lower than the top surface of the semiconductor substrate.

[0022] In one embodiment of the present application, the semi-floating gate includes a first gate and a second gate; the first gate is isolated from the semiconductor substrate by the gate insulation layer, the second gate is in contact with the semiconductor substrate, and the second gate is in contact with the first gate, wherein in the first direction, the width of the second gate is greater than the width of the first gate.

[0023] In one embodiment of the present application, the control gate further includes a source / drain, wherein the source / drain are formed in the semiconductor substrate on both sides of the control gate in the second direction.

[0024] In one embodiment of the present application, the device further includes: a first isolation layer formed on a sidewall of the control gate.

[0025] In the current technology, the memory device provided by the present application includes: a semiconductor substrate, which is divided into storage areas; a plurality of first trenches are formed in the semiconductor substrate; a gate insulating layer and a semi-floating gate are formed in the first trenches; a plurality of second trenches are formed in the semiconductor substrate, each second trench is located above the plurality of first trenches, and each second trench is connected to the plurality of first trenches in the same row in the first direction; an inter-gate dielectric layer and a control gate in the second trench of the storage area; a second isolation layer is formed in the second trench, and the second isolation layer is located above the control gate, wherein the top surface of the control gate is lower than the top surface of the semiconductor substrate; that is, in the present application, by forming the second isolation layer on the control gate, the top surface of the control gate is lower than the top surface of the semiconductor substrate, thereby ensuring the distance between the control gate and the source / drain, which can effectively reduce the leakage and breakdown between the control gate and the source / drain, and improve the performance of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0027] Figure 1 is a three-dimensional diagram from a first perspective of an embodiment of a memory device in this application;

[0028] Figure 2 is a three-dimensional diagram from a second perspective of an embodiment of a memory device in this application;

[0029] Figure 3 is a three-dimensional diagram from a third perspective of an embodiment of a memory device in this application;

[0030] Figure 4 This is a flow chart of an embodiment of a method for manufacturing a memory device in the present application;

[0031] Figure 5 is a schematic structural diagram of an embodiment of a semiconductor substrate in the present application;

[0032] Figure 6A This is a three-dimensional diagram from a first perspective of an embodiment of forming a plurality of first grooves and a plurality of second grooves in this application. Figure 6B For this application Figure 6A A second perspective diagram of Figure 6C This application Figure 6A Schematic diagram of the third perspective;

[0033] Figure 7 1 is a structural diagram of an embodiment of forming a gate insulating layer and a first gate material in the present application;

[0034] Figure 8A This is a first-perspective three-dimensional diagram of an embodiment of forming a contact window in this application. Figure 8B This application Figure 8A A second perspective diagram of Figure 8C This application Figure 8A Schematic diagram of the third perspective;

[0035] Figure 9 This is a three-dimensional diagram from a first perspective of an embodiment of the second gate material in the present application;

[0036] Figure 10 This is a three-dimensional diagram from a first perspective of an embodiment of forming a half floating gate in this application;

[0037] Figure 11 This is a three-dimensional diagram from a first perspective of an embodiment of forming an inter-gate dielectric layer and a control gate in this application;

[0038] Figure 12 This is a three-dimensional diagram from a first perspective of an embodiment of forming a second isolation layer in the present application;

[0039] Figure 13This is a three-dimensional diagram from a fourth perspective of an embodiment of the present application in which at least a portion of the first sub-dielectric layer and the second isolation layer of the storage area are removed;

[0040] Figure 14A This is a three-dimensional diagram from the first perspective of an embodiment of forming a source / drain in this application. Figure 14B This application Figure 14A Schematic diagram of the second perspective;

[0041] Figure 15A This is a schematic diagram of the first perspective structure of a transistor embodiment of the present application. Figure 15B This is a schematic structural diagram of a transistor embodiment from the second perspective in this application.

[0042] In the accompanying drawings, the memory device 10, the transistor 20, the semiconductor substrate 100, the isolation structure 110, the first trench 101, the second trench 102, the second sub-trench 1021, the third trench 103, the gate structure 200, the gate insulation layer 210, the semi-floating gate 220, the first gate 221, the first gate material 2211, the second gate 222, the second gate material 2221, the intergate dielectric layer 230, the control gate 240, the third gate material 241, the lead line 250, the first isolation layer 300, the second isolation layer 400, the first dielectric layer 500, the first sub-dielectric layer 510, the second sub-dielectric layer 520, the source / drain S / D, the source S, the drain D, the storage area A, the lead-out area B, the active area C1, the first spare area F, the contact window K, the width K1 of the second gate in the first direction, and the width K2 of the first gate in the first direction. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0044] Provided is a memory device capable of effectively reducing leakage and breakdown between a control gate and a source / drain, thereby improving the performance of the memory device.

[0045] See also Figure 1 、 Figure 2 and Figure 3 , Figure 1 This is a three-dimensional diagram from a first perspective of an embodiment of a storage device in this application. Figure 2 This is a three-dimensional diagram from a second perspective of an embodiment of a memory device in this application. Figure 3 This is a three-dimensional diagram from a third perspective of an embodiment of a storage device in this application.

[0046] like Figure 1 、 Figure 2 and Figure 3 As shown, the memory device of the present application includes: a semiconductor substrate 100, which is divided into a storage area A; a plurality of first trenches 101 are formed in the semiconductor substrate 100; a gate insulating layer 210 and a semi-floating gate 220 are formed in the first trenches 101; a plurality of second trenches 102 are formed in the semiconductor substrate 100, each second trench 102 is located above the plurality of first trenches 101, and each second trench 102 is connected to the plurality of first trenches 101 in the same row in a first direction; an inter-gate dielectric layer 230 and a control gate 240 are formed in the second trenches of the storage area, a second isolation layer 400 is formed in the second trench 102, and the second isolation layer 400 is located above the control gate 240, and the second isolation layer 400 is in contact with the control gate 240, wherein the top surface of the control gate 240 is lower than the top surface of the semiconductor substrate 100.

[0047] The first direction may be an X direction, the second direction may be a Y direction, and the first direction and the second direction are perpendicular to each other on a horizontal plane.

[0048] The semiconductor substrate may be any suitable base material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).

[0049] In some embodiments, a second isolation layer 400 is formed on the control gate 240 so that the top surface of the control gate 240 is lower than the top surface of the semiconductor substrate 100, which can ensure the distance between the control gate and the source / drain and effectively reduce leakage and breakdown between the control gate and the source / drain.

[0050] The second isolation layer is made of an oxidized material, such as silicon oxide.

[0051] In some embodiments, the thickness of the second isolation layer can be set according to actual conditions, and can be 200A-800A, such as 200A, 300A, 400A, 500A, 600A, 700A, 800A, etc., where A is angstrom and 1A is equal to 10 -10 m, which is 0.1 nanometer.

[0052] In some embodiments, a plurality of isolation structures 110 are formed in the semiconductor substrate 100 . The plurality of isolation structures 110 extend along the second direction to divide the semiconductor substrate 100 into a plurality of active regions. Please refer to the following drawings for details.

[0053] In some embodiments, source / drain electrodes are formed on the semiconductor substrate 100 on both sides of the gate structure 200 in the second direction.

[0054] Specifically, the gate structure 200 includes a gate insulation layer 210, a semi-floating gate 220, an inter-gate dielectric layer 230 and a control gate 240; the gate insulation layer 210 covers at least part of the side wall of the first trench 101, the semi-floating gate 220 is formed in the first trench 101, the inter-gate dielectric layer 230 covers the semi-floating gate 220 and the side wall of the second trench 102, and the control gate 240 is formed in the second trench 102, that is, the control gate 240 is on the semi-floating gate 220, the second isolation layer 400 is formed on the control gate, and the top surface of the control gate 240 is lower than the top surface of the semiconductor substrate 100.

[0055] In this embodiment, a second isolation layer is formed on the control gate so that the top surface of the control gate is lower than the top surface of the semiconductor substrate, thereby ensuring a certain distance between the control gate and the source / drain. This can effectively reduce leakage and breakdown between the control gate and the source / drain, thereby improving the performance of the storage device.

[0056] In some embodiments, the semiconductor substrate 100 is further divided into a lead-out area B, and a gate insulation layer 210 and a semi-floating gate 220 are formed in the first trench 101 of the lead-out area B, and an inter-gate dielectric layer 230 and a lead-out line 250 are formed in the second trench 102. Moreover, the top surface of the lead-out line 250 is higher than the top surface of the semiconductor substrate 100 in the storage area A, and the lead-out line 250 is connected to multiple control gates 240 in the same row in the first direction.

[0057] Specifically, a semiconductor substrate 100 is divided into a storage region A and an extraction region B. A plurality of first trenches 101 are distributed in the storage region A and the extraction region B. Second trenches 102 extend along a first direction, spanning the storage region A and the extraction region B. Each second trench 102 is located above the plurality of first trenches 101 and communicates with the plurality of first trenches 101 in the same row in the first direction. A gate insulating layer 210 and a semi-floating gate 220 are formed in the first trenches 101. An inter-gate dielectric layer 230 and a control gate 240 are formed in the second trenches 102, with the inter-gate dielectric layer 230 contacting the semi-floating gate 220. A second isolation layer 400 is formed on the control gate 240. In some embodiments, the inter-gate dielectric layer 230 and an extraction line 250 are formed in the second trenches 102 in the extraction region B. The extraction line 250 is connected to the plurality of control gates 240 in the same row in the first direction.

[0058] In some embodiments, a first sub-dielectric layer 510 is further included. The first sub-dielectric layer 510 is formed on the semiconductor substrate 100 on both sides of the lead wires 250, and the top surface of the first sub-dielectric layer 510 and the top surface of the lead wires 250 are located in the same plane. The plurality of lead wires 250 in the second direction are separated by the first sub-dielectric layer 510.

[0059] The first sub-dielectric layer 510 may be a nitride layer, such as a silicon nitride layer.

[0060] Specifically, in the lead-out area B, multiple lead lines 250 are spaced apart in the second direction, and a first sub-dielectric layer 510 is provided between two adjacent lead lines 250, so that the multiple lead lines 250 in the second direction are separated by the first sub-dielectric layer 510; and there is no first sub-dielectric layer 510 in the storage area A, or the first sub-dielectric layer 510 formed in the storage area A is removed.

[0061] In some embodiments, a first isolation layer 300 may also be included, and the first isolation layer 300 is located on the side walls of the second trench on both sides of the control gate of the storage area A; the first isolation layer is formed on the side walls of the second trench on both sides of the control gate to ensure that the width of the control gate is smaller than the width of the semi-floating gate in the second direction, which can ensure the distance between the control gate and the source / drain, and can further effectively reduce leakage and breakdown between the control gate and the source / drain.

[0062] The material of the first isolation layer 300 can be the same as that of the second isolation layer 400 , that is, an oxidized material, such as silicon oxide; or they can be different.

[0063] The first isolation layer 300 is also located on the sidewalls of the second trench on both sides of the lead-out line in the lead-out region B.

[0064] In some embodiments, a plurality of half-floating gates 220 in the same row in the first direction are isolated by the isolation structure 110 in the semiconductor substrate 100 , wherein the top surface of the half-floating gates 220 is higher than the top surface of the isolation structure 110 exposed by the second trench 102 .

[0065] Specifically, an isolation structure 110 is also formed in the semiconductor substrate 100, and multiple isolation structures extend along the second direction to divide the semiconductor substrate into multiple active areas; and in the first direction, multiple isolation structures 110 are arranged at intervals, that is, a first trench 101 is provided between adjacent isolation structures 110, so that multiple half-floating gates 220 in the same row in the first direction are isolated by the isolation structure 110.

[0066] Furthermore, a plurality of half-floating gates 220 in the same row in the second direction are isolated by the semiconductor substrate 100 .

[0067] In some embodiments, the half-floating gate 220 may include a first gate 221 and a second gate 222 .

[0068] The first gate 221 is isolated from the semiconductor substrate 100 by the gate insulating layer 210 , and the second gate 222 is in contact with the semiconductor substrate 100 . In the first direction, the width of the second gate 222 is greater than that of the first gate 221 .

[0069] Specifically, a gate insulating layer 210 is formed in the first trench 101, and a first gate 221 and a second gate 222 are formed on the gate insulating layer 210. The first gate 221 is isolated from the semiconductor substrate 100 by the gate insulating layer 210, and the second gate 222 is in contact with the semiconductor substrate 100, and the second gate 222 is in contact with the first gate 221. The semi-floating gate 220 includes the first gate 221 and the second gate 222; wherein, in the first direction, the width of the second gate 222 is greater than the width of the first gate 221.

[0070] It is understandable that the material of the first gate 221 is different from the material of the second gate 222. For example, the first gate 221 is a single crystal material, and the second gate 222 is a polycrystalline material. The control gate can be made of a polycrystalline material.

[0071] Specifically, an inter-gate dielectric layer 230 is formed on the semi-floating gate 220 of the first trench 101 so that the inter-gate dielectric layer 230 covers the semi-floating gate 220 and the sidewalls of the second trench 102, and then a control gate 240 is formed on the inter-gate dielectric layer 230 of the storage area A, that is, the control gate 240 is formed in the second trench 102 of the storage area A, and then a second isolation layer 400 is formed on the control gate 240 to fill the second trench 102.

[0072] Furthermore, a lead line 250 is formed in the second groove 102 of the lead area B. Therefore, the lead line 250 of the lead area B can be connected to the control gate 240 of the storage area A, that is, each lead line 250 can be connected to multiple control gates 240 in the same row in the first direction.

[0073] In some embodiments, multiple source / drains are also formed, wherein in the storage area A, source / drains are formed in the active area C1 on both sides of the second direction of the gate structure 200; that is, multiple source / drains are formed in the semiconductor substrate on both sides of the second direction of the first trench.

[0074] Metal silicide is formed on the source, drain and lead lines to reduce contact resistance.

[0075] In this embodiment, by forming a second isolation layer on the control gate, the top surface of the control gate is lower than the top surface of the semiconductor substrate, thereby ensuring the distance between the control gate and the source / drain, which can effectively reduce the leakage and breakdown between the gate structure and the source / drain, and improve the performance of the storage device.

[0076] The present application also provides a method for manufacturing a memory device.

[0077] See Figure 4 , Figure 4 This is a flow chart of an embodiment of a method for manufacturing a memory device in the present application.

[0078] like Figure 4 As shown, a method for manufacturing a memory device may include the following operations.

[0079] S10. Provide a semiconductor substrate, wherein the semiconductor substrate is divided into storage areas.

[0080] Specifically, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 is divided into storage areas A.

[0081] S20. Form a plurality of first trenches and a plurality of second trenches, wherein the plurality of first trenches and the plurality of second trenches are located in the semiconductor substrate, each second trench is located above the plurality of first trenches, and each second trench is connected to the plurality of first trenches in the same row in the first direction.

[0082] The first trench 101 refers to a trench formed in the semiconductor substrate 100, and multiple first trenches 101 in the same row in the first direction are separated by isolation structures in the semiconductor substrate, while multiple first trenches 101 in the same column in the second direction are separated by the semiconductor substrate, that is, the first trenches 101 are distributed in the semiconductor substrate; the second trench 102 also refers to a trench formed in the semiconductor substrate 100, and each second trench 102 is located above the multiple first trenches 101. The second trench 102 extends along the first direction, so that each second trench 102 is connected to the multiple first trenches 101 in the same row in the first direction; the first direction is the X direction.

[0083] S30 , forming a gate insulating layer and a semi-floating gate in each first trench.

[0084] Among them, the gate insulation layer 210 refers to an insulating layer formed on at least part of the sidewall of the first trench, which is used to isolate the semiconductor substrate 100 and at least part of the semi-floating gate 220; the semi-floating gate 220 refers to the gate material formed in the first trench of the semiconductor substrate 100.

[0085] S40 , forming an inter-gate dielectric layer and a control gate in each second trench.

[0086] The inter-gate dielectric layer 230 refers to a dielectric layer between the semi-floating gate 220 and the control gate 240 ; and the control gate 240 refers to a gate material formed on the inter-gate dielectric layer.

[0087] S50 , forming a second isolation layer on the control gate in the second trench, wherein a top surface of the control gate is lower than a top surface of the semiconductor substrate.

[0088] The second isolation layer 400 refers to an isolation layer formed on the control gate 240 .

[0089] Specifically, after forming the control gate 240 in the second trench 102 of the storage region A, the second isolation layer 400 is further formed in the second trench 102 , ie, the second isolation layer 400 contacts the control gate 240 to cover the gate structure 200 of the storage region A.

[0090] In some embodiments, the thickness of the second isolation layer can be set according to actual conditions, and can be 200A-800A, such as 200A, 300A, 400A, 500A, 600A, 700A, 800A, etc., where A is angstrom and 1A is equal to 10 -10 m, which is 0.1 nanometer.

[0091] In this embodiment, by forming a second isolation layer on the control gate, the top surface of the control gate is lower than the top surface of the semiconductor substrate, thereby ensuring the distance between the control gate and the source / drain, which can effectively reduce leakage and breakdown between the control gate and the source / drain, thereby improving the performance of the memory device.

[0092] The manufacturing method is described below with reference to the accompanying drawings.

[0093] A semiconductor substrate is provided, wherein the semiconductor substrate is divided into storage areas.

[0094] See 5, Figure 5 It is a structural schematic diagram of an embodiment of a semiconductor substrate in this application.

[0095] like Figure 5 As shown, a semiconductor substrate 100 is provided and divided into a storage area A. A plurality of third trenches 103 extending along the second direction are formed in the semiconductor substrate 100, and an isolation structure is formed in each third trench 103. An active region C1 extending along the second direction is formed between adjacent isolation structures 110; that is, in the first direction, the isolation structure 110 and the active region C1 are spaced apart.

[0096] Specifically, a plurality of isolation structures 110 extending along the second direction are formed in the semiconductor substrate 100 to form a plurality of strip-shaped active regions C1 , and then the isolation structures 110 and the active regions C1 spaced apart are exposed on the surface of the semiconductor substrate 100 .

[0097] Furthermore, a plurality of first trenches and a plurality of second trenches are formed.

[0098] See also Figure 6A 、 Figure 6B and Figure 6C , Figure 6A This is a three-dimensional diagram from a first perspective of an embodiment of forming a plurality of first grooves and a plurality of second grooves in this application. Figure 6B For this application Figure 6A A second perspective diagram of Figure 6C This application Figure 6A Schematic diagram of the third perspective.

[0099] like Figure 6A 、 Figure 6B and Figure 6C As shown, in Figure 5 On the basis of the above, at least part of the isolation structure and the semiconductor substrate is removed to form a plurality of first trenches 101 and a plurality of second trenches 102 in the semiconductor substrate 100, each second trench 102 is located above the plurality of first trenches 101, and the plurality of first trenches 101 in the same row in the first direction are isolated by the isolation structure, and each second trench 102 is connected to the plurality of first trenches in the same row in the first direction.

[0100] Specifically, the semiconductor substrate 100 is etched, and the etching rate of the semiconductor substrate 100 is greater than the etching rate of the isolation structure 110, that is, the semiconductor substrate and the isolation structure are at least partially removed, and finally the trench above the isolation structure in the formed trench is used as the second trench 102, and the trench below the isolation structure is used as the first trench 101. The multiple first trenches 101 are arranged at intervals along the first direction and separated by the isolation structure. Each second trench 102 is connected to the multiple first trenches 101 in the same row in the first direction.

[0101] In some embodiments, before forming the plurality of first trenches 101 and the plurality of second trenches 102 , the following operations may be further included.

[0102] A first dielectric layer 500 is formed to cover the semiconductor substrate 100 and the isolation structure 110 . The semiconductor substrate 100 is etched using the first dielectric layer 500 as a mask to form a plurality of first trenches 101 and a plurality of second trenches 102 in the semiconductor substrate.

[0103] In some embodiments, the first dielectric layer 500 may include a first sub-dielectric layer 510 and a second sub-dielectric layer 520 . The first sub-dielectric layer 510 may be a nitride layer, such as a silicon nitride layer; and the second sub-dielectric layer 520 may be an oxide layer, such as a silicon oxide layer.

[0104] Next, a gate insulating layer 210 and a half-floating gate 220 are formed in each first trench.

[0105] Forming the gate insulating layer 210 and the semi-floating gate 220 may include the following operations.

[0106] First, a gate insulating layer 210 and a first gate material are formed.

[0107] See also Figure 7 , Figure 7 It is a structural diagram of an embodiment of forming a gate insulating layer and a first gate material in this application.

[0108] like Figure 7 As shown, in Figure 6A On this basis, a gate insulating layer 210 is formed on the sidewalls of the first trench 101 and the second trench 102 , and then a first gate material 2211 is formed in the first trench 101 and the second trench 102 formed with the gate insulating layer 210 .

[0109] Next, at least a portion of the first gate material and at least a portion of the gate insulating layer are removed to form a contact window.

[0110] See also Figure 8A 、 Figure 8B and Figure 8C , Figure 8A This is a first-perspective three-dimensional diagram of an embodiment of forming a contact window in this application. Figure 8B This application Figure 8A A second perspective diagram of Figure 8C This application Figure 8A Schematic diagram of the third perspective.

[0111] like Figure 8A 、 Figure 8B and Figure 8C As shown, in Figure 7 On this basis, at least part of the first gate material 2211 in the second trench 102 and the first trench 101 is removed, and at least part of the exposed gate insulation layer 210 is removed to form a contact window K, that is, the semiconductor substrate 100 at the contact window K is exposed.

[0112] Specifically, a hard mask can be used to cover at least part of the first gate material 2211, and the first gate material 2211 not covered by the hard mask can be removed. When the contact window K is formed, the top surface of the remaining first gate material 2211 at the contact window K is lower than the top surface of the isolation structure exposed by the second trench 102.

[0113] In some embodiments, when forming the contact window K, at least a portion of the isolation structure exposed by the second trench 102 is removed, so that the width of the exposed isolation structure in the first direction is smaller than the width of the isolation structure between the first gate materials. Figure 8B and Figure 8C As shown, the width of the second gate formed subsequently in the first direction is greater than the width of the first gate. Figure 10 .

[0114] Furthermore, a second gate material is formed above the contact window.

[0115] See also Figure 9 , Figure 9 This is a three-dimensional diagram from a first perspective of an embodiment of the second gate material in this application.

[0116] like Figure 9 As shown, in Figure 8A On this basis, a second gate material 2221 is formed above the contact window to refill the first trench 101 and the second trench 102. The second gate material 2221 and the first gate material 2211 are made of silicon, but of different materials. For example, the second gate material 2221 is made of single crystal, while the first gate material 2211 is made of polycrystalline. The second gate material 2221 is formed using an epitaxial process.

[0117] Furthermore, at least a portion of the first gate material 2211 , the second gate material 2221 and the gate insulating layer 210 is removed to form a first gate 221 and a second gate 222 . The semi-floating gate 220 includes the first gate 221 and the second gate 222 .

[0118] See also Figure 10 , Figure 10 This is a three-dimensional diagram from a first perspective of an embodiment of forming a half floating gate in this application.

[0119] like Figure 10 As shown, in Figure 9 On this basis, at least part of the first gate material 2211 and the second gate material 2221 is removed, and the remaining first gate material is used as the first gate 221, and the remaining second gate material is used as the second gate 222. The semi-floating gate 220 includes the first gate 221 and the second gate 222.

[0120] In some embodiments, because at least a portion of the isolation structure exposed by the contact window is removed when the contact window is formed, the width K1 of the second gate 222 in the semi-floating gate in the first direction is greater than the width K2 of the first gate.

[0121] Specifically, when forming the semi-floating gate 220, at least a portion of the isolation structure 110 exposed by the second trench 102 can also be removed, that is, at least a portion of the side wall of the isolation structure 110 can be removed, so that the width K1 of the second gate 222 in the semi-floating gate 220 in the first direction is greater than the width K2 of the first gate 221.

[0122] In some embodiments, at least a portion of the isolation structure may be removed from the top, so that the top surface of the half-floating gate 220 is higher than the top surface of the isolation structure 110 exposed by the second trench 102 .

[0123] Furthermore, an inter-gate dielectric layer 230 and a control gate 240 are formed, and the inter-gate dielectric layer is in contact with the semi-floating gate.

[0124] See Figure 11 , Figure 11 This is a three-dimensional diagram from a first perspective of an embodiment of forming an inter-gate dielectric layer and a control gate in this application.

[0125] like Figure 11 As shown, in Figure 10 On this basis, an inter-gate dielectric layer 230 is formed to cover the inner wall of the second trench 102 .

[0126] In some embodiments, the inter-gate dielectric layer 230 may be an ON structure, ie, a double-layer structure consisting of an oxide layer and a nitride layer.

[0127] Furthermore, a third gate material 241 is formed to cover the inter-gate dielectric layer 230 and fill the second trench 102 , wherein at least a portion of the third gate material in the storage area A is used as the control gate 240 , and the third gate material in the lead-out area B is used as the lead-out line 250 .

[0128] In some embodiments, the lead-out line 250 is connected to a plurality of control gates 240 in the same row in the first direction.

[0129] In some embodiments, at least a portion of the gate structure 200 of the storage area A is removed to form a first vacant area F, and the third gate material remaining in the second trench 102 of the storage area A is used as the control gate 240; that is, the height of the third gate material of the storage area A is lowered to form the control gate 240.

[0130] Furthermore, at least a portion of the third gate material of the storage area A is removed to form a first vacant area F, while the third gate material of the lead-out area B is retained, wherein the remaining third gate material of the storage area A is used as the control gate 240, and the third gate material of the lead-out area B is used as the lead-out line 250.

[0131] In some embodiments, before forming the inter-gate dielectric layer, a first isolation layer 300 may be formed on the sidewall of the second trench 102 , wherein the first isolation layer 300 may be made of an oxidized material, such as silicon oxide.

[0132] In some embodiments, because a first sub-dielectric layer 510 and a second sub-dielectric layer 520 are also formed on the semiconductor substrate 100, and the second sub-dielectric layer 520 is an oxide layer, when the first isolation layer 300 is formed, that is, when the isolation material on the half-floating gate 220 is removed, the second sub-dielectric layer 520 is removed at the same time, and the first sub-dielectric layer 510 is retained.

[0133] Next, a second isolation layer 400 is formed in the first vacant region F.

[0134] See also Figure 12 , Figure 12 This is a three-dimensional diagram from a first perspective of an embodiment of forming a second isolation layer in this application.

[0135] like Figure 12 As shown, in Figure 11 On this basis, a second isolation layer 400 is formed in the first vacant region F of the memory region A to cover the control gate 240 of the memory region A. The second isolation layer 400 contacts the lead-out line 250 of the lead-out region B.

[0136] The second isolation layer 400 is made of an oxidized material, such as silicon oxide.

[0137] Specifically, a second isolation layer 400 is formed in the first vacant region F. The second isolation layer 400 is located above the control gate 240 in the second trench 102 of the storage region A. In some embodiments, a bottom surface of the second isolation layer 400 is lower than a top surface of the semiconductor substrate.

[0138] In some embodiments, at least a portion of the first sub-dielectric layer and the second isolation layer of the storage area may be removed to expose the semiconductor substrate of the storage area.

[0139] See also Figure 13 , Figure 13 This is a three-dimensional diagram from a fourth perspective of an embodiment of the present application in which at least part of the first sub-dielectric layer and the second isolation layer of the storage area are removed.

[0140] like Figure 13 As shown, in Figure 12On the basis of the above, at least a portion of the first sub-dielectric layer 510 and the second isolation layer 400 of the storage area A is removed to expose the semiconductor substrate 100 of the storage area A. Because the semiconductor substrate 100 of the storage area A is covered by the first sub-dielectric layer 510, after the first sub-dielectric layer 510 is removed, the semiconductor substrate 100 of the storage area A is exposed. At the same time, at least a portion of the second isolation layer 400 is removed. The top surface of the remaining second isolation layer 400 is located in the same plane as the top surface of the semiconductor substrate 100. The first sub-dielectric layer 510 of the lead-out area B is retained, that is, the first sub-dielectric layer 510 exists between adjacent lead lines 250 in the lead-out area B.

[0141] Furthermore, source / drain electrodes are formed on the semiconductor substrate.

[0142] See also Figure 14A and Figure 14B , Figure 14A This is a three-dimensional diagram from the first perspective of an embodiment of forming a source / drain in this application. Figure 14B This application Figure 14A Schematic diagram from the second perspective.

[0143] like Figure 14A and Figure 14B As shown, in Figure 13 On this basis, source / drain electrodes S / D are formed on the surface of the semiconductor substrate 100 exposed in the storage region A. That is, source / drain electrodes are formed on the semiconductor substrate on both sides of the gate structure 200 in the second direction. Metal silicide is formed on the source / drain electrodes to reduce contact resistance. That is, source / drain electrodes S / D are formed in the semiconductor substrate on both sides of the first trench in the second direction.

[0144] The drain electrode is located near the contact window, and the source electrode is located on the other side. In some embodiments, metal silicide may also be formed on the surface of the lead-out line 250 .

[0145] In this embodiment, by forming a second isolation layer on the control gate, the top surface of the control gate is lower than the top surface of the semiconductor substrate, thereby ensuring the distance between the control gate and the source / drain of the gate structure, which can effectively reduce leakage and breakdown between the control gate and the source / drain, and improve the performance of the storage device.

[0146] The present application also provides a transistor.

[0147] See also Figure 15A and Figure 15B , Figure 15A This is a schematic diagram of the first perspective structure of a transistor embodiment of the present application. Figure 15B This is a schematic structural diagram of a transistor embodiment from the second perspective in this application.

[0148] like Figure 15A and Figure 15B As shown, the transistor 20 includes a semiconductor substrate 100, a gate insulating layer 210 and a semi-floating gate 220 formed in the semiconductor substrate 100; an intergate dielectric layer 230 and a control gate 240 are formed in the semiconductor substrate 100 and are located above the semi-floating gate 220, wherein the control gate 240 is isolated from the semi-floating gate 220 by the intergate dielectric layer 230; a second isolation layer 400 is formed above the control gate 240; wherein the top surface of the control gate 240 is lower than the top surface of the semiconductor substrate 100.

[0149] Specifically, the transistor 20 includes a semiconductor substrate 100, in which a first trench 101 is formed; a gate insulating layer 210 and a semi-floating gate 220 are formed in the first trench 101; a second sub-trench 1021 is formed in the semiconductor substrate, the second sub-trench 1021 is located above the first trench 101, and the second sub-trench 1021 is connected to the first trench 101; an inter-gate dielectric layer 230 and a control gate 240 are formed in the second sub-trench 1021, a second isolation layer 400 is formed in the second sub-trench, and the second isolation layer 400 is formed above the control gate 240, wherein the top surface of the control gate 240 is lower than the top surface of the semiconductor substrate 100.

[0150] It can be understood that the second sub-trench 1021 is a part of the second trench 102 in the memory device; that is, the second trench 102 in the memory device includes multiple second sub-trenches 1021 in the first direction; that is, in the memory device, the control gates of multiple transistors in the same row in the first direction are connected.

[0151] In some embodiments, the semi-floating gate 220 may include a first gate 221 and a second gate 222. The first gate 221 is isolated from the semiconductor substrate 100 by the gate insulating layer 210, and the second gate 222 is in contact with the semiconductor substrate 100. In the first direction, the width of the second gate 222 is greater than the width of the first gate 221.

[0152] In some embodiments, the first isolation layer 300 is formed on the sidewalls of the second sub-trench 1021, that is, the first isolation layer 300 is formed on the sidewalls of the control gate 240. In the second direction, the width of the control gate 240 is smaller than the width of the semi-floating gate 220. By forming the first isolation layer 300 on both sides of the control gate, the width of the control gate in the second direction is smaller than the width of the semi-floating gate, thereby ensuring the distance between the control gate and the source / drain. This can effectively reduce leakage and breakdown between the control gate and the source / drain, thereby improving transistor performance.

[0153] Specifically, a gate insulating layer 210 is formed in the first trench 101, and a first gate 221 and a second gate 222 are formed on the gate insulating layer 210. The first gate 221 is isolated from the semiconductor substrate 100 by the gate insulating layer 210, while the second gate 222 is in contact with the semiconductor substrate 100 and the second gate 222 is in contact with the first gate 221. The semi-floating gate 220 includes the first gate 221 and the second gate 222. In the first direction, the width of the second gate 222 is greater than the width of the first gate 221. It is understood that the material of the first gate 221 and the material of the second gate 222 are different. For example, the first gate 221 is a polycrystalline material, and the second gate 222 is a single crystal material.

[0154] In some embodiments, multiple source / drain electrodes are further included, wherein source / drain electrodes S / D are formed in the active region C1 on both sides of the second direction of the gate structure 200; that is, the source / drain electrodes are formed in the semiconductor substrate on both sides of the second direction of the control gate 240; that is, multiple source / drain electrodes are formed in the semiconductor substrate on both sides of the second direction of the first trench; for example, the source electrode is S and the drain electrode is D.

[0155] In this embodiment, by forming a second isolation layer on the control gate, the top surface of the control gate is lower than the top surface of the semiconductor substrate, thereby ensuring the distance between the control gate and the source / drain, which can effectively reduce leakage and breakdown between the control gate and the source / drain, and improve the performance of the transistor.

[0156] The above description is only an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A memory device, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate is divided into storage areas; A plurality of first trenches are formed in the semiconductor substrate; A gate insulating layer and a semi-floating gate are formed in the first trench; A plurality of second trenches are formed in the semiconductor substrate, each of the second trenches is located above the plurality of first trenches, and each of the second trenches is connected to the plurality of first trenches in the same row in the first direction; An inter-gate dielectric layer and a control gate are formed in the second trench of the storage region; A second isolation layer is formed in the second trench, and the second isolation layer is located on the control gate, wherein a top surface of the control gate is lower than a top surface of the semiconductor substrate.

2. The memory device according to claim 1, wherein: The semiconductor substrate is further divided into a lead-out region, and the gate insulating layer and the semi-floating gate are formed in the first trench of the lead-out region; An inter-gate dielectric layer and a lead line are formed in the second trench of the lead area, wherein a top surface of the lead line is higher than a top surface of the semiconductor substrate of the storage area, and the lead line is connected to a plurality of the control gates in the same row in the first direction.

3. The memory device according to claim 2, wherein: Also includes: A first sub-dielectric layer is formed on the semiconductor substrate on both sides of the lead wires, and a top surface of the first sub-dielectric layer and a top surface of the lead wires are located in the same plane, wherein a plurality of the lead wires in the second direction are separated by the first sub-dielectric layer.

4. The memory device according to claim 1, wherein: Also includes: A first isolation layer is located on a sidewall of the second trench.

5. The memory device according to claim 1, wherein A plurality of isolation structures are formed in the semiconductor substrate, wherein the plurality of isolation structures extend along a second direction to divide the semiconductor substrate into a plurality of active regions.

6. The memory device according to claim 5, wherein: A plurality of the half-floating gates in the same row in the first direction are isolated by the isolation structure in the first trench, wherein a top surface of the half-floating gate is higher than a top surface of the isolation structure in the first trench.

7. The memory device according to claim 1, wherein: The semi-floating gate includes a first gate and a second gate; The first gate is isolated from the semiconductor substrate by the gate insulating layer, and the second gate is in contact with the semiconductor substrate. In the second direction, the width of the second gate is greater than the width of the first gate.

8. The memory device according to claim 1, wherein: Also includes: A plurality of source / drain electrodes are formed in the semiconductor substrate on both sides of the first trench in the second direction.

9. A method for manufacturing a memory device, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate is divided into storage areas; forming a plurality of first trenches and a plurality of second trenches, wherein the plurality of first trenches and the plurality of second trenches are located in the semiconductor substrate, each of the second trenches is located above the plurality of first trenches, and each of the second trenches is connected to the plurality of first trenches in the same row in a first direction; forming a gate insulating layer and a semi-floating gate in each of the first trenches; forming an inter-gate dielectric layer and a control gate in each of the second trenches; A second isolation layer is formed on the control gate of the second trench, wherein a top surface of the control gate is lower than a top surface of the semiconductor substrate.

10. The manufacturing method according to claim 9, characterized in that: The forming of the plurality of first trenches and the plurality of second trenches comprises: forming a plurality of third trenches in the semiconductor substrate, and forming an isolation structure in each of the third trenches, wherein the plurality of third trenches extend along the second direction; At least a portion of the isolation structure and the semiconductor substrate is removed to form a plurality of second trenches and a plurality of first trenches, wherein the plurality of first trenches in the same row in a first direction are isolated by the isolation structure.

11. The manufacturing method according to claim 9, characterized in that: The forming of a gate insulating layer and a semi-floating gate in each of the first trenches includes: forming the gate insulating layer on a sidewall of each of the first trenches; forming a first gate material in the first trench forming the gate insulating layer; removing at least a portion of the first gate material and at least a portion of the gate insulating layer to form a contact window, and forming a second gate material above the contact window; At least part of the first gate material and the second gate material is removed to form the semi-floating gate, with the remaining first gate material serving as the first gate and the remaining second gate material serving as the second gate. The semi-floating gate includes the first gate and the second gate.

12. The manufacturing method according to claim 11, characterized in that: When forming the half floating gate, the method further includes: At least a portion of the isolation structure exposed by the second trench is removed so that the top surface of the semi-floating gate is higher than the top surface of the isolation structure exposed by the second trench, wherein in a first direction, the width of the isolation structure exposed by the second trench is smaller than the width of the isolation structure in the semiconductor substrate, so that the width of the second gate formed in the first trench is larger than the width of the first gate.

13. The manufacturing method according to claim 9, characterized in that The forming of an inter-gate dielectric layer and a control gate in each of the second trenches includes: forming an inter-gate dielectric layer, wherein the inter-gate dielectric layer is in contact with the semi-floating gate; forming a third gate material to cover the inter-gate dielectric layer; The height of the third gate material in the storage region is reduced to form the control gate.

14. The manufacturing method according to claim 9, characterized in that The semiconductor substrate is further divided into a lead-out region, and the gate insulating layer and the semi-floating gate are formed in the first trench of the lead-out region; An inter-gate dielectric layer and a lead line are formed in the second trench of the lead area, wherein a top surface of the lead line is higher than a top surface of the semiconductor substrate of the storage area, and the lead line is connected to a plurality of the control gates in the same row in the first direction.

15. The manufacturing method according to claim 9, characterized in that Source / drain electrodes are formed in the semiconductor substrate on both sides of the first trench in the second direction.

16. The manufacturing method according to claim 9, characterized in that Before forming the inter-gate dielectric layer, a first isolation layer is formed on the sidewall of the second trench.

17. A transistor, characterized in that: include: semiconductor substrates; A gate insulating layer and a semi-floating gate are formed in the semiconductor substrate; An intergate dielectric layer and a control gate are formed in the semiconductor substrate and are located above the semi-floating gate, wherein the control gate is isolated from the semi-floating gate by the intergate dielectric layer; A second isolation layer is formed on the control gate; Wherein, the top surface of the control gate is lower than the top surface of the semiconductor substrate.

18. The transistor according to claim 17, wherein: The semi-floating gate includes a first gate and a second gate; The first gate is isolated from the semiconductor substrate by the gate insulating layer, the second gate is in contact with the semiconductor substrate, and the second gate is in contact with the first gate, wherein in a first direction, a width of the second gate is greater than a width of the first gate.

19. The transistor according to claim 17, wherein: Also includes: Source / drain electrodes are formed in the semiconductor substrate on both sides of the control gate in the second direction.

20. The transistor according to claim 17, wherein Also includes: A first isolation layer is formed on a sidewall of the control gate.

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