Semiconductor device and chip

Abstract

The invention provides a semiconductor device and a chip, relates to the technical field of semiconductors, and aims to solve the problem of poor performance of a semiconductor device. The semiconductor device comprises a substrate and a plurality of transistors; the plurality of transistors are located on one side of the substrate, and each transistor comprises a channel layer, a barrier layer and a grid electrode; the barrier layer is located on the side, away from the substrate, of the channel layer; the gate is located at one side of the barrier layer away from the substrate; wherein the plurality of transistors comprise a first type of transistors, the first type of transistors further comprise at least one cap layer, and the cap layer is located between the grid electrode and the barrier layer; the first type of transistors comprise a first transistor and a second transistor, and the total thickness of a cap layer in the first transistor is greater than the total thickness of a cap layer in the second transistor; the semiconductor device is applied to a chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a chip. Background Art

[0002] Gallium nitride semiconductor materials are known as third-generation semiconductor materials. Compared with first-generation semiconductor materials represented by silicon, they have higher bandgap width, critical breakdown field strength, and electron saturation drift velocity. They have significant advantages in high frequency, high voltage resistance, high power, and low on-resistance. They can be used as core components in various power conversion systems and have broad prospects in consumer electronics, fifth-generation mobile communication technology (5G) radio frequency, server and telecommunications applications. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor device and a chip, aiming to solve the problem of poor performance of semiconductor devices.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions: In one aspect, a semiconductor device is provided. The semiconductor device includes a substrate and multiple transistors. The multiple transistors are located on one side of the substrate, and the transistors include a channel layer, a barrier layer, and a gate. The barrier layer is located on a side of the channel layer away from the substrate; the gate is located on a side of the barrier layer away from the substrate. The multiple transistors include a first type of transistor, the first type of transistor also including at least one cap layer, the cap layer being located between the gate and the barrier layer. The first type of transistor includes a first transistor and a second transistor, and the total thickness of the cap layer in the first transistor is greater than the total thickness of the cap layer in the second transistor.

[0005] The total thickness of the cap layer in the first transistor in the semiconductor device provided by the above-mentioned embodiments of the present disclosure is greater than the total thickness of the cap layer in the second transistor, so that the energy band difference between the cap layer and the barrier layer in the first transistor is unequal to the energy band difference between the cap layer and the barrier layer in the second transistor, so that the concentration of the two-dimensional electron gas under the gate of the first transistor is unequal to the concentration of the two-dimensional electron gas under the gate of the second transistor, thereby making the concentration of the two-dimensional electron gas in at least two transistors different, and the threshold voltage of at least two transistors unequal. The threshold voltage requirements of the transistors required by power devices and logic devices are met, which is conducive to improving the performance of the semiconductor device.

[0006] In some embodiments, the number of the capping layers in the first transistor is greater than the number of the capping layers in the second transistor, the concentrations of p-type doping elements in any two capping layers in the first transistor are not equal, and each capping layer in the second transistor is made of the same material as one capping layer in the first transistor.

[0007] In some embodiments, the first transistor includes two capping layers, the second transistor includes one capping layer, and the material of the two capping layers in the first transistor both includes gallium nitride.

[0008] In some embodiments, along a direction from the transistor to the substrate, doping concentrations of the multiple capping layers in the first transistor decrease.

[0009] In some embodiments, one of the two capping layers in the first transistor that is away from the substrate is a first capping layer, and the other is a second capping layer; wherein the orthographic projection of the first capping layer on the substrate is located within the orthographic projection of the second capping layer on the substrate; or, the orthographic projection of the first capping layer on the substrate coincides with the orthographic projection of the second capping layer on the substrate; or, the first capping layer includes a first sub-portion and a second sub-portion, the first sub-portion is located on a side of the second sub-portion away from the substrate, the orthographic projection of the first sub-portion on the substrate is located within the orthographic projection of the second sub-portion on the substrate, and the orthographic projection of the second sub-portion on the substrate coincides with the orthographic projection of the second capping layer on the substrate.

[0010] In some embodiments, the first transistor and the second transistor include a capping layer, and the capping layer of the first transistor and the capping layer of the second transistor are made of the same material, and the thickness of the capping layer in the first transistor is greater than the thickness of the capping layer in the second transistor.

[0011] In some embodiments, the first type of transistor further includes a third transistor, the number of the capping layers in the third transistor is less than the number of the capping layers in the second transistor, and each capping layer in the third transistor is made of the same material as a capping layer in the second transistor.

[0012] In some embodiments, the plurality of transistors further include a second type of transistor, and the gate and the barrier layer are in contact with each other in the second type of transistor.

[0013] On the other hand, a chip is provided, comprising the semiconductor device described in any one of the above embodiments.

[0014] It can be understood that the beneficial effects that can be achieved by the chip provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure.

[0016] Figure 1 FIG. 1 is a schematic diagram of the structure of an electronic device according to some embodiments Figure 1 ; Figure 2 FIG. 1 is a schematic diagram of the structure of an electronic device according to some embodiments Figure 2 ; Figure 3 A cross-sectional view of a semiconductor device according to some embodiments Figure 1 ; Figure 4 A cross-sectional view of a semiconductor device according to some embodiments Figure 2 ; Figure 5 A cross-sectional view of a semiconductor device according to some embodiments Figure 3 ; Figure 6 A cross-sectional view of a semiconductor device according to some embodiments Figure 4 ; Figure 7 A cross-sectional view of a semiconductor device according to some embodiments Figure 5 ; Figure 8 The process of the method for manufacturing a semiconductor device according to some embodiments Figure 1 ; Figure 9 The process of the method for manufacturing a semiconductor device according to some embodiments Figure 2 ; Figure 10 for Figure 9 A schematic structural diagram of a semiconductor device corresponding to step S10 in the flowchart in FIG; Figure 11 for Figure 9 A schematic structural diagram of a semiconductor device corresponding to step S20 in the flowchart in FIG; Figure 12 for Figure 9 The structure of the semiconductor device corresponding to step S30 in the flowchart is shown in FIG. Figure 1 ; Figure 13 for Figure 9 A schematic structural diagram of a semiconductor device corresponding to step S40 in the flowchart in FIG; Figure 14 for Figure 9 A schematic structural diagram of a semiconductor device corresponding to step S50 in the flowchart in FIG; Figure 15 for Figure 9 The structure of the semiconductor device corresponding to step S30 in the flowchart is shown in FIG. Figure 2 ; Figure 16 for Figure 9 The structure of the semiconductor device corresponding to step S30 in the flowchart is shown in FIG. Figure 3 . DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0018] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0019] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0020] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0021] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0022] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0023] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0024] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0025] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0026] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0027] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0028] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0029] A semiconductor is a material with electrical conductivity between that of a conductor and an insulator at room temperature. Semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor free of impurities and defects, with equal electron and hole concentrations, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an extrinsic semiconductor. When the impurities doped into an impurity semiconductor can provide a certain concentration of carriers (such as holes; impurity semiconductors doped with hole-providing impurities (such as magnesium) are also called hole-type semiconductors or P (positive)-type semiconductors), they can improve the conductivity of the intrinsic semiconductor. Generally, a higher carrier concentration results in a lower resistivity and better conductivity. In the embodiments of this application, such impurity semiconductors are also referred to as conductive semiconductors. For example, the impurities doped are magnesium, zinc, beryllium, or carbon. Furthermore, when the impurities doped into the impurity semiconductor can compensate for the impurity semiconductor, the donor electrons are just sufficient to fill the acceptor energy levels but are unable to contribute electrons or holes to the conduction and valence bands, resulting in a wide-bandgap semiconductor material with a resistivity similar to that of an insulator.

[0030] like Figure 1 As shown, some embodiments of the present disclosure provide an electronic device 1000. The electronic device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images. The embodiments of the present application do not impose any particular restrictions on the specific form of the electronic device 1000.

[0031] For example, the electronic device 1000 may be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, or an aircraft display.

[0032] Alternatively, illustratively, the electronic device may also be a communication device, a radar device, a radio navigation device, or the like.

[0033] Alternatively, for example, the electronic device 1000 may also be a device or component with signal receiving / transmitting functions in equipment such as an amplifier, a modulator, a base station, or a radar.

[0034] The following uses the electronic device 1000 as an example of an electronic device having a power conversion function to schematically illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited to this, and any other electronic device can also be considered as long as the same technical concept is applied.

[0035] like Figure 2 As shown, the electronic device 1000 includes a chip 100 and a circuit board 200. The chip 100 and the circuit board 200 are electrically connected, and the circuit board 200 is configured to provide power and / or signals to the chip 100.

[0036] Exemplarily, the circuit board 200 may include a printed circuit board (PCB) or the like.

[0037] Illustratively, chip 100 may include a processor chip. For example, the processor chip may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or any conventional processor.

[0038] In some embodiments, as Figures 3 to 7 As shown, the chip 100 includes a semiconductor device 10, and the semiconductor device 10 includes a substrate 11 and a plurality of transistors 12. For example, the material of the substrate 11 may include at least one of silicon (Si), silicon carbide (SiC), sapphire, and the like.

[0039] like Figures 3 to 7 As shown, a plurality of transistors 12 are located on one side of a substrate 11 . The transistor 12 includes a channel layer 121 , a barrier layer 122 , a gate 123 , a source 124 , and a drain 125 .

[0040] Exemplarily, the material of the channel layer 121 may include gallium nitride (GaN).

[0041] As Figures 3 to 7 shown, the barrier layer 122 is located on the side of the channel layer 121 away from the substrate 11.

[0042] Exemplarily, the material of the barrier layer 122 may include nitrides of various different components, such as Al x In y Ga (1-x-y) N, at least one of (0 < x ≤ 1, 0 ≤ y ≤ 1). For example, the material of the barrier layer 122 may include nitrides of various different components, such as Al x In y Ga (1-x-y) N. Again, for example, the material of the barrier layer 122 may include multiple of nitrides of various different components, such as Al x In y Ga (1-x-y) N.

[0043] On this basis, the band gap of the material of the barrier layer 122 (e.g., aluminum gallium nitride (AlGaN)) is greater than the band gap of the material of the channel layer 121 (e.g., gallium nitride (GaN)). A heterojunction structure will be formed at the connection interface between the barrier layer 122 and the channel layer 121. Since nitride semiconductors are usually in a hexagonal wurtzite structure, nitride semiconductors have spontaneous polarization effects and piezoelectric polarization effects. The polarization effects can form a two-dimensional electron gas with a high concentration at the heterojunction interface, which is beneficial to improving the electron mobility and the performance of the transistor 12.

[0044] The above-mentioned band gap refers to: in a solid, the energy of electrons cannot be continuously valued, but forms some discontinuous energy bands, and the energy difference between the conduction band and the valence band is the band gap. Specifically, for a bound electron to become a free electron or a hole, it must obtain enough energy to jump from the valence band to the conduction band, and the minimum value of this energy is the band gap.

[0045] As Figures 3 to 7 shown, the gate 123 is located on the side of the barrier layer 122 away from the substrate 11. The gate 123 controls the concentration of the two-dimensional electron gas in the channel layer 121 through the field effect, thereby controlling the current in the transistor 12.

[0046] Exemplarily, the material of gate 123 may include at least one of a conductive material such as aluminum (Al), nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN). For example, the material of gate 123 may include one of a conductive material such as Al, Ni, Au, titanium, and TiN. For another example, the material of gate 123 may include multiple conductive materials such as Al, Ni, Au, titanium, and TiN. For example, gate 123 may include a stacked layer of TiN, Al, and TiN.

[0047] like Figures 3 to 7 As shown, the source 124 and the drain 125 are located on opposite sides of the gate 123 in the semiconductor device 10 , and are both disposed on a side of the barrier layer 122 away from the substrate 11 .

[0048] Exemplarily, the material of the source electrode 124 may include at least one of nickel, gold, titanium, and titanium nitride. For example, the material of the source electrode 124 may include one of a conductive material such as aluminum, nickel, gold, titanium, and titanium nitride. For another example, the material of the source electrode 124 may include multiple conductive materials such as aluminum, nickel, gold, titanium, and titanium nitride. For example, the source electrode 124 includes titanium, aluminum, titanium, and titanium nitride arranged in a stacked manner.

[0049] For example, the material of the drain electrode 125 may be the same as that of the source electrode 124 .

[0050] When a two-dimensional electron gas is formed in the semiconductor device 10, the source 124 and the drain 125 in the semiconductor device 10 can form an ohmic contact with the two-dimensional electron gas, which can reduce the contact resistance between the source 124 and the two-dimensional electron gas, as well as the contact resistance between the drain 125 and the two-dimensional electron gas. A low-impedance current channel can be formed between the source 124, the drain 125 and the two-dimensional electron gas in the semiconductor device 10, allowing current to flow smoothly, which is beneficial to improving the performance of the transistor 12.

[0051] In related technologies, semiconductor devices have poor performance. The inventors discovered that multiple transistors in a semiconductor device are used to form different devices, and these devices have different requirements for transistor threshold voltages. For example, multiple transistors in a semiconductor device are used to form both power devices and logic devices. Power devices require transistors with high threshold voltages, while logic devices do not. However, if the threshold voltages of the multiple transistors in the semiconductor device are equal, the threshold voltage of the transistor required by at least one of the power device and the logic device may not meet the requirement, resulting in poor performance of the semiconductor device.

[0052] In order to solve the above technical problems, Figures 3 to 7As shown, the plurality of transistors 12 include a first type of transistor 12A. The first type of transistor 12A further includes at least one capping layer 126, which is located between the gate 123 and the barrier layer 122. The capping layer 126 and the barrier layer 122 have an energy band difference (e.g., a conduction band difference). This energy band difference between the capping layer 126 and the barrier layer 122 can regulate the concentration of the two-dimensional electron gas near the interface between the barrier layer 122 and the channel layer 121, thereby changing the threshold voltage of the transistor 12.

[0053] On this basis, the first type of transistor 12A includes a first transistor 12A1 and a second transistor 12A2, and the total thickness of the cap layer in the first transistor 12A1 is greater than the total thickness of the cap layer 126 in the second transistor 12A2. This allows the energy band difference between the cap layer 126 and the barrier layer 122 in the first transistor 12A1 to be unequal to the energy band difference between the cap layer 126 and the barrier layer 122 in the second transistor 12A2, thereby causing the concentration of the two-dimensional electron gas below the gate 123 of the first transistor 12A1 to be unequal to the concentration of the two-dimensional electron gas below the gate 123 of the second transistor 12A2. Consequently, the two-dimensional electron gas concentrations in at least two transistors 12 differ, resulting in unequal threshold voltages for at least two transistors 12. This ensures that the threshold voltages of the transistors 12 required for both power devices and logic devices meet the requirements, thereby improving the performance of the semiconductor device 10.

[0054] In some embodiments, as Figures 3 to 6 As shown, the number of capping layers 126 in the first transistor 12A1 is greater than the number of capping layers 126 in the second transistor 12A2, the concentrations of p-type doping elements in any two capping layers 126 in the first transistor 12A1 are not equal, and each capping layer 126 in the second transistor 12A2 is made of the same material as a capping layer 126 in the first transistor 12A1.

[0055] With this arrangement, the total thickness of the cap layer 126 in the first transistor 12A1 can be greater than the total thickness of the cap layer 126 in the second transistor 12A2, so that the concentrations of the two-dimensional electron gas in at least two transistors 12 are different, and the threshold voltages of at least two transistors 12 are not equal. The threshold voltages of the transistors 12 required by power devices and logic devices meet the requirements, which is beneficial to improving the performance of the semiconductor device 10.

[0056] In some embodiments, as Figures 3 to 5 As shown, the first transistor 12A1 includes two capping layers 126 , and the second transistor 12A2 includes one capping layer 126 . Both capping layers 126 in the first transistor 12A1 include gallium nitride.

[0057] In some examples, the first transistor 12A1 includes two capping layers 126, both of which include doped semiconductor materials, and the doping concentration of one of them is less than or equal to 1×10 18 cm -3 , and the doping concentration of the other one is 1×10 18 cm -3 ~10×10 19 cm -3 .

[0058] Exemplarily, the doped semiconductor material includes a semiconductor material doped with elements such as iron (Fe) and magnesium (Mg). For example, the two capping layers 126 included in the first transistor 12A1 both include a semiconductor material doped with magnesium.

[0059] In some embodiments, as Figure 3 As shown, one of the two capping layers 126 in the first transistor 12A1, which is away from the substrate 11, is a first capping layer 1261, and the other is a second capping layer 1262. The orthographic projection of the first capping layer 1261 on the substrate 11 coincides with the orthographic projection of the second capping layer 1262 on the substrate 11.

[0060] In other embodiments, Figure 4 As shown, one of the two capping layers 126 in the first transistor 12A1 is away from the substrate 11 and is the first capping layer 1261, while the other is the second capping layer 1262. The orthographic projection of the first capping layer 1261 on the substrate 11 is within the orthographic projection of the second capping layer 1262 on the substrate 11.

[0061] In some other embodiments, Figure 5 As shown, the first capping layer 1261 includes a first sub-portion 12611 and a second sub-portion 12612. The first sub-portion 12611 is located on the side of the second sub-portion 12612 away from the substrate 11. The orthographic projection of the first sub-portion 12611 on the substrate 11 is located within the orthographic projection of the second sub-portion 12612 on the substrate 11. The orthographic projection of the second sub-portion 12612 on the substrate 11 coincides with the orthographic projection of the second capping layer 1262 on the substrate 11.

[0062] In some embodiments, the first type transistor 12A further includes an etch stop layer, and the etch stop layer is located between the first capping layer 1261 and the second capping layer 1262 .

[0063] In some embodiments, the doping concentration of the multilayer capping layer 126 in the first transistor 12A1 is reduced along the direction of the transistor 12 pointing to the substrate 11, which can make the difference between the threshold voltage of the first transistor 12A1 and the threshold voltage of the second transistor 12A2 larger, further meeting the needs of each device in the semiconductor device, and helping to further improve the performance of the semiconductor device 10.

[0064] The doping concentration of the multi-layer capping layer 126 in the first transistor 12A1 is reduced layer by layer.

[0065] In some embodiments, as Figure 6 As shown, the first type of transistor 12A also includes a third transistor 12A3. The number of capping layers 126 in the third transistor 12A3 is less than the number of capping layers 126 in the second transistor 12A2. Each capping layer 126 in the third transistor 12A3 is made of the same material as a capping layer 126 in the second transistor 12A2.

[0066] By configuring in this manner, the total thickness of the cap layer 126 in the second transistor 12A2 can be greater than the total thickness of the cap layer 126 in the third transistor 12A3, and the concentration of the two-dimensional electron gas in the second transistor 12A2 is unequal to the concentration of the two-dimensional electron gas in the third transistor 12A3, thereby making the concentrations of the two-dimensional electron gas in at least three transistors 12 unequal, and the threshold voltages of at least three transistors 12 unequal, which is beneficial to further expanding the scope of application of the semiconductor device 10.

[0067] In some examples, such as Figure 6 As shown, the first transistor 12A1 includes three capping layers 126 , that is, the first transistor 12A1 includes a first capping layer 1261 , a second capping layer 1262 and a third capping layer 1263 that are stacked.

[0068] The second transistor 12A2 includes two capping layers 126 , namely, a second capping layer 1262 and a third capping layer 1263 . The third transistor 12A3 includes one capping layer 126 , namely, a third capping layer 1263 .

[0069] In some embodiments, as Figure 7 As shown, the first transistor 12A1 and the second transistor 12A2 include a capping layer 126, and the capping layer 126 of the first transistor 12A1 and the capping layer 126 of the second transistor 12A2 are made of the same material. The thickness of the capping layer 126 of the first transistor 12A1 is greater than the thickness of the capping layer 126 of the second transistor 12A2.

[0070] In this manner, the total thickness of the cap layer 126 in the first transistor 12A1 can be greater than the total thickness of the cap layer 126 in the second transistor 12A2. This allows the concentrations of the two-dimensional electron gas in at least two transistors 12 to be different, resulting in unequal threshold voltages for at least two transistors 12. This ensures that the threshold voltages of the transistors 12 required for both power devices and logic devices meet the requirements, thereby improving the performance of the semiconductor device 10.

[0071] In some embodiments, as Figure 3 、 Figure 4 、 Figure 5 and Figure 7 As shown, the plurality of transistors 12 further include a second type of transistor 12B, in which the gate 123 of the second type of transistor 12B is in contact with the barrier layer 122 , that is, the second type of transistor does not include the cap layer 126 .

[0072] In this arrangement, the threshold voltages of the first type of transistor 12A and the second type of transistor 12B are different, which can make the concentrations of the two-dimensional electron gas in the at least three transistors 12 unequal, thereby making the threshold voltages of the at least three transistors 12 unequal. This helps further expand the scope of application of the semiconductor device 10.

[0073] In some embodiments, as Figures 3 to 7 As shown, the semiconductor device 10 further includes an insertion layer 13 , which is located between the barrier layer and the substrate.

[0074] In this manner, on the one hand, when there is a lattice constant mismatch or a difference in thermal expansion coefficient between the substrate 11 and the barrier layer 122, the insertion layer 13 can alleviate the stress caused by the lattice constant mismatch or the difference in thermal expansion coefficient between the substrate 11 and the barrier layer 122, thereby reducing the impact of the stress on the performance of the semiconductor device 10. On the other hand, the insertion layer 13 can improve the interface characteristics between the substrate 11 and the barrier layer 122, reduce interface defects between the substrate 11 and the barrier layer 122, and thus improve the stability and reliability of the semiconductor device 10.

[0075] For example, the material of the insertion layer 13 may include aluminum nitride (AIN) or the like.

[0076] In some embodiments, the semiconductor device may be a wafer.

[0077] Some embodiments of the present disclosure also provide a method for preparing a semiconductor, such as Figure 8 As shown, the preparation method includes S100.

[0078] S100 , forming a plurality of transistors 12 on one side of a substrate 11 .

[0079] In the above steps, the transistor 12 includes a channel layer 121, a barrier layer 122, a gate 123, and at least one capping layer 126. The barrier layer 122 is located on a side of the channel layer 121 away from the substrate 11. The gate 123 is located on a side of the barrier layer 122 away from the substrate 11. The multiple transistors 12 include a first type of transistor 12A, which further includes at least one capping layer 126. The at least one capping layer 126 is located between the gate 123 and the barrier layer 122. The first type of transistor 12A includes a first transistor 12A1 and a second transistor 12A2. The total thickness of the capping layer 126 in the first transistor 12A1 is greater than the total thickness of the capping layer 126 in the second transistor 12A2.

[0080] In some embodiments, as Figure 9 As shown, S100 includes S10 to S50.

[0081] like Figure 10 As shown, S10 , a channel layer film 1 , a barrier layer film 2 , a second initial capping layer 3 and a first initial capping layer 4 are stacked and formed on one side of the substrate 11 along a direction perpendicular to the substrate 11 and away from the substrate 11 .

[0082] In the above steps, the channel layer film 1 includes the channel layers 121 of the plurality of transistors 12 , and the barrier layer film 2 includes the plurality of barrier layers 122 .

[0083] For example, the channel layer film 1, the barrier layer film 2, the second initial capping layer 3 and the first initial capping layer 4 can be formed by processes such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or physical vapor deposition (PVD).

[0084] In the process of forming the second initial capping layer 3 and the first initial capping layer 4, the doping concentrations of the second initial capping layer 3 and the first initial capping layer 4 may be equal or unequal. In the process of making the doping concentrations of the second initial capping layer 3 and the first initial capping layer 4 equal, the annealing temperatures of the second initial capping layer 3 and the first initial capping layer 4 are unequal, so that the effective p-type doping element concentrations of the second initial capping layer 3 and the first initial capping layer 4 are unequal.

[0085] like Figure 11 As shown, S20 , the first initial capping layer 4 outside the first predetermined area Y1 is removed to form a first capping layer 1261 for the first transistor 12A1 .

[0086] For example, the first initial capping layer 4 outside the first predetermined region Y1 can be removed by a photolithography process to form the first capping layer 1261 of the first transistor 12A1. When removing the first initial capping layer 4 outside the first predetermined region Y1 by the photolithography process, a mixed gas such as Cl2 / ClB3 can be used as an etching gas. The first predetermined region Y1 is a region pre-determined for forming the first capping layer 1261 of the first transistor 12A1.

[0087] like Figure 12 As shown, S30 , the second initial capping layer 3 outside the second preset area Y2 and the third preset area Y3 is removed to form the second capping layer 1262 of the first transistor 12A1 and the second capping layer 1262 of the second transistor 12A2 .

[0088] For example, the second initial capping layer 3 outside the second preset region Y2 and the third preset region Y3 can be removed by a photolithography process to form the second capping layer 1262 of the first transistor 12A1 and the second capping layer 1262 of the second transistor 12A2. When removing the second initial capping layer 3 outside the second preset region Y2 and the third preset region Y3 by a photolithography process, a mixed gas such as Cl2 / ClB3 can be used as an etching gas. The second preset region Y2 is a region pre-set for forming the second capping layer 1262 of the first transistor 12A1. The third preset region Y3 is a region pre-set for forming the second capping layer 1262 of the second transistor 12A2.

[0089] like Figure 13 As shown, S40 , a source electrode 124 and a drain electrode 125 are formed.

[0090] For example, the source and drain metals may be grown by a sputtering process, and the source and drain metals outside the source and drain regions may be removed by a dry etching process to form the source 124 and the drain 125 .

[0091] For example, a portion of the barrier layer film 2 in the source region and the drain region can be removed by a photolithography process to reduce the thickness of the barrier layer film 2 to facilitate the formation of the source electrode 124 and the drain electrode 125. When removing a portion of the barrier layer film 2 in the source region and the drain region by a photolithography process, a mixed gas such as Cl2 / ClB3 can be used as an etching gas.

[0092] like Figure 14 As shown, S50 , a gate 123 is formed on a side of the first capping layer 1261 and the second capping layer 1262 away from the substrate 11 .

[0093] For example, the gate metal may be grown by a sputtering process, and the gate metal outside the gate region may be removed by a dry etching process to form the gate 123 .

[0094] In some embodiments, as Figure 12 As shown, during the process of forming the second capping layer 1262, the orthographic projection of the second preset area Y2 on the substrate coincides with the orthographic projection of the first preset area Y1 on the substrate. At this time, the orthographic projection of the first capping layer 1261 on the substrate 11 coincides with the orthographic projection of the second capping layer 1262 on the substrate 11. Alternatively, as Figure 15 The orthographic projection of the second preset area Y2 on the substrate covers the orthographic projection of the first preset area Y1 on the substrate and is spaced from the boundary of the orthographic projection of the first preset area Y1 on the substrate. In this case, the orthographic projection of the first capping layer 1261 on the substrate 11 is within the orthographic projection of the second capping layer 1262 on the substrate 11. Alternatively, as Figure 16 As shown, the orthographic projection of the second preset area Y2 on the substrate is located within the overlap of the orthographic projection of the first preset area Y1 on the substrate. At this time, the first cap layer 1261 includes a first sub-portion 12611 and a second sub-portion 12612. The first sub-portion 12611 is located on the side of the second sub-portion 12612 away from the substrate 11. The orthographic projection of the first sub-portion 12611 on the substrate 11 is located within the orthographic projection of the second sub-portion 12612 on the substrate 11. The orthographic projection of the second sub-portion 12612 on the substrate 11 coincides with the orthographic projection of the second cap layer 1262 on the substrate 11.

[0095] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0096] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of transistors are located on one side of the substrate, wherein the transistors include: channel layer; a barrier layer, located on a side of the channel layer away from the substrate; a gate, located on a side of the barrier layer away from the substrate; Among them, the multiple transistors include a first type of transistor, the first type of transistor also includes at least one capping layer, the capping layer is located between the gate and the barrier layer; the first type of transistor includes a first transistor and a second transistor, the total thickness of the capping layer in the first transistor is greater than the total thickness of the capping layer in the second transistor.

2. The semiconductor device according to claim 1, wherein The number of the capping layers in the first transistor is greater than the number of the capping layers in the second transistor, the concentrations of p-type doping elements in any two capping layers in the first transistor are not equal, and each capping layer in the second transistor is made of the same material as one capping layer in the first transistor.

3. The semiconductor device according to claim 2, wherein The first transistor includes two capping layers, the second transistor includes one capping layer, and the material of the two capping layers in the first transistor both includes gallium nitride.

4. The semiconductor device according to claim 3, wherein One of the two capping layers in the first transistor that is away from the substrate is a first capping layer, and the other is a second capping layer; In which, the orthographic projection of the first capping layer on the substrate is located within the orthographic projection of the second capping layer on the substrate; or, the orthographic projection of the first capping layer on the substrate coincides with the orthographic projection of the second capping layer on the substrate; or, the first capping layer includes a first sub-portion and a second sub-portion, the first sub-portion is located on the side of the second sub-portion away from the substrate, the orthographic projection of the first sub-portion on the substrate is located within the orthographic projection of the second sub-portion on the substrate, and the orthographic projection of the second sub-portion on the substrate coincides with the orthographic projection of the second capping layer on the substrate.

5. The semiconductor device according to claim 2, wherein Along a direction from the transistor to the substrate, the doping concentrations of the multiple capping layers in the first transistor decrease.

6. The semiconductor device according to claim 2, wherein The first type of transistor also includes a third transistor, the number of the capping layers in the third transistor is less than the number of the capping layers in the second transistor, and each capping layer in the third transistor is made of the same material as a capping layer in the second transistor.

7. The semiconductor device according to claim 1, wherein The first transistor and the second transistor include a capping layer, and the capping layer of the first transistor and the capping layer of the second transistor are made of the same material. The thickness of the capping layer in the first transistor is greater than the thickness of the capping layer in the second transistor.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The plurality of transistors further include a second type of transistor, wherein the gate and the barrier layer are in contact with each other in the second type of transistor.

9. A chip, characterized in that: The semiconductor device comprises the semiconductor device according to any one of claims 1 to 8.

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