Semiconductor device and manufacturing method thereof

Abstract

According to the semiconductor device and the manufacturing method thereof provided by the invention, a crystal boundary in a shared polycrystalline silicon gate is reduced in a mode of forming the shared polycrystalline silicon gate with the crystal grain size of 10-100nm; therefore, the problem that n-type ions in the part, located in the nMOS region, of the shared polycrystalline silicon grid electrode and p-type ions in the part, located in the pMOS region, of the shared polycrystalline silicon grid electrode are mutually diffused at the boundary between the nMOS region and the pMOS region is solved, the boundary problem between an nMOS transistor and a pMOS transistor is solved, and the problem that a semiconductor device and part of elements in the semiconductor device fail is solved. Moreover, the problem that n-type ions in the part, located in the nMOS region, of the shared polycrystalline silicon grid are diffused into the shared polycrystalline silicon grid in the pMOS region along the shared polycrystalline silicon grid is inhibited, so that p-type ions of the shared polycrystalline silicon grid in the nMOS region can be prevented from being partially neutralized by the diffused n-type ions; and therefore, the problems of mismatch and threshold voltage offset of the pMOS transistor can be improved, and the problem of failure of the minimum working voltage of the device can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The CMOS (Complementary Metal-Oxide-Semiconductor) process involves fabricating both nMOS and pMOS transistors on the same semiconductor substrate, creating CMOS integrated circuits. CMOS integrated circuits offer numerous advantages, including low power consumption, high speed, strong anti-interference capabilities, and high integration. They have become the mainstream manufacturing technology for semiconductor devices such as memory (e.g., static random access memory (SRAM), microcontroller units (MCUs), ring oscillators, and logic devices.

[0003] However, as CMOS process nodes gradually shrink to 65nm and below (for example, 40nm), the size of semiconductor devices is getting smaller and smaller, the density of internal components is getting higher and higher, and the spacing between nMOS transistors and pMOS transistors is decreasing accordingly. The boundary (np boundary, hereinafter referred to as np boundary) problem between nMOS transistors and pMOS transistors is also becoming increasingly prominent, which can easily cause some internal circuits to fail, and in severe cases, even cause the entire semiconductor device to fail.

[0004] Please refer to Figure 1Taking SRAM as an example, its minimum storage unit (i.e., one bit) is composed of multiple nMOS transistors and multiple pMOS transistors formed on the same substrate. The nMOS transistors are manufactured based on the p-well (p Well) 100pw, and the pMOS transistors are manufactured based on the n-well (n Well) 100nw. Adjacent nMOS transistors and pMOS transistors are isolated by an element isolation structure (such as a shallow trench isolation structure STI) 101, and usually share the same polysilicon gate 103 (hereinafter referred to as "shared polysilicon gate", with a gate oxide layer 102 sandwiched between it and the substrate). The shared polysilicon gate 103 extends continuously from above the p-well 100pw through the element isolation structure 101 to above the n-well 100nw. The portion of the shared polysilicon gate 103 located above the p-well 100pw is doped with n-type during the source / drain ion implantation (i.e., nSD implant, in which n-type ions such as phosphorus ions P+ and arsenic ions As+ are implanted) of the nMOS transistor, thereby serving as the n-type polysilicon gate (i.e., n+ poly gate) of the nMOS transistor. The portion of the shared polysilicon gate 103 located above the n-well 100nw is doped with p-type during the source / drain ion implantation (i.e., pSD implant, in which p-type ions such as boron ions B+, aluminum ions Al+, and gallium ions Ga+ are implanted), thereby serving as the p-type polysilicon gate (i.e., p+ polygate) of the pMOS transistor.

[0005] The inventors conducted PFA (Probability of Failure Analysis) analysis on the failed bits of SRAM and TEM (Transmission Voltage Scaling) on ​​the scattered points of the threshold voltage (Vt) of the pMOS transistor. Analysis using a transmission electron microscope (TEM) revealed that SRAM has a high transistor density. As transistor size and the overall size of the SRAM shrink, n-type ions (such as phosphorus ions P+ and arsenic ions As+) in the n-type polysilicon gate at the n-p boundary in the failed bit (i.e., the portion of the shared polysilicon gate 103 located in the nMOS transistor area) diffuse across the n-p boundary along the shared polysilicon gate 103 and into the p-type polysilicon gate (i.e., the portion of the shared polysilicon gate 103 located in the pMOS transistor area) through thermal diffusion. These ions then react with p-type ions (such as boron ions B+ and gallium ions Ga+) doped in the p-type polysilicon gate, leading to performance degradation of the pMOS transistor (e.g., changes in work function, increased threshold voltage Vt shift, failure of the minimum operating voltage Vmin, and increased pMOS transistor mismatch), thus causing failure of the corresponding bit or even the entire SRAM. Summary of the Invention

[0006] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the boundary problem between nMOS transistors and pMOS transistors, reduce pMOS transistor mismatch and threshold voltage offset, and avoid failure of part or all circuits inside the device.

[0007] To achieve the above object, the present invention provides a semiconductor device comprising:

[0008] a substrate having an element isolation structure and at least one nMOS region and at least one pMOS region defined by the element isolation structure;

[0009] a shared polysilicon gate, formed above the adjacent nMOS region and the pMOS region and the element isolation structure between the boundaries thereof, with a gate oxide layer sandwiched between the top surface of the substrate so as to be shared by the adjacent nMOS region and the pMOS region;

[0010] Wherein, the grain size of the shared polysilicon gate is 10nm-100nm.

[0011] Optionally, a portion of the shared polysilicon gate located above the pMOS region is p-type doped, and a portion of the shared polysilicon gate located above the nMOS region is n-type doped.

[0012] Optionally, a p-type source and drain region is formed in the substrate of the pMOS region, and part or all of the p-type ions doped in the shared polysilicon gate and the p-type ions doped in the p-type source and drain region are derived from the same ion implantation process; and / or, an n-type source and drain region is formed in the nMOS region, and part or all of the n-type ions doped in the shared polysilicon gate and the n-type ions doped in the n-type source and drain region are derived from the same ion implantation process.

[0013] Optionally, an n-well is formed in the substrate of the pMOS region, and the p-type source and drain regions are formed in the surface layer of the n-well; and / or a p-well is formed in the substrate of the nMOS region, and the n-type source and drain regions are formed in the surface layer of the p-well.

[0014] Optionally, the element isolation structure has at least one of the following features:

[0015] (1) The element isolation structure is a shallow trench isolation structure;

[0016] (2) The top surface of the element isolation structure is higher than the top surface of the substrate;

[0017] (3) The top surface of the element isolation structure has an uneven pattern.

[0018] Optionally, the semiconductor device includes at least one of an SRAM, a ring oscillator, a microcontroller, and a logic device.

[0019] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which includes:

[0020] Providing a substrate, forming an element isolation structure in the substrate to define at least one nMOS region and at least one pMOS region;

[0021] forming a gate oxide layer on the substrate and covering the gate oxide layer and the element isolation structure with a polysilicon layer;

[0022] The polysilicon layer is etched to form at least a shared polysilicon gate. The shared polysilicon gate is formed above the adjacent nMOS region and the pMOS region and the element isolation structure between the boundaries thereof so as to be shared by the adjacent nMOS region and the pMOS region, and the grain size of the shared polysilicon gate is 10nm to 100nm.

[0023] Optionally, the manufacturing method further includes at least one of the following features:

[0024] (1) directly depositing the polysilicon layer on the gate oxide layer and the element isolation structure by low-temperature chemical vapor deposition, low-pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma chemical vapor deposition, or atomic layer deposition, or first depositing an amorphous silicon layer on the gate oxide layer and the element isolation structure, and then converting the amorphous silicon layer into the polysilicon layer by a corresponding crystallization process;

[0025] (2) controlling the grain size of the deposited polysilicon layer by increasing the deposition temperature and / or decreasing the deposition rate;

[0026] (3) The deposition temperature of the polysilicon layer or the amorphous silicon layer is 600° C. to 700° C.;

[0027] (4) after covering the polysilicon layer and before etching the polysilicon layer, performing a thermal annealing treatment on the polysilicon layer in a nitrogen atmosphere;

[0028] (5) after covering the polysilicon layer and before etching the polysilicon layer, pre-doping the portion of the polysilicon layer located above the nMOS region with n-type ions, and / or pre-doping the portion of the polysilicon layer located above the pMOS region with p-type ions;

[0029] (6) After forming the element isolation structure in the substrate and before forming a gate oxide layer on the substrate, the substrate is further subjected to well ion implantation to form an n-well in the substrate of the pMOS region and / or to form a p-well in the substrate of the nMOS region.

[0030] Optionally, the process of thermal annealing the polysilicon layer includes at least one of a furnace annealing process, a rapid thermal annealing process and a laser annealing process; and / or the temperature of thermal annealing the polysilicon layer is 600°C to 1250°C.

[0031] Optionally, the manufacturing method, after etching the polysilicon layer to at least form the shared polysilicon gate, further comprises:

[0032] Under the shielding of the remaining polysilicon layer including the shared polysilicon gate, etching the gate oxide layer to the top surface of the substrate to form a corresponding gate structure;

[0033] forming sidewall spacers on sidewalls of the gate structure;

[0034] Using the gate structure and the sidewall as masks, source and drain ion implantation is performed on the substrate and the remaining polysilicon layer to form corresponding source and drain regions in the substrate, wherein the source and drain ions implanted into the nMOS region are n-type ions to form n-type source and drain regions in the substrate of the nMOS region, and the portion of the shared polysilicon gate located in the nMOS region is n-doped, and the source and drain ions implanted into the pMOS region are p-type ions to form p-type source and drain regions in the substrate of the pMOS region, and the portion of the shared polysilicon gate located in the pMOS region is p-doped.

[0035] Optionally, the step of forming the element isolation structure in the substrate includes:

[0036] forming a pad oxide layer on the substrate and depositing a hard mask layer;

[0037] etching the hard mask layer, the pad oxide layer, and the substrate to form an isolation trench;

[0038] depositing a dielectric material to fill the isolation trench and planarizing a top surface of the dielectric material to a top surface of the hard mask layer;

[0039] The hard mask layer and the pad oxide layer are removed by etching to form the element isolation structure with a top surface higher than a top surface of the substrate.

[0040] Optionally, when etching and removing the pad oxide layer, over-etching is generated, and the over-etching etches the exposed top surface and sidewalls of the element isolation structure to form side grooves at top corners in the isolation trench;

[0041] And / or, after etching away the hard mask layer and the pad oxide layer to form the element isolation structure, at least the top surface of the element isolation structure in the corresponding shared polysilicon gate covering area is patterned through corresponding photolithography and etching processes to form an uneven pattern.

[0042] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0043] 1. By forming a shared polysilicon gate with a grain size of 10nm to 100nm (the grain size is larger than that of the prior art), the grain boundary in the shared polysilicon gate is reduced, thereby suppressing the mutual diffusion of n-type ions in the portion of the shared polysilicon gate located in the nMOS region and p-type ions in the portion located in the pMOS region at the boundary between the nMOS region and the pMOS region, improving the boundary problem between the nMOS transistor and the pMOS transistor, and avoiding the failure of the semiconductor device and some components inside it.

[0044] 2. Since the problem of n-type ions in the part of the shared polysilicon gate located in the nMOS region diffusing along the shared polysilicon gate into the shared polysilicon gate in the pMOS region is suppressed, the p-type ions in the shared polysilicon gate located in the nMOS region can be prevented from being partially neutralized by the diffused n-type ions, thereby improving the problems of pMOS transistor mismatch and threshold voltage shift, and avoiding the problem of failure of the minimum operating voltage of the device.

[0045] 3. The grain size of the shared polysilicon gate formed can be controlled by regulating the deposition process conditions of the polysilicon layer. This can improve the boundary problem between the nMOS transistor and the pMOS transistor without changing the process flow, and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0047] Figure 1 This is the cross-sectional structure of adjacent nMOS and pMOS transistors in a bit of an existing SRAM.

[0048] Figure 2 It is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0049] Figure 3 It is a schematic diagram of a cross-sectional structure of a device in an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0050] Figure 4 It is a schematic diagram of a cross-sectional structure of a device in another example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0051] Figure 5 It is a schematic diagram of the cross-sectional structure of a device after source and drain ion implantation in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0052] Figure 6 This is a schematic diagram of the circuit structure of one bit of 6T SRAM.

[0053] Figure 7 It is a diagram showing the relationship between the threshold voltage Vtsat mismatch of the pMOS tube of the SRAM and the critical dimension of the np boundary.

[0054] Figure 8 This is a schematic diagram of the threshold voltage distribution of the pMOS transistor of the SRAM on the wafer under the existing technology.

[0055] Figure 9 FIG. 1 is a schematic diagram of a simulation curve showing the relationship between the diffusion length of n+ ions (eg, As+) and the grain size of the shared polysilicon gate in an SRAM according to an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0057] The technical solutions proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0058] Please refer to Figure 2 Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which includes:

[0059] S1, providing a substrate, and forming an element isolation structure in the substrate to define at least one nMOS region and at least one pMOS region;

[0060] S2, performing well ion implantation on the substrate to form an n-well in the substrate of the pMOS region and a p-well in the substrate of the nMOS region;

[0061] S3, forming a gate oxide layer on the substrate and covering the gate oxide layer and the element isolation structure with a polysilicon layer;

[0062] S4, etching the polysilicon layer to form at least a shared polysilicon gate, wherein the shared polysilicon gate is formed above the adjacent nMOS region and the pMOS region and the element isolation structure between the boundaries thereof, so as to be shared by the adjacent nMOS region and the pMOS region, and the grain size of the shared polysilicon gate is 10nm to 100nm.

[0063] Please refer to Figure 3 In step (A), in step S1, first, a substrate 200 is provided, which can be any suitable semiconductor substrate material in the art, such as silicon, silicon-on-insulator (SOI), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide, etc. As an example, the constituent material of the substrate 200 is selected from p-type single crystal silicon. Then, a device isolation structure 203 can be formed in the substrate 200 using shallow trench isolation (STI) technology or local isolation (LOCOS) technology to define an nMOS region (i.e., the active area AA of the nMOS transistor) and a pMOS region (i.e., the active area AA of the pMOS transistor).

[0064] Optionally, in step S1, the process of forming the element isolation structure 203 in the substrate 200 includes:

[0065] First, please refer to Figure 3In (A), a pad oxide layer (Pad Oxide) 201 can be formed on the substrate 200 by any suitable process such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), etc., and a dielectric material such as silicon nitride can be deposited on the pad oxide layer 201 by any suitable process such as chemical vapor deposition to form a hard mask layer 202.

[0066] Next, please continue to refer to Figure 3 In (A), a patterned photoresist layer (not shown) is formed on the hard mask layer 202 through a series of photolithography processes such as photoresist coating, exposure, and development to define the isolation trench pattern. The patterned photoresist layer is further used as a mask to etch the hard mask layer 202, the pad oxide layer 201, and the substrate 200 through an etching process such as dry etching to form isolation trenches (not shown). The patterned photoresist layer is then removed through commonly used stripping processes such as ashing and wet stripping.

[0067] Then, please continue to refer to Figure 3 In step (A), a liner oxide layer (not labeled) is first formed on the inner surface of the isolation trench (i.e., the bottom surface and sidewalls of the isolation trench) by a thermal oxidation process, and then a dielectric material such as silicon dioxide is filled into the isolation trench to fill the isolation trench by any suitable process such as a high-density plasma chemical vapor deposition (HDPCVD) process or a high aspect ratio filling process (HARP) to planarize the top surface of the deposited dielectric material by a chemical mechanical polishing (CMP) process until the top surface of the hard mask layer 202 is formed.

[0068] Afterwards, please refer to Figure 3 In (B), the pad oxide layer 201 is first used as an etching stop layer, and any suitable process such as dry etching or wet etching is adopted to etch away the hard mask layer 202, and then any suitable etching process such as wet etching or dry etching is adopted to etch away the pad oxide layer 201 to form a component isolation structure 203 with a top surface higher than the top surface of the substrate 200.

[0069] In an example, please refer to Figure 3In (A), when the pad oxide layer 201 is etched and removed by any suitable etching process such as wet etching (e.g., etching with a hydrofluoric acid solution) or dry etching, since the etching selectivity of the pad oxide layer 201 and the element isolation structure is relatively small, a certain amount of over-etching can be generated by appropriately extending the etching time and / or increasing the amount of etchant, thereby etching the top surface of the element isolation structure 203 exposed by the substrate 200 (i.e., the surface of the portion of the element isolation structure 203 that is higher than the substrate 200, including the sidewalls and the top surface) through the over-etching, so that the top height of the element isolation structure 203 is reduced. , and a side groove 203a is generated between the top corner of the isolation trench (i.e., the top sidewall of the isolation trench) and the active area, thereby increasing the unevenness of the top surface of the element isolation structure 203 exposed by the substrate 200. As a result, the uneven top surface of the element isolation structure 203 in the boundary area between the nMOS transistor and the pMOS transistor can be used to further block ion diffusion in the shared polysilicon gate on the boundary area. This is especially effective when the ion implantation in the shared polysilicon gate is deep and the ion diffusion in the shared polysilicon gate is closer to the surface of the element isolation structure 203. In addition, because the overetching can etch the element isolation structure 203 to a certain extent, the height of the step formed between the top of the element isolation structure 203 and the substrate 200 can be adjusted by controlling the degree of overetching.

[0070] In another example, see Figure 4 In (A) and (B), after etching the pad oxide layer 201 to form the element isolation structure 203, any photolithography and etching process in the subsequent process can be used to perform photolithography and etching on the top surface of the element isolation structure 203, including the element isolation structure 203 to be covered by the shared polysilicon gate (that is, a patterned photoresist layer is formed through a series of photolithography processes such as photoresist coating, exposure, and development, and the top surface of the element isolation structure 203 is etched using the patterned photoresist layer as a mask). Therefore, without changing the process steps of the subsequent process, only by modifying the corresponding mask pattern used in the subsequent existing process, at least the top surface of the element isolation structure 203 to be covered by the shared polysilicon gate can be patterned, so that the top surface of the element isolation structure 203 forms an uneven pattern, that is, the unevenness of the top surface of the element isolation structure 203 exposed by the substrate 200 is increased. This increases the blocking effect on ion diffusion in the shared polysilicon gate on the boundary area, especially when the ion implantation in the shared polysilicon gate is deeper and the ion diffusion in the shared polysilicon gate is closer to the surface of the element isolation structure 203, the effect is better.

[0071] In other embodiments of the present invention, after etching the pad oxide layer 201 to form the device isolation structure 203, new photolithography and etching processes can be added to pattern at least the top surface of the device isolation structure 203 to be covered by the shared polysilicon gate, so that the top surface of the device isolation structure 203 forms an uneven pattern, that is, the unevenness of the top surface of the device isolation structure 203 exposed by the substrate 200 is increased. This method relatively increases the mask cost and process cost.

[0072] It should be understood that in each of the above examples, the top surface of the element isolation structure 203 to be covered by the shared polysilicon gate needs to be etched to a certain extent. Therefore, the thickness of these film layers can be appropriately increased when forming the pad oxide layer 201 or depositing the hard mask layer 202, so that the height difference between the element isolation structure 203 after the top surface is flattened and the substrate 200 can be increased relative to the existing technology, for example, increased by about 20%.

[0073] Please refer to Figure 3 In (C), in step S2, the nMOS region can be masked first, the pMOS region can be opened, and at least one n-type ion such as phosphorus ions (P+), germanium ions (Ge+), arsenic ions (As+), and antimony ions (Sb+) can be used to perform well ion implantation on the substrate 200 of the pMOS region to form an n-well 200nw in the substrate 200 of the pMOS region. Then, the nMOS region can be opened, the pMOS region can be masked, and at least one p-type ion such as boron ions (B+), boron fluoride ions (BF+), Al ions (Al+), indium ions (In+), and gallium ions (Ga+) can be used to perform well ion implantation on the substrate 200 of the nMOS region to form a p-well 200pw in the substrate 200 of the nMOS region. Alternatively, the nMOS region may be opened first, the pMOS region may be masked, and well ion implantation may be performed on the substrate 200 of the nMOS region using p-type ions to form a p-well 200pw in the substrate 200 of the nMOS region. Then, the nMOS region may be masked, the pMOS region may be opened, and well ion implantation may be performed on the substrate 200 of the pMOS region using n-type ions to form an n-well 200nw in the substrate 200 of the pMOS region.

[0074] In one example, a patterned photoresist layer 300 can be formed on the substrate 200 and the element isolation structure 203 through a series of photolithography processes such as photoresist coating, exposure, and development to open the nMOS region and mask the pMOS region. Further, using the patterned photoresist layer 300 as a mask, any one or more p-type ions such as boron ions (B+), boron fluoride (BF+), gallium ions (Ga+), etc., are used to perform well ion implantation on the active region of the substrate 200 in the nMOS region to form a p-well 200pw in the active region of the substrate 200 in the nMOS region.

[0075] In the above example, well ion implantation can be performed after the pad oxide layer 201 is removed, but in other examples, well ion implantation can be performed after the hard mask layer 202 is removed and before the pad oxide layer 201 is removed, thereby preventing the well ion implantation process from causing ion implantation damage to the channel surface.

[0076] Please refer to Figure 3 In (D), in step S3, a gate oxide layer 204 can be formed on the substrate 200 by any suitable process such as furnace oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), atomic layer deposition, chemical vapor deposition, etc. Then, any suitable polysilicon formation process can be used to form a polysilicon layer 205 covering the gate oxide layer 204 and the element isolation structure 203. The grain size (which can be understood as the "average grain size") of the formed polysilicon layer 205 needs to be effectively controlled. It cannot be too large, otherwise it will lead to uncontrollable diffusion of doped ions in the subsequently formed polysilicon gate, which may further lead to adverse problems such as excessive increase in the work function of the polysilicon gate, serious threshold voltage shift of the formed MOS transistor, and serious poly depletion of the polysilicon gate in subsequent processes. It also cannot be too small to prevent the mutual diffusion of ions between the nMOS transistor and the nMOS transistor in the shared polysilicon gate.

[0077] Optionally, the grain size of at least the portion of the polysilicon layer 205 used for manufacturing the shared polysilicon gate is controlled to be between 10 nm and 100 nm.

[0078] In an example, please refer to Figure 3 In (D), in step S3, a polysilicon layer 205 can be directly deposited on the gate oxide layer 204 and the element isolation structure 203 by any suitable chemical vapor deposition process such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), atomic layer deposition, etc. The grain size of the deposited polysilicon layer 205 can be controlled by controlling the deposition process conditions. For example, the grain size of the deposited polysilicon layer 205 can be controlled to be within the range of 10nm to 100nm by increasing the deposition temperature and / or reducing the deposition rate. For another example, the deposition temperature can be controlled to be between 600°C and 700°C to control the grain size of the deposited polysilicon layer 205 to be within the range of 10nm to 100nm.

[0079] Furthermore, in this example, after depositing the polysilicon layer 205, the polysilicon layer 205 may be thermally annealed in a nitrogen (N2) atmosphere to appropriately increase the grain size and uniformity of the polysilicon layer 205. The grain size of the polysilicon layer after annealing is within a range of 10 nm to 100 nm. Optionally, the process of thermally annealing the deposited polysilicon layer 205 may include at least one of a furnace annealing process, a rapid thermal annealing process, and a laser annealing process, with the annealing temperature being 600° C. to 1250° C.

[0080] For another example, see Figure 3 In (D), in step S3, a low-temperature polysilicon (LTPS) process can be used to form a polysilicon layer 205 having a grain size in the range of 10 nm to 100 nm. The specific process includes: first, directly depositing an amorphous silicon layer at a low temperature on the gate oxide layer 204 and the element isolation structure 203, and then using any suitable crystallization process such as excimer laser annealing (ELA) to convert the deposited amorphous silicon layer into the polysilicon layer 205. In this example, by controlling the crystallization process conditions such as the laser annealing process conditions, the grain size of the formed polysilicon layer 205 can be controlled to be in the range of 10 nm to 100 nm.

[0081] In the above embodiments, the grain size of the subsequently formed shared polysilicon gate is controlled by regulating the deposition process conditions, post-deposition annealing process conditions, etc. of the polysilicon layer. Compared with the prior art, the boundary problem between the nMOS transistor and the pMOS transistor can be improved without changing the process flow, which is easy to implement.

[0082] Optionally, after completing step S3 and before performing step S4, a series of photolithography processes such as photoresist coating, exposure, and development are performed to mask the polysilicon layer above each pMOS region and expose the polysilicon layer above each nMOS region, and then one or more n-type ions are used to pre-dope the polysilicon layer 205 located above the nMOS region to increase the n-type ion doping concentration in the polysilicon gate of the subsequent nMOS transistor, thereby reducing the resistance of the polysilicon gate of the nMOS transistor and improving the electrical performance of the nMOS transistor.

[0083] Optionally, after completing step S3 and before performing step S4, a series of photolithography processes such as photoresist coating, exposure, and development are performed to mask the polysilicon layer above each nMOS region and expose the polysilicon layer above each pMOS region, and then one or more p-type ions are used to pre-dope the polysilicon layer 205 located above the pMOS region to increase the p-type ion doping concentration in the polysilicon gate of the subsequent pMOS transistor, thereby reducing the resistance of the polysilicon gate of the pMOS transistor and improving the electrical performance of the pMOS transistor.

[0084] In step S4, please combine Figure 3 (D) and Figure 5 First, silicon nitride or the like can be deposited on the polysilicon layer 205 to form a hard mask layer (not shown). Then, a patterned photoresist layer (not shown) is formed on the hard mask layer through a series of photolithography processes such as photoresist coating, exposure, and development to define the patterns of the individual polysilicon gates, including the shared polysilicon gate. Next, the hard mask layer is etched to the top surface of the polysilicon layer 205 using any suitable etching process, such as a dry etching process, using the patterned photoresist layer as a mask. Then, the patterned photoresist layer is removed, and the polysilicon layer 205 is etched to the top surface of the gate oxide layer 204 using any suitable etching process, such as a dry etching process, using the hard mask layer as a mask. In this way, the individual polysilicon gates, including the shared polysilicon gate, are formed. The shared polysilicon gate is formed above the element isolation structure 203 between the adjacent nMOS region and pMOS region and the boundary between the two, so as to be shared by the adjacent nMOS region and pMOS region. That is, the polysilicon gate 205a of the nMOS transistor formed in the nMOS region and the polysilicon gate 205b of the pMOS transistor formed in the pMOS region are connected together to form a shared polysilicon gate (in the shape of a strip). The shared polysilicon gate extends from above the active area of ​​the nMOS transistor, across the element isolation structure 203 in the boundary area between the nMOS transistor and the pMOS transistor, and extends all the way to above the active area of ​​the pMOS transistor.

[0085] In the above example, the same polysilicon layer is photolithographically and etched using a single mask, thereby forming a shared polysilicon gate and other relatively independent polysilicon gates at the same time, thereby saving process and mask costs. In this case, the grain size range of the shared polysilicon gate and the other relatively independent polysilicon gates is the same. However, if cost and process design permit, the shared polysilicon gate and the other relatively independent polysilicon gates can also be manufactured separately. In this case, the grain size of the other relatively independent polysilicon gates can also be different from the grain size range of the shared polysilicon gate. For example, the grain size of the shared polysilicon gate is increased by 10% to 30% (for example, by about 15% or 20%) relative to the grain size of the polysilicon gates other than the shared polysilicon gate.

[0086] Please refer to Figure 3 (E) and (F) in Figure 5 In the method for manufacturing the semiconductor device of this embodiment, after completing step S4 and forming the polysilicon gates required on each MOS region, the following steps may be further performed:

[0087] First, under the shielding of the remaining polysilicon layer 205 including the shared polysilicon gate (i.e., each polysilicon gate including the shared polysilicon gate), the gate oxide layer 204 is wet-etched to the top surface of the substrate 200 using an etching solution such as a hydrofluoric acid solution to form a corresponding gate structure (i.e., formed by stacking a gate oxide layer and a polysilicon gate).

[0088] Then, through processes such as dielectric material deposition and etching, sidewalls 206 are formed on the sidewalls of the gate structure (i.e., the sidewalls of the polysilicon gate and the sidewalls of the gate oxide layer 204). The sidewalls 206 can be a single-layer film structure or a multi-layer film structure (for example, a double-layer sidewall formed by silicon oxide and silicon nitride, or a triple-layer sidewall formed by silicon oxide, silicon nitride and silicon oxide).

[0089] Next, a patterned photoresist layer can be formed through a series of photolithography processes such as photoresist coating, exposure, and development. First, each pMOS region is masked to expose each nMOS region. Then, using the gate structure and sidewall on each nMOS region and the patterned photoresist layer on the pMOS region as a mask, one or more n-type ions are used to perform source and drain ion implantation on the substrate of each nMOS region and the polysilicon gate in each gate structure (i.e., the remaining polysilicon layer 205) to form corresponding source and drain regions 200nsd in the substrate 200 outside each gate structure of each nMOS region (i.e., the surface layer of the p-well 200pw of each nMOS region). At the same time, corresponding n-type ions are doped into the polysilicon gate of each nMOS region, thereby making the portion 205a of the shared polysilicon gate located in the nMOS region n-doped and the doping concentration of the n-type ions meet the required high doping requirements.

[0090] Then, the patterned photoresist layer on the pMOS region is removed, and a new patterned photoresist layer is re-formed through a series of photolithography processes such as photoresist coating, exposure, and development to mask the nMOS regions and expose the pMOS regions. Then, using the gate structure and sidewall on each pMOS region and the patterned photoresist layer on the nMOS region as a mask, one or more p-type ions are used to perform source and drain ion implantation on the substrate of each pMOS region and the polysilicon gate in each gate structure (i.e., the remaining polysilicon layer) to form corresponding source and drain regions 200psd in the substrate 200 outside each gate structure of each pMOS region (i.e., the surface layer of the n-well 200nw of each pMOS region). At the same time, corresponding p-type ions are doped into the polysilicon gate of each pMOS region, thereby ensuring that the portion 205b of the shared polysilicon gate located in the pMOS region is p-doped and the doping concentration of the p-type ions meets the required high doping requirement.

[0091] The semiconductor device manufacturing method of this embodiment is applicable to the manufacture of semiconductor devices in which nMOS transistors and pMOS transistors have a shared polysilicon gate (i.e., the nMOS transistors and pMOS transistors form an np boundary). Semiconductor devices with a shared polysilicon gate are, for example, SRAMs, ring oscillators, microcontrollers, logic devices, or any combination thereof.

[0092] Based on this, please refer to Figure 3 (E) and (F) in Figure 5 An embodiment of the present invention further provides a semiconductor device, which can be manufactured using the semiconductor device manufacturing method of this embodiment or any other suitable semiconductor device manufacturing method. The semiconductor device includes a substrate 200 and a shared polysilicon gate.

[0093] The substrate 200 includes an element isolation structure 203 and at least one nMOS region and at least one pMOS region defined by the element isolation structure 203. A shared polysilicon gate is formed above the element isolation structure 203 between the adjacent nMOS and pMOS regions and their boundaries, with a gate oxide layer 204 sandwiched between the top surface of the substrate 200 so as to be shared by the adjacent nMOS and pMOS regions. The portion 205b of the shared polysilicon gate located above the pMOS region is p-type doped, while the portion 205a located above the nMOS region is n-type doped. The grain size of the shared polysilicon gate is 10nm to 100nm.

[0094] Each element isolation structure may be a shallow trench isolation structure formed by using a shallow trench isolation technology, or may be a local isolation structure formed by using a local isolation technology.

[0095] Alternatively, refer to Figure 3 and Figure 4 , the top surface of the element isolation structure 203 is higher than the top surface of the substrate 200 .

[0096] Alternatively, refer to Figure 4 In (B), at least the top surface of the device isolation structure 203 covered by the shared polysilicon gate has an uneven pattern.

[0097] In this embodiment, an n-well 200nw is formed in the substrate 200 of the pMOS region, a p-type source and drain region 200psd is formed in the surface layer of the n-well 200nw, and a shared polysilicon gate (ie Figure 3 and Figure 5 Part or all of the p-type ions doped in 205b) and the p-type ions doped in the p-type source and drain regions 200psd are derived from the same ion implantation process (e.g., the source and drain ion implantation process of the pMOS transistor). A p-well 200pw is formed in the substrate of the nMOS region, and an n-type source and drain region 200nsd is formed in the surface layer of the p-well 200pw, sharing a polysilicon gate (i.e., Figure 3 and Figure 5 Part or all of the n-type ions doped in 205a) and the n-type ions doped in the n-type source and drain regions are derived from the same ion implantation process (eg, the source and drain ion implantation process of an nMOS transistor).

[0098] In order to illustrate the technical effect of the technical solution of the present invention, a detailed description is given below taking a 6T (transistor) SRAM as an example.

[0099] Static Random-Access Memory (SRAM) is a type of random access memory that features high speed and low leakage current. It is widely used in CPUs and System-on-Chip (SoCs), meeting the cache capacity, bandwidth, and speed requirements of CPUs and SoCs. A typical SRAM's smallest storage unit (i.e., a bit) can only store a single signal, 0 or 1, and is constructed from six transistors (also known as a 6T structure). See [the rest of the text for a more complete explanation of the SRAM structure and its structure]. Figure 5, divided into 2 pMOS transistors PU1, PU2 and 4 nMOS transistors PD1, PD2, PG1 and PG2. PU1 and PD1 form an inverter, PU2 and PD2 form another inverter, and the two inverters form an interlocking structure. This characteristic is used to achieve data preservation. PMOS transistors PU1 and PU2 act as pull-up transistors (also called load transistors) to achieve a high potential (i.e., a state of 1) at node N1 or N2. NMOS transistors PD1 and PD2 act as pull-down transistors (also called drive transistors) to achieve a low potential (i.e., a state of 0) at node N1 or N2. By swapping the high and low potentials of nodes N1 and N2 within a bit, the storage of states 0 and 1 can be achieved. NMOS transistors PG1 and PG2 act as pass gate transistors (also called access transistors) to enable access to bitlines BL and BLB for read and write functions. When manufacturing SRAM using a CMOS process, the polysilicon gates of PU1 and PD1 of each bit are connected together to form a shared polysilicon gate, and the polysilicon gates of PU2 and PD2 are connected together to form a shared polysilicon gate.

[0100] When the minimum operating voltage Vmin of the SRAM fails, the Probability of Failure Analysis (PFA) finds that n+ ions (such as As+) diffuse into the polysilicon gate of the pMOS transistor at the np boundary of the failed bit. In order to improve the problem of n+ ions (such as As+) at the np boundary diffusing into the polysilicon gate of the pMOS transistor, the critical dimension reduction (np CD-) of the shared polysilicon gate constituting the np boundary is reduced (for example, from 60nm to 20nm). Figure 7 It can be clearly seen that the threshold voltage mismatch (Vt mismatch) of the pMOS transistor PU1 or PU2 in the SRAM is getting better as the critical dimension (np CD) of the shared polysilicon gate constituting the np boundary is continuously reduced. However, even if the critical dimension of the shared polysilicon gate is reduced to 20nm (i.e., np CD-20), the threshold voltage deviation (Vt variation) of the pMOS transistor in the SRAM manufactured on the whole wafer still has a large scatter, such as Figure 8As shown in the dotted box in FIG, further TEM analysis of these scattered points revealed that n+ ion (eg, As+) signals still exist in the polysilicon gate of the pMOS transistor in the SRAM.

[0101] The technical solution of the present invention, compared with the prior art, is to increase the grain size of the shared polysilicon gate. Figure 9 The simulation results shown in the figure show that as the grain size of the shared polysilicon gate increases from 0.5nm to 50nm, the diffusion length of n+ ions (such as As+) at the np boundary in the SRAM decreases from 145nm to 71nm. When the grain size is further increased, the diffusion length of n+ ions (such as As+) at the np boundary also tends to be flat. This shows that the shared polysilicon gate with a larger grain size can effectively suppress the n+ ions (such as As+) at the np boundary, thereby reducing the threshold voltage offset of the pMOS transistor constituting the np boundary, improving the problem of pMOS threshold voltage mismatch and failure of the SRAM minimum operating voltage.

[0102] In addition, it should be understood that the grain size of the shared polysilicon gate cannot be increased indefinitely. If the grain size is too large, the ions injected into the shared polysilicon gate (for example, the p-type ions injected into the polysilicon gate portion of the pMOS transistor) will diffuse uncontrollably, which may lead to severe polysilicon depletion (polydepletion worse), increase the work function, and further increase the transistor threshold voltage offset. Therefore, combined with Figure 9 It can be seen that the grain size of the shared polysilicon gate is controlled within the range of 10nm to 100nm, achieving the best effect.

[0103] In summary, the semiconductor device and its manufacturing method of the present invention form a shared polysilicon gate with a grain size of 10nm to 100nm (the grain size is larger than that of the prior art), thereby reducing the grain boundaries in the shared polysilicon gate. This suppresses the mutual diffusion of n-type ions in the portion of the shared polysilicon gate located in the nMOS region and p-type ions in the portion located in the pMOS region at the boundary between the nMOS and pMOS regions, improves the boundary between the nMOS and pMOS transistors, and avoids failure of the semiconductor device and some components therein. Furthermore, because the problem of n-type ions in the portion of the shared polysilicon gate located in the nMOS region being prevented from diffusing along the shared polysilicon gate into the shared polysilicon gate in the pMOS region, the p-type ions in the shared polysilicon gate located in the nMOS region are prevented from being partially neutralized by the diffused n-type ions. This, in turn, improves the mismatch and threshold voltage shift of the pMOS transistor, and avoids failure of the device at the minimum operating voltage.

[0104] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate having an element isolation structure and at least one nMOS region and at least one pMOS region defined by the element isolation structure; a shared polysilicon gate, formed above the adjacent nMOS region and the pMOS region and the element isolation structure between the boundaries thereof, with a gate oxide layer sandwiched between the top surface of the substrate so as to be shared by the adjacent nMOS region and the pMOS region; Wherein, the grain size of the shared polysilicon gate is 10nm-100nm.

2. The semiconductor device according to claim 1, wherein A portion of the shared polysilicon gate located above the pMOS region is p-type doped, and a portion of the shared polysilicon gate located above the nMOS region is n-type doped.

3. The semiconductor device according to claim 2, wherein A p-type source and drain region is formed in the substrate of the pMOS region, and part or all of the p-type ions doped in the shared polysilicon gate and the p-type ions doped in the p-type source and drain region are derived from the same ion implantation process; and / or, an n-type source and drain region is formed in the nMOS region, and part or all of the n-type ions doped in the shared polysilicon gate and the n-type ions doped in the n-type source and drain region are derived from the same ion implantation process.

4. The semiconductor device according to claim 3, wherein An n-well is formed in the substrate of the pMOS region, and the p-type source and drain regions are formed in the surface layer of the n-well; and / or a p-well is formed in the substrate of the nMOS region, and the n-type source and drain regions are formed in the surface layer of the p-well.

5. The semiconductor device according to claim 1, wherein The device isolation structure has at least one of the following features: (1) The element isolation structure is a shallow trench isolation structure; (2) The top surface of the element isolation structure is higher than the top surface of the substrate; (3) The top surface of the element isolation structure has an uneven pattern.

6. The semiconductor device according to any one of claims 1 to 5, wherein The semiconductor device includes at least one of an SRAM, a ring oscillator, a microcontroller, and a logic device.

7. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, forming an element isolation structure in the substrate to define at least one nMOS region and at least one pMOS region; forming a gate oxide layer on the substrate and covering the gate oxide layer and the element isolation structure with a polysilicon layer; The polysilicon layer is etched to form at least a shared polysilicon gate. The shared polysilicon gate is formed above the adjacent nMOS region and the pMOS region and the element isolation structure between the boundaries thereof so as to be shared by the adjacent nMOS region and the pMOS region, and the grain size of the shared polysilicon gate is 10nm to 100nm.

8. The manufacturing method according to claim 7, wherein: Also includes at least one of the following features: (1) directly depositing the polysilicon layer on the gate oxide layer and the element isolation structure by low-temperature chemical vapor deposition, low-pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma chemical vapor deposition, or atomic layer deposition, or first depositing an amorphous silicon layer on the gate oxide layer and the element isolation structure, and then converting the amorphous silicon layer into the polysilicon layer by a corresponding crystallization process; (2) controlling the grain size of the deposited polysilicon layer by increasing the deposition temperature and / or decreasing the deposition rate; (3) The deposition temperature of the polysilicon layer or the amorphous silicon layer is 600° C. to 700° C.; (4) after covering the polysilicon layer and before etching the polysilicon layer, performing a thermal annealing treatment on the polysilicon layer in a nitrogen atmosphere; (5) after covering the polysilicon layer and before etching the polysilicon layer, pre-doping the portion of the polysilicon layer located above the nMOS region with n-type ions, and / or pre-doping the portion of the polysilicon layer located above the pMOS region with p-type ions; (6) After forming the element isolation structure in the substrate and before forming a gate oxide layer on the substrate, the substrate is further subjected to well ion implantation to form an n-well in the substrate of the pMOS region and / or to form a p-well in the substrate of the nMOS region.

9. The manufacturing method according to claim 8, wherein: The process of thermal annealing the polysilicon layer includes at least one of a furnace annealing process, a rapid thermal annealing process and a laser annealing process; and / or the temperature of thermal annealing the polysilicon layer is 600° C. to 1250° C.

10. The manufacturing method according to claim 7, wherein: After etching the polysilicon layer to at least form the shared polysilicon gate, the method further includes: Under the shielding of the remaining polysilicon layer including the shared polysilicon gate, etching the gate oxide layer to the top surface of the substrate to form a corresponding gate structure; forming sidewall spacers on sidewalls of the gate structure; Using the gate structure and the sidewall as masks, source and drain ion implantation is performed on the substrate and the remaining polysilicon layer to form corresponding source and drain regions in the substrate, wherein the source and drain ions implanted into the nMOS region are n-type ions to form n-type source and drain regions in the substrate of the nMOS region, and the portion of the shared polysilicon gate located in the nMOS region is n-doped, and the source and drain ions implanted into the pMOS region are p-type ions to form p-type source and drain regions in the substrate of the pMOS region, and the portion of the shared polysilicon gate located in the pMOS region is p-doped.

11. The manufacturing method according to claim 7, wherein: The step of forming the element isolation structure in the substrate includes: forming a pad oxide layer on the substrate and depositing a hard mask layer; etching the hard mask layer, the pad oxide layer, and the substrate to form an isolation trench; depositing a dielectric material to fill the isolation trench and planarizing a top surface of the dielectric material to a top surface of the hard mask layer; The hard mask layer and the pad oxide layer are removed by etching to form the element isolation structure with a top surface higher than a top surface of the substrate.

12. The manufacturing method according to claim 11, wherein: When etching and removing the pad oxide layer, over-etching is generated, wherein the over-etching etches the exposed top surface and sidewall of the element isolation structure to form side grooves at the top corners of the isolation trench; And / or, after etching away the hard mask layer and the pad oxide layer to form the element isolation structure, at least the top surface of the element isolation structure in the corresponding shared polysilicon gate covering area is patterned through corresponding photolithography and etching processes to form an uneven pattern.

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