Semiconductor device
By introducing doping regions of different doping types into the semiconductor body, a new vertical parasitic transistor structure is constructed, which solves the problem of high Gummel ratio and realizes the application of low-loss circuits.
Patent Information
- Application Number
- CN202510650594.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-20
- Publication Date
- 2025-08-22
Smart Images
Figure CN120529643A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a semiconductor device. Background Art
[0002] Existing integrated embedded semiconductor devices employ isolation structures to isolate different types of devices within a single chip or integrated circuit. The semiconductor device's main body comprises a substrate, a buried layer, and an epitaxial layer. Traditionally, a first deep trench structure (extending deep into the substrate) is used to bring the substrate within the semiconductor body to the surface, while a second deep trench structure (extending deep into the buried layer) is used to bring the buried layer within the semiconductor body to the surface. Applying a voltage forms an isolation region within the epitaxial layer, within the area enclosed by the second deep trench structure.
[0003] In the aforementioned semiconductor device, the epitaxial layer serves as the emitter, the buried layer derived from the second deep trench structure serves as the base, and the substrate serves as the collector. This results in a vertical parasitic PNP or NPN transistor structure within the semiconductor body. This vertical parasitic PNP or NPN transistor structure has a Gummel ratio of approximately 0.1 to 0.2, meaning that the substrate leakage current, Ic, is 10% to 20% of the base current, Ib. While this Gummel ratio is typical for vertical parasitic PNP or NPN transistor structures, it is still too high in practice and is unsuitable for low-leakage circuit applications.
[0004] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention
[0005] An object of the present invention is to provide a semiconductor device, which can reduce the Gummel ratio of parasitic transistors in the device and improve circuit performance.
[0006] In order to achieve the above object, a specific embodiment of the present invention provides the following technical solutions:
[0007] A semiconductor device comprising:
[0008] A semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer;
[0009] a first trench extending from the top surface of the epitaxial layer into the substrate, wherein a first conductive material having a first doping type is disposed in the first trench, and the first conductive material electrically connects the substrate to the top surface of the epitaxial layer;
[0010] a second trench extending from the top surface of the epitaxial layer into the buried layer, wherein a second conductive material having a second doping type is disposed in the second trench, and the second conductive material electrically connects the buried layer to the top surface of the epitaxial layer;
[0011] A first doped region is disposed in the epitaxial layer and is located within a range enclosed by the second trench, wherein the first doped region has a first doping type;
[0012] a second doped region disposed in the epitaxial layer, the second doped region being located between the second trench and the first doped region and being disposed close to a sidewall of the second trench, the second doped region having a second doping type;
[0013] The third doping region is disposed in the second doping region, and the third doping region has a first doping type.
[0014] In one or more embodiments of the present invention, the second conductive material is electrically connected to both the second doping region and the third doping region.
[0015] In one or more embodiments of the present invention, there is a preset distance between the bottom of the third doping region and the bottom of the second doping region, and the preset distance ranges from 50 nm to 1000 nm.
[0016] In one or more embodiments of the present invention, the first doping region and the second doping region are separated by the epitaxial layer.
[0017] In one or more embodiments of the present invention, the first doped region includes a first well region and a first heavily doped region located in the first well region, the first heavily doped region is formed on the surface layer of the first well region, and the doping concentration of the first heavily doped region is greater than the doping concentration of the first well region.
[0018] In one or more embodiments of the present invention, the second doped region includes a second well region and a second heavily doped region located in the second well region, the second heavily doped region is formed on the surface layer of the second well region, and the doping concentration of the second heavily doped region is greater than the doping concentration of the second well region.
[0019] In one or more embodiments of the present invention, the third doped region is disposed in the second well region and located on a side of the second heavily doped region away from the second trench; and / or the third doped region is disposed adjacent to the second heavily doped region.
[0020] In one or more embodiments of the present invention, the third doped region is a third heavily doped region, and the third heavily doped region is formed on the surface layer of the second well region. There is a preset distance between the bottom of the third heavily doped region and the bottom of the second well region, and the preset distance range is 350nm-960nm.
[0021] The third doped region includes a third well region and a third heavily doped region located in the third well region. The third heavily doped region is formed on the surface layer of the third well region. The doping concentration of the third heavily doped region is greater than the doping concentration of the third well region.
[0022] There is a preset distance between the bottom of the third well region and the bottom of the second well region, and the preset distance ranges from 50 nm to 550 nm.
[0023] In one or more embodiments of the present invention, the semiconductor device further includes a fourth doping region, which is disposed in the epitaxial layer. The fourth doping region is located between the second trench and the first trench and is disposed close to the sidewall of the second trench, and the fourth doping region has a second doping type.
[0024] In one or more embodiments of the present invention, the fourth doped region includes a fourth well region and a fourth heavily doped region located in the fourth well region, the fourth heavily doped region is formed on the surface layer of the fourth well region, and the doping concentration of the fourth heavily doped region is greater than the doping concentration of the fourth well region.
[0025] In one or more embodiments of the present invention, the semiconductor device further includes a fifth doping region, the fifth doping region is disposed in the fourth well region, and the fifth doping region has the first doping type;
[0026] The fifth doped region is located on a side of the fourth heavily doped region away from the second trench, and / or the fifth doped region is arranged adjacent to the fourth heavily doped region.
[0027] In one or more embodiments of the present invention, the fifth doped region is a fifth heavily doped region, and the fifth heavily doped region is formed on the surface layer of the fourth well region. There is a preset distance between the bottom of the fifth heavily doped region and the bottom of the fourth well region, and the preset distance range is 350nm-960nm.
[0028] In one or more embodiments of the present invention, the second conductive material is electrically connected to both the fourth heavily doped region and the fifth doped region.
[0029] In one or more embodiments of the present invention, the first trench, the second trench, the second doping region, and the third doping region are all arranged as a ring structure.
[0030] Compared with the prior art, the semiconductor device of the present invention introduces a new vertical parasitic transistor structure next to the second trench by setting a third doping region with a different doping type in the second doping region near the second trench, thereby helping to increase the base current of the parasitic vertical transistor structure originally formed by the epitaxial layer, the buried layer and the substrate (the buried layer is led out by the second conductive material as the base), thereby reducing the Gummel ratio of the original parasitic vertical transistor structure.
[0031] The semiconductor device of the present invention also provides a fifth doping region with a different doping type in the fourth doping region near the second trench, thereby introducing another new vertical parasitic transistor structure next to the second trench, further increasing the base current of the original parasitic vertical transistor structure and reducing the Gummel ratio of the original parasitic vertical transistor structure.
[0032] The semiconductor device of the present invention is compatible with existing manufacturing processes during manufacture without adding any additional manufacturing processes, thereby reducing substrate leakage current and improving circuit operating performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0034] Figure 1 A schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
[0035] Figure 2 for Figure 1 A top view of the semiconductor device shown (the surface STI is not shown);
[0036] Figure 3 A schematic structural diagram of a semiconductor device in another embodiment of the present invention;
[0037] Figure 4 for Figure 3 A top view of the semiconductor device is shown (the surface STI is not shown). DETAILED DESCRIPTION
[0038] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0039] As mentioned in the background art, existing integrated embedded semiconductor devices form a vertical parasitic PNP or NPN transistor structure within the semiconductor body. The Gummel ratio of this vertical parasitic PNP or NPN transistor structure is approximately 0.1 to 0.2. The high Gummel ratio makes the semiconductor device unsuitable for low leakage loss circuit applications.
[0040] Based on this, the present invention provides a semiconductor device comprising a semiconductor body, a first trench, a second trench, a first doped region, a second doped region, and a third doped region disposed within the semiconductor body. The semiconductor body comprises a substrate having a first doping type, a buried layer having a second doping type disposed above the substrate, and an epitaxial layer having the first doping type disposed above the buried layer. A first conductive material having the first doping type is disposed within the first trench, the first conductive material electrically connecting the substrate to the top surface of the epitaxial layer. A second conductive material having the second doping type is disposed within the second trench, the second conductive material electrically connecting the buried layer to the top surface of the epitaxial layer. A first doped region is disposed in the epitaxial layer and is located within an area enclosed by the second trench, the first doped region having the first doping type. A second doped region is disposed in the epitaxial layer, the second doped region being located between the second trench and the first doped region and adjacent to the sidewalls of the second trench, the second doped region having the second doping type. A third doped region is disposed within the second doped region, the third doped region having the first doping type.
[0041] The semiconductor device of the present invention provides a third doping region with a different doping type in a second doping region near a second trench within a semiconductor body, thereby introducing a new vertical parasitic transistor structure consisting of the third doping region, the second doping region, and an epitaxial layer next to the second trench, thereby helping to increase the base current of the parasitic vertical transistor structure originally formed by the epitaxial layer, the buried layer, and the substrate (the buried layer is led out by the second conductive material as the base), thereby reducing the Gummel ratio of the original parasitic vertical transistor structure and improving the circuit performance of the device.
[0042] The semiconductor device of the present invention is described in detail below with reference to a number of specific embodiments and accompanying drawings.
[0043] like Figure 1 and Figure 2As shown, an embodiment of the present invention provides a semiconductor device, including a semiconductor body 10, a first trench 20, a second trench 30, a first doping region 40, a second doping region 50 and a third doping region.
[0044] The semiconductor body 10 includes a substrate 11 having a first doping type, a buried layer 12 having a second doping type disposed on the substrate 11, and an epitaxial layer 13 having the first doping type disposed on the buried layer 12. The second doping type is opposite to the first doping type. In this embodiment, the first doping type is P-type and the second doping type is N-type. In other embodiments, the first doping type may be N-type and the second doping type may be P-type. P-type dopants may include boron (B), aluminum (Al), indium (In), or a combination thereof, while N-type dopants may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. The buried layer 12 may have a blanket structure, having substantially the same horizontal extension as the substrate 11 and being laid flat on the substrate 11. In other embodiments, the buried layer 12 may have a patterned structure. The epitaxial layer 13 may be used to form different device regions.
[0045] Both the first trench 20 and the second trench 30 are formed in the semiconductor body 10, and are arranged in an annular structure. The second trench 30 is located within the area enclosed by the first trench 20, and the width of the second trench 30 is smaller than the width of the first trench 20. The first trench 20 extends from the top surface of the epitaxial layer 13 into the substrate 11. The second trench 30 extends from the top surface of the epitaxial layer 13 into the buried layer 12. It is understood that the trench depth is proportional to the trench width; the wider the trench width, the deeper the trench is in the semiconductor body 10. By limiting the CD (width) of the first trench 20 to be greater than the CD of the second trench 30, the first trench 20 can be extended deeper into the substrate 11, and the second trench 30 can be extended deeper into the buried layer 12.
[0046] A first trench structure is disposed in the first trench 20 . The first trench structure includes a first conductive material 21 having a first doping type, and the first conductive material 21 is configured to electrically connect the substrate 11 to the top surface of the epitaxial layer 13 .
[0047] like Figure 1As shown, the first trench structure includes a first dielectric layer 22 and a first conductive material 21 having a first doping type. The first dielectric layer 22 is formed on the sidewalls of the first trench 20 and on a portion of the bottom wall of the first trench 20. The first dielectric layer 22 may include an oxide layer; or the first dielectric layer 22 may include an oxide layer and a nitride layer, with the nitride layer being located on the surface of the oxide layer. The first conductive material 21 fills the first trench 20, i.e., extends from the top surface of the epitaxial layer 13 to the bottom of the first trench 20 and contacts the substrate 11. With this arrangement, the first conductive material 21 can serve as a pickup structure for the substrate 11 to electrically connect the substrate 11 to the top surface of the epitaxial layer 13. In this embodiment, the first conductive material 21 is polysilicon.
[0048] A second trench structure is disposed in the second trench 30 . The second trench structure includes a second conductive material 31 having a second doping type, and the second conductive material 31 is configured to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13 .
[0049] like Figure 1 As shown, the second trench structure includes a second dielectric layer 32 and a second conductive material 31 having a second doping type. The second dielectric layer 32 is formed on the sidewalls of the second trench 30 and on a portion of the bottom wall of the second trench 30. In this embodiment, the second dielectric layer 32 may also include an oxide layer; or, the second dielectric layer 32 may also include an oxide layer and a nitride layer, with the nitride layer being located on the surface of the oxide layer. The second conductive material 31 fills the second trench 30, i.e., extends from the top surface of the epitaxial layer 13 to the bottom of the second trench 30 and contacts the buried layer 12. With this arrangement, the second conductive material 31 can serve as a pickup structure for the buried layer 12 to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13. In this embodiment, the second conductive material 31 is polysilicon.
[0050] The first doped region 40 is formed in the epitaxial layer 13 and is located within the range surrounded by the second trench 30. In this embodiment, the first doped region 40 is separated from the second trench 30 by the epitaxial layer 13. The first doped region 40 has a first doping type.
[0051] To reduce contact resistance, in this embodiment, the first doped region 40 may include a first well region 41 and a first heavily doped region 42 located within the first well region 41. The first heavily doped region 42 is formed on the surface of the first well region 41, and the doping concentration of the first heavily doped region 42 is greater than the doping concentration of the first well region 41. The carrier concentration (electrons) of the first heavily doped region 42 is much higher than that of the first well region 41. The provision of the first heavily doped region 42 can significantly reduce the contact resistance with subsequent metal electrodes, improve device performance, and avoid voltage drop or heat generation problems caused by high-resistance contact.
[0052] like Figure 1 As shown, the doping type of the first doped region 40 is the same as that of the epitaxial layer 13, and opposite to that of the buried layer 12. Therefore, the epitaxial layer 13 extending from the first doped region 40 serves as the emitter, the buried layer 12 extending from the second trench structure serves as the base, and the substrate 11 extending from the first trench structure serves as the collector, thereby forming a vertical parasitic transistor structure within the semiconductor body 10. In this embodiment, it is a vertical parasitic PNP transistor structure.
[0053] A second doped region 50 is formed in the epitaxial layer 13. The second doped region 50 is configured as a ring structure. The second doped region 50 is located between the second trench 30 and the first doped region 40 and is disposed near the sidewalls of the second trench 30. The second doped region 50 has a second doping type. In this embodiment, the second doped region 50 is separated from the first doped region 40 by the epitaxial layer 13. The provision of the second doped region 50 helps to increase the breakdown voltage between the second trench structure and the first doped region in the semiconductor device.
[0054] It can be understood that because the doping type of the second doping region 50 is the same as the doping type of the second conductive material 31 within the second trench 30, the doping type of the first doping region 40 is the same as the doping type of the epitaxial layer 13, and the doping type of the second doping region 50 and the second conductive material 31 within the second trench 30 is opposite to the doping type of the first doping region 40 and the epitaxial layer 13, when a voltage is applied to the first doping region 40 as an emitter, the voltage is directly transmitted to the epitaxial layer 13; when another voltage is applied to the buried layer 12 extending from the second conductive material 31 as a base, the voltage on the second conductive material 31 is coupled to the second doping region 50, causing the second doping region 50 to also have a certain voltage. Because the doping types of the second doping region 50 and the epitaxial layer 13 are opposite, a depletion region exists between them, which can improve the breakdown voltage between them to a certain extent. In addition, when the voltage applied to the first doping region 40 is conducted to the epitaxial layer 13 and transmitted within the epitaxial layer 13, it will be consumed along with the transmission distance in the epitaxial layer 13. Therefore, by adjusting the width of the epitaxial layer 13 between the second doping region 50 and the first doping region 40 (the distance between the second doping region 50 and the first doping region 40), the breakdown resistance between the second doping region 50 and the first doping region 40 can be further improved, which is beneficial to the application of the device.
[0055] It can be understood that the doping type of the second doping region 50 is the same as the doping type of the buried layer 12. Therefore, after the second doping region 50 is set and voltage is applied thereto, an inversion layer can be formed between the second doping region 50 and the buried layer 12 along the side wall of the second trench 30, thereby improving the breakdown resistance between the epitaxial layer 13 and the second conductive material 31 in the second trench 30, which is beneficial to the application of the device.
[0056] Similarly, to reduce contact resistance, in this embodiment, the second doped region 50 may include a second well region 51 and a second heavily doped region 52 located within the second well region 51. The second heavily doped region 52 is formed on the surface of the second well region 51, and the doping concentration of the second heavily doped region 52 is greater than the doping concentration of the second well region 51. The carrier concentration (electrons) of the second heavily doped region 52 is much higher than that of the second well region 51. The provision of the second heavily doped region 52 can significantly reduce the contact resistance with subsequent metal electrodes, improve device performance, and avoid voltage drop or heat generation problems caused by high-resistance contact.
[0057] The vertical parasitic PNP transistor structure formed in the semiconductor body 10 described above, with the epitaxial layer 13 derived from the first doping region 40 as the emitter, the buried layer 12 derived from the second trench structure as the base, and the substrate 11 derived from the first trench structure as the collector, has a high β gain, which is not conducive to the application of the device in low-loss applications. Therefore, in this embodiment, a third doping region with a doping type opposite to that of the second doping region 50 is also provided in the second doping region 50, thereby constructing a new vertical parasitic transistor composed of the third doping region, the second doping region 50 and the epitaxial layer 13. This new vertical parasitic transistor can contribute current to the base (second conductive material) of the original vertical parasitic PNP transistor structure, thereby increasing the base current and reducing the Gummel ratio. Preferably, the third doping region is configured as a ring structure.
[0058] In this embodiment, the second conductive material 31 is electrically connected to the second doping region 50 and the third doping region, so that the second conductive material 31, the second doping region 50 and the third doping region maintain the same voltage, preventing breakdown between the second doping region 50 and the third doping region, which affects device performance.
[0059] Preferably, the third doped region is completely located within the second doped region 50, and the third doped region is disposed within the second well region 51, on a side of the second heavily doped region 52 facing away from the second trench 30. Furthermore, the third doped region is disposed adjacent to the second heavily doped region 52. A predetermined distance is provided between the bottom of the third doped region and the bottom of the second doped region 50, with the predetermined distance ranging from 50 nm to 1000 nm.
[0060] In this embodiment, the third doped region is a third heavily doped region 62, which is formed on the surface of the second well region 51. There is a preset distance between the bottom of the third heavily doped region 62 and the bottom of the second well region 51, and the preset distance range is 350nm-960nm.
[0061] In other embodiments, the third doped region may also include a third well region (not shown) and a third heavily doped region 62 located within the third well region. The third heavily doped region 62 is formed on the surface of the third well region, and the doping concentration of the third heavily doped region 62 is greater than the doping concentration of the third well region. A predetermined distance is defined between the bottom of the third well region and the bottom of the second well region 51, with the predetermined distance ranging from 50 nm to 550 nm.
[0062] The provision of the third heavily doped region 62 can also significantly reduce the contact resistance with subsequent metal electrodes, thereby improving device performance and avoiding voltage drop or heating problems caused by high-resistance contact.
[0063] In the above technical solution, a third doping region with a different doping type is set in the second doping region 50 near the second trench 30, and a new vertical parasitic transistor structure is introduced next to the second trench 30, which helps to increase the base current of the parasitic vertical transistor structure originally formed by the epitaxial layer 13, the buried layer 12 and the substrate 11 (the buried layer is led out by the second conductive material 31 as the base), thereby reducing the Gummel ratio of the original parasitic vertical transistor structure, so that the device can be suitable for low-loss circuit applications.
[0064] Figure 3 and Figure 4 FIG. 1 shows a structure of another embodiment of a semiconductor device according to the present invention.
[0065] like Figure 3 and Figure 4 As shown, the semiconductor device in this embodiment completely includes Figure 1 and Figure 2 The semiconductor device of this embodiment has the same structure as the semiconductor device shown in FIG. Figure 1 and Figure 2 Based on the semiconductor device shown, a fourth doped region 70 having a first doping type is further provided between the second trench 30 and the first trench 20, and a fifth doped region having a doping type opposite to that of the fourth doped region 70 is provided within the fourth doped region 70. That is, in the semiconductor device of this embodiment, a new vertical parasitic transistor structure is constructed in the epitaxial layer between the second trench 30 and the first trench 20, contributing current to the base (second conductive material) of the original vertical parasitic PNP transistor structure, further increasing the base current and reducing the Gummel ratio. Preferably, the fourth doped region 70 and the fifth doped region are also configured as a ring structure.
[0066] Similarly, in order to prevent breakdown between the fourth doping region 70 and the fifth doping region and affect device performance, in this embodiment, the second conductive material 31 is electrically connected to the fourth doping region 70 and the fifth doping region, so that the second conductive material 31, the fourth doping region 70, and the fifth doping region maintain the same voltage.
[0067] like Figure 3 As shown, the fourth doped region 70 is disposed in the epitaxial layer 13 and is disposed near the sidewall of the second trench 30. The fourth doped region 70 includes a fourth well region 71 and a fourth heavily doped region 72 located within the fourth well region 71. The fourth heavily doped region 72 is formed on the surface of the fourth well region 71, and the doping concentration of the fourth heavily doped region 72 is greater than the doping concentration of the fourth well region 71.
[0068] The fifth doping region is arranged in the fourth well region 71. The fifth doping region is located on the side of the fourth heavily doped region 72 away from the second trench 30. Preferably, the fifth doping region is arranged adjacent to the fourth heavily doped region 72. In this embodiment, the fifth doping region is the fifth heavily doped region 82, which is formed on the surface of the fourth well region 71. There is a preset distance between the bottom of the fifth heavily doped region 82 and the bottom of the fourth well region 71, and the preset distance range is 350nm-960nm. In other embodiments, the fifth doping region may also include a fifth well region (not shown) and a fifth heavily doped region 82 located in the fourth well region 71, the fifth heavily doped region 82 is formed on the surface of the fourth well region 71, and the doping concentration of the fifth heavily doped region 82 is greater than the doping concentration of the fifth well region. There is a preset distance between the bottom of the fifth well region and the bottom of the fourth well region 71, and the preset distance range is 50nm-550nm.
[0069] It can be understood that the fourth doping region 70 and the second doping region 50 in this embodiment can be completed simultaneously in the same process, and the fifth doping region and the third doping region can also be completed simultaneously in the same process.
[0070] In the above technical solution, a fifth doping region with a different doping type is also provided in the fourth doping region 70 near the second trench 30, thereby introducing another new vertical parasitic transistor structure next to the second trench 30, thereby further increasing the base current of the original parasitic vertical transistor structure and reducing the Gummel ratio of the original parasitic vertical transistor structure.
[0071] The semiconductor device of the present invention can be manufactured using existing manufacturing methods.
[0072] Specifically, the method for manufacturing a semiconductor device of the present invention includes the following specific steps:
[0073] S1 , providing a semiconductor body, wherein the semiconductor body includes a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer.
[0074] S2, forming a second trench in the semiconductor body, the second trench extending from the top surface of the epitaxial layer into the buried layer. A second trench structure is formed in the second trench, the second trench structure including a second conductive material having a second doping type, the second conductive material electrically connecting the buried layer to the top surface of the epitaxial layer.
[0075] S3, forming a first trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer into the substrate, forming a first trench structure in the first trench, the first trench structure including a first conductive material having a first doping type, the first conductive material electrically connecting the substrate to the top surface of the epitaxial layer.
[0076] S4, forming a second doping region and / or a fourth doping region having a second doping type in the epitaxial layer, wherein the second doping region and / or the fourth doping region are arranged close to the sidewall of the second trench.
[0077] S5 , forming a first doping region having a first doping type in the epitaxial layer, wherein the first doping region is located within a range surrounded by the second trench and is isolated from the second doping region and / or the fourth doping region by the epitaxial layer.
[0078] During step S5, different device structures may also be formed in the epitaxial layer of the semiconductor body. After step S5, the second doped region and / or the fourth doped region are electrically connected to the second conductive material in the second trench.
[0079] Exemplarily, a semiconductor body is provided. The semiconductor body includes a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer. The epitaxial layer can be used to form different device regions. The second doping type is opposite to the first doping type. In this embodiment, the first doping type is P-type and the second doping type is N-type. In other embodiments, the first doping type is N-type and the second doping type is P-type. P-type dopants may include boron (B), aluminum (Al), indium (In) or a combination thereof, while N-type dopants may include phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof. The buried layer may have a blanket structure having substantially the same horizontal extension as the substrate and being laid flat on the substrate. In other embodiments, the buried layer may have a patterned structure. The epitaxial layer can be used to form different device regions.
[0080] A hard mask layer is formed on the top surface of the epitaxial layer. Forming the hard mask layer may include: growing or depositing a first oxide layer on the top surface of the epitaxial layer, the thickness of the first oxide layer being 100A to 200A; depositing a first nitride layer on the first oxide layer, the thickness of the first nitride layer being 1000A to 3000A. Preferably, the thickness of the first oxide layer is 200A, and the thickness of the first nitride layer is 1600A. It is understood that the first oxide layer can be densified to achieve a better effect of the hard mask layer. In some embodiments, the substrate, the buried layer, and the epitaxial layer are formed of silicon material, the first oxide layer is formed of silicon dioxide, and the first nitride layer is formed of silicon nitride.
[0081] The hard mask layer and the semiconductor body can be etched in a single pass using the first soft mask layer to form a second trench in the hard mask layer and the semiconductor body, extending through the hard mask layer and into the semiconductor body. The second trench extends from the top surface of the epitaxial layer into the buried layer. In some embodiments, the first soft mask layer can be a photoresist. After the second trench is etched, the first soft mask layer is stripped.
[0082] A second dielectric layer is formed on the sidewalls and bottom wall of the second trench. The second dielectric layer may include a combined layer structure of an oxide layer and a nitride layer, or may be a single oxide layer. For example, the sidewalls and bottom wall of the second trench may be thinly oxidized to form an oxide layer, and then a thin nitride layer may be formed on the oxide layer within the second trench. Alternatively, the oxide layer may be formed directly on the sidewalls and bottom wall of the second trench, in which case the oxide layer may have a thickness of 300 Å to 1000 Å, for better isolation.
[0083] Optionally, before forming the second dielectric layer on the sidewalls and bottom wall of the second trench, a sacrificial oxide layer 110A may be grown on the sidewalls and bottom wall of the second trench and then removed by wet stripping. Stripping the sacrificial oxide layer removes damage to the sidewalls and bottom wall caused by etching, thereby smoothing the sidewalls of the second trench.
[0084] The second dielectric layer at the bottom of the second trench is removed by dry etching, allowing the second trench to directly connect to the buried layer of the semiconductor body, facilitating subsequent electrical connection between the second conductive material and the buried layer. It should be noted that during dry etching, the first nitride layer in the hard mask layer may experience a loss of several hundred Å, depending on the dry etching selectivity.
[0085] Depositing a second conductive material having a second doping type such that the second conductive material fills the second trench. In some embodiments, the second conductive material is deposited such that the second conductive material covers a top surface of the first nitride layer. The second conductive material is selected from polysilicon.
[0086] Excess second conductive material can be removed by a chemical mechanical polishing (CMP) process, for example, removing the second conductive material from the hard mask layer. Depending on the polishing selectivity, the CMP process may stop at the first nitride layer within the hard mask layer. Because the deposition of the second conductive material may also deposit some of the second conductive material on the semiconductor substrate, the second conductive material on the semiconductor substrate is removed simultaneously with the removal of the second conductive material from the first nitride layer.
[0087] An etch-back process is performed on the second conductive material by dry etching. By etching back, the top surface of the second conductive material is maintained at the same level as the first nitride layer. This step can ensure that no excess second conductive material remains on the top surface of the first nitride layer. The first nitride layer can serve as a protective layer during the etch-back. In some embodiments, the chemical mechanical polishing process can be omitted and the etch-back process can be performed directly. The etch-back process can more effectively remove excess second conductive material. The second oxide layer and the second conductive material in the second trench form a second trench structure. Since the second conductive material extends from the top surface of the epitaxial layer to the bottom of the second trench and contacts the buried layer, the second conductive material can be used as a pick-up structure of the buried layer to electrically connect the buried layer to the top surface of the epitaxial layer. In addition, since the second oxide layer provided in the second trench extends from the top surface of the epitaxial layer to the bottom of the trench, it can isolate different device areas to a certain extent, thereby enhancing the isolation performance.
[0088] A second nitride layer is deposited on the first nitride layer, covering the second conductive material in the second trench. Exemplarily, the second nitride layer has a thickness of 500 Å to 1000 Å. The second nitride layer can protect the second trench and the second trench structure during subsequent fabrication of the first trench.
[0089] A second soft mask layer can be used to perform a single etching of the second nitride layer, the hard mask layer, and the semiconductor body to form a first trench in the second nitride layer, the hard mask layer, and the semiconductor body that penetrates the second nitride layer, the hard mask layer, and extends deep into the semiconductor body. The first trench is formed outside the area enclosed by the second trench structure. The first trench extends from the top surface of the epitaxial layer into the substrate. During this etching process, only the second soft mask layer is consumed, and no loss of the second nitride layer is caused. In some embodiments, the second soft mask layer can be a photoresist. After the first trench is etched, the second soft mask layer is stripped.
[0090] A first dielectric layer is formed on the sidewalls and bottom wall of the first trench. The first dielectric layer may also include an oxide layer; alternatively, the first dielectric layer may include an oxide layer and a nitride layer, with the nitride layer located on the surface of the oxide layer. Exemplarily, the sidewalls and bottom wall of the first trench are oxidized using a thermal oxidation process, with the oxide layer having a thickness of approximately 3000 Å to 5000 Å. Alternatively, a high aspect ratio process (HARP) may be used for chemical vapor deposition of the first dielectric layer.
[0091] Anisotropic etching is performed on the first dielectric layer in the first trench to at least partially remove the first dielectric layer on the bottom wall of the first trench and open at least a portion of the bottom of the first trench.
[0092] Optionally, after the first dielectric layer is formed, an annealing process may be performed to densify the first dielectric layer to achieve a better isolation effect.
[0093] Optionally, low energy boron implantation (eg, 5E15 / 5 KeV / 0 degree tilt) may be performed on the bottom of the first trench to increase the doping level at the bottom of the first trench, thereby achieving better connection to the substrate.
[0094] Deposition of a first conductive material having a first doping type is performed so that the first conductive material fills the first trench and the first conductive material in the first trench is in full contact with the substrate and electrically connected.
[0095] Optionally, to better achieve electrical extraction from the substrate, a conductive material can be deposited in the first trench in two steps. For example, after the first conductive material deposition, the conductive material can be dry-etched back to further widen the opening width at the top of the first trench, thereby achieving better conductive material filling and reducing voids in the first trench. The first conductive material is preferably polysilicon.
[0096] Excess first conductive material and a portion of the first nitride layer can be removed through a chemical mechanical polishing (CMP) process. The first nitride layer serves as a stop layer for the CMP. The loss of the first nitride layer depends on the polishing selectivity rate, with normal loss less than 500 Å. Because the first conductive material may also be deposited on the semiconductor substrate during deposition, the first conductive material on the semiconductor substrate is removed simultaneously with the removal of the first conductive material on the first nitride layer, resulting in improved wafer warpage and reduced stress.
[0097] Using the hard mask layer as an etch protection layer, an anisotropic plasma dry etch process is performed on the first conductive material and the second conductive material. Through the etch back, the top surface of the first conductive material and the second conductive material is maintained at the same level as the top surface of the epitaxial layer. The anisotropic plasma dry etch can ensure that no excess first conductive material remains on the top surface of the first nitride layer. In some embodiments, the chemical mechanical polishing process can be omitted and the etch back process can be directly performed. The etch back process can more effectively remove the excess first conductive material and the second conductive material.
[0098] The remaining first nitride layer in the hard mask layer on the surface of the epitaxial layer is removed through a wet process using H₃PO₄. The first oxide layer in the hard mask layer is then wet removed using diluted HF. The first dielectric layer and the first conductive material in the first trench form a first trench structure. Because the first conductive material extends from the top surface of the epitaxial layer to the bottom of the first trench and contacts the substrate, it can serve as a pickup structure for the substrate, electrically connecting the substrate to the top surface of the epitaxial layer.
[0099] like Figure 1 or Figure 3 As shown, the normal processes of subsequent CMOS devices are carried out within the range enclosed by the second trench and the second trench structure: such as pad oxide, STI (shallow trench isolation structure), LOCOS, well implantation, gate, LDD implantation, spacer formation, source / drain implantation, silicide formation, ILD (interlayer dielectric layer), contact formation, BEoL metal layer and passivation, etc.
[0100] In one embodiment, during the well injection process, a second well region and a fourth well region having a second doping type are formed in the epitaxial layer on both sides of the second trench in the width direction and close to the sidewalls of the second trench. At the same time, a first well region having a first doping type is formed in the middle area within the range enclosed by the second trench.
[0101] In this embodiment, during the source / drain implantation process, a second heavily doped region and a fourth heavily doped region are formed on the surface of the second well region and the fourth well region, respectively, with the same doping type as the second well region and the fourth well region but with a higher doping concentration than the second well region and the fourth well region; the second well region and the second heavily doped region together constitute the second doped region, and the fourth well region and the fourth heavily doped region together constitute the fourth doped region. A first heavily doped region is formed on the surface of the first well region with the same doping type as the first well region but with a higher doping concentration than the first well region; the first well region and the first heavily doped region together constitute the first doped region; and simultaneously, a third heavily doped region and a fifth heavily doped region are formed on the surface of the second well region and the fourth well region, respectively, with the opposite doping type as the second well region and the fourth well region.
[0102] The third heavily doped region is disposed in the second well region and is located on a side of the second heavily doped region away from the second trench; preferably, the third heavily doped region is disposed adjacent to the second heavily doped region. The fifth heavily doped region is located on a side of the fourth heavily doped region away from the second trench; preferably, the fifth heavily doped region is disposed adjacent to the fourth heavily doped region.
[0103] In the above embodiment, the third heavily doped region, the second well region and the epitaxial layer constitute a new vertical parasitic transistor, and the fifth heavily doped region, the fourth well region and the epitaxial layer constitute another new vertical parasitic transistor. Both new vertical parasitic transistors can contribute current to the base (second conductive material) of the original vertical parasitic PNP transistor structure, thereby increasing the base current and reducing the Gummel ratio.
[0104] In another embodiment, during the well injection process, a second well region and a fourth well region with a second doping type are formed in the epitaxial layer on both sides of the width direction of the second trench and close to the side walls of the second trench. At the same time, a first well region with a first doping type is formed in the middle area within the range enclosed by the second trench, and a third well region and a fifth well region with opposite doping types are formed in the second well region and the fourth well region, respectively.
[0105] In this embodiment, during the source / drain implantation process, a second heavily doped region and a fourth heavily doped region are formed on the surface of the second well region and the fourth well region, respectively, with the same doping type as the second well region and the fourth well region but with a greater doping concentration than the second well region and the fourth well region. The second well region and the second heavily doped region together constitute the second doped region, and the fourth well region and the fourth heavily doped region together constitute the fourth doped region. A first heavily doped region is formed on the surface of the first well region with the same doping type as the first well region but with a greater doping concentration than the first well region. The first well region and the first heavily doped region together constitute the first doped region. Simultaneously, a third heavily doped region and a fifth heavily doped region are formed on the surface of the third well region and the fifth well region, respectively. The third well region and the third heavily doped region together constitute the third doped region, and the fifth well region and the fifth heavily doped region together constitute the fifth doped region.
[0106] The third doped region is disposed in the second well region and is located on a side of the second heavily doped region away from the second trench; preferably, the third doped region is disposed adjacent to the second heavily doped region. The fifth doped region is located on a side of the fourth heavily doped region away from the second trench; preferably, the fifth doped region is disposed adjacent to the fourth heavily doped region.
[0107] In the above embodiment, the third doped region, the second well region and the epitaxial layer constitute a new vertical parasitic transistor, and the fifth doped region, the fourth well region and the epitaxial layer constitute another new vertical parasitic transistor. Both new vertical parasitic transistors can contribute current to the base (second conductive material) of the original vertical parasitic PNP transistor structure, thereby increasing the base current and reducing the Gummel ratio.
[0108] During the contact formation process, the second doping region, the second conductive material in the second trench, and the third doping region can be electrically connected; or, the second doping region, the second conductive material in the second trench, the third doping region, the fourth doping region, and the fifth doping region can all be electrically connected.
[0109] Since the normal processes of the above-mentioned CMOS devices can be manufactured using existing processes, and the process is not the innovation of this application, it will not be elaborated in detail here.
[0110] Compared with the prior art, the semiconductor device of the present invention introduces a new vertical parasitic transistor structure next to the second trench by setting a third doping region with a different doping type in the second doping region near the second trench, thereby helping to increase the base current of the parasitic vertical transistor structure originally formed by the epitaxial layer, the buried layer and the substrate (the buried layer is led out by the second conductive material as the base), thereby reducing the Gummel ratio of the original parasitic vertical transistor structure.
[0111] The semiconductor device of the present invention also provides a fifth doping region with a different doping type in the fourth doping region near the second trench, thereby introducing another new vertical parasitic transistor structure next to the second trench, further increasing the base current of the original parasitic vertical transistor structure and reducing the Gummel ratio of the original parasitic vertical transistor structure.
[0112] The semiconductor device of the present invention is compatible with existing manufacturing processes during manufacture without adding any additional manufacturing processes, thereby reducing substrate leakage current and improving circuit operating performance.
[0113] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.
[0114] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.
Claims
1. A semiconductor device, characterized in that: include: A semiconductor body comprising a substrate (11) having a first doping type, a buried layer (12) having a second doping type disposed on the substrate, and an epitaxial layer (13) having a first doping type disposed on the buried layer; a first trench (20) extending from the top surface of the epitaxial layer (13) into the substrate (11), wherein a first conductive material (21) having a first doping type is disposed in the first trench (20), and the first conductive material (21) electrically connects the substrate (11) to the top surface of the epitaxial layer (13); a second trench (30) extending from the top surface of the epitaxial layer (13) into the buried layer (12), wherein a second conductive material (31) having a second doping type is disposed in the second trench (30), and the second conductive material (31) electrically connects the buried layer (12) to the top surface of the epitaxial layer (13); a first doping region (40) disposed in the epitaxial layer (13) and located within a range surrounded by the second trench (30), the first doping region (40) having a first doping type; a second doping region (50) disposed in the epitaxial layer (13), the second doping region (50) being located between the second trench (30) and the first doping region (40) and being disposed close to a sidewall of the second trench (30), the second doping region (50) having a second doping type; A third doping region is provided in the second doping region (50), and the third doping region has a first doping type.
2. The semiconductor device according to claim 1, wherein The second conductive material (31) is electrically connected to the second doping region (50) and the third doping region.
3. The semiconductor device according to claim 1, wherein There is a preset distance between the bottom of the third doping region and the bottom of the second doping region (50), and the preset distance ranges from 50nm to 1000nm.
4. The semiconductor device according to claim 1, wherein The first doping region (40) and the second doping region (50) are separated by the epitaxial layer (13).
5. The semiconductor device according to claim 1, wherein The first doping region (40) includes a first well region (41) and a first heavily doped region (42) located in the first well region (41); the first heavily doped region (42) is formed on the surface layer of the first well region (41); and the doping concentration of the first heavily doped region (42) is greater than the doping concentration of the first well region (41). The semiconductor device according to claim 1 , wherein: The second doping region (50) comprises a second well region (51) and a second heavily doped region (52) located in the second well region (51); the second heavily doped region (52) is formed on the surface layer of the second well region (51); and the doping concentration of the second heavily doped region (52) is greater than the doping concentration of the second well region (51).
7. The semiconductor device according to claim 6, wherein: The third doping region is arranged in the second well region (51) and is located on a side of the second heavily doped region (52) away from the second trench (30); and / or the third doping region is arranged adjacent to the second heavily doped region (52).
8. The semiconductor device according to claim 7, wherein: The third doping region is a third heavily doped region (62), and the third heavily doped region (62) is formed on the surface layer of the second well region (51). There is a preset distance between the bottom of the third heavily doped region (62) and the bottom of the second well region (51), and the preset distance ranges from 350nm to 960nm.
9. The semiconductor device according to claim 7, wherein: The third doping region comprises a third well region (61) and a third heavily doped region (62) located in the third well region (61); the third heavily doped region (62) is formed on the surface layer of the third well region (61); and the doping concentration of the third heavily doped region (62) is greater than the doping concentration of the third well region (61).
10. The semiconductor device according to claim 9, wherein There is a preset distance between the bottom of the third well region (61) and the bottom of the second well region (51), and the preset distance ranges from 50 nm to 550 nm.
11. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a fourth doping region (70), the fourth doping region (70) being arranged in the epitaxial layer (13), the fourth doping region (70) being located between the second trench (30) and the first trench (20) and being arranged close to the sidewall of the second trench (30), and the fourth doping region (70) having a second doping type.
12. The semiconductor device according to claim 11, wherein The fourth doping region (70) includes a fourth well region (71) and a fourth heavily doped region (72) located in the fourth well region (71); the fourth heavily doped region (72) is formed on the surface layer of the fourth well region (71); and the doping concentration of the fourth heavily doped region (72) is greater than the doping concentration of the fourth well region (71).
13. The semiconductor device according to claim 12, wherein: The semiconductor device further comprises a fifth doping region, the fifth doping region being arranged in the fourth well region (71), and the fifth doping region having a first doping type; The fifth doping region is located on a side of the fourth heavily doped region (72) away from the second trench (30), and / or the fifth doping region is arranged adjacent to the fourth heavily doped region (72).
14. The semiconductor device according to claim 13, wherein: The fifth doping region is a fifth heavily doped region (82), and the fifth heavily doped region (82) is formed on the surface layer of the fourth well region (71). There is a preset distance between the bottom of the fifth heavily doped region (82) and the bottom of the fourth well region (71), and the preset distance range is 350nm-960nm.
15. The semiconductor device according to claim 13, wherein The second conductive material (31) is electrically connected to the fourth heavily doped region (72) and the fifth heavily doped region.
16. The semiconductor device according to claim 1, wherein The first trench (20), the second trench (30), the second doping region (50) and the third doping region are all arranged in a ring structure.