Substrate for semiconductor device, and method for manufacturing substrate for semiconductor device

Abstract

This substrate for a semiconductor device is provided with: a silicon nitride ceramic substrate having a first surface and a second surface; a bonding layer disposed on the first surface and the second surface; and a copper plate disposed on the bonding layer, the copper plate having a region in which the average crystal grain size of copper increases as the distance from the interface between the bonding layer and the copper plate increases, and the average crystal grain size of copper at a first position 20 [mu] m away from the interface is 25 [mu] m or more and less than 100 [mu] m, and the average crystal grain size of copper at a second position 20 [mu] m away from the interface is 10 [mu] m or more and less than 100 [mu] m. The average crystal grain size of copper at a second position 250 [mu] m away from the interface is 100 [mu] m or more.

Description

Technical Field

[0001] The present invention relates to a semiconductor device substrate and a method for manufacturing the semiconductor device substrate. Background Art

[0002] As a semiconductor device substrate used in a power transistor module or the like, there is known a substrate including a copper plate provided on the surface of a silicon nitride ceramic substrate via an adhesive (for example, Patent Document 1).

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Laid-Open No. 2022-173209 Summary of the Invention Problems to be solved by the invention However, durability under thermal cycling conditions is an issue for semiconductor device substrates, and a semiconductor device substrate that can suppress peeling of the copper plate even under such conditions is desired. The present invention was developed to address this issue, and its object is to provide a semiconductor device substrate that can suppress peeling of the copper plate even under thermal cycling conditions, and a method for manufacturing the same.

[0004] Technical solutions to problems Item 1. A semiconductor device substrate comprising: A ceramic substrate having a first surface and a second surface; a bonding layer disposed on the first surface and the second surface; and a copper plate disposed on the bonding layer, The thickness of the copper plate is 0.3 mm or more. The copper plate has the following area: the average grain size of the copper increases as the distance from the interface between the bonding layer and the copper plate increases, and the average grain size of the copper at a first position 20 μm away from the interface is greater than 25 μm and less than 100 μm, and the average grain size of the copper at a second position 250 μm away from the interface is greater than 100 μm.

[0005] Item 2. The semiconductor device substrate according to Item 1, wherein in the copper plate, an average crystal grain size of copper at the second position is 100 μm or more and 600 μm or less.

[0006] Item 3. The semiconductor device substrate according to Item 1 or 2, wherein in the copper plate, an average crystal grain size of copper at a third position 100 μm away from the interface is 50 μm or more and less than 150 μm.

[0007] Item 4. The semiconductor device substrate according to any one of Items 1 to 3, wherein the copper plate is formed of oxygen-free copper.

[0008] Item 5. A method for manufacturing a semiconductor device substrate, comprising: In the first step, a ceramic substrate having a first surface and a second surface is prepared; A second step is to form a solder layer on the first surface and the second surface; A third step is to arrange a copper plate on the brazing material layer to obtain an intermediate product having a ceramic substrate, the brazing material layer, and the copper plate; and The fourth step is to place the intermediate product in a furnace and perform heating and pressurizing treatment. In the fourth step, the intermediate product is heated to 800 to 900° C. and then cooled to the softening point of copper constituting the copper plate at a first average cooling rate of 2.8 to 12° C. / min.

[0009] Item 6. The method for manufacturing a semiconductor device substrate according to Item 5, wherein in the fourth step, after the intermediate product is cooled to the softening point, it is cooled at a second average cooling rate lower than the first average cooling rate.

[0010] Item 7. The method for manufacturing a semiconductor device substrate according to Item 5 or 6, wherein in the fourth step, the pressure during the heat and pressurization treatment is 0.2 to 22 MPa.

[0011] Item 8. The method for manufacturing a semiconductor device substrate according to any one of Items 5 to 7, wherein cooling is performed in an inert gas atmosphere during at least a portion of the fourth step.

[0012] Item 9. The semiconductor device substrate according to any one of Items 5 to 8, wherein in the fourth step, the copper plate is formed of oxygen-free copper.

[0013] Effects of the Invention According to the present invention, a bonding substrate having high thermal cycle durability can be obtained, and peeling of the copper plate caused by temperature changes can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a cross-sectional view showing one embodiment of a semiconductor device including a semiconductor device substrate according to the present invention.

[0015] Figure 2 It is a cross-sectional view showing the interface between the copper plate and the bonding layer.

[0016] Figure 3 This is a flowchart showing a method for manufacturing a semiconductor device substrate.

[0017] Figure 4It is a cross-sectional view showing the manufacturing process of the semiconductor device substrate.

[0018] Figure 5 It is a cross-sectional view showing the manufacturing process of the semiconductor device substrate.

[0019] Figure 6 It is a cross-sectional view showing the manufacturing process of the semiconductor device substrate.

[0020] Figure 7 This is a temperature distribution diagram during the manufacturing process of a semiconductor device substrate.

[0021] Figure 8 This is a graph schematically showing the tendency of the relationship between the stress when a force acts in a direction to separate the plate from the bonding layer and the distance in the planar direction from the end of the circuit pattern.

[0022] Figure 9 Yes Figure 8 A sectional view for explanation along the horizontal axis. DETAILED DESCRIPTION

[0023] Hereinafter, one embodiment of a semiconductor device substrate according to the present invention will be described with reference to the drawings. Figure 1 It is a cross-sectional view of an example of a semiconductor device including the semiconductor device substrate according to the present embodiment.

[0024] <1. Overview of Semiconductor Devices> The semiconductor device involved in this embodiment is used as a power module in various electronic devices, such as smartphones, personal computers, large household appliances, railways, electric vehicles, power generation (wind power generation, solar power generation, fuel cells, etc.), air conditioners, industrial robots, commercial elevators, household microwave ovens, IH rice cookers, and UPS (uninterruptible power supplies).

[0025] like Figure 1 As shown, the semiconductor device 1 according to the present embodiment includes a semiconductor device substrate 2 , a first bonding material 5 , a second bonding material 5 ′, a semiconductor chip 6 , bonding wires 7 , and a heat sink 8 .

[0026] The semiconductor device substrate 2 includes a plate-shaped ceramic substrate 3 serving as an insulator, a first copper plate 4 bonded to the upper surface (first surface) of the ceramic substrate 3 via a bonding layer 9, and a second copper plate 4' bonded to the lower surface (second surface) of the ceramic substrate 3 via a bonding layer 9. For example, an alumina substrate, an aluminum nitride substrate, or a silicon nitride substrate can be used as the ceramic substrate 3.

[0027] The bonding layer 9 can contain an active metal. The active metal can be, for example, at least one selected from titanium and zirconium. Alternatively, the bonding layer 9 can contain a metal other than an active metal. The metal other than an active metal contained in the bonding layer 9 is, for example, at least one selected from silver, copper, indium, and tin. In addition, the bonding layer 9 can contain nitrogen and / or silicon supplied from the ceramic substrate 3, and the supplied nitrogen and / or silicon can also form a compound with the active metal. Furthermore, the bonding layer 13 can also contain copper supplied from the copper plate 12.

[0028] The first copper plate 4 is patterned to form a transmission circuit. On the other hand, the second copper plate 4' is formed into a flat plate. The copper plates 4, 4' can be formed of, for example, oxygen-free copper.

[0029] A semiconductor chip 6 is bonded to the upper surface of the semiconductor device substrate 2, that is, to a portion of the upper surface of the first copper plate 4, via a first bonding material 5. The semiconductor chip 6 and the first copper plate 4 are connected by bonding wires 7.

[0030] Meanwhile, a heat sink 8 is bonded to the lower surface of the semiconductor device substrate 2, ie, the lower surface of the second copper plate 4', via a second bonding material 5'. The heat sink 8 is a well-known heat sink and can be made of metal such as copper.

[0031] The thicknesses of the ceramic substrate 3, copper plates 4, 4', and bonding layer 9 are not particularly limited. However, for example, the thickness of the ceramic substrate is preferably 0.2 to 0.5 mm, the thickness of the copper plate is preferably 0.3 to 2 mm, more preferably 0.5 to 1.5 mm, and particularly preferably 0.7 to 1.3 mm. Furthermore, the thickness of the bonding layer is preferably 0.1 to 20 μm.

[0032] <2. Characteristics of Semiconductor Device Substrates> In the semiconductor device substrate 2 according to this embodiment, Figure 2 As shown, the copper has a characteristic that the average crystal grain size increases from the interface between the bonding layer 9 and the copper plates 4, 4' along the thickness direction of the copper plates 4, 4'. The average crystal grain size distribution diagram is constructed as follows.

[0033] (1) In the copper plates 4 and 4 ′, the average crystal grain size of copper at the first position separated by 20 μm from the interface with the bonding layer 9 in the thickness direction is 25 μm or more and less than 100 μm.

[0034] (2) In the copper plates 4 and 4 ′, the average crystal grain size of copper at the second position separated by 250 μm from the interface with the bonding layer 9 in the thickness direction is 100 μm or more.

[0035] In (2), the upper limit of the average grain size is preferably 600 μm. In addition, the following (3) is preferably defined.

[0036] (3) In the copper plates 4 and 4', the average grain size of copper at the third position separated 100 μm in the thickness direction from the interface with the bonding layer 9 is 50 μm or more and less than 150 μm.

[0037] In the present embodiment, in the region from at least the interface to 250 μm, the average grain size of copper increases as it moves away from the interface, but it is sufficient that such a tendency exists in the region from at least the interface to 250 μm.

[0038] The average grain size can be calculated as follows. First, on the surface of the copper plates 4 and 4' of the semiconductor device substrate 2, a region capable of ensuring a length of 10 mm or more is selected. That is, a region on the copper plates 4 and 4' that is not cut due to patterning and can ensure a length of 10 mm or more is selected. Next, a length of 10 mm is selected, and the semiconductor device substrate 2 is cut so that a cross-section including the midpoint thereof is exposed. Then, the cut surface is polished by wide-area cross-section polishing (Japanese: 広域クロスセクションポリッシング).

[0039] Next, EBSD analysis is performed on the polished cross-section to obtain an image. Then, the obtained image is magnified 50 times. Next, the number of intersections of the reference lines 1 to 3 with a length of 1 mm and the copper grain boundaries is counted, and the average grain size is calculated by dividing the reference line length by the number of intersections. Figure 2 This is an example. The black dots marked on the reference line 2 are intersections. In this example, there are 8 intersections on the reference line 2, so the average grain size is 1000 μm / 8 = 125 μm.

[0040] As Figure 1 shown, the above measurement method and measurement results can be applied to any of the semiconductor device substrates in which the copper plates 4 and 4' have been patterned and the semiconductor device substrates in which no patterning has been performed.

[0041] <3. Manufacturing method of semiconductor device substrate> Next, the manufacturing method of the semiconductor device substrate will be described. Figure 3 This is a flowchart showing the manufacturing method of the semiconductor device substrate of the present embodiment. Figure 4 , Figure 5 and Figure 6 are schematic cross-sectional views of intermediate products obtained during the manufacturing process of the semiconductor device substrate.

[0042] First, a ceramic substrate 3 is prepared (step S1). Next, as Figure 4As shown, a brazing material layer 9i is formed on the upper and lower surfaces of the ceramic substrate 3 (step S1). At this time, a paste containing an active metal brazing material, a binder, and a solvent is prepared as the brazing material layer 9i. The paste may also contain a dispersant, a defoaming agent, etc. Next, the prepared paste is printed on the upper and lower surfaces of the ceramic substrate 3 by screen printing. Thus, a screen-printed film is formed on each surface of the ceramic substrate 3. Next, the solvent contained in the formed screen-printed film is volatilized. Thus, the screen-printed film is transformed into the brazing material layer 9i (step S2). The brazing material layer 9i contains an active metal brazing material and a binder. However, the brazing material layer 9i can also be formed by a method different from this method.

[0043] The active metal brazing filler metal includes a hydrogenation active metal powder and a metal powder. The hydrogenation active metal powder includes a hydride of at least one active metal selected from titanium and zirconium. The metal powder includes silver. The metal powder may also include a metal other than silver. The metal other than silver is at least one selected from copper, indium, and tin. When the active metal brazing filler metal includes at least one metal selected from copper, indium, and tin, the melting point of the active metal brazing filler metal is lowered.

[0044] The active metal brazing filler metal preferably comprises a powder having an average particle size of 0.1 μm or more and 20 μm or less. The average particle size can be determined by measuring the particle size distribution using a commercially available laser diffraction particle size analyzer and calculating the D50 (median diameter) from the measured particle size distribution. By using a powder having such a small average particle size, the brazing filler metal layer 9i can be made thinner.

[0045] The brazing material layer 9i preferably has a thickness of 0.1 μm or more and 20 μm or less, and more preferably has a thickness of 0.1 μm or more and 5 μm or less.

[0046] Then, if Figure 5 As shown, the copper plates 4 and 4' are placed on the formed brazing material layer 9i (step S3). Thus, an intermediate product 2i including the ceramic substrate 3, the copper plates 4 and 4', and the brazing material layer 9i is obtained.

[0047] Next, the intermediate product 2i is placed in a heating furnace and subjected to heating and pressurization treatment (step S4). Figure 6 As shown, a bonding layer 9 is generated. As a result, a Figure 6 The semiconductor device substrate 2 shown includes a ceramic substrate 3, copper plates 4, 4', and a bonding layer 9. The copper plates 4, 4' are bonded to the ceramic substrate 3 via the bonding layer 9.

[0048] When the intermediate product 2i is subjected to heat and pressure treatment, Figure 7 The temperature distribution diagram shown in the figure is used for heating. Figure 7As shown, the temperature in the furnace is raised in a vacuum atmosphere so that the temperature of the intermediate product 1i reaches a maximum of 800 to 900°C (hereinafter referred to as the upper limit temperature). The heating rate at this time can be set to, for example, 2 to 10°C / min. In this process, the vacuum atmosphere in the furnace is adjusted to 10°C in the bonding layer formation temperature range, that is, the time period from approximately 750°C to the start of cooling. -2 Pa or less. The intermediate product 2i is pressurized during the heating process and until cooling is complete. The surface pressure applied to the intermediate product 2i can be adjusted, for example, between 0.2 Pa and 22 MPa. Pressurization ensures that the ceramic substrate 3, the brazing material layer 9i, and the copper plates 4 and 4' are in contact and react with each other, forming the bonding layer 9.

[0049] Next, the intermediate product 2i is cooled after maintaining the temperature at 800 to 900°C for a predetermined time (e.g., 15 to 120 minutes). As a cooling method, for example, a method of injecting an inert gas such as nitrogen into the furnace and lowering the temperature in an inert gas atmosphere, or a cooling method in a vacuum atmosphere can be applied. When cooling in an inert gas atmosphere, the pressure is preferably equal to or higher than atmospheric pressure. It should be noted that Figure 7 , a distribution diagram is shown when cooling is performed using an inert gas such as nitrogen.

[0050] During the cooling process of the intermediate product 2i, the intermediate product 2i is rapidly cooled from 800 to 900°C to the softening point of copper at a first average cooling rate of 2.8 to 12°C / min (preferably 5.0 to 9.0°C / min). After cooling to the softening point of copper, the intermediate product 2i is cooled at a second average cooling rate lower than the first average cooling rate. The second average cooling rate can be set to, for example, 1.5 to 2.8°C / min. It should be noted that the softening point of copper depends on the material of the copper and is approximately 200 to 300°C ( Figure 7 250°C is used as an example).

[0051] Next, the copper plate 4 and the bonding layer 9 are patterned by etching or the like. As a result, the copper plate 4 is changed into Figure 1 The copper plate 4 after patterning is shown. In addition, the bonding layer 9 is also changed to Figure 1 The bonding layer 13 after patterning is shown.

[0052] <4. Features> As described above, in this embodiment, there is a region where the average crystal grain size of copper increases along the thickness direction of the copper plates 4 and 4' starting from the interface between the bonding layer 9 and the copper plates 4 and 4', and in particular, the above (1) and (2) are satisfied, so that the peeling of the copper plates 4 and 4' can be suppressed. As in the above (1), if the average crystal grain size at the first position is small, it is easy to suppress peeling. Regarding this point, refer to Figure 8 and Figure 9Provide explanation.

[0053] Figure 8 Indicates the stress distribution generated at the joint interface during thermal cycling. Figure 9 It is an explanation Figure 8 During the hot and cold cycle, high stress is generated at the bonding interface due to the thermal expansion difference between copper 4, 4' and ceramic substrate 3. Figure 8 As shown, if the copper plates 4 and 4' have a gradient with increasing average copper grain size, the force is dispersed and the peak stress generated at the interface is reduced. Therefore, the peak stress is lower than the threshold for peeling, which can suppress peeling.

[0054] On the other hand, when the cooling rate is low, there is a tendency for the average crystal grain size to be substantially the same or to be larger in the thickness direction.

[0055] Furthermore, as described above, after heating the intermediate product to 800-900°C and then cooling it to its softening point at a first average cooling rate of 2.8-12°C / min, a gradient in the average copper grain size can be formed within the copper plate. This is because cooling at a temperature above the softening point facilitates the movement of copper grains, allowing for controlled grain size. Consequently, it is possible to manufacture a semiconductor device substrate that suppresses copper delamination, as described above.

[0056] Example Hereinafter, examples of the present invention will be described, but the present invention is not limited to the following examples.

[0057] <1. Fabrication of semiconductor device substrates> Prepare a 0.32mm-thick silicon nitride ceramic substrate and a 0.8mm-thick copper plate. Also, prepare a brazing filler metal with a thickness of 0.1μm to 20μm containing an active metal brazing filler metal comprising 40% to 95% by weight of silver and titanium hydride. This brazing filler metal is then applied to the upper and lower surfaces of the silicon nitride ceramic substrate by screen printing. A copper plate made of oxygen-free copper is placed on top of the substrate to form an intermediate product. The softening point of this oxygen-free copper is 250°C.

[0058] Next, the intermediate product is placed in a furnace and Figure 7The substrate was heated according to the temperature distribution diagram shown in FIG. In the heating process, the temperature was raised to about 850°C at a rate of about 5°C / min, and the pressure was applied to about 20 MPa at the Max temperature. Then, the substrate was cooled at the cooling rate shown in Tables 1 to 4, and when the temperature was lowered to about 250°C, it was slowly cooled to room temperature. In this way, the substrates for semiconductor devices involved in Examples 1 to 9 and Comparative Examples 1 to 3 were completed. That is, three substrates for semiconductor devices were produced at one cooling temperature. It should be noted that patterning of the copper plate was not performed on these substrates for semiconductor devices.

[0059] <2. Evaluation> The average crystal grain sizes of copper at the first to third positions were measured for the semiconductor device substrates according to Examples 1 to 9 and Comparative Examples 1 to 3. The results are shown in Tables 1 to 4. The measurement conditions were as described above.

[0060] [Table 1] [Table 2] [Table 3] [Table 4] Next, a hot and cold cycle test was performed on the semiconductor device substrates involved in these Examples 1 to 9 and Comparative Examples 1 to 3. That is, after 3000 cycles of heating and cooling between -40°C and 175°C, an ultrasonic flaw detection test was performed to confirm the peeling of the end of the copper plate. In the ultrasonic flaw detection test, an ultrasonic flaw detection device FSesIII manufactured by Hitachi Power Solutions was used to inspect by reflection method. The results are as follows: the case where peeling could not be confirmed was set as OK, and the case where peeling could not be confirmed was set as NO. In the image obtained by the ultrasonic flaw detection test, since the gap between the copper plate and the bonding layer is generated at the location where peeling occurs, the gap appears as white, so peeling can be confirmed.

[0061] [Table 5] According to the results of Table 5, it was confirmed that if the copper plate has a region in which the average grain size of copper increases as it moves away from the interface between the copper plate and the bonding layer, the copper plate does not peel off during the hot and cold cycle test. On the other hand, in Comparative Examples 1 and 2, the average grain size is the same regardless of the position from the interface. In addition, in Comparative Example 3, the average grain size of copper increases as it moves away from the interface, but the average grain size at the first position exceeds 100 μm. Therefore, peeling of the copper plate occurred in Comparative Examples 1 to 3. Therefore, it can be seen that if the copper plate has a gradient of the average grain size as described above and the average grain size at the first position is less than 100 μm, peeling of the copper plate can be suppressed.

[0062] Explanation of symbols 2: Substrates for semiconductor devices 3: Ceramic substrate 4, 4': copper plate 9: Bonding layer.

Claims

1. A semiconductor device substrate comprising: A ceramic substrate having a first surface and a second surface; a bonding layer disposed on the first surface and the second surface; and a copper plate disposed on the bonding layer, The thickness of the copper plate is 0.3 mm or more. The copper plate has the following area: the average grain size of the copper increases as the distance from the interface between the bonding layer and the copper plate increases, and the average grain size of the copper at a first position 20 μm away from the interface is greater than 25 μm and less than 100 μm, and the average grain size of the copper at a second position 250 μm away from the interface is greater than 100 μm.

2. The semiconductor device substrate according to claim 1, wherein In the copper plate, an average crystal grain size of copper at the second position is 100 μm or more and 600 μm or less.

3. The semiconductor device substrate according to claim 1 or 2, wherein In the copper plate, an average crystal grain size of copper at a third position 100 μm away from the interface is 50 μm or more and less than 150 μm.

4. The semiconductor device substrate according to claim 1 or 2, wherein The copper plate is formed of oxygen-free copper.

5. A method for manufacturing a semiconductor device substrate, comprising: In the first step, a ceramic substrate having a first surface and a second surface is prepared; A second step is to form a solder layer on the first surface and the second surface; A third step is to arrange a copper plate on the brazing material layer to obtain an intermediate product having a ceramic substrate, the brazing material layer, and the copper plate; and The fourth step is to place the intermediate product in a furnace and perform heating and pressurizing treatment. In the fourth step, the intermediate product is heated to 800 to 900° C. and then cooled to the softening point of copper constituting the copper plate at a first average cooling rate of 2.8 to 12° C. / min.

6. The method for manufacturing a semiconductor device substrate according to claim 5, wherein: In the fourth step, after the intermediate product is cooled to the softening point, it is cooled at a second average cooling rate that is lower than the first average cooling rate.

7. The method for manufacturing a semiconductor device substrate according to claim 5 or 6, wherein: In the fourth step, the pressure during the heating and pressurizing treatment is 0.2 to 22 MPa.

8. The method for manufacturing a semiconductor device substrate according to claim 5 or 6, wherein: During at least a portion of the fourth step, cooling is performed in an inert gas atmosphere.

9. The method for manufacturing a semiconductor device substrate according to claim 5 or 6, wherein: The copper plate is formed of oxygen-free copper.

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