Server and server power management method

Abstract

The invention relates to the technical field of servers, and discloses a server and a server power management method. The server comprises a first controller, a second controller, a first register and a plurality of board cards. And the first controller writes a board card power-on state value into the first register when receiving the power-on instruction so as to synchronize the running state of the server to the second controller. And the second controller can execute a corresponding control flow according to the state value read from the first register. The first register can also carry out state transition condition judgment according to a control flow result of the second controller. Therefore, on the basis of a state transition mechanism, the power-on control logic of the board card is simplified, and the reusability of the power-on control logic is improved.

Description

Technical Field

[0001] The present application belongs to the field of server technology, and in particular relates to a server and a server power management method. Background Art

[0002] For example, computing devices like servers include a central management board (CMB) and various components connected to it. These components implement various functions, such as fan control, information retrieval, and hard drive data access. The power-on sequence and logic of these components vary, making the server power-on and power-off process complex and prone to system failures. Therefore, it's necessary to manage the power-on and power-off processes of various board components to ensure stable server operation and data security.

[0003] To ensure optimal server performance and stability, the server's power-on and power-off processes can be optimized by optimizing the power-on and power-off sequences of each component. For example, nested loops can be used to control the power-on and power-off of each component in a preset order to ensure consistent power-on and power-off timing.

[0004] However, the loop-based control approach leads to strong coupling between the various power-up steps. Consequently, when replacing different components on the central management board or changing the power-up sequence of components, the control logic must be adjusted overall, making it difficult to reuse control logic for different central management boards. Therefore, it is necessary to address the problem of complex control logic that makes it difficult to reuse. Summary of the Invention

[0005] The embodiments of the present application provide a server and a server power management method, which can control the power-on of the server based on a state machine to simplify the control logic of the power-on process and improve the reusability of the control logic.

[0006] In a first aspect, the present application provides a server comprising a central management board. The central management board is provided with a first controller, a second controller, a first register, and a plurality of boards. The first controller is connected to the second controller, the first register, and the plurality of boards. The second controller is connected to the first register and the plurality of boards.

[0007] The first controller is configured to write a board power-on status value into a first register upon receiving a power-on instruction. The second controller is configured to control the function board to power on upon reading the board power-on status value from the first register. The first controller is further configured to write an abnormal power-on status value into the first register when at least one board experiences an abnormal power-on. The abnormal power-on status value is used to indicate that the server's operating status is an abnormal power-on state. When multiple boards are powered on, a working status value is written into the first register. The working status value is used to indicate that the server's operating status is a working state.

[0008] Based on this implementation, the server's current state is determined by the state value, and the power-on operation corresponding to the current state is executed. When the state transition condition is met, the state value is updated to the next state, allowing the server to enter the next operating state. The combination of state value and state transition condition simplifies the board power-on control logic, facilitates the reuse of board power-on control logic, and thus improves the development efficiency of board power-on control logic.

[0009] In another possible implementation, the central management board is further provided with a power chip. The power chip includes at least one power supply port for supplying power to the boards. The power chip is connected to the first controller, the second controller, and the plurality of boards.

[0010] The first controller is further configured to write the power-on status value of the power chip into the first register before writing the power-on status value of the board into the first register. The second controller is configured to control the power-on of at least one power port upon reading the power-on status value of the power chip. The first controller is further configured to write the abnormal power-on status value into the first register when at least one power port experiences a power-on abnormality and / or when the in-place status of at least one board changes to an abnormal state. When all power ports are powered on and the in-place status of the board remains unchanged, the board power-on status value is written into the first register.

[0011] Based on this implementation, the power-on timing of the board and the power chip can be controlled based on the status value and the status transition condition. When the second controller receives the power-on instruction, it can first control the power-on of the power chip. And when at least one power supply port is powered on abnormally, the first controller writes the abnormal power-on status value to the first register to make the server enter the abnormal power-on state. When all the power supply ports are powered on, the first controller can write the board power-on status value to the first register to make the server enter the board power-on state. Through the combination of status value and status transition condition, the power-on timing of the board and the power chip can be effectively controlled, and the control logic is simple, which is conducive to abnormality troubleshooting.

[0012] In another possible implementation, the second controller is further configured to control the board and power supply port to power off when an abnormal power-on status value is read from the first register and at least one board experiences a power-on abnormality. The board is powered off before the power supply port. The first controller is configured to write the power-off status value to the first register when both the board and the power supply port are powered off. The power-off status value indicates that the server is in a powered-off state.

[0013] Based on this implementation, when a power chip is used to power a card, the second controller can first power off the card and then the power chip. This sequential control of powering off the card and power chip prevents data loss and other issues caused by abnormal power-off of the card.

[0014] In another possible implementation, the server further includes a second register configured to store a first abnormality identifier, which is configured to indicate a power-on abnormality of the board.

[0015] The first controller is further configured to write a first abnormality record status value into the first register before writing the abnormal power-on status value into the first register. The first abnormality identifier is written into the second register. The second controller is configured to, upon reading the first abnormality record status value from the first register, generate a first abnormality log based on the first abnormality identifier stored in the second register. The first controller is further configured to write the abnormal power-on status value into the first register after the first abnormality identifier is deleted.

[0016] Based on this implementation, when the board is powered on abnormally, the first controller can first write the first exception identifier to the second register. After writing the first exception identifier, the first exception record status value is written to the first register to make the server enter the abnormal record state. When the second controller reads the first exception record status value, it can generate a first exception log based on the first exception identifier to provide abnormal information, which is beneficial to the maintenance and abnormal tracing of the server. In addition, when the first controller generates the first log record and deletes the first exception identifier in the second register, the first controller can write the power-off status value to the first register to make the server enter the power-off execution state to ensure that the server will not cause equipment failure due to the power-on abnormality of the board.

[0017] In another possible implementation, the first controller is further configured to, upon receiving a target board power-off instruction, write a separate power-off status value into the first register. The second controller is configured to, upon reading the separate power-off status value from the first register, control powering off the target board. The second controller is further configured to, upon successful power-off of the target board, generate a first prompt indicating that the target board is removable. The first controller is further configured to, upon successful power-off of the target board, write a working status value into the first register.

[0018] Based on this implementation, when the server is in operation and receives a separate power-off instruction for a target board, the first controller can write a separate power-off state value to the first register, causing the server to enter the target board's separate power-off state. When the target board is successfully powered off, the second controller can generate a first prompt message to inform the operator that the target board has been powered off and can be removed. This allows individual boards to be removed while the server is operating normally, facilitating debugging or replacement of individual boards.

[0019] In another possible implementation, the server further includes a third register configured to store a second abnormality flag, which indicates that a target board is abnormally powered off individually.

[0020] The first controller is further configured to write a second exception flag into a third register when the target board experiences an abnormal power-off. The first controller is further configured to write a second exception record status value into the first register. The second controller is configured to generate a second exception log based on the second exception flag when the second exception record status value is read from the first register. The second exception flag is deleted from the third register. The first controller is further configured to write a working status value into the first register after the second exception flag is deleted.

[0021] Based on this implementation, when a target board experiences an abnormal power-off, the second controller can generate a second exception log to facilitate abnormality tracing and device maintenance. This allows the target board to be powered off independently without affecting other boards, facilitating debugging or replacing a single board. Furthermore, after the second exception flag is deleted, the first controller can write an operating status value to the first register to maintain the server in normal operation. This ensures that the server's normal operation is not affected by whether the target board is powered off independently.

[0022] In another possible implementation, the first controller is further configured to, upon receiving a target board power-on instruction, write a separate power-on status value into the first register. The second controller is configured to, upon reading the separate power-on status value from the first register, control the target board to power on. The second controller is further configured to, upon successful power-on of the target board, generate second prompt information indicating successful power-on of the target board. The first controller is further configured to, upon successful power-on of the target board, write a working status value into the first register.

[0023] Based on this implementation, when the server is in operation and receives a separate power-on instruction from a target board, the first controller can write a separate power-on status value to the first register, causing the server to enter the separate power-on execution state for the target board without affecting normal server operation. Furthermore, the second controller can generate a second prompt message to indicate whether the separate power-on of the board was successful. This combination of separate power-on and power-off of boards facilitates debugging and replacement of individual boards.

[0024] In another possible implementation, the server further includes a fourth register configured to store a third abnormality flag, which is configured to indicate an abnormality in the power-on of a target board.

[0025] The first controller is further configured to write a third exception flag into the fourth register and a third exception record status value into the first register when a power-on abnormality occurs on the target board. The second controller is configured to generate a third exception log based on the third exception flag upon reading the third exception record status value from the first register. The third exception flag is deleted from the fourth register. The first controller is further configured to write a working status value into the first register after the third exception flag is deleted.

[0026] Based on this implementation, the first controller can write a third exception identifier to the fourth register when a separate power-on exception occurs. And after writing the third exception identifier, the third exception record status value is written to the first register to facilitate the generation of an exception log. When the second controller reads the third exception record status value, it can generate a third exception log to facilitate the tracing and investigation of the separate power-on exception of the board. When the second controller deletes the third exception identifier, the first controller can write a working status value to the first register to restore the server to a normal working state. In this way, it can be ensured that the server can still operate normally in the scenario where the board fails to power on separately, without affecting the function of the server.

[0027] In another possible implementation, the first controller is further configured to control the board and / or the power chip to power off when receiving a reset instruction, wherein the board is powered off before the power chip.

[0028] Based on this implementation, upon receiving a reset command, the first controller can write the power-off state value to the first register to restore the server to its powered-off state. Furthermore, the first controller can forcefully power off the control board and / or power chip. The hardware power-off method provided by the first controller ensures the execution priority of the reset command.

[0029] In yet another possible implementation, the triggering mode of the power-on instruction includes key triggering and / or register writing triggering.

[0030] Based on this implementation, the power-on instruction may be input to the server through a button provided on the server, or by modifying a register value.

[0031] In another possible implementation, the first controller is further configured to, upon receiving a power-off instruction, write a board power-off status value into the first register. The board power-off status value indicates that the server is in a powered-off state. The second controller is configured to, upon reading the board power-off status value from the first register, control the board to power off. The first controller is further configured to write the power-off status value into the first register when multiple boards are powered off. The power-off status value indicates that the server is in a powered-off state.

[0032] Based on this implementation, upon receiving a power-off command, the first controller can write the board power-off status value to the first register, thereby causing the server to enter the board power-off state. Furthermore, upon reading the board power-off status value from the first register, the second controller can control the board power-off. When multiple boards are powered off, the first controller can write the power-off status value to the first register, thereby causing the server to enter the powered-off state. The coordination of state transition conditions and status values ​​can simplify the board power-off control logic.

[0033] In another possible implementation, the first controller is further configured to write the power-off status value of the power chip into the first register before writing the power-off status value into the first register. The second controller is configured to control powering off the power chip upon reading the power-off status value of the power chip from the first register. The first controller is further configured to write the power-off status value into the first register when the power chip is powered off.

[0034] Based on this implementation, when a power chip is powering a board, the first controller can write the power-off status value of the power chip to the first register upon receiving a power-off command. The second controller can control the power chip to power off upon reading the power-off status value from the first register. Furthermore, when all power chips are powered off, the first controller writes the power-off status value to the first register. This allows for increased adaptability to various types of central management boards by adding state transition conditions and state values, improving the reusability of the power-off control logic.

[0035] In a second aspect, the present application provides a server power management method, comprising: in response to a received power-on instruction, writing a board power-on status value into a first register. The board power-on status value is used to indicate that the server's operating state is a power-on execution state. If at least one board is abnormally powered on, the abnormal power-on status value is written into the first register. The abnormal power-on status value is used to indicate that the server's operating state is a power-off execution state. If multiple boards are powered on, a working status value is written into the first register. The working status value is used to indicate that the server's operating state is a working state.

[0036] This implementation allows you to set different status values ​​to correspond to multiple server power-on phases, and combine these with state transition conditions to determine which power-on phase a board should enter. This combination of status values ​​and transition conditions simplifies board power-on control logic and facilitates reuse of server power-on control logic. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 A diagram of the server hardware architecture provided for an embodiment of the present application;

[0039] Figure 2 This is the internal timing diagram of the board when it is powered on according to the embodiment of the present application;

[0040] Figure 3 This is an internal timing diagram of the power chip provided in the embodiment of the present application when it is powered on;

[0041] Figure 4 A schematic diagram of the connection relationship between the first power supply port and the board provided in an embodiment of the present application;

[0042] Figure 5 A schematic diagram of the connection relationship between the second power supply port and the board provided in an embodiment of the present application;

[0043] Figure 6 An internal timing diagram for generating a first abnormality log according to an embodiment of the present application;

[0044] Figure 7 This is the internal timing diagram of the target board provided in the embodiment of the present application when it is successfully powered off separately;

[0045] Figure 8 An internal timing diagram for generating a second abnormality log provided by an embodiment of the present application;

[0046] Figure 9 This is an internal timing diagram of the target board provided in the embodiment of the present application when it is successfully powered on separately;

[0047] Figure 10 This is an internal timing diagram when generating the third abnormality log provided by an embodiment of the present application;

[0048] Figure 11 This is a reset and power-off flowchart provided in an embodiment of the present application;

[0049] Figure 12 This is an internal timing diagram of the board when it is powered off according to an embodiment of the present application;

[0050] Figure 13 This is an internal timing diagram of the power chip when it is powered off according to an embodiment of the present application;

[0051] Figure 14 A flowchart for powering on a server board provided in an embodiment of the present application;

[0052] Figure 15 This is a flowchart of powering off a server board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. To facilitate the clear description of the technical solutions in the embodiments of the present application, the first, second, etc. descriptions in the embodiments of the present application are only used for illustration and to distinguish the described objects. There is no order, nor does it represent a special limitation on the number of devices in the embodiments of the present application, and it does not constitute any limitation on the embodiments of the present application.

[0054] In order to facilitate the understanding of this application, the terms involved in this application are now explained.

[0055] Server, the physical type of the server may include a cabinet server, a rack server, a high-density server, a graphics processing unit (GPU) server, a tower server, and may also be a blade server, an artificial intelligence (AI) server, etc. The embodiment of the present application does not limit the type of server.

[0056] Server components include a central management board (CMB), which hosts various hardware components, such as the BMC, CPLD, and various boards. The CMB connects to these hardware components via slots or interfaces, enabling data transmission and functional expansion. For example, the BMC monitors and manages hardware components to ensure stable server operation. Furthermore, the CPLD allows for flexible configuration of hardware logic to meet diverse application requirements.

[0057] A card is a hardware module installed independently on the central management board (CMB) and equipped with specific functions, such as a network card, memory card, graphics card, or fan management card. Each card is used to perform a specific task. For example, a network card performs network communication tasks. A memory card stores data. A graphics card improves the server's computing speed and graphics processing capabilities. A fan management card controls the server's fans. The CMB can coordinate the operation of multiple cards to meet the needs of different application scenarios.

[0058] The Baseboard Management Controller (BMC) is a controller in the server that provides management for the central management board. As an independent processor embedded in the server, the BMC can be used to monitor the server's hardware and software information, health status, and operating status. It should be noted that BMC can also be called the Integrated Lights-Out (iLO), the Integrated Dell Remote Access (IDRAC), the Hardware Device Management (HDM), the Integrated Management Module (IMM), etc. The embodiment of this application does not limit the name of the BMC.

[0059] In some scenarios, the baseboard management controller can also be integrated into a control board other than the central management board. In the embodiment of the present application, the baseboard management controller is described as being arranged in the central management board.

[0060] A complex programmable logic device (CPLD) is a digital integrated circuit that allows users to customize their logic functions based on their needs. Its basic design approach uses an integrated development software platform, schematics, hardware description languages, and other methods to generate the corresponding target files. The code is then downloaded and stored via a download cable to implement the designed digital system.

[0061] Figure 1 This is a hardware architecture diagram of the server 10 provided in the embodiment of the present application. Figure 1 As shown, an embodiment of the present application provides a server 10 , which includes a first controller 1001 , a second controller 102 , a first register 1002 , and a board 401 .

[0062] In some embodiments, the power supply unit 300 is used to convert AC power to DC power, for example, converting 220V AC power to 12V DC power. Furthermore, the power supply unit 300 can transmit the converted power to the central management board 100 via the power adapter board 200, and the central management board 100 can then supply power to the board 401 plugged into the central management board 100.

[0063] The board 401 may include various boards plugged into the central management board 100, such as memory cards, graphics cards, fan management cards and other hardware modules with specific functions. When the server 10 is in the power-off state, the board 401 is also in the power-off state. The board 401 needs to be powered on before the server 10 can enter the working state. The complex programmable device includes a first controller 1001 and a first register 1002. The first register 1002 can be used to store a status value used to characterize the operating status of the server 10. And the number of bits of the first register 1002 can be predefined to set the data capacity of the first register 1002. For example, the number of bits of the first register 1002 is defined as 6 bits, and the status value can be represented by a 6-bit binary number. Taking the status value corresponding to the power-off state of the server 10 as 4 as an example, the 6-bit binary number in the first register 1002 should be arranged as "000100". In this way, the second controller 102 can convert the binary number in the first register 1002 into a status value, and further control the board 401 to perform power-on and power-off operations according to the status value.

[0064] The first controller 1001 is the control logic execution part in the complex programmable device. It can be connected to various components plugged into the central management board 100 through the preset hardware circuit interface on the central management board 100. In this way, the first controller 1001 can receive feedback signals from various components in different operating states, and determine the state value based on the received feedback signal, and then write the state value into the first register 1002, so that the second controller 102 can determine the operating status of the server 10.

[0065] The second controller 102 may be a BMC. During the power-on process, the second controller 102 may continuously read the status value in the first register 1002 to determine the current operating state of the server 10. After determining the operating state, the second controller 102 may execute an operation corresponding to the operating state. For example, if the second controller 102 determines that the current operating state of the server 10 is the power-on execution state, the second controller 102 may control the board 401 to power on.

[0066] It should be noted that while the server 10 is in the powered-off state, the first controller 1001, the first register 1002, and the second controller 102 can still receive power to continuously monitor the circuit status in the powered-off state. For example, the server 10 can still receive a power-on command input by the user in the powered-off state.

[0067] The second controller 102 can coordinate with the first controller 1001 to control the server 10 based on the status value stored in the first register 1002. For example, upon receiving a power-on command input by the user, the second controller 102 can control the board 401 to power on, so that the server 10 is in an operating state. For another example, upon detecting an abnormal power-on status value, the second controller 102 can control the board 401 to power off, so as to ensure that the server 10 does not cause a system failure due to a failure of an individual board 401.

[0068] Furthermore, the first controller 1001 provided on the central management board is connected to the second controller 102, the first register 1002, and the plurality of boards 401. The second controller 102 is also connected to the first register 1002 and the plurality of boards 401. This allows the first controller 1002 and the second controller 102 to jointly control the power-on process of the boards 401.

[0069] Figure 2 The timing diagram of the server 10 responding to the power-on instruction provided in the embodiment of the present application. Figure 2 As shown, when the first controller 1001 of the server 10 receives the power-on instruction, it writes the board power-on status value into the first register 1002.

[0070] In some embodiments, when a power-on button preset on the outside of the server 10 is triggered, the flag in the register corresponding to the power-on button changes. For example, when the power-on button is triggered, the flag in the register corresponding to the power-on button changes from 0 to 1. Thus, when the first controller 1001 detects that the flag in the register corresponding to the power-on button changes to 1, it can determine the board power-on status value corresponding to flag 1 and write the board power-on status value to the first register 1002.

[0071] It should be noted that writing the board power-on status value into the first register 1002 here may refer to modifying the status value recorded in the first register 1002 to the board power-on status value. When the server 10 is in a powered-off state, the status value recorded in the first register 1002 may be a status value corresponding to the powered-off state.

[0072] In other embodiments, the second controller 1002 may directly modify the flag in the register corresponding to the power-on button, for example, by setting the register corresponding to the power-on button to 1. Thus, when the first controller 1001 detects that the flag in the register corresponding to the power-on button has changed to 1, it may determine the board power-on status value corresponding to flag 1 and write the board power-on status value into the first register 1002.

[0073] It is understood that when the server 10 is in the power-off state, the state value in the first register 1002 is the state value corresponding to the power-off state. Therefore, when the server 10 receives a power-on command, the first controller 1001 implements a state transition by monitoring the identifier in the register corresponding to the power-on button and writing the board power-on state value to the first register 1002. The second controller 102 can then determine the current operating state of the server 10 based on the state value updated by the first controller 1001 and execute the control flow corresponding to the current operating state.

[0074] In this way, when the second controller 102 reads the board power-on status value from the first register 1002, it controls the board 401 to power on. The second controller 102 can send a control signal to the board 401. After receiving the control signal from the second controller 102, the board 401 can turn on its internal power supply, receive power from the central management board 100 via the internal power supply, and power various internal modules via the internal power supply, thereby completing the power-on process.

[0075] During the power-up process, the board 401 can also provide a power-on signal (PG, PowerGood) back to the first controller 1001. For example, PG = 1 indicates successful power-up, and PG = 0 indicates power-up failure. The first controller 1001 can obtain the power-up status of the board 401 and determine whether the state transition conditions are met based on the power-up status to implement the state transition and facilitate the second controller 102 to execute subsequent control processes based on the state transition result.

[0076] In this way, when at least one of the boards 401 experiences a power-on abnormality, the first controller 1001 writes the abnormal power-on status value into the first register 1002. When all the boards 401 are powered on, the working status value is written into the first register 1002. When the first controller 1001 writes a new status value into the first register 1002, the new status value overwrites the previous status value.

[0077] In some embodiments, the working status value can indicate that the server 10 is in a working state. When the first controller 1001 receives the power-on signal PG=1 fed back by the board 401, it can determine that the board 401 is powered on normally. Specifically, the first controller 1001 satisfies the state transition condition only when it receives the PG=1 fed back by all the boards 401, and then determines the working status value corresponding to the board 401 being powered on, and writes the working status value into the first register 1002. It is understandable that the first controller 1001 can match the power-on signal fed back by the received board 401 with the pre-set state transition condition. If a specific state transition condition is matched, the first controller 1001 can select the state value corresponding to the state transition condition and write the state value into the first register 1002. Then, the second controller 102 can execute the corresponding process according to the read state value.

[0078] In some embodiments, the abnormal power-on status value may indicate that the current operating state of the server 10 is a power-off execution state. When the first controller 1001 detects a power-on abnormality in at least one board 401, that is, when the first controller 1001 receives feedback from at least one board 401 that PG=0, it may determine the abnormal power-on status value corresponding to the power-on abnormality in the board 401 and write the abnormal power-on status value into the first register 1002.

[0079] In this way, the first controller 1001 can determine whether to trigger the state transition condition corresponding to the power-on abnormality of the board 401 based on the power-on signal fed back by the board 401, and promptly modify the state value in the first register 1002, so that the second controller 102 can promptly determine that the server 10 currently has a power-on abnormality by reading the state value in the first register 1002, and control the board 401 to power off. This is beneficial to prevent the overall operating state of the server 10 from being affected by the power-on abnormality of the board 401.

[0080] In other embodiments, the first controller 1001 can use a timer to record the power-on time of the board 401. When the power-on time of the board 401 exceeds a power-on time threshold, it can be considered that a power-on abnormality of the board 401 has been detected. For example, the power-on time threshold can be set to 800ms. In this way, if the first controller 1001 does not receive PG=1 feedback from the board 401 within 800ms, it can determine that the board 401 has a power-on abnormality, determine an abnormal power-on status value corresponding to the power-on abnormality of the board 401, and write the abnormal power-on status value into the first register 1002. The power-on time threshold can be stored in a corresponding threshold register.

[0081] In this way, the first controller 1001 can determine whether the board 401 is powered on normally based on the power-on time threshold, and can also limit the power-on time of the board 401 based on the power-on time threshold. When the board 401 is powered on abnormally, the status value in the first register 1002 is modified in time to make the server 10 enter the power-off execution state, thereby avoiding the power-on waiting time of the board 401 being too long, affecting the overall operation status of the server 10.

[0082] Furthermore, the first controller 1001 can control the timing of the board 401 during the power-on process based on the state transition conditions and the state value, and the second controller 102 can cooperate with the first controller 1001 to control the board 401 by reading the state value. This allows different tasks to be executed in different states of the server 10, which helps simplify the power-on control logic of the board 401.

[0083] In some embodiments, the central management board 100 may further include a power chip 402. The power supply port of the power chip 402 can supply power to the board 401 after power is applied. The power chip includes at least one power supply port for supplying power to the board 401. The power chip can be connected to the first controller, the second controller, and the plurality of boards 401.

[0084] To improve the stability and safety of the board 401 power-up process, it is necessary to first control the power-up of the power chip 402, and then control the power-up of the board 401. The power-up of the power chip 402 and the board 401 can be considered different operating stages. Therefore, a board power-up status value and a power chip power-up status value can be preset. Specifically, the board power-up status value indicates that the server 10 is in the board power-up state, while the power chip power-up status value indicates that the server 10 is in the power-up state.

[0085] In this way, different status values ​​can be generated by the first controller 1001 to limit the power-on sequence of the power chip 402 and the board 401 to ensure the stability and safety of the server power-on process.

[0086] Figure 3 The server 10 provided in the embodiment of the present application sequentially controls the internal timing diagram of the power chip 402 when it is powered on. Figure 3 As shown, when the first controller 1001 receives the power-on instruction, it can write the power-on status value of the power chip into the first register 1002 to synchronize the operating status of the server 10 with the second controller 102.

[0087] Thus, when the second controller 102 reads the power chip power-on status value in the first register 1002, it can execute the steps of controlling the power-on of the power chip 402. For example, the second controller 102 can send a control signal to the power chip 402 to control the power-on of the power chip 402, or to control the power-on of the power supply port of the power chip 402. The power-on of the power supply port of the power chip 402 can adopt a soft start method to improve the safety and stability of the power-on process.

[0088] During the power-on process, the power chip 402 can feed back a power-on signal to the first controller 1001 to indicate whether the power-on is successful. The first controller 1001 can then identify whether the power chip 402 is successfully powered on based on the power-on signal fed back by the power chip 402.

[0089] In this way, the first controller can write the abnormal power-on status value into the first register when at least one power supply port is powered on abnormally and / or the in-position status of at least one board 401 changes to abnormal. When all power supply ports are powered on and the in-position status of the board 401 does not change, the board power-on status value is written into the first register.

[0090] For example, when the first controller 1001 receives the power-on signal PG=0 fed back by the power chip 402, the first controller 1001 can determine that the power-on of the power chip 402 is abnormal, and then determine the abnormal power-on status value corresponding to the power-on abnormality of the power chip 402, and write the abnormal power-on status value into the first register 1002.

[0091] In this way, when the second controller 102 reads the abnormal power-on status value from the first register 1002, it can execute the step of controlling the power chip 402 to power off, so as to restore the server 10 to the power-off state, thereby preventing damage to other components in the server 10 caused by abnormal power-on of the power chip 402.

[0092] For another example, when the first controller 1001 receives the power-on signal PG=1 fed back by the power chip 402, the first controller 1001 can determine that the power chip 402 is powered on successfully, and then determine the board power-on status value corresponding to the successful power-on of the power chip 402, and write the board power-on status value into the first register 1002 to synchronize the operating status of the server 10 to the second controller 102.

[0093] In this way, based on the state transition result provided by the first controller 1001, the second controller 102 only needs to execute corresponding steps according to the state value read from the first register 1002. That is, when the second controller 102 reads the board power-on state value from the first register 1002, it controls the board 401 to power on.

[0094] Therefore, the control logic of the power chip 402 and the board 401 can be implemented by first controller 1001 determining the state transition condition, generating a state value, and then controlling the power chip 402 to power off by the second controller reading the state value. Furthermore, during the power-on process, by associating the state transition condition with the power-on signal, first controller 1001 can promptly synchronize the abnormal state to second controller 102 when a power-on abnormality occurs, allowing second controller 102 to promptly control the power chip 402 to power off, thereby protecting the components.

[0095] In addition, when the first controller 1001 is powered on successfully, it can also promptly synchronize the power-on success status to the second controller 102, so that the second controller 102 can promptly execute the control process corresponding to the subsequent status, thereby improving the power-on efficiency of the server 10.

[0096] Figure 4 This is a schematic diagram of the first power chip 402 providing power to the board 401 according to the embodiment of the present application. Figure 5 As shown, the power chip 402 includes a plurality of power supply ports, which can be connected to the board 401 to supply power to the board 401 when the power supply ports are powered on.

[0097] In some embodiments, the power supply ports may correspond one to one with the boards 401 , that is, each power supply port may supply power to one board 401 .

[0098] Figure 5 This is a schematic diagram of the second power chip 402 providing power to the board 401 according to the embodiment of the present application. Figure 6 As shown, in other embodiments, one power port can power multiple boards 401. For example, each power port of the power chip 402 powers two boards 401. If there are ten boards 401, these ten boards 401 can be powered by five power ports, with each power port corresponding to two boards 401.

[0099] It is understood that the connection relationship between the power supply port and the slot where the board 401 is located is pre-configured on the central management board 100. After the power supply port is successfully powered on, it can supply power to the board 401 in the corresponding slot according to the pre-configured connection relationship. After the board 401 is successfully powered on, it can receive power from the power supply port.

[0100] It should be noted that the power chip 402 can feed back the power-on status of the power supply port to the first controller 1001 during the power-on process. For example, when at least one power supply port is abnormally powered on, the power chip 402 can feed back the abnormal power-on signal PG=0 of the power supply port to the first controller 1001.

[0101] When the board 401 is inserted into the slot, it generates a presence signal, indicating that it has been inserted into the slot. The first controller 1001 can obtain the presence signal of the board 401 and modify the flag in the presence status register corresponding to the board 401 to indicate that the board 401 is in place.

[0102] The second controller 102 can obtain the information that the board 401 is in place, and then control the power supply port corresponding to the board 401 in the power chip 402 to power on.

[0103] Furthermore, in some embodiments, the state transition condition during the power-on phase of the power chip 402 may be composed of the power-on status of the power supply port and the in-place status of the board 401. That is, the first controller 1001 may determine whether the server 10 can enter the board-powered state based on the power-on status of the power supply port and whether the in-place status of the board 401 has changed.

[0104] For example, when the first controller 1001 receives an abnormal power-on signal with PG=0, it can match the state transition condition corresponding to the power-on abnormality and then write the power-on state value of the power chip corresponding to the state transition condition into the first register 1002 to synchronize the operating state of the server 10 with the second controller 102. Furthermore, when the second controller 102 reads the power-on state value of the power chip from the first register 1002, it can control the power chip 402 to power off to protect the various components in the server 10.

[0105] For another example, when the power supply port is being powered on, or when the power supply port is successfully powered on, the first controller 1001 detects that the in-place status of the board 401 has changed from in-place to abnormal, and may also match a state transition condition corresponding to the power-on abnormality, and then write the abnormal power-on state value corresponding to the state transition condition into the first register 1002 to synchronize the operating status of the server 10 with the second controller 102. Furthermore, when the second controller 102 reads the abnormal power-on state value from the first register 1002, it may control the power chip 402 to power off to protect the various components in the server 10.

[0106] The second controller 102 can control the power supply port to be powered on by modifying the flag in the register corresponding to the power supply port. For example, the flag in the register corresponding to the power supply port is set to 1. When the flag in the register is set to 1, the power chip 402 can power on the power supply port in a slow start manner.

[0107] In this way, by setting appropriate state transition conditions, the first controller 1001 can monitor whether the current power-on process is safe when determining whether the state transition conditions are met, and synchronize the operating state that the server 10 will subsequently enter to the second controller 102.

[0108] In some embodiments, if there are sequential requirements for powering up the power ports, different status values ​​can be set for different power ports to ensure a consistent power-up sequence. For example, for the first power port and the second power port, corresponding first and second power port status values ​​can be set. In this way, after the first power port is successfully powered up, the first controller 1001 can write the second power port status value to the first register 1002. The second controller 102 controls the powering up of the second power port only after reading the second power port status value.

[0109] In this way, by adding or removing status values ​​and setting status transition conditions corresponding to the status values, it is possible to adapt to a wider range of server 10 power-on scenarios. Furthermore, when a new board 401 is added to the power-on scenario, even if new timing control logic needs to be configured for the new board 401, only the status values ​​and state transition conditions need to be added, and the power-on control logic can still be reused, which helps reduce development time.

[0110] In some embodiments, when the second controller 102 reads the abnormal power-on status value from the first register 1002, it can determine that the server 10 is in an abnormal power-off state and needs to control the board 401 and / or the power chip 402 to power off. That is, when the second controller 102 reads the abnormal power-on status value from the first register and at least one board is abnormally powered on, it controls the board 401 and the power supply port to power off. The board 401 is powered off before the power supply port.

[0111] It is understood that, when controlling the power-off of the boards 401, the second controller 102 not only controls the power-off of the boards 401 that have experienced power-on anomalies, but also controls the power-off of the boards 401 that have successfully powered on. This prevents the normally powered-on boards 401 from experiencing operational malfunctions due to the abnormally powered-on boards 401, thereby protecting the boards 401. In this way, when a power-on anomaly occurs, the server 10 can be restored to a powered-off state and await a power-on instruction, which is also beneficial for protecting the boards 401 in the server 10.

[0112] The first controller 1001 can monitor the process of powering off the board 401 due to power-on abnormality. That is, when both the power chip 402 and the board 401 are powered off, the first controller 1001 writes the power-off status value into the first register 1002 .

[0113] In some embodiments, the power-off status value can be used to indicate that the operating state of the server 10 is a powered-off state. The first controller 1001 can determine whether the board 401 is successfully powered off by receiving a power-off signal fed back by the board 401 when it is powered off. After receiving the power-off signals fed back by all boards 401, the first controller 1001 can write the power-off status value into the first register 1002 to synchronize the server 10 with the second controller 102 to enter the powered-off state.

[0114] In other embodiments, the board 401 may have a corresponding power-on register, which stores a power-on identifier for characterizing the power-on status of the board 401. The first controller 1001 can determine the power-on / power-off status of the board 401 by reading the power-on identifier in the power-on register. For example, when the server 10 is in the power-off execution state, the first controller 1001 reads that the power-on identifiers in the power-on registers corresponding to all the boards 401 are "0", then it can be confirmed that all the boards 401 are powered off, and then the power-off status value can be determined based on the state that all the boards 401 are powered off. And the power-off status value is written into the first register 1002 to synchronize the current operating status of the server 10.

[0115] In this way, the first controller 1001 can monitor the power-off process of the board 401 due to a power-on anomaly, and then determine whether to write the power-off status value into the first register 1002 based on the state transition condition corresponding to the power-off status value to synchronize the operating state of the server 10. Furthermore, the method of the first controller 1001 monitoring the board 401 based on the signal or identifier generated in the hardware circuit has a higher timeliness, thereby more efficiently synchronizing the operating state of the server 10.

[0116] In some embodiments, the central management board 100 is provided with a power chip 402 and a board 401. Therefore, when an abnormality occurs during the power-on process of the power chip 402, the first controller 1001 can write an abnormal power-on status value to the first register 1002 to synchronize the abnormal power-on status of the server 10 with the second controller 102. The second controller 102 can control the power chip 402 to power off.

[0117] Furthermore, if an abnormality occurs during the power-on process of the board 401, the power chip 402 is already powered on. Therefore, the first controller 1001 can still write the abnormal power-on status value to the first register 1002 to synchronize the abnormal power-on status of the server 10 with the second controller 102. In this case, the second controller 102 needs to control the power-off of the board 401 first, and then control the power chip 402 to power off. This improves the safety of the power-off of the board 401 and prevents data loss, hardware damage, and other problems caused by sudden power failure of the board 401.

[0118] It should be noted that, when the second controller 102 reads an abnormal power-on status value, it can control the board 401 and the power chip 402 to power off by modifying the registers corresponding to the board 401 and the power chip 402. That is, when the second controller 102 reads an abnormal power-on status value, it can modify the registers in the order of powering off the board 401 first and then the power chip 402, thereby ensuring the control of the power-off timing of the board 401 and the power chip 402, thereby protecting the board 401 in the abnormal power-on scenario.

[0119] Figure 6 This is an internal sequence diagram of the server 10 provided in the embodiment of the present application when generating an abnormal log. Figure 6 As shown, in an embodiment of the present application, when a power-on anomaly occurs on board 401, an exception log can be generated to record the power-on anomaly of board 401, so as to facilitate subsequent troubleshooting and maintenance of the abnormal board 401 based on the exception log. Specifically, a state value corresponding to the generation of the exception log can be pre-set to cause server 10 to enter a state where the exception log is generated. This state can be placed before the power-off execution state to prevent difficulty in tracing the board that caused the anomaly after board 401 is powered off.

[0120] It should be noted that the server 10 further includes a second register 1003 , which can be used to store a first abnormality identifier for indicating abnormal power-on of the board 401 .

[0121] That is, the first controller 1001 writes the first abnormality flag into the second register 1003 before writing the abnormal power-on status value into the first register 1002 .

[0122] In some embodiments, the first abnormal record status value is used to represent the operating state of the server 10, which is a state of generating a log for representing the power-on abnormality of the board 401. The first controller 1001 can receive the power-on signal PG=0 fed back by the board 401 with the power-on abnormality, and then set the flag of the corresponding bit in the second register 1003 corresponding to the board 401 with the power-on abnormality to 1 to indicate that the board 401 has a power-on abnormality, so that the second controller 102 can read the flag from the second register 1003. In addition, after modifying the flag in the second register 1003, the first controller 1001 can determine that the server 10 needs to enter an abnormal power-on state, and then write the abnormal power-on state value into the first register.

[0123] In this way, when the second controller 102 reads the first abnormality record status value from the first register 1002, the server 10 generates a first abnormality log according to the first abnormality identifier stored in the second register 1003. The first abnormality identifier in the second register 1003 is deleted.

[0124] In some embodiments, the second controller 102 can continuously read the identifier stored in the second register 1003, such as the first exception identifier. Furthermore, when the second controller 102 reads the first exception identifier from the first register 1002, it can generate a first exception log based on the first exception identifier read from the second register 1003. The number of bits occupied by the second register 1003 can be predefined, and the power-on status of a board 401 can be recorded based on each bit in the second register 1003.

[0125] For example, bit 0 in second register 1003 is defined to record the power-on status of the fan management card. When a fan management card experiences a power-on anomaly, bit 0 is set to 1, indicating the fan management card power-on anomaly. In this way, bit 0 can be recorded as 1 in the first anomaly log. In subsequent troubleshooting, the first anomaly flag recorded in the first anomaly log can be used to determine that the fan management card experienced an anomaly during power-on.

[0126] In this way, the recording of power-on abnormalities of the board 401 is realized based on the register, and the first abnormality log is generated, as well as the method of setting a status value specifically for putting the server 10 in the abnormal log generation state, will not interfere with the timing of powering on / powering off of the board 401 due to power-on abnormalities. At the same time, the board 401 with power-on abnormalities can be recorded accurately and in real time, which is conducive to the tracing and maintenance of the abnormal board 401.

[0127] Furthermore, after generating the first exception log, the second controller 102 can modify the first exception flag recorded in the second register 1003, that is, delete the first exception flag. This can prevent the subsequent power-on process from being affected by the remaining first exception flag. Furthermore, it can enable the first controller 1001 to match the state transition condition based on the change in the flag in the second register 1003, so that the server 10 enters the subsequent power-off execution process.

[0128] In this way, when the first controller 1001 continuously reads the second register 1003 and detects that the first abnormal flag has been deleted, it can match the state transition condition corresponding to the abnormal power-on state value to determine the abnormal power-on state value, and write the abnormal power-on state value into the first register 1002 to synchronize the operating status of the server 10 to the second controller 102.

[0129] It is understood that after reading the abnormal power-on status value from the first register 1002, the second controller 102 may execute the operation steps corresponding to the abnormal power-on status value, that is, control the power chip 402 and / or the board 401 to power off. The process of the second controller 102 controlling the power chip 402 and / or the board 401 to power off has been described in detail in the previous embodiment and will not be repeated here.

[0130] Figure 7 This is the internal timing diagram of the target board powering off separately provided in the embodiment of the present application. Figure 7 As shown, the server 10 provided in the embodiment of the present application supports the power-off operation of the individual board 401 during operation. That is, the first controller 1001 writes the individual power-off state value into the first register 1002 when receiving the target board power-off instruction.

[0131] In some embodiments of the server 10, individual power-off status values ​​can be input via the second controller 102. Each board 401 has a corresponding individual power-off register, allowing the second controller 102 to individually control the power-off of a target board by modifying the value in the individual power-off register. Furthermore, the first controller 1001 can also read the individual power-off register to determine the status value based on the value recorded in the individual power-off register. For example, when a user inputs a power-off command for a fan management card, the second controller 102 can modify the flag in the individual power-off register corresponding to the fan management card so that the modified flag indicates that the fan management card needs to be powered off.

[0132] When reading the flags in the individual power-off register, the first controller 1001 reads a flag indicating that the fan management card needs to be powered off. It then matches the state transition condition corresponding to the individual power-off state value to determine the individual power-off state value. The individual power-off state value is then written into the first register 1002, causing the server 10 to enter the individual power-off state for the target board. This state is then synchronized with the second controller 102.

[0133] It should be noted that the identifier in the individual power-off register is only used to control the target board 401 corresponding to the identifier. That is, modifying a single identifier will not affect the power-on status of other boards 401. Thus, even if two boards 401 share a single power port, modifying the identifier in the individual power-off register will only power off the board 401 corresponding to the identifier, without affecting the power supply port to the other board 401. In other words, powering off a single board 401 will not affect other boards.

[0134] Based on this control method of being able to power off individually, it is beneficial to eliminate each board 401 one by one when an abnormality occurs in the operation of the server 10, which is beneficial to the problem tracing and maintenance, and thus maintain the stability of the operation of the server 10.

[0135] It is understood that, upon reading the independent power-off status value from the first register 1002, the second controller 102 may control the target board corresponding to the power-off instruction to be independently powered off. Furthermore, upon successfully independently powering off the target board, the second controller 102 may generate first prompt information indicating that the target board is ready for removal.

[0136] For example, when the second controller 102 reads the corresponding flag of the fan management card in the third register 1004 as 1, it determines that the fan management card has been successfully powered off and generates a first prompt message. The first prompt message can be used to indicate that the fan management card has been successfully powered off and can be removed. The first prompt message can be displayed in various ways, including, but not limited to, a lighting indicator or a buzzer.

[0137] Furthermore, after the second abnormality flag is deleted, the first controller 1001 can write the working status value into the first register 1002 to synchronize the server 10 with the second controller 102 to restore the server 10 to a normal working state. In this way, whether the target board is powered off successfully or unsuccessfully will not affect the normal operation of the server 10, which is conducive to improving stability in the scenario where the target board is powered off alone.

[0138] In addition, the value in the separate power-off register will not change after the target board is successfully powered off separately, so as to ensure that when the target board is powered on separately later, the target board is in an unpowered state when inserted into the slot of the central management board 100 to protect the target board.

[0139] In some embodiments, server 10 further includes a third register 1004 for storing a second exception flag. The second exception flag can be used to indicate an abnormality in the power-off of a target board. Furthermore, third register 1004 can use a multi-bit binary warning code to reflect different causes of the power-off failure, more clearly indicating the cause of the power-off failure and facilitating troubleshooting, tracing, and maintenance.

[0140] Figure 8 This is the internal timing diagram of the target board provided in the embodiment of the present application when it is abnormally powered off. Figure 8 As shown, when the first controller 1001 detects that the target board is abnormally powered off, it can write a second abnormality flag to the third register 1004 to enable the server 10 to enter a subsequent state. That is, when the target board is abnormally powered off, the first controller writes the second abnormality flag to the third register 1004. The second abnormality record status value is written to the first register.

[0141] For example, when the first controller 1001 detects that the target board card is powered off abnormally, it first writes the second exception flag into the third register 1004. Then, since the second exception flag is written into the third register 1004, the subsequent state transfer condition can be triggered, that is, the second exception record state value is written into the first register to synchronize this state to the second controller 102.

[0142] When the second controller 102 reads the second abnormality record status value from the first register 1002 , it can generate a second abnormality log according to the second abnormality identifier and delete the second abnormality identifier in the third register 1004 .

[0143] The second controller 102 can read the second exception identifier from the third register 1004 and generate a second exception log based on the second exception identifier, so that maintenance personnel can trace the target board power-off anomaly based on the second exception log. In addition, after generating the second exception log, the second controller 102 can delete the second exception identifier. On the one hand, it can prevent the remaining second exception identifier from affecting the subsequent separate power-off process. On the other hand, it can be used to enable the first controller 1001 to match the state transition condition so that the server 10 can be restored to a normal working state.

[0144] In this way, when the first controller 1001 detects that the second exception flag has been deleted during the process of reading the third register 1004, it can match the corresponding state transition condition and determine the working state value corresponding to the state transition condition, and then write the working state value into the first register 1002 to restore the server 10 to normal working state.

[0145] It should be noted that the failure of the target board card of server 10 to power off alone does not affect the normal operation of server 10. After the second controller 102 generates a second exception log for recording the failure of the target board card to power off alone, the server 10 can still be restored to a working state through the state transfer judgment of the first controller 1001.

[0146] It is understood that the process of individually powering off a target board only occurs when all boards 401 are powered on, that is, when server 10 is in operation. This method of individually powering off a target board allows for flexible replacement of the desired target board and accommodates other scenarios requiring individual target board replacement. Furthermore, the process of replacing a target board does not affect other boards or the normal operation of server 10.

[0147] Figure 9 This is the internal timing diagram of the target board provided in the embodiment of the present application when it is powered on separately. Figure 9 As shown, in some embodiments, after a target board is powered off individually, it can be powered on individually. After the target board is powered off individually, it can be removed from the slot of the central management board 100. Furthermore, during the process of powering on individually, the target board can be inserted into the slot first. In this case, the target board will not receive power even if it is inserted into the slot because the value in the individual power-off register has not changed.

[0148] After the target board is accurately inserted into the slot, the first controller 1001 may respond to the target board power-on instruction. That is, upon receiving the target board power-on instruction, the first controller 1001 writes the individual power-on status value into the first register 1002 .

[0149] In some embodiments, the target board power-on instruction may be inputted through the second controller 102, that is, the flag in the separate power-off register corresponding to the target board may be modified through the second controller 102. For example, the flag may be modified from 1 to 0 to indicate that the target board needs to be powered on.

[0150] When the first controller 1001 detects that the flag in the individual power-off register changes from 1 to 0, it can match the state transition condition corresponding to the individual power-on state value, determine the individual power-on state value, and write the individual power-on state value into the first register 1002. When the second controller 102 reads the individual power-on state value from the first register 1002, it can control the target board to power on individually.

[0151] It is understood that the target board has a corresponding register for recording the power-on / power-off status of the target board. Therefore, the second controller 102 can determine whether the target board has been successfully powered on by reading an identifier in the register. For example, if the second controller 102 reads an identifier corresponding to the target board from the fourth register 1005 and finds that it is 1, the target board can be determined to have been successfully powered on independently. Furthermore, the second controller 102 can generate a second prompt indicating that the target board has been successfully powered on independently.

[0152] It is understood that the second prompt information may include, but is not limited to, a flashing indicator light and a beeping buzzer. The flashing mode of the indicator light for the second prompt information may be different from that of the first prompt information, or the color of the indicator light may be different from that of the first prompt information, so as to facilitate the distinction between the power-on and power-off states of the target board. Similarly, the beeping mode of the buzzer should also be different.

[0153] Furthermore, when the target board is powered on successfully, the first controller 1001 can write the working state value into the first register. In this way, the first controller 1001 can quickly restore the server 10 to a normal working state after the independent power-on is completed.

[0154] Figure 10 This is an internal timing diagram of the target board that fails to power on independently provided by the embodiment of the present application. Figure 10As shown, in some embodiments, the server 10 further includes a fourth register 1005. The fourth register 1005 is used to store a third exception identifier, which can be used to indicate a power-on anomaly of a target board. The first controller 1001 can generate the third exception identifier and a status value based on the power-on status of the target board. Specifically, when a power-on anomaly occurs on the target board, the first controller 1001 writes the third exception identifier into the fourth register 1005 and writes the third exception record status value into the first register 1002.

[0155] For example, when the first controller 1001 receives a power-on signal PG=0 from the target board, or when the duration of waiting for the target board to return a power-on signal exceeds a power-on time threshold, the first controller 1001 sets the flag corresponding to the target board in the fourth register 1005 to 0, i.e., sets the flag to the third abnormality flag. Furthermore, after the third abnormality flag is written to the fourth register 1005, a state transition condition can be triggered, i.e., the first controller 1001 continues to write the third abnormality record state value to the first register to synchronize this state with the second controller 102.

[0156] In this way, when the second controller 102 reads the third abnormal record status value, it can generate a third abnormal log according to the third abnormal flag of the target board in the fourth register 1005 and delete the third abnormal flag in the fourth register 1005 .

[0157] After the third abnormality flag is deleted, the first controller 1001 writes the working status value into the first register 1002 to synchronize the status with the second controller 102 and restore the server 10 to a normal working state.

[0158] Deleting the third exception flag in the fourth register 1005 can, on the one hand, ensure the normal operation of subsequent target board cards when they are powered on / off separately, and on the other hand, enable the first controller 1001 to continue to trigger subsequent state transfer conditions to restore the server 10 to a normal operating state.

[0159] Furthermore, the functional architecture setting based on the target board's independent power-off / independent power-on can facilitate the debugging or replacement of an individual board, and the normal operation of the server 10 is not affected during the debugging or replacement process.

[0160] Figure 11 This is a reset diagram provided by the embodiment of the present application. Figure 11As shown, the server 10 also includes a reset button, which can be used to input a reset command to the server 10, thereby restoring the server 10 to a powered-off state. Upon receiving the reset command, the first controller 1001 controls the board 401 and / or the power chip 402 to power off. The board 401 is powered off before the power chip 402.

[0161] In some embodiments, the reset instruction is a reset method implemented by hardware circuits. When the server 10 receives the reset instruction, the value recorded in the reset register corresponding to the reset button changes, for example, from 0 to 1. Thus, when the first controller 1001 reads the value in the reset register and sees it change from 0 to 1, it can match the state transition condition corresponding to the reset, confirm the power-off state value corresponding to the state transition condition, and write the power-off state value to the first register 1002.

[0162] In this way, the first controller 1001 can restore the server 10 to the powered-off state. Therefore, in the scenario where the server 10 runs abnormally, the server 10 can be powered off by triggering the reset button to prevent the server 10 from running abnormally and causing damage to the board 401.

[0163] In addition, the first controller 1001 can also sequentially modify the values ​​in the registers used to control the power-on state of the board 401 to power off the board 401 based on hardware control, so that the board 401 is restored to the powered-off state. For example, the value in the register is set to 0 to control the corresponding board 401 to power off. Specifically, when the board 401 includes a power chip 402 and the board 401, and the power chip 402 is a power chip used to supply power to the board 401, the first controller 1001 can first modify the values ​​in the registers corresponding to the board 401 to 0 one by one, then modify the values ​​in the registers corresponding to the power supply ports of the power chip 402 to 0 one by one, and finally restore the power-on threshold register, warning code register, and other registers to the initial value of 0.

[0164] It should be noted that the reset instruction corresponds to the highest execution priority. When the server 10 receives the reset instruction, the first controller 1001 will immediately respond to the reset instruction to execute the relevant control process corresponding to the reset instruction.

[0165] It is understood that in the embodiment of the present application, the first controller 1001 may include three sections of control logic. One section is used to synchronize the operating status of the server 10. When a reset instruction is received (if (sys_rst == 1`b0)), the server 10 is restored to the state value of the power-off state, for example, power_current_state[5:0] <= STATE_STBY. The reset instruction is triggered by a low level, and [5:0] indicates that the state value is recorded from bit 0 to bit 5 of the occupied register.

[0166] When no reset instruction is received, the state value of the synchronization server 10 is the state value corresponding to the matched state transition condition, ie, power_current_state[5:0]<=power_next_state[5:0], so that the second controller 102 can execute the control steps corresponding to the subsequent state value.

[0167] The second section of control logic responds to power-on commands triggered by a button or register write. Upon receiving a power-on command, it determines the state transition conditions and generates the state transition results (i.e., if (bmc_write_pwrbtn_s == 1`b1), power_next_state[5:0] <= STATE_SOFTSTART_ON). If no power-on command is received, the power-off state remains unchanged (i.e., power_next_state[5:0] <= STATE_STBY).

[0168] The third section of control logic is used to respond to the reset instruction to restore the board 401 to the power-off state by modifying the hardware control method of the register, and to initialize registers such as the power-on threshold register and the warning code register so that the server 10 can enter the power-off state after receiving the reset instruction.

[0169] It should be noted that these three stages of control logic can run continuously based on the always statement, where the trigger conditions of the always statement can include a rising edge transition of the server 10 system clock and a falling edge transition of the reset signal. In this way, the triggering method based on the rising edge transition of the system clock can achieve a synchronous logic design, namely a three-stage state machine design. Furthermore, the triggering method based on the falling edge transition of the reset signal, combined with the relevant judgment statements and execution statements of the reset instruction, can ensure the highest execution priority of the reset instruction.

[0170] In this way, based on the three-stage control logic characteristics of the first controller 1001, the second controller 102 and the first controller 1001 can form a coordinated control of the power-on process of the server 10. Through simple and clear control logic, the power-on timing of the board 401 can be controlled, and the cause of the abnormality and the abnormal object can be accurately recorded when the board 401 is powered on abnormally, which is convenient for abnormal investigation, tracing and maintenance. Moreover, even when new components such as the board 401 are added to the server 10, it is only necessary to add corresponding state transfer conditions and state values ​​on the basis of the original control logic, so that the control logic can be reused on a large scale, which is conducive to reducing development costs.

[0171] Figure 12 This is the internal timing diagram of the board when it is powered off according to the embodiment of the present application. Figure 12 As shown, an embodiment of the present application further provides a server 10, which includes a central management board 100. The central management board 100 is provided with a first controller 1001, a second controller 102, a first register 1002, and a board 401. The board 401 can be used to implement a hardware module with specific functions, such as a graphics card, a memory card, a fan management card, etc. The first controller 1001 is connected to the second controller 102, the first register 1002, and a plurality of boards 401; the second controller 102 is connected to the first register 1002 and a plurality of boards 401. When the operating state of the server 10 is the working state, the boards 401 are all powered on.

[0172] The server 10 can receive a power-off instruction in the working state. When the first controller 1001 receives the power-off instruction, it can write a board power-off state value into the first register 1002. The board power-off state value is used to indicate that the operating state of the server 10 is the board power-off state.

[0173] The power-off command can be triggered by a power-off button or by modifying a register value. When the power-off button is triggered, the triggering result is also a register value change. Thus, when the first controller 1001 detects a change in the register value corresponding to the power-off button, it matches the state transition condition, determines the board power-off state value corresponding to the state transition condition, and writes the board power-off state value into the first register 1002. This can then cause the server 10 to enter the board power-off state and synchronize this state with the second controller 102.

[0174] Thus, when the second controller 102 reads the board power-off status value from the first register 1002, it can control the board 401 to power off. Specifically, it sends a control signal to the board 401 to control the board 401 to power off. The second controller 102 can control the board 401 to power off by modifying the register. Thus, when the first controller 1001 reads a change in the register value, it can match the state transition condition and determine the corresponding state value.

[0175] For example, when the first controller 1001 detects that all boards 401 are powered off, it can match a state transition condition corresponding to a power-off state value, determine the power-off state value, and write the power-off state value into the first register 1002. The power-off state value indicates that the operating state of the server 10 is powered off. In this way, the first controller 1001 can synchronize the operating state of the server 10 with the second controller 102, causing the second controller 102 to execute control steps corresponding to the powered-off state.

[0176] In this way, based on the state condition judgment and state transition capabilities provided by the first controller 1001, the second controller 102 can execute control steps corresponding to the state of the server 10. This helps simplify the control logic for powering off the board 401 and facilitates reuse. By adding or removing state values ​​and state transition conditions, it can adapt to newly added components such as the board 401.

[0177] Figure 13 This is the internal timing diagram of the power chip when it is powered off according to the embodiment of the present application. Figure 13 As shown, in some embodiments, the central management board 100 may also be provided with a power chip 402. The power chip 402 can supply power to the boards 401. The power chip is connected to the first controller, the second controller, and the plurality of boards 401. To prevent data loss or corruption caused by sudden power outages during the power-off process of the boards 401, the power-off sequence of the power chip 402 and the boards 401 needs to be controlled.

[0178] It is understandable that a power-off state value of the power chip corresponding to the power-off of the power chip 402 may be set, and the power-off sequence of the power chip 402 and the board 401 may be controlled by judging the state transition condition.

[0179] It should be noted that the power-off sequence for board 401 must precede the power-off sequence for power chip 402. That is, the first controller can write the power-off status value of the power chip into first register 1002 before writing the power-off status value into first register 1002. In this way, upon reading the power-off status value from first register 1002, second controller 102 can control power chip 402 to power off. Furthermore, when power chip 402 is powered off, first controller 1001 can write the power-off status value into first register 1002 to synchronize this status with second controller 102 and restore server 10 to a powered-off state.

[0180] In some embodiments, when the first controller 1001 monitors that the value in the register corresponding to the power-off instruction changes from 0 to 1, it can match the state transition condition corresponding to the power-off status value of the board card to determine the power-off status value of the board card, and write the power-off status value of the board card into the first register 1002 to synchronize the state to the second controller 102.

[0181] In this way, when the second controller 102 reads the board power-off status value from the first register 1002, it can prioritize controlling the power-off of the board 401. In some embodiments, the second controller 102 can control the power-off of the board 401 by modifying the value of a register related to the power supply of the board 401. In this way, the first controller 1001 can match the state transition condition by reading the value of a register related to the power supply of the board 401. For example, if the value of the register related to the power supply of the board 401 is 0, it can indicate that the board 401 has been powered off. If the value of the register related to the power supply of the board 401 is 1, it can indicate that the board 401 has not been powered off.

[0182] In this way, when the first controller 1001 reads the registers related to the power supply of the board 401 and all the registers are 0, it can further match the state transition condition corresponding to the power-off state value of the power chip, confirm the power-off state value of the power chip, and write the power-off state value of the power chip into the first register 1002. Then, the state corresponding to the power-off state value of the power chip is synchronized to the second controller 102.

[0183] In this way, when the board 401 is powered off, the board 401 can be controlled to be powered off first to prevent data loss or damage caused by sudden power off of the board 401. Then, the power chip 402 is controlled to be powered off, so that the server 10 is restored to the powered-off state.

[0184] In some embodiments, when the second controller 102 reads the power-off status value of the power chip from the first register 1002, it can execute control steps corresponding to the power-off status value of the power chip, i.e., control the power chip to power off. Specifically, the second controller 102 can control the power chip 402 to power off by modifying a register related to the power supply of the power chip 402, i.e., control the power supply port of the power chip 402 to power off.

[0185] In this way, the first controller 1001 can also determine whether the power chip 402 has been powered off by reading the registers associated with the power supply port. For example, if the first controller 1001 reads that the values ​​in the registers associated with the power supply port are all 0, it can match the state transition condition corresponding to the power-off state value, confirm the power-off state value, and write the power-off state value to the first register 1002, thereby restoring the server 10 to the powered-off state. It also synchronizes the server 10's entry into the powered-off state to the second controller 102.

[0186] Figure 14 This is a server power-on flow chart provided in the embodiment of this application. Figure 14 As shown, the embodiment of the present application provides a server power management method that can be applied to the normal power-on process of the server 10. The power-on method includes:

[0187] S100: In response to a received power-on instruction, a board power-on status value is written into a first register. The board power-on status value is used to indicate that the running state of the server is a power-on execution state.

[0188] S101: If at least one board is powered on abnormally, an abnormal power-on status value is written into the first register. The abnormal power-on status value is used to indicate that the running state of the server is a power-off state.

[0189] S102: If the plurality of boards are powered on, a working status value is written into the first register, wherein the working status value is used to indicate that the running status of the server is a working status.

[0190] Figure 15 This is a server power-off flow chart provided in the embodiment of this application. Figure 15 As shown, the embodiment of the present application provides a server power management method that can be applied to the normal power-off process of the server 10. The power-off method includes:

[0191] S201: In response to a received power-off instruction, write a board power-off state value into a first register, wherein the board power-off state value is used to indicate that the server is in a board power-off state.

[0192] S202: If multiple boards are powered off, write a power-off status value into the first register. The power-off status value is used to indicate that the server is in a powered-off state.

[0193] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without expending creative work shall fall within the scope of protection of this application.

Claims

1. A server, characterized in that: The server includes a central management board; the central management board is provided with a first controller, a second controller, a first register and a plurality of boards; the first controller is connected to the second controller, the first register and the plurality of boards; the second controller is connected to the first register and the plurality of boards; The first controller is configured to write the board power-on status value into the first register upon receiving a power-on instruction; The second controller is configured to control the power-on of the plurality of boards when the board power-on status value is read from the first register; The first controller is further configured to: When at least one of the boards is abnormally powered on, an abnormal power-on status value is written into the first register; the abnormal power-on status value is used to indicate that the running state of the server is an abnormal power-on state; When the plurality of boards are powered on, writing the working status value into the first register; The working status value is used to indicate that the running status of the server is a working status.

2. The server according to claim 1, wherein: The central management board is also provided with a power chip; the power chip includes at least one power supply port for supplying power to the board; the power chip is connected to the first controller, the second controller and the plurality of boards; The first controller is further configured to write the power-on status value of the power chip into the first register before writing the power-on status value of the board into the first register; when the second controller reads the power-on status value of the power chip, it controls the power supply port to be powered on; The first controller is further configured to: When at least one of the power supply ports is powered on abnormally, and / or the in-position state of at least one of the boards is changed to abnormal, writing the abnormal power-on state value into the first register; When the power supply ports are all powered on and the in-position state of the board card is unchanged, the power-on state value of the board card is written into the first register.

3. The server according to claim 2, wherein: The second controller is further configured to control the board and the power supply port to be powered off when the abnormal power-on status value is read from the first register and at least one of the board cards is powered on abnormally; wherein the power-off sequence of the board card is before the power-off sequence of the power supply port; The first controller is used to write a power-off status value into the first register when the board and the power supply port are both powered off; the power-off status value is used to indicate that the running status of the server is a powered-off state.

4. The server according to claim 1, wherein: The server further includes a second register; the second register is used to store a first abnormality identifier; the first abnormality identifier is used to indicate abnormal power-on of the board; The first controller is further configured to write the first abnormality flag into the second register before writing the abnormal power-on state value into the first register; Writing the first abnormal record status value into the first register; The second controller is configured to generate a first exception log according to the first exception identifier stored in the second register when the first exception record status value is read from the first register; and delete the first exception identifier in the second register; The first controller is further configured to write the abnormal power-on status value into the first register after the first abnormal flag is deleted.

5. The server according to claim 1, wherein: The first controller is further configured to write a separate power-off status value into the first register upon receiving a target board power-off instruction; The second controller is configured to control the target board to power off when the individual power-off status value is read from the first register; The second controller is further configured to generate a first prompt message for prompting that the target board is detachable when the target board is powered off successfully; The first controller is further configured to write the working status value into the first register when the target board is powered off successfully.

6. The server according to claim 5, wherein: The server further includes a third register; the third register is used to store a second abnormality identifier; the second abnormality identifier is used to indicate an abnormality in which the target board is powered off alone; The first controller is further configured to write the second abnormality identifier into the third register when the target board is abnormally powered off; and write the second abnormality record status value into the first register; The second controller is configured to generate a second exception log according to the second exception identifier when the second exception record status value is read from the first register; and delete the second exception identifier in the third register; The first controller is further configured to write the working status value into the first register after the second abnormality flag is deleted.

7. The server according to claim 5, wherein: The first controller is further configured to write a separate power-on status value into the first register upon receiving a target board power-on instruction; The second controller is configured to control the target board to power on when the individual power-on status value is read from the first register; The second controller is further configured to generate second prompt information for prompting that the target board is successfully powered on when the target board is successfully powered on; The first controller is further configured to write the working status value into the first register when the target board is powered on successfully.

8. The server according to claim 7, wherein: The server further includes a fourth register; the fourth register is used to store a third abnormality identifier; the third abnormality identifier is used to indicate abnormal power-on of the target board; The first controller is further configured to write the third abnormality identifier into the fourth register when the target board is powered on abnormally; and write the third abnormality record status value into the first register; The second controller is configured to generate a third exception log according to the third exception identifier when reading the third exception record status value from the first register; and delete the third exception identifier in the fourth register; The first controller is further configured to write the working status value into the first register after the third abnormality flag is deleted.

9. The server according to claim 1, wherein: The first controller is further configured to write a board power-off state value into the first register upon receiving a power-off instruction; the board power-off state value is used to indicate that the server is in a board power-off state; The second controller is configured to control the board to power off when the board power-off status value is read from the first register; The first controller is further configured to write a power-off status value into the first register when the plurality of boards are powered off; the power-off status value is configured to indicate that the server is in a powered-off state.

10. A server power management method, characterized in that: include: In response to the received power-on instruction, writing the board power-on status value into the first register; The board power-on state value is used to indicate that the server's operating state is a board power-on state; If at least one of the boards is powered on abnormally, writing the abnormal power-on status value into the first register; The abnormal power-on state value is used to indicate that the operating state of the server is an abnormal power-on state; If the boards are all powered on, writing the working status value into the first register; The working status value is used to indicate that the running status of the server is a working status.

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