In-memory computing module, in-memory computing method, device, storage medium

Abstract

The application provides a storage-in-computing module, a storage-in-computing method, equipment and a storage medium. The storage-in-computing module comprises a memory and a processing unit. The memory is connected with the processing unit. The processing unit is configured to receive a first instruction sent by a controller. If a second instruction is received within a preset number of current forward periods, the storage of second storage data corresponding to the second instruction is stopped, the second storage data is taken as first calculation data, calculation is performed according to the first calculation data and the first instruction, first storage data is obtained, and the first storage data is stored in the memory. After the storage-in-computing module of the application receives instructions with the same memory access address within a preset number of current forward periods, data is no longer read from the memory, but the storage data corresponding to the instruction is taken as calculation data for calculation, the number of times of accessing the memory to obtain data through a bus or a network is reduced, the delay is reduced, and the performance is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an in-memory computing module, an in-memory computing method, an apparatus, and a storage medium. Background Technology

[0002] In-memory computing is an emerging computing model that embeds computational tasks directly into data storage for processing. This avoids the frequent data transfers and complex memory management of traditional computing models, thereby improving computational efficiency and performance. In-memory computing technology has shown potential in various fields, from big data analytics to artificial intelligence applications, all of which can benefit from this revolutionary computing model.

[0003] In existing in-memory computing implementations, whenever a computation task involving stored data is encountered, the processor accesses the memory via the bus or network to retrieve the data, which leads to increased latency and decreased performance. Summary of the Invention

[0004] To address one of the aforementioned technical deficiencies, this application provides an in-memory computing module, an in-memory computing method, an apparatus, and a storage medium.

[0005] In a first aspect, this application provides an in-memory computing module, which includes: a memory and a processing unit;

[0006] The memory is connected to the processing unit;

[0007] The processing unit is used to receive a first instruction sent by the controller, wherein the first instruction is used to execute a memory access request; if a second instruction is received within a preset number of cycles forward, the storage of the second storage data corresponding to the second instruction is stopped, the second storage data is used as the first calculation data, calculation is performed according to the first calculation data and the first instruction to obtain the first storage data, and the first storage data is stored in the memory;

[0008] Both the second instruction and the first instruction include a memory access address, and they are identical.

[0009] Optionally, the read / write bit width of the memory is twice the data bit width it stores;

[0010] The memory supports simultaneous read and write operations on one odd address and one even address within the same cycle, but does not support simultaneous read and write operations on two odd addresses or two even addresses within the same cycle.

[0011] Optionally, the instructions include: data signals and computation signals;

[0012] Among them, the data signal is used to indicate the second computational data involved in the memory access request;

[0013] A computation signal is used to indicate whether a memory access request requires computation.

[0014] Address signals are used to indicate memory access addresses;

[0015] If the compute signal indicates that a memory access request requires compute, the instruction also includes: a type signal;

[0016] The type signal is used to indicate the first calculation type.

[0017] Optionally, if the calculation signal indicates that a memory access request is to be calculated, the instruction may further include: a self-processing signal;

[0018] Among them, the self-processing signal is used to indicate the self-processing value;

[0019] The in-storage calculation module also performs calculations of the first calculation type based on the second calculation data and the self-processed value to obtain the third storage data, and stores the third storage data in the memory.

[0020] Optionally, the processing unit is also configured to send an occupancy signal to the controller in the cycle preceding the storage of the first storage data into the memory;

[0021] The occupancy signal is used to prevent the upstream module from sending a third instruction. The third instruction includes a memory access address, and both of these addresses are either odd or even.

[0022] Optionally, the processing unit includes a computation subunit and registers;

[0023] The calculation subunit is used to perform calculations based on the first calculation data and the first instruction to obtain the first stored data; or, to perform calculations of the first calculation type based on the second calculation data and the self-processed value to obtain the third stored data.

[0024] Registers are used to store stored data calculated by the computing subunit, data read from memory, instructions, and data indicated in the instructions;

[0025] Data is stored in registers before being stored in memory by the processing unit.

[0026] A second aspect of this application provides an in-memory computing method, which is executed by the in-memory computing module as described in the first aspect above, the method comprising:

[0027] The processing unit receives a first instruction sent by the controller; wherein the first instruction is used to execute a memory access request;

[0028] The processing unit parses each signal in the first instruction; wherein the signals in the first instruction include: a data signal, a calculation signal, and an address signal; or, the signals in the first instruction include: a data signal, a calculation signal, an address signal, and a type signal; or, the signals in the first instruction include: a data signal, a calculation signal, an address signal, a type signal, and a self-processing signal; the data signal is used to indicate the second calculated data involved in the memory access request; the calculation signal is used to indicate whether the memory access request performs a calculation; the address signal is used to indicate the memory access address; the type signal is used to indicate the first calculation type; the self-processing signal is used to indicate the self-processing value; and, when the first instruction includes a type signal, the calculation signal indicates that the memory access request performs a calculation;

[0029] If the first instruction includes a self-processing signal, the processing unit performs a calculation of the first calculation type based on the second calculation data and the self-processing value to obtain the third storage data, and stores the third storage data in the memory;

[0030] If the first instruction does not include a self-processing signal but includes a type signal, when the processing unit receives the second instruction within a preset number of cycles forward, it stops storing the second stored data corresponding to the second instruction and uses the second stored data as the first calculation data; it performs calculations based on the first calculation data and the first instruction to obtain the first stored data and stores the first stored data in the memory;

[0031] Both the second instruction and the first instruction include a memory access address, and they are identical.

[0032] Optionally, the processing unit performs calculations based on the first calculation data and the first instruction to obtain the first stored data, including:

[0033] The processing unit determines the fourth calculation data and the second calculation type from the first instruction;

[0034] The processing unit performs a second type of calculation between the first calculated data and the fourth calculated data to obtain the first stored data.

[0035] In a third aspect, this application provides an electronic device that includes the in-memory computing module described in the first aspect above.

[0036] In a fourth aspect of this application, a computer-readable storage medium is provided that is connected to the electronic device described in the third aspect above; and a computer program is stored on the computer-readable storage medium; the computer program is executed to implement the method described in the second aspect above.

[0037] This application provides an in-memory computing module, an in-memory computing method, an apparatus, and a storage medium. The in-memory computing module includes a memory and a processing unit; wherein the memory and the processing unit are connected; the processing unit is configured to receive a first instruction sent by a controller, wherein the first instruction is used to execute a memory access request; if a second instruction is received within a preset number of forward cycles, the storage of the second memory corresponding to the second instruction is stopped, the second memory is used as first calculation data, calculations are performed based on the first calculation data and the first instruction to obtain the first memory data, and the first memory data is stored in the memory; wherein both the second instruction and the first instruction include a memory access address, and the two are the same. The in-memory computing module of this application includes a memory and a processing unit; wherein, after the processing unit receives an instruction with the same memory access address within a preset number of forward cycles, it no longer reads data from the memory, but stops storing the memory data corresponding to the instruction, and uses the stored data as calculation data for calculation, thereby reducing the number of times data is accessed from the memory via the bus or network, reducing latency, and improving performance. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0039] Figure 1 This is a schematic diagram of the structure of an in-memory computing module provided in an embodiment of this application;

[0040] Figure 2 This is a schematic diagram of an in-memory computing module provided in an embodiment of this application during practical application;

[0041] Figure 3 This is a flowchart illustrating an in-memory computing method provided in an embodiment of this application. Detailed Implementation

[0042] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0043] In developing this application, the inventors discovered that in-memory computing is an emerging computing model that embeds computational tasks directly into data storage for processing. This avoids the frequent data transfers and complex memory management inherent in traditional computing models, thereby improving computational efficiency and performance. In-memory computing technology shows potential in various fields, from big data analytics to artificial intelligence applications, all of which can benefit from this revolutionary computing model. In existing in-memory computing implementations, whenever a computational task involving stored data is encountered, the processor accesses memory via a bus or network to retrieve the data, leading to increased latency and decreased performance.

[0044] To address the aforementioned issues, this application provides an in-memory computing module, an in-memory computing method, an apparatus, and a storage medium. The in-memory computing module includes a memory and a processing unit; the memory and processing unit are connected. The processing unit receives a first instruction sent by a controller, wherein the first instruction is used to execute a memory access request. If a second instruction is received within a preset number of forward cycles, the storage of the second stored data corresponding to the second instruction is stopped, and the second stored data is used as first computational data. Calculations are performed based on the first computational data and the first instruction to obtain the first stored data, which is then stored in the memory. Both the second and first instructions include a memory access address, and they are identical. The in-memory computing module of this application includes a memory and a processing unit. When the processing unit receives an instruction with the same memory access address within a preset number of forward cycles, it no longer reads data from the memory but stops storing the stored data corresponding to the instruction, using the stored data as computational data for calculation. This reduces the number of times data is accessed from the memory via a bus or network, reducing latency and improving performance.

[0045] See Figure 1 This embodiment provides an in-memory computing module, which includes a memory and a processing unit.

[0046] The memory is connected to the processing unit. Furthermore, the memory and processing unit are very close together, ensuring that the processing unit can complete the task of reading data from the memory within one cycle.

[0047] 1. Memory

[0048] A memory used to store data.

[0049] The read / write bit width of the memory is twice the data bit width it stores (e.g., if the stored data is 512 bits, then the read / write bit width of the memory is 1024 bits). This configuration allows data to be read from half the bit width and written to the other half in the same cycle, thus ensuring simultaneous read and write operations on the memory within the same cycle and improving the computation speed of the computing modules within the memory.

[0050] Furthermore, the memory supports simultaneous read / write operations on one odd address and one even address within the same cycle, but not on two odd addresses or two even addresses within the same cycle. This configuration ensures simultaneous processing of odd and even addresses within the same cycle, improving the computation speed of the memory's internal computing modules.

[0051] 2. Processing Unit

[0052] The processing unit is used to receive a first instruction sent by the controller. If a second instruction is received within a preset number of forward cycles, the storage of the second stored data corresponding to the second instruction is stopped, the second stored data is used as the first calculation data, calculation is performed according to the first calculation data and the first instruction to obtain the first stored data, and the first stored data is stored in the memory.

[0053] The first instruction is used to execute a memory access request, which is to access... Figure 1 The memory request in the in-memory computing module shown.

[0054] Both the second instruction and the first instruction include a memory access address, and they are identical. That is, the second instruction includes a memory access address, and the first instruction also includes a memory access address, and the memory access address included in the second instruction is the same as the memory access address included in the first instruction.

[0055] In practice, the instructions include: data signals, calculation signals, and address signals.

[0056] 1) Data signal

[0057] A data signal is used to indicate the second computed data involved in the memory access request. This second computed data is the data involved in the execution of the memory access request by the instruction.

[0058] The data indicated by the data signal may be used for calculation and then stored. Figure 1 The memory of the in-memory computing module shown may also not be used for computation, and the data may be directly stored. Figure 1 The memory of the in-memory computing module shown.

[0059] Figure 2 This diagram illustrates the in-memory computing module provided in this embodiment during practical application. Figure 2 In this context, "Data" refers to the data signal.

[0060] It should be noted that Figure 2 The Data in this example is just one example of a data signal. In a specific implementation, the data signal can be other than that, and this embodiment does not limit it.

[0061] 2) Calculate the signal

[0062] The computation signal indicates whether a memory access request requires computation. In other words, the data indicated by the data indicator signal is processed before being stored. Figure 1 The memory of the in-memory computing module shown in the diagram still does not perform calculations; it is directly stored. Figure 1 The memory of the in-memory computing module shown.

[0063] like Figure 2 In this context, AccEn is a computation signal used to indicate that a memory access request should be computed. AccUn is also a computation signal used to indicate that a memory access request should not be computed.

[0064] It should be noted that Figure 2 The AccEn and AccUn in the example are just examples of computation signals. In a specific implementation, the computation signal can be other than the one used to indicate that a memory access request should be computed. The computation signal used to indicate that a memory access request should not be computed can also be other than the one used to indicate that a memory access request should not be computed. This embodiment does not limit this.

[0065] 3) Address signals

[0066] Address signals are used to indicate memory access addresses.

[0067] The memory access address is Figure 1 The address in the memory of the in-memory computing module shown.

[0068] The memory access address indicated by the address signal is the address at which the instruction needs to store data in memory. If the calculation signal indicates that the memory access request requires calculation, then the address indicated by the address signal is the address at which the calculation result is stored in memory after the data indicated by the data signal is calculated. If the calculation signal indicates that the memory access request does not require calculation, then the address indicated by the address signal is the address at which the data indicated by the data signal is stored in memory.

[0069] Furthermore, if the calculation signal indicates a memory access request to perform a calculation, then the address indicated by the address signal is not only the address where the calculation result is stored in memory, but also the address of another piece of data to be calculated during the calculation. In other words, if the calculation signal indicates a memory access request to perform a calculation, the processing unit will first read the data stored at the memory access address, perform a calculation with the data indicated by the data signal and the read data stored at the memory access address, and then store the calculation result back at the address indicated by the address signal.

[0070] like Figure 2 Addr in this context refers to the address signal.

[0071] It should be noted that Figure 2 Addr in this example is just one example of an address signal. In a specific implementation, the address signal can be other than that. This embodiment does not limit this.

[0072] If the calculation signal indicates that a memory access request is to be performed, then the instruction will also include a type signal.

[0073] Of course, in a specific implementation, if the calculation signal indicates that the memory access request does not require calculation, the instruction may also include a type signal, but it can be empty or other pre-agreed content. This embodiment does not limit the other signals included in the instruction when the calculation signal indicates that the memory access request does not require calculation.

[0074] 4) Type signal

[0075] The type signal is used to indicate the first calculation type.

[0076] like Figure 2 The AccType in the code is the type signal.

[0077] It should be noted that Figure 2 The AccType in this example is just one example of a type signal. In a specific implementation, the type signal can be other types as well, and this embodiment does not limit it.

[0078] 5) Self-processing signals

[0079] If the calculation signal indicates that a memory access request is to be performed, the instruction also includes: a self-processing signal.

[0080] The self-processing signal is used to indicate the self-processing value.

[0081] The in-storage calculation module also performs calculations of the first calculation type based on the second calculation data and the self-processed value to obtain the third storage data, and stores the third storage data in the memory.

[0082] In a practical implementation, the processing unit includes a computation subunit and registers.

[0083] The calculation subunit is used to perform calculations based on first calculation data and first instructions to obtain first stored data. Alternatively, it can perform calculations of a first calculation type based on second calculation data and self-processed values ​​to obtain third stored data.

[0084] Registers are used to store stored data calculated by the computing subunit, data read from memory, instructions, and data indicated in the instructions.

[0085] Data is stored in registers before being stored in memory by the processing unit.

[0086] In other words, the computation subunit is used to implement the computational tasks of the processing unit, and the register is used to store all data involved in the processing unit, including all data transmitted from outside the processing unit and all data generated by the processing unit itself. Since it is impossible to exhaustively list all possible operations, this embodiment and subsequent embodiments do not limit the types of operations that the computation subunit can perform, nor the specific sources of the data stored in the register.

[0087] like Figure 2 In this context, Calculator refers to the calculation subunit, and Result refers to the register of the processing unit.

[0088] In other words, when an instruction only needs to store one piece of data, the instruction will only include a data signal, a calculation signal, and an address signal. The data signal is used to indicate the data to be stored (i.e., the second calculated data, which is stored in the processing unit's register), the calculation signal is used to indicate that no calculation is performed, and the address signal is used to indicate the memory access address (i.e., the storage location of the second calculated data). Subsequently, the processing unit will store the second calculated data in the storage location (the processing unit will retrieve the second calculated data from the register and then store it in the storage location).

[0089] When an instruction only needs to store the result of an operation between one piece of data and another piece of data already stored in memory (referred to as the third computed data for ease of description), the instruction includes a data signal, a computed signal, an address signal, and a type signal. The data signal indicates a piece of data (i.e., the second computed data, which is stored in a register of the processing unit); the computed signal indicates that a computation should be performed; the address signal indicates the memory access address (i.e., the storage location of the third computed data, which is also the storage location of the computation result); and the type signal indicates the first computation type (i.e., the computation type between the second and third computed data, such as addition or multiplication, which is also stored in a register). The processing unit determines whether there are other instructions (i.e., second instructions) indicating the storage location of the third calculated data in the current processing unit. If there are no second instructions, the processing unit reads the third calculated data from the memory access address (i.e., the storage location of the third calculated data) and stores the read third calculated data in the processing unit's register. The processing unit's calculation subunit performs a first calculation type calculation on the second and third calculated data to obtain the first stored data (the first stored data is stored in the register). Subsequently, the processing unit stores the first stored data in the storage location (the processing unit retrieves the first stored data from the register and then stores it in the storage location). If there is a second instruction (it should be noted that from the perspective of the first instruction, the data stored at the memory access address is the third calculated data, but from the perspective of the second instruction, the data stored at the memory access address is the second stored data; for example, if the second instruction calculates data x and stores x in the memory access address X, then x is the second stored data of the second instruction. Subsequently, when the first instruction is executed, x will be read from the memory access address X. At this time, for the first instruction, x is the third calculated data).In other words, in this case, the third calculated data and the second stored data are actually the same data, only at different stages (one is the calculation result of the preceding instruction, and the other is the data read in the subsequent instruction). This means that the third calculated data is the stored data of the second instruction (that is, the second stored data). At this time, there is no need for the second instruction to store the second stored data at the memory access address, and for the first instruction to read from the memory access address, because reading would cause a delay. Instead, the storage of the second stored data corresponding to the second instruction will be stopped (and it will only be stored in the register). The second stored data will be directly used as the first calculated data. Calculation will be performed based on the first calculated data and the first instruction (that is, the calculation subunit of the processing unit will perform the first calculation type calculation on the second calculated data and the first calculated data (at this time, the first calculated data is the second stored data, which is also the third calculated data, i.e., the three are actually the same data, just with multiple names), thus reducing one memory write and read operation). The first stored data will be obtained (the first stored data will be stored in the register). Subsequently, the processing unit will store the first stored data in the storage location (the processing unit will retrieve the first stored data from the register and then store it in the storage location).

[0090] In this case, stopping the storage process of the second data corresponding to the second instruction can be achieved by: canceling the first instruction's data reading from memory; sending an indication signal to the computing subunit and bypassing it internally.

[0091] When an instruction only needs to store the result of a self-operation on a single data item (such as incrementing the data by one), the instruction includes a data signal, a calculation signal, an address signal, a type signal, and a self-processing signal. The data signal indicates a data item (i.e., the second calculated data, which is stored in the processing unit's register); the calculation signal indicates that a calculation is to be performed; the address signal indicates the memory access address (i.e., the storage location of the calculation result); the type signal indicates the first calculation type (i.e., the calculation type of the second calculated data, such as addition, which is also stored in the register); and the self-processing signal indicates the self-processing value (such as 1). The processing unit performs a calculation of the first calculation type (e.g., calculating second calculated data = second calculated data + 1) on the second calculated data and the self-processing value to obtain the first stored data (which is stored in the register). Subsequently, the processing unit stores the first stored data in the storage location (the processing unit retrieves the first stored data from the register and then stores it in the storage location).

[0092] In other words, the in-storage computing module provided in this embodiment can be used for various scenarios such as data storage, storage of data after its own calculation, and storage of data after calculation with existing data.

[0093] Furthermore, in scenarios where data is calculated and stored along with existing data, the storage location of the existing data is the same as the storage location of the calculation result. For example, the processing unit first reads the data stored at the memory access address (this data is the third calculation data), performs calculations on the data indicated by the data signal and the read data stored at the memory access address (i.e., the third calculation data), and then stores the calculation result back at the address indicated by the address signal.

[0094] In other words, when a calculation signal indicates a memory access request to perform a calculation, the processing unit will perform the calculation required by the instruction on a data already existing in memory and the data carried by the instruction. The calculation result will replace the data already existing in memory as the new value, thereby updating the data stored in memory.

[0095] This process can be used for calculations in various scenarios such as AI and sparse matrices. Therefore, the in-memory computing module provided in this embodiment can also be used in various scenarios such as AI and sparse matrices. This embodiment does not limit the application scenarios of the in-memory computing module.

[0096] For ease of explanation, the following description will only use the scenario of storing data after calculation with existing data as an example to introduce the implementation details of the in-storage calculation module provided in this embodiment. For other scenarios, please refer to the scenario of storing data after calculation with existing data, which will not be repeated here.

[0097] The preset quantity can be determined based on the depth of the production line. The deeper the production line, the larger the preset quantity. For example, the preset quantity is 3.

[0098] Figure 2 In the scenario shown, the preset data is 3. If the second instruction is received within the current three cycles, it means that the data stored at the memory access address (indicated by the address signal of the first instruction) included in the first instruction has already been read from the memory in the processing unit (i.e., read from the memory when processing the second instruction). At this time, the existing technology will still read the data from the memory access address, and the process of reading the data will lead to increased latency and decreased performance.

[0099] The processing unit of the in-memory computing module provided in this embodiment does not read the data from the memory access address. Instead, it stops storing the second stored data corresponding to the second instruction, uses the second stored data as the first computing data, performs calculations based on the first computing data and the first instruction to obtain the first stored data, and stores the first stored data in the memory.

[0100] In other words, the processing unit of the in-memory computing module provided in this embodiment stops storing the second stored data after executing the second instruction (this second stored data may or may not be the calculation result data; when the calculation signal of the second instruction indicates a memory access request to perform calculation, the second stored data is the calculation result data; when the calculation signal of the second instruction indicates that the memory access request does not perform calculation, the second stored data is not the calculation result data, but the data indicated by the data signal of the second instruction). Instead, the second data is directly used as a computed value in the calculation of the first instruction, and after performing the calculation with the data indicated by the data signal of the first instruction, the calculation result at this time (i.e., the first stored data) is stored in the memory. This saves one data read from the memory, reduces latency, and improves performance.

[0101] In the above process, the processing unit parses each signal in the first instruction (such as data signals, calculation signals, and address signals) in one cycle, and when the calculation signal indicates a memory access request to perform calculation, it acquires the data indicated by the address signal (this acquisition may be from memory or not; if the second instruction is not received within a preset number of cycles forward, it is read from memory; if the second instruction is received within a preset number of cycles forward, the data corresponding to the second instruction is directly acquired). Then, it executes the signal in one cycle (e.g., when the calculation signal indicates a memory access request to perform calculation, the calculation indicated by the type signal is performed). In the third cycle, it stores the calculation result in the processing unit's register. Finally, in the fourth cycle, it writes the data corresponding to the first instruction (the data corresponding to the first instruction is the first stored data; the first stored data may be the calculation result data or not; when the calculation signal of the first instruction indicates a memory access request to perform calculation, the first stored data is the calculation result data; when the calculation signal of the first instruction indicates no calculation, the first stored data is not the calculation result data, but the data indicated by the data signal of the first instruction) into memory.

[0102] The above analysis shows that an instruction takes four cycles to complete. Furthermore, the second cycle does not involve memory reads, allowing processing of the next instruction to begin. In the first cycle, instruction 1 is parsed, and the data indicated by the address signal is obtained when the calculation signal indicates a memory access request for calculation. In the second cycle, the calculation subunit calculates instruction 1, and simultaneously parses instruction 2, obtaining the data indicated by the address signal when the calculation signal indicates a memory access request for calculation. In the third cycle, the calculation result of instruction 1 is stored in the register of the processing unit. At the same time, the calculation subunit calculates instruction 2, and can also parse instruction 3, obtaining the data indicated by the address signal when the calculation signal indicates a memory access request for calculation. In the fourth cycle, the calculation result of instruction 1 stored in the register of the processing unit is written into the memory (at this time, instruction 1 has been executed). At the same time, the calculation result of instruction 2 is stored in the register of the processing unit. Simultaneously, the calculation subunit calculates instruction 3, and can also parse instruction 4, obtaining the data indicated by the address signal when the calculation signal indicates a memory access request for calculation. ... Through the above process, parallel processing of instructions can be achieved, further improving the performance of the in-memory calculation module provided in this embodiment.

[0103] Furthermore, while memory supports simultaneous read / write operations at one odd and one even address within the same cycle, it does not support simultaneous read / write operations at two odd or two even addresses within the same cycle. As seen in the processing flow of the aforementioned processing unit, within the same cycle, one instruction can be written to memory (e.g., memory address 1), one instruction can be stored in the processing unit's registers (this process does not involve memory read / write), one instruction can be computed (this process also does not involve memory read / write), and one instruction can be parsed, potentially retrieving data from memory (e.g., memory address 2). This results in two memory addresses within the same cycle, one for writing data and one for reading data. The requirement that the memory's read / write bit width be twice its data storage bit width is sufficient to support simultaneous read / write operations within the same cycle. However, since memory does not support simultaneous read / write operations at two odd or two even addresses within the same cycle, it is necessary to ensure that memory address 1 and memory address 2 cannot both be odd or both be even addresses simultaneously. During execution, the processing unit is also configured to send an occupancy signal to the controller in the cycle preceding the storage of the first memory data into the memory, such as... Figure 2 Occupy in the context of .

[0104] The occupancy signal is used to prevent the upstream module from sending a third instruction. This third instruction includes a memory access address, and both must be either odd or even addresses. In other words, the occupancy signal tells the upstream module that it can no longer send memory accesses with conflicting addresses.

[0105] The occupancy signal ensures that memory address 1 and memory address 2 cannot both be odd addresses or both be even addresses.

[0106] The execution process of the in-memory computing module provided in this embodiment will be explained again below. Figure 3 A flowchart of an in-memory computing method is shown, which is a feasible implementation of an in-memory computing module.

[0107] 301, The processing unit receives the first instruction sent by the controller.

[0108] The first instruction is used to execute the memory access request.

[0109] 302, The processing unit parses the signals in the first instruction.

[0110] The signals in the first instruction include: a data signal, a calculation signal, and an address signal (i.e., for data storage scenarios); or, the signals in the first instruction include: a data signal, a calculation signal, an address signal, and a type signal (i.e., for storage scenarios after data is calculated with existing data); or, the signals in the first instruction include: a data signal, a calculation signal, an address signal, a type signal, and a self-processing signal (i.e., for storage scenarios after data itself is calculated).

[0111] Data signals are used to indicate the second computational data involved in the memory access request.

[0112] The calculation signal indicates whether a memory access request requires calculation. The address signal indicates the memory access address.

[0113] A type signal indicates the first calculation type. A self-processing signal indicates the self-processed value. Furthermore, when the first instruction includes a type signal, the calculation signal indicates a memory access request to perform a calculation.

[0114] 303. If the first instruction includes a self-processing signal, the processing unit performs a calculation of the first calculation type based on the second calculation data and the self-processing value to obtain the third storage data, and stores the third storage data in the memory.

[0115] In the storage scenario after the data itself is calculated, the processing unit performs a calculation of the first calculation type based on the second calculated data and the self-processed value to obtain the third stored data, and stores the third stored data in the memory.

[0116] 304. If the first instruction does not include a self-processing signal but includes a type signal, when the processing unit receives the second instruction within a preset number of cycles forward, it stops storing the second stored data corresponding to the second instruction and uses the second stored data as the first calculation data. Calculations are performed based on the first calculation data and the first instruction to obtain the first stored data, and the first stored data is stored in the memory. When the processing unit does not receive the second instruction within the preset number of cycles forward, it reads the data stored at the memory access address, uses the read data stored at the memory access address as the first calculation data, performs calculations based on the first calculation data and the first instruction to obtain the first stored data, and stores the first stored data in the memory.

[0117] Both the second instruction and the first instruction include a memory access address, and they are identical.

[0118] In the storage scenario after the data is calculated and stored, if the existing data already exists in the current processing unit, it is used directly; if the existing data does not exist in the current processing unit, it is read from the memory.

[0119] Furthermore, the process by which the processing unit calculates the first stored data based on the first calculated data and the first instruction is as follows: 1) The processing unit determines the fourth calculated data and the second calculated type from the first instruction. 2) The processing unit performs a calculation of the second calculated type between the first calculated data and the fourth calculated data to obtain the first stored data.

[0120] 305. If the first instruction does not include a type signal, the processing unit stores the second computational data in memory.

[0121] This refers to scenarios where data is stored directly.

[0122] It should be noted that the first instruction, the second instruction, and the third instruction involved in this embodiment and subsequent embodiments are all used to execute memory access requests. The memory access requests corresponding to the first instruction, the second instruction, and the third instruction may be the same or different, and this embodiment does not limit this.

[0123] Furthermore, both the first and second stored data are the results of calculations based on instructions, and these results need to be stored in the memory. While the first and second stored data are obtained by calculations based on different instructions, the calculation processes for obtaining the first and second stored data can be the same or different, and their values ​​can also be the same or different. This embodiment does not limit whether the calculation processes for obtaining the first and second stored data are the same, or whether their values ​​are the same.

[0124] Furthermore, both the first calculated data and the second calculated data are data indicated by data signals in the instruction, and both are data involved in the memory access request executed by the instruction. The instruction involved in the first calculated data and the instruction involved in the second calculated data can be the same instruction or different instructions. The values ​​of the first calculated data and the second calculated data can be the same or different. This embodiment does not limit whether the instructions involved in the first calculated data and the second calculated data are the same, or whether the values ​​of the first calculated data and the second calculated data are the same.

[0125] Furthermore, the result of the calculation based on the instructions needs to be stored in the memory. The first stored data and the second stored data are the results of calculations based on different instructions. However, the calculation processes for obtaining the first stored data and the second stored data can be the same or different, and the values ​​of the first stored data and the second stored data can also be the same or different. This embodiment does not limit whether the calculation processes for obtaining the first stored data and the second stored data are the same, or whether the values ​​of the first stored data and the second stored data are the same.

[0126] The first calculation type and the second calculation type are both calculation types, only located in different instructions. The terms "first" and "second" are merely used to identify which instruction the calculation instruction originates from and do not imply any other meaning. That is, the first calculation type and the second calculation type can be the same, such as both being addition calculations, or they can be different, such as one being an addition calculation and the other a multiplication calculation. This embodiment does not limit whether the first calculation type and the second calculation type are the same.

[0127] Based on the same inventive concept as an in-memory computing module, an electronic device includes an in-memory computing module, which includes the aforementioned... Figure 1 Or any of the in-memory computing modules shown in Figure 2.

[0128] The in-memory computing module includes: memory and processing unit.

[0129] The memory is connected to the processing unit.

[0130] The processing unit is configured to receive a first instruction sent by the controller, wherein the first instruction is used to execute a memory access request. If a second instruction is received within a preset number of forward cycles, the storage of the second memory corresponding to the second instruction is stopped, the second memory is used as the first calculation data, calculations are performed based on the first calculation data and the first instruction to obtain the first memory, and the first memory is stored in the memory.

[0131] Both the second instruction and the first instruction include a memory access address, and they are identical.

[0132] Optionally, the read / write bit width of the memory is twice the width of its stored data bit width.

[0133] The memory supports simultaneous read and write operations on one odd address and one even address within the same cycle, but does not support simultaneous read and write operations on two odd addresses or two even addresses within the same cycle.

[0134] Optionally, the instructions include: data signals and computation signals.

[0135] Among them, the data signal is used to indicate the second computational data involved in the memory access request.

[0136] A computation signal is used to indicate whether a memory access request requires computation.

[0137] Address signals are used to indicate memory access addresses.

[0138] If the compute signal indicates that a memory access request is to be computed, the instruction also includes: a type signal.

[0139] The type signal is used to indicate the first calculation type.

[0140] Optionally, if the calculation signal indicates that a memory access request is to be performed, the instruction may also include a self-processing signal.

[0141] The self-processing signal is used to indicate the self-processing value.

[0142] The in-storage calculation module also performs calculations of the first calculation type based on the second calculation data and the self-processed value to obtain the third storage data, and stores the third storage data in the memory.

[0143] Optionally, the processing unit is also configured to send an occupancy signal to the controller in the cycle preceding the storage of the first storage data into the memory.

[0144] The occupancy signal is used to prevent the upstream module from sending a third instruction. The third instruction includes a memory access address, and both of these addresses are either odd or even.

[0145] Optionally, the processing unit includes a computation subunit and a register.

[0146] The calculation subunit is used to perform calculations based on first calculation data and first instructions to obtain first stored data. Alternatively, it can perform calculations of a first calculation type based on second calculation data and self-processed values ​​to obtain third stored data.

[0147] Registers are used to store stored data calculated by the computing subunit, data read from memory, instructions, and data indicated in the instructions.

[0148] Data is stored in registers before being stored in memory by the processing unit.

[0149] The electronic device provided in this embodiment, after receiving an instruction with the same memory access address within a preset number of forward cycles, no longer reads data from the memory, but stops storing the stored data corresponding to the instruction and uses the stored data as calculation data for calculation. This reduces the number of times data is accessed from the memory via the bus or network, thereby reducing latency and improving performance.

[0150] Based on the same inventive concept as the in-memory computing module, a computer-readable storage medium is provided, which is connected to the aforementioned electronic device. The electronic device includes an in-memory computing module, which comprises the aforementioned... Figure 1 Or any of the in-memory computing modules shown in Figure 2.

[0151] Furthermore, a computer program is stored on the computer-readable storage medium. The computer program is executed to perform the above-described actions. Figure 3 The in-memory computation method is shown.

[0152] Specifically, the processing unit receives a first instruction sent by the controller. This first instruction is used to execute a memory access request.

[0153] The processing unit parses the signals in the first instruction. The signals in the first instruction include: a data signal, a calculation signal, and an address signal; or, the signals in the first instruction include: a data signal, a calculation signal, an address signal, and a type signal; or, the signals in the first instruction include: a data signal, a calculation signal, an address signal, a type signal, and a self-processing signal. The data signal indicates the second calculated data involved in the memory access request. The calculation signal indicates whether the memory access request requires calculation. The address signal indicates the memory access address. The type signal indicates the first calculation type. The self-processing signal indicates the self-processed value. Furthermore, when the first instruction includes a type signal, the calculation signal indicates that the memory access request requires calculation.

[0154] If the first instruction includes a self-processing signal, the processing unit performs a calculation of the first calculation type based on the second calculation data and the self-processing value to obtain the third storage data, and stores the third storage data in the memory.

[0155] If the first instruction does not include a self-processing signal but includes a type signal, when the processing unit receives the second instruction within a preset number of forward cycles, it stops storing the second stored data corresponding to the second instruction and uses the second stored data as the first calculated data. Calculations are performed based on the first calculated data and the first instruction to obtain the first stored data, which is then stored in the memory.

[0156] Both the second instruction and the first instruction include a memory access address, and they are identical.

[0157] Optionally, the processing unit performs calculations based on the first calculation data and the first instruction to obtain the first stored data, including:

[0158] The processing unit determines the fourth calculation data and the second calculation type from the first instruction.

[0159] The processing unit performs a second type of calculation between the first calculated data and the fourth calculated data to obtain the first stored data.

[0160] The computer-readable storage medium provided in this embodiment allows a computer program thereon to be executed by a processor. After receiving an instruction with the same memory access address within a preset number of forward cycles, the program stops reading data from the memory and instead stops storing the data corresponding to the instruction. The stored data is then used as computational data for calculation, reducing the number of times data is accessed from the memory via a bus or network, thus reducing latency and improving performance.

[0161] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0162] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0163] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0164] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0165] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0166] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A storage compute module, comprising: The in-memory computing module includes: a memory and a processing unit; The memory is connected to the processing unit; the read / write bit width of the memory is twice the data bit width it stores. The processing unit is configured to receive a first instruction sent by the controller, wherein the first instruction is used to execute a memory access request; if a second instruction is received within a preset number of cycles forward, the storage of the second storage data corresponding to the second instruction is stopped, the second storage data is used as the first calculation data, calculation is performed according to the first calculation data and the first instruction to obtain the first storage data, and the first storage data is stored in the memory; wherein the processing unit parses each signal in the first instruction in one cycle, and obtains the data indicated by the address signal when the calculation signal indicates that the memory access request is to be calculated; executes the signal in another cycle, stores the calculation result in the register of the processing unit in a third cycle, and writes the data corresponding to the first instruction into the memory in a fourth cycle; Wherein, both the second instruction and the first instruction include a memory access address, and the two are identical; the instruction includes: a data signal, a calculation signal, and an address signal; The data signal is used to indicate the second computational data involved in the memory access request; The computation signal is used to indicate whether a memory access request should be computed; The address signal is used to indicate the memory access address; If the computation signal indicates that a memory access request is to be computed, the instruction further includes: a type signal; The type signal is used to indicate the first calculation type.

2. The in-memory computing module of claim 1, wherein, The memory supports simultaneous read and write operations on one odd address and one even address within the same cycle, but does not support simultaneous read and write operations on two odd addresses or two even addresses within the same cycle.

3. The in-memory computing module of claim 2, wherein, If the computation signal indicates that a memory access request should be performed, the instruction further includes: a self-processing signal; The self-processing signal is used to indicate the self-processing value; The in-storage computing module further performs the first computing type calculation based on the second computing data and the self-processing value to obtain third storage data, and stores the third storage data in the memory.

4. The in-memory computing module of claim 1, wherein, The processing unit is further configured to send an occupancy signal to the controller in the cycle preceding the storage of the first storage data into the memory; The occupancy signal is used to prevent the upstream module from sending a third instruction, which includes a memory access address, and both of these addresses are either odd or even.

5. The in-memory computing module of any of claims 1-4, wherein, The processing unit includes a computing subunit and a register; The calculation subunit is used to perform calculations based on the first calculation data and the first instruction to obtain the first stored data; or, to perform calculations of the first calculation type based on the second calculation data and the self-processed value to obtain the third stored data. The register is used to store the stored data calculated by the computing subunit, the data read from the memory, the instructions, and the data indicated in the instructions; Data is stored in the registers before being stored in the memory by the processing unit.

6. A storage-in-compute method, comprising: The method is performed by the in-memory computing module as described in any one of claims 1-5, the method comprising: The processing unit receives a first instruction sent by the controller; wherein the first instruction is used to execute a memory access request; The processing unit parses each signal in the first instruction; wherein, the signals in the first instruction include: a data signal, a calculation signal, and an address signal; or, the signals in the first instruction include: a data signal, a calculation signal, an address signal, and a type signal; or, the signals in the first instruction include: a data signal, a calculation signal, an address signal, a type signal, and a self-processing signal; the data signal is used to indicate the second calculation data involved in the memory access request; the calculation signal is used to indicate whether the memory access request performs calculation; the address signal is used to indicate the memory access address; the type signal is used to indicate the first calculation type; the self-processing signal is used to indicate the self-processing value; and, when the first instruction includes a type signal, the calculation signal indicates that the memory access request performs calculation; If the first instruction includes a self-processing signal, the processing unit performs the first calculation type calculation based on the second calculation data and the self-processing value to obtain the third storage data, and stores the third storage data in the memory; If the first instruction does not include a self-processing signal but includes a type signal, when the processing unit receives the second instruction within a preset number of cycles forward, it stops storing the second stored data corresponding to the second instruction and uses the second stored data as the first calculated data; it performs calculations based on the first calculated data and the first instruction to obtain the first stored data and stores the first stored data in the memory; Both the second instruction and the first instruction include a memory access address, and they are identical.

7. The method of claim 6, wherein, The processing unit performs calculations based on the first calculated data and the first instruction to obtain the first stored data, including: The processing unit determines the fourth calculation data and the second calculation type from the first instruction; The processing unit performs the second type of calculation between the first calculated data and the fourth calculated data to obtain the first stored data.

8. An electronic device, comprising: The electronic device includes the in-memory computing module as described in any one of claims 1-5.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium is connected to the electronic device of claim 8; and a computer program is stored on the computer-readable storage medium; the computer program is executed to implement the method of claim 6 or 7.

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