Verification method, device and equipment for QSPI bus data transmission and medium

Abstract

The invention discloses a QSPI bus data transmission verification method and device, equipment and a medium, and relates to the technical field of chip verification, and the method comprises the steps: obtaining the number of bits, needing to be transmitted, of a test case in each stage; controlling a state machine to execute a state jump operation based on each bit number, and entering a data sampling process of a corresponding stage based on each jumped state so as to sample first QSPI data from the output end of the QSPI controller; the state machine is preset with states corresponding to different stages, if the bit number corresponding to the current stage is a non-zero value, the state machine jumps to a first state corresponding to the current stage, otherwise, a target stage corresponding to the bit number of the next non-zero value is determined, and the state machine jumps to a second state corresponding to the target stage; sending the first QSPI data to a checker so as to compare the consistency between the first QSPI data and the second QSPI data to obtain a verification result; the second QSPI data is obtained by sampling from the input end of the QSPI controller.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a method, device, equipment and medium for verifying QSPI bus data transmission. Background Art

[0002] During the chip development process, chip verification is a critical step in ensuring chip quality and performance. Its core task is to verify the logical functionality accuracy of the DUT (Device Under Test) design code and the reliability of the chip's performance. During the early and middle stages of development, chip verification personnel must thoroughly study design and architecture documents to accurately grasp module functions, their roles within subsystems or system-on-chips, and their interactions with other devices, thereby developing a comprehensive verification plan.

[0003] QSPI (Quad Serial Peripheral Interface) is a serial data transmission protocol widely used for data exchange between SoCs and external devices such as flash memory. QSPI supports 4-bit data transmission within a single clock cycle and is compatible with both single- and dual-wire operation modes. The QSPI protocol specifies a data flow consisting of five phases: instruction, address, alternating byte, null instruction cycle, and data. In practice, some phases can be skipped as needed, but at least one of the instruction, address, alternating byte, or data phases must be included. To enable communication with external flash devices, SoCs typically integrate a QSPI controller. Its primary function is to read and write flash memory by sending and receiving QSPI data streams.

[0004] When verifying a QSPI controller, ensuring that the data written to and read from Flash memory is consistent with expectations is crucial. Traditional verification methods involve having the QSPI controller write data to Flash memory, then reading the data and comparing the two for consistency. However, this approach only indirectly verifies data consistency and cannot directly monitor the data on the QSPI's four serial data transmission lines. It cannot determine whether the data transmitted at each stage of the data stream sent by the QSPI controller fully matches the configuration data. This poses a risk to the accuracy of the verification results and can potentially lead to data transmission errors and other issues in actual chip use, affecting the chip's overall performance and reliability.

[0005] In summary, how to accurately check whether the data transmitted at each stage in the data stream sent by the QSPI controller is correct to reduce the risk of missed detection is a problem that needs to be solved. Summary of the Invention

[0006] In view of this, the present invention aims to provide a method, apparatus, device, and medium for verifying QSPI bus data transmission, which can accurately check whether the data transmitted at each stage of the data stream sent by the QSPI controller is correct, thereby reducing the risk of missed detection. The specific solution is as follows:

[0007] In a first aspect, the present application discloses a method for verifying QSPI bus data transmission, which is applied to a preset QSPI monitor, comprising:

[0008] Obtaining the number of bits required to be transmitted in each phase of the test case from a preset global configuration database; wherein each phase includes, in a target order, an instruction phase, an address phase, an alternating byte phase, an empty instruction cycle phase, and a data phase;

[0009] Controlling a local state machine to execute a state jump operation based on each bit number to obtain each post-jump state, and entering a data sampling process of a corresponding stage based on each post-jump state to sample first QSPI data from an output end of the QSPI controller; wherein the local state machine is pre-set with states corresponding to different stages, and if the number of bits corresponding to the current stage is a non-zero value, controlling the local state machine to jump to a first state corresponding to the current stage; otherwise, determining a target stage corresponding to the next non-zero number of bits based on a target sequence, and controlling the local state machine to jump to a second state corresponding to the target stage;

[0010] The first QSPI data is sent to a preset checker so that the checker compares the consistency between the first QSPI data and the second QSPI data and obtains a verification result; wherein the second QSPI data is data sampled from the input end of the QSPI controller.

[0011] Optionally, entering a data sampling process of a corresponding stage based on each post-jump state to sample first QSPI data from an output terminal of the QSPI controller includes:

[0012] Entering the data sampling process of the corresponding stage based on the current post-jump state, and starting the counter corresponding to the current post-jump state;

[0013] Sampling QSPI data from the output of the QSPI controller, and using a counter to count the number of bits of the currently sampled QSPI data to obtain a counter value;

[0014] When the counter value is the same as the number of bits of the corresponding stage obtained from the global configuration database, the data sampling operation corresponding to the current jump state is stopped, and the first QSPI data is obtained based on the currently sampled QSPI data;

[0015] Determine the next post-jump state and use the next post-jump state as the current post-jump state, then jump again to the step of executing the data sampling process of the corresponding stage based on the current post-jump state until the data sampling processes corresponding to each post-jump state are completed.

[0016] Optionally, the number of bits required to be transmitted in each stage includes the number of instruction bits, the number of address bits, the number of alternating byte bits, the number of empty cycles, and the number of data bits;

[0017] Accordingly, the local state machine is controlled to perform state jump operations based on each bit number to obtain each state after the jump, including:

[0018] If the instruction bit number is a non-zero value, the local state machine is controlled to jump from the initial state to the instruction state corresponding to the instruction stage, and the data sampling operation of the instruction stage is performed;

[0019] If the number of address bits is non-zero, then after executing the data sampling operation of the instruction phase, the local state machine is controlled to jump from the instruction state to the address state corresponding to the address phase, and the data sampling operation of the address phase is executed;

[0020] If the number of alternating byte bits is non-zero, then after executing the data sampling operation of the address phase, the local state machine is controlled to jump from the address state to the alternating byte state corresponding to the alternating byte phase, and the data sampling operation of the alternating byte phase is executed;

[0021] If the number of empty cycles is a non-zero value, after executing the data sampling operation of the alternating byte phase, the local state machine is controlled to jump from the alternating byte state to the empty instruction cycle state corresponding to the empty instruction cycle phase, and the data sampling operation of the empty instruction cycle phase is executed;

[0022] If the number of data bits is a non-zero value, after executing the data sampling operation of the empty instruction cycle phase, the local state machine is controlled to jump from the empty instruction cycle state to the data state corresponding to the data phase, and the data sampling operation of the data phase is executed. Then, after executing the data sampling operation of the data phase, the local state machine is controlled to jump from the empty instruction cycle state to the initial state.

[0023] Optionally, the data phase includes a data writing phase and a data reading phase, and the number of data bits includes a number of write data bits and a number of read data bits;

[0024] Correspondingly, if the number of data bits is a non-zero value, after executing the data sampling operation in the idle instruction cycle phase, the local state machine is controlled to jump from the idle instruction cycle state to the data state corresponding to the data phase, including:

[0025] If the preset read / write flag is a first preset value and the number of write data bits is a non-zero value, then after executing the data sampling operation in the idle instruction cycle phase, the local state machine is controlled to jump from the idle instruction cycle state to the write data state corresponding to the write data phase;

[0026] If the preset read / write flag is a second preset value and the number of read data bits is a non-zero value, then after executing the data sampling operation of the empty instruction cycle phase, the local state machine is controlled to jump from the empty instruction cycle state to the read data state corresponding to the read data phase.

[0027] Optionally, the output end of the QSPI controller includes four input and output signal lines;

[0028] Accordingly, the QSPI data is sampled from the output of the QSPI controller, including:

[0029] Get the input and output enable signals sent by the QSPI controller through the target interface;

[0030] Determining a target input / output signal line currently used by the QSPI controller based on the input / output enable signal; wherein the target input / output signal line is any one, any two, or any four of the four input / output signal lines;

[0031] The QSPI data is sampled from the target input and output signal lines of the QSPI controller through the target interface.

[0032] Optionally, sending the first QSPI data to a preset checker includes:

[0033] Converting the first QSPI data from a serial data format to a parallel data format to obtain converted first QSPI data;

[0034] The converted first QSPI data is encapsulated into a transaction object, and the transaction object is sent to a preset checker through a transaction-level modeling port.

[0035] Optionally, the QSPI monitor and the checker are located in a preset verification platform, which also includes an AHB master device verification component; wherein the AHB master device verification component and the QSPI monitor are respectively connected to the checker, and the AHB master device verification component includes a driver and a monitor;

[0036] Accordingly, the process of the checker obtaining the second QSPI data includes:

[0037] The driver in the AHB master device verification component writes the second QSPI data to the register in the QSPI monitor through the target interface;

[0038] The monitor in the AHB master verification component sends the second QSPI data to the checker.

[0039] In a second aspect, the present application discloses a QSPI bus data transmission verification device, which is applied to a preset QSPI monitor, and the device includes:

[0040] A bit number acquisition module is used to obtain the number of bits required to be transmitted in each phase of the test case from a preset global configuration database; wherein each phase includes, in the target order, the instruction phase, the address phase, the alternating byte phase, the empty instruction cycle phase, and the data phase;

[0041] a state machine control module, configured to control a local state machine to execute a state jump operation based on each bit number to obtain each post-jump state, and to enter a data sampling process of a corresponding stage based on each post-jump state to sample first QSPI data from an output of the QSPI controller; wherein the local state machine is pre-set with states corresponding to different stages, and if the number of bits corresponding to the current stage is non-zero, the local state machine is controlled to jump to a first state corresponding to the current stage; otherwise, a target stage corresponding to the next non-zero number of bits is determined based on a target sequence, and the local state machine is controlled to jump to a second state corresponding to the target stage;

[0042] The comparison module is configured to send the first QSPI data to a preset checker so that the checker compares the consistency between the first QSPI data and the second QSPI data and obtains a verification result; wherein the second QSPI data is data sampled from the input end of the QSPI controller.

[0043] In a third aspect, the present application discloses an electronic device, comprising:

[0044] Memory, used to store computer programs;

[0045] A processor is used to execute a computer program to implement the steps of the aforementioned QSPI bus data transmission verification method.

[0046] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned QSPI bus data transmission verification method are implemented.

[0047] As can be seen, the QSPI monitor in the present application obtains the number of bits required to be transmitted in each phase of the test case from a preset global configuration database; wherein each phase includes, in a target order, an instruction phase, an address phase, an alternating byte phase, an empty instruction cycle phase, and a data phase; based on each bit number, controls the local state machine to perform a state jump operation to obtain each post-jump state, and enters the data sampling process of the corresponding phase based on each post-jump state to sample the first QSPI data from the output end of the QSPI controller; wherein the local state machine is pre-set with states corresponding to different phases; if the number of bits corresponding to the current phase is non-zero, the local state machine is controlled to jump to the first state corresponding to the current phase; otherwise, the target phase corresponding to the next non-zero bit number is determined based on the target order, and the local state machine is controlled to jump to the second state corresponding to the target phase; the first QSPI data is sent to a preset checker so that the checker compares the consistency between the first QSPI data and the second QSPI data and obtains a verification result; wherein the second QSPI data is data sampled from the input end of the QSPI controller.

[0048] Beneficial Effects: The QSPI monitor in this application first needs to obtain the number of bits required to be transmitted in each stage of the test case from a preset global configuration database, and then control the local state machine to perform state jump operations based on the number of bits to obtain each post-jump state, and then enter the data sampling process of the corresponding stage based on each post-jump state to sample the first QSPI data from the output end of the QSPI controller. In other words, the post-jump data sampling process of the state machine can be accurately controlled according to specific test requirements through the number of bits. Considering that different test cases may have different requirements for the number of bits in each stage, this method can ensure that the expected amount of data is accurately collected in each stage, avoiding deviations in the verification results due to inaccurate sampling. In addition, this application covers the instruction stage, address stage, alternating byte stage, empty instruction cycle stage and data stage of QSPI bus data transmission. Through the state jump operation of the state machine, data in each stage can be sampled, ensuring that the verification process fully covers the entire QSPI data transmission process, thereby more accurately detecting possible problems. In addition, through the automatic state jump operation of the local state machine, automatic control of data sampling at each stage is achieved, without the need for manual intervention in the switching of each stage, reducing human errors in the verification process and improving verification efficiency. Furthermore, the present application samples the data of each stage separately, and compares the consistency of the first QSPI data sampled from the output end with the second QSPI data sampled from the input end, and obtains a verification result. If inconsistency is found during the comparison process, it can be easily determined which stage of the data has a problem, thereby quickly locating the fault point and facilitating debugging and repair. In this way, the present application can accurately check whether the data transmitted at each stage in the data stream sent by the QSPI controller is correct, so as to reduce the risk of missed detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0050] Figure 1 A flow chart of a method for verifying QSPI bus data transmission disclosed in this application;

[0051] Figure 2 A schematic diagram of a UVM-based QSPI controller verification platform disclosed in this application;

[0052] Figure 3 This is a schematic diagram of the different stages of the QSPI data transmission process;

[0053] Figure 4 This is a flow chart of a data sampling method disclosed in this application;

[0054] Figure 5 A schematic diagram of state transition in a state machine disclosed in this application;

[0055] Figure 6 This is a schematic diagram of the structure of a verification device for QSPI bus data transmission disclosed in this application;

[0056] Figure 7 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0058] When verifying the QSPI controller, it is crucial to ensure that the data written to and read from Flash is consistent with expectations. The traditional verification method is to first let the QSPI controller write data to Flash, then read it out and compare whether the two are consistent. However, this method only indirectly verifies the data consistency and cannot directly monitor the data on the four serial data transmission lines of the QSPI. It is impossible to determine whether the data transmitted at each stage in the data stream sent by the QSPI controller is completely consistent with the configuration data, thereby bringing risks to the correctness of the verification results. It may cause data transmission errors and other problems in the actual use of the chip, affecting the overall performance and reliability of the chip. To this end, the embodiment of the present application discloses a verification method, device, equipment and medium for QSPI bus data transmission, which can accurately check whether the data transmitted at each stage in the data stream sent by the QSPI controller is correct, so as to reduce the risk of missed detection.

[0059] See also Figure 1 As shown, an embodiment of the present application discloses a method for verifying QSPI bus data transmission, which is applied to a preset QSPI monitor. The method includes:

[0060] Step S11: Obtain the number of bits required to be transmitted in each phase of the test case from a preset global configuration database; wherein each phase includes, in target order, an instruction phase, an address phase, an alternating byte phase, an empty instruction cycle phase, and a data phase.

[0061] This embodiment discloses a QSPI monitor (i.e., QSPI_Monitor) for collecting QSPI data based on the QSPI data stream format and UVM (Universal Verification Methodology), and integrates the QSPI monitor into the verification platform. The integration method is as follows: Figure 2 In this verification platform, the QSPI controller is the DUT (Device Under Test) to be verified. Its QSPI output port signal is connected to Flash memory. When receiving a write command, Flash can store the data output on the QSPI controller's IO (Input / Output) line. When receiving a read command, Flash can drive the stored data to the IO line according to the timing specified by QSPI.

[0062] The QSPI monitor first needs to obtain the number of bits required to be transmitted in each phase of the test case from a preset global configuration database. The phases include the instruction phase, address phase, alternating byte phase, empty instruction cycle phase and data phase in the target order. Figure 3 Schematic diagram of the different stages in the QSPI data transmission process.

[0063] It should be noted that this embodiment utilizes the uvm_config_db mechanism to pass the bit count of serial data at each stage to the QSPI monitor in the top-level test case, so that the QSPI monitor can determine the subsequent sampling times based on the bit count of the data at each stage. The uvm_config_db mechanism is a global configuration database used to dynamically transfer configuration parameters between different components.

[0064] Step S12: Controlling the local state machine to perform a state jump operation based on each bit number to obtain each post-jump state, and entering a data sampling process of the corresponding stage based on each post-jump state to sample the first QSPI data from the output end of the QSPI controller; wherein the local state machine is pre-set with states corresponding to different stages, and if the number of bits corresponding to the current stage is a non-zero value, the local state machine is controlled to jump to the first state corresponding to the current stage; otherwise, the target stage corresponding to the next non-zero number of bits is determined based on the target sequence, and the local state machine is controlled to jump to the second state corresponding to the target stage.

[0065] In this embodiment, the acquired bit count allows precise control of the state machine's post-jump data sampling process based on specific test requirements. Considering that different test cases may have different bit count requirements for each stage, this approach ensures that the expected amount of data is accurately collected at each stage, avoiding deviations in verification results due to inaccurate sampling. Therefore, this embodiment requires controlling the local state machine to execute state jump operations based on the bit count to obtain each post-jump state. Based on each post-jump state, the data sampling process for the corresponding stage is then initiated to sample the first QSPI data from the output of the QSPI controller.

[0066] Furthermore, the embodiments of the present application cover the instruction phase, address phase, alternating byte phase, empty instruction cycle phase, and data phase of QSPI bus data transmission. By using the state machine's state transition operations, data can be sampled at each phase, ensuring that the verification process fully covers the entire QSPI data transmission process, thereby more accurately detecting potential problems. Furthermore, through the local state machine's automatic state transition operations, automated control of data sampling at each phase is achieved, eliminating the need for manual intervention in switching between phases. This reduces human error during the verification process and improves verification efficiency.

[0067] In a specific embodiment, Figure 4 As shown, the data sampling process of entering the corresponding stage based on each jump state to sample the first QSPI data from the output end of the QSPI controller includes the following steps:

[0068] Step S121: Entering the data sampling process of the corresponding stage based on the current post-jump state, and starting the counter corresponding to the current post-jump state.

[0069] In this embodiment, for each post-jump state, a corresponding phase of the data sampling process needs to be entered, and a corresponding counter is set for each post-jump state. Therefore, after entering the data sampling process corresponding to the current post-jump state, the counter corresponding to the current post-jump state needs to be started.

[0070] Step S122: sampling QSPI data from the output end of the QSPI controller, and using a counter to count the number of bits of the currently sampled QSPI data to obtain a counter value.

[0071] In this embodiment, QSPI data is sampled from the output end of the QSPI controller, and a counter is used to count the number of bits of the currently sampled QSPI data to obtain a counter value.

[0072] Step S123: When the counter value is the same as the number of bits of the corresponding phase obtained from the global configuration database, the data sampling operation corresponding to the current post-jump state is stopped, and the first QSPI data is obtained based on the currently sampled QSPI data.

[0073] In this embodiment, when the counter value is equal to the number of bits of the corresponding stage obtained from the global configuration database, it indicates that the data sampling operation of the stage corresponding to the current post-jump state has been completed, and the QSPI data collected at this time is recorded as the first QSPI data.

[0074] Step S124: Determine the next post-jump state and use the next post-jump state as the current post-jump state, then jump again to the step of executing the data sampling process of the corresponding stage based on the current post-jump state, until the data sampling processes corresponding to each post-jump state are completed.

[0075] In this embodiment, after completing the data sampling of the corresponding stage of the current post-jump state, the next post-jump state is determined, and the next post-jump state is used as the current post-jump state. Then, the process jumps again to the step of executing the data sampling process of entering the corresponding stage based on the current post-jump state until the data sampling processes corresponding to each post-jump state are completed.

[0076] It should be noted that the output end of the QSPI controller includes four input / output signal lines. Accordingly, sampling QSPI data from the output end of the QSPI controller includes: obtaining an input / output enable signal sent by the QSPI controller via a target interface; determining the target input / output signal line currently used by the QSPI controller based on the input / output enable signal; wherein the target input / output signal line is any one, any two, or any four of the four input / output signal lines; and sampling QSPI data from the target input / output signal line of the QSPI controller via the target interface. That is, the QSPI controller can transmit the input / output enable signal of the IO line to the QSPI monitor via the target interface (i.e., interface); the QSPI monitor can determine the target input / output signal line currently used by the QSPI controller based on the input / output enable signal, thereby sampling QSPI data from the target input / output signal line of the QSPI controller via the target interface; wherein the target input / output signal line is any one, any two, or any four of the four input / output signal lines. That is, this embodiment can utilize the input / output enable signal to simultaneously support single-line, dual-line, and quad-line sampling. When the required number of bits is 8, 8 clock cycles are required in single-wire mode, that is, 1 bit is sampled per cycle, and 2 clock cycles are required in four-wire mode, that is, 4 bits are sampled per cycle.

[0077] Specifically, the number of bits required to be transmitted in each stage includes the number of instruction bits, the number of address bits, the number of alternating byte bits, the number of empty cycles and the number of data bits; accordingly, based on each bit number, the local state machine is controlled to perform a state jump operation to obtain each post-jump state, including: if the number of instruction bits is a non-zero value, the local state machine is controlled to jump from the initial state to the instruction state corresponding to the instruction stage, and the data sampling operation of the instruction stage is performed; if the number of address bits is a non-zero value, the local state machine is controlled to jump from the instruction state to the address state corresponding to the address stage after the data sampling operation of the instruction stage is performed, and the data sampling operation of the address stage is performed; if the number of alternating byte bits is a non-zero value, the local state machine is controlled to jump from the instruction state to the address state corresponding to the address stage after the data sampling operation of the address stage is performed. The local state machine jumps from the address state to the alternate byte state corresponding to the alternate byte stage, and performs the data sampling operation of the alternate byte stage; if the number of empty cycles is a non-zero value, then after executing the data sampling operation of the alternate byte stage, the local state machine is controlled to jump from the alternate byte state to the empty instruction cycle state corresponding to the empty instruction cycle stage, and performs the data sampling operation of the empty instruction cycle stage; if the number of data bits is a non-zero value, then after executing the data sampling operation of the empty instruction cycle stage, the local state machine is controlled to jump from the empty instruction cycle state to the data state corresponding to the data stage, and performs the data sampling operation of the data stage, and then after executing the data sampling operation of the data stage, the local state machine is controlled to jump from the empty instruction cycle state to the initial state.

[0078] Among them, the data stage includes a write data stage and a read data stage, and the number of data bits includes a write data bit number and a read data bit number; accordingly, if the number of data bits is a non-zero value, then after executing the data sampling operation of the empty instruction cycle stage, the local state machine is controlled to jump from the empty instruction cycle state to the data state corresponding to the data stage, including: if the preset read-write flag is a first preset value and the number of write data bits is a non-zero value, then after executing the data sampling operation of the empty instruction cycle stage, the local state machine is controlled to jump from the empty instruction cycle state to the write data state corresponding to the write data stage; if the preset read-write flag is a second preset value and the number of read data bits is a non-zero value, then after executing the data sampling operation of the empty instruction cycle stage, the local state machine is controlled to jump from the empty instruction cycle state to the read data state corresponding to the read data stage.

[0079] First, it should be pointed out that the complete data flow on the QSPI bus includes five phases: the instruction phase, the address phase, the alternating byte phase, the empty instruction cycle phase, and the data phase. In some cases, there may be fewer than these five phases. For example, when a write-enable instruction is sent to Flash, the serial data stream only has the instruction phase. QSPI also supports single-line, dual-line, and quad-line transmission. This requires the QSPI monitor to accurately identify each data phase from the serial data stream, sample the data at each phase, and support single-line, dual-line, and quad-line sampling. To achieve these functions, this embodiment designs a state machine in the QSPI monitor. The state machine includes six states: the initial state (i.e., IDLE), the instruction state (i.e., INSTRUCTION) corresponding to the instruction phase, the address state (i.e., ADDR) corresponding to the address phase, the alternate byte state (i.e., ALT) corresponding to the alternate byte phase, the empty instruction cycle state (i.e., DUMMY) corresponding to the empty instruction cycle phase, the write data state (i.e., WRITE_DATA) corresponding to the write data phase, and the read data state (READ_DATA) corresponding to the read data phase. By controlling the jump of the state machine, it is ensured that the QSPI monitor can correctly sample the data in each phase.

[0080] First, the local state machine is in the initial state. If the number of instruction bits, address bits, alternating byte bits, empty cycle number and data bits are all non-zero values, the local state machine is first controlled to jump from the initial state to the instruction state, and perform the data sampling operation of the instruction stage. Further, the local state machine is controlled to jump from the instruction state to the address state, and perform the data sampling operation of the address stage; further, the local state machine is controlled to jump from the address state to the alternating byte state, and perform the data sampling operation of the alternating byte stage; further, the local state machine is controlled to jump from the alternating byte state to the empty instruction cycle state, and perform the data sampling operation of the empty instruction cycle stage; further, the local state machine is controlled to jump from the empty instruction cycle state to the data state, and perform the data sampling operation of the data stage. Then, after executing the data sampling operation of the data stage, the local state machine is finally controlled to restore from the empty instruction cycle state to the initial state. Among them, the data stage can specifically include a write data stage and a read data stage, and the corresponding number of data bits includes a write data bit number and a read data bit number. The embodiment of the present application is specifically provided with a preset read-write flag is_write. If the read-write flag is_write is equal to the first preset value 1, and the number of write data bits is not equal to 0, the local state machine is controlled to jump to the write data state. If the read-write flag is_write is equal to the second preset value 0, and the number of read data bits is not equal to 0, the local state machine is controlled to jump to the read data state.

[0081] Step S13: Sending the first QSPI data to a preset checker so that the checker compares the consistency between the first QSPI data and the second QSPI data and obtains a verification result; wherein the second QSPI data is data sampled from the input end of the QSPI controller.

[0082] In this embodiment, data from each phase is sampled separately, and the first QSPI data sampled from the output end is compared with the second QSPI data sampled from the input end for consistency, and a verification result is obtained. If an inconsistency is found during the comparison process, it is easy to determine which phase of the data has a problem, thereby quickly locating the fault point and facilitating debugging and repair. In this way, the present application can accurately check whether the data transmitted at each phase in the data stream sent by the QSPI controller is correct, thereby reducing the risk of missed detection.

[0083] When collecting data from multiple stages, each stage collects corresponding first QSPI data. Therefore, depending on verification requirements and design complexity, one of the following two approaches can be used to send the first QSPI data to the checker. In the first approach, after collecting data from each stage, the corresponding first QSPI data is sent to the checker for comparison. This approach is suitable for scenarios with high real-time requirements and can quickly detect errors in specific stages (such as instructions or addresses) without waiting for the complete data flow. Furthermore, this approach provides strong independence between stages, allowing the correctness of data from each stage to be verified independently. For example, errors in the instruction stage are immediately reported without correlating to subsequent data. In the second approach, after data from each stage is collected, the first QSPI data from each stage is aggregated and sent to the checker for comparison. This approach is suitable for scenarios with strong inter-stage correlation and can verify the correctness of a multi-stage combination, such as the complete transmission of the instruction stage, address stage, and data stage. It can also be used for protocol integrity checks, for example, where QSPI read and write operations require data consistency across all stages, such as a complete match between the written address and data.

[0084] In a specific embodiment, sending the first QSPI data to a predetermined checker includes: converting the first QSPI data from a serial data format to a parallel data format to obtain converted first QSPI data; encapsulating the converted first QSPI data into a transaction object; and sending the transaction object to the predetermined checker via a transaction-level modeling port. Specifically, the QSPI monitor in this embodiment can collect data from the QSPI serial data stream during the instruction phase, address phase, alternate byte phase, null instruction phase, and data phase of the QSPI data stream; then convert the collected first QSPI data from a serial data format to a parallel data format to obtain converted first QSPI data; then encapsulating the converted first QSPI data into a transaction object (Transaction); and sending the transaction object to the checker in the predetermined verification platform via a transaction-level modeling port (TLM_port) to verify whether the data at each phase of the QSPI serial data stream is consistent with expected data.

[0085] It should also be pointed out that the QSPI monitor and the checker are located in a preset verification platform, which also includes an AHB master device verification component; wherein the AHB master device verification component and the QSPI monitor are respectively connected to the checker, and the AHB master device verification component includes a driver and a monitor; accordingly, the process of the checker obtaining the second QSPI data includes: the driver in the AHB master device verification component writes the second QSPI data to the register in the QSPI monitor through the target interface; the monitor in the AHB master device verification component sends the second QSPI data to the checker. It can be understood that, if Figure 2 As shown, the verification environment consists of three main components: the AHB master verification component (AHB_MASTER), the checker, and the QSPI monitor. The AHB master verification component and the QSPI monitor are each connected to the checker. The driver in the AHB master verification component writes the desired instructions, addresses, and data to the QSPI controller's registers via the target interface, which is recorded as the second QSPI data. The monitor in the AHB master verification component then passes this second QSPI data to the checker. The QSPI monitor is responsible for collecting serial data from the four QSPI IO lines via the target interface, namely the aforementioned first QSPI data, and sending it to the checker to check whether the data input to the QSPI controller and the data output from the QSPI are consistent.

[0086] As can be seen, the QSPI monitor in this application first needs to obtain the number of bits required to be transmitted at each stage of the test case from a preset global configuration database, and then control the local state machine to perform state jump operations based on the bit number to obtain each post-jump state. Based on each post-jump state, the data sampling process of the corresponding stage is entered to sample the first QSPI data from the output of the QSPI controller. In other words, the number of bits can be used to accurately control the post-jump data sampling process of the state machine according to specific test requirements. Considering that different test cases may have different requirements for the number of bits in each stage, this method can ensure that the expected amount of data is accurately collected at each stage, avoiding deviations in verification results due to inaccurate sampling. In addition, this application covers the instruction stage, address stage, alternating byte stage, empty instruction cycle stage, and data stage of QSPI bus data transmission. Through the state jump operation of the state machine, data at each stage can be sampled, ensuring that the verification process fully covers the entire QSPI data transmission process, thereby more accurately detecting potential problems. In addition, through the automatic state jump operation of the local state machine, automatic control of data sampling at each stage is achieved, without the need for manual intervention in the switching of each stage, reducing human errors in the verification process and improving verification efficiency. Furthermore, the present application samples the data of each stage separately, and compares the consistency of the first QSPI data sampled from the output end with the second QSPI data sampled from the input end, and obtains a verification result. If inconsistency is found during the comparison process, it can be easily determined which stage of the data has a problem, thereby quickly locating the fault point and facilitating debugging and repair. In this way, the present application can accurately check whether the data transmitted at each stage in the data stream sent by the QSPI controller is correct, so as to reduce the risk of missed detection.

[0087] Figure 5 This is a state jump diagram in a state machine disclosed in this application. The conditions for jumping between various states are as follows, where the following sequence numbers (1) to (21) are related to Figure 5 The serial numbers in the table correspond one to one:

[0088] (1) The initial state of the state machine is IDLE. When the number of instruction bits instruction_bits is not equal to 0, the state machine jumps to INSTRUCTION state and starts sampling instruction data. At the same time, the counter instruction_cnt also records the number of sampled instruction bits.

[0089] (2) When the value of instruction_cnt is equal to the number of instruction bits instruction_bits, it means that the instruction stage sampling is completed. At this time, if the number of address bits addr_bits is not equal to 0, the state machine jumps to the ADDR state and starts sampling address data. At the same time, the counter addr_cnt also records the number of sampled address bits.

[0090] (3) When the value of instruction_cnt is equal to the number of instruction bits instruction_bits, it means that the instruction stage sampling is completed. At this time, if the number of address bits addr_bits is equal to 0 and the number of alternate byte bits alt_bits is not equal to 0, the state machine jumps to the ALT state and starts sampling the alternate byte data. At the same time, the counter alt_cnt will also record the number of sampled alternate byte bits.

[0091] (4) When the value of instruction_cnt is equal to the number of instruction bits instruction_bits, it means that the instruction stage sampling is completed. At this time, if the number of address bits addr_bits is equal to 0, the number of alternate byte bits alt_bits is equal to 0, and the number of empty cycles dummy_num is not equal to 0, the state machine jumps to the DUMMY state, and the counter dummy_cnt also records the number of empty cycles.

[0092] (5) When the value of instruction_cnt is equal to the number of instruction bits instruction_bits, it means that the instruction stage sampling is completed. At this time, if the number of address bits addr_bits is equal to 0, the number of alternate byte bits alt_bits is equal to 0, the number of empty cycles dummy_num is equal to 0, the read / write flag is_write is equal to 1, and the number of write data bits wdata_bits is not equal to 0, the state machine jumps to the WRITE_DATA state, and the counter wdata_cnt also records the number of write data bits.

[0093] (6) When the value of instruction_cnt is equal to the number of instruction bits instruction_bits, it means that the instruction stage sampling is completed. At this time, if the number of address bits addr_bits is equal to 0, the number of alternate byte bits alt_bits is equal to 0, the number of empty cycles dummy_num is equal to 0, the read-write flag is_write is equal to 0, and the number of read data bits rdata_bits is not equal to 0, the state machine jumps to the READ_DATA state, and the counter rdata_cnt also records the number of read data bits.

[0094] (7) When the value of instruction_cnt is equal to the number of instruction bits instruction_bits, it means that the instruction stage sampling is completed. At this time, if the number of address bits addr_bits is equal to 0, the number of alternate byte bits alt_bits is equal to 0, the number of empty cycles dummy_num is equal to 0, the number of write data bits wdata_bit is equal to 0, and the number of read data bits rdata_bits is equal to 0, the state machine jumps to the IDLE state.

[0095] (8) When the value of addr_cnt is equal to the number of address bits addr_bits, it means that the address stage sampling is completed. At this time, if the number of alternate byte bits alt_bits is not equal to 0, the state machine jumps to the ALT state and starts sampling the alternate byte data. At the same time, the counter alt_cnt also records the number of sampled alternate byte bits.

[0096] (9) When the value of addr_cnt is equal to the number of address bits addr_bits, it means that the address stage sampling is completed. At this time, if the number of alternate byte bits alt_bits is equal to 0 and the number of empty cycles dummy_num is not equal to 0, the state machine jumps to the DUMMY state, and the counter dummy_cnt also records the number of empty cycles.

[0097] (10) When the value of addr_cnt is equal to the number of address bits addr_bits, it means that the address stage sampling is completed. At this time, if the number of alternate byte bits alt_bits is equal to 0, the number of empty cycles dummy_num is equal to 0, the read / write flag is_write is equal to 1, and the number of write data bits wdata_bits is not equal to 0, the state machine jumps to the WRITE_DATA state, and the counter wdata_cnt also records the number of write data bits.

[0098] (11) When the value of addr_cnt is equal to the number of address bits addr_bits, it means that the address stage sampling is completed. At this time, if the number of alternating byte bits alt_bits is equal to 0, the number of empty cycles dummy_num is equal to 0, the read / write flag is_write is equal to 0, and the number of read data bits rdata_bits is not equal to 0, the state machine jumps to the READ_DATA state, and the counter rdata_cnt also records the number of read data bits.

[0099] (12) When the value of addr_cnt is equal to the number of address bits addr_bits, it means that the address stage sampling is completed. At this time, if the number of alternate byte bits alt_bits is equal to 0, the number of empty cycles dummy_num is equal to 0, the number of write data bits wdata_bit is equal to 0, and the number of read data bits rdata_bits is equal to 0, the state machine jumps to the IDLE state.

[0100] (13) When the value of alt_cnt is equal to the number of alternating byte bits alt_bits, it means that the alternating byte sampling is completed. At this time, if the number of empty cycles dummy_num is not equal to 0, the state machine jumps to the DUMMY state, and the counter dummy_cnt also records the number of empty cycles.

[0101] (14) When the value of alt_cnt is equal to the number of alternate byte bits alt_bits, it means that the alternate byte sampling is completed. At this time, if the number of empty cycles dummy_num is equal to 0, the read / write flag is_write is equal to 1, and the number of write data bits wdata_bits is not equal to 0, the state machine jumps to the WRITE_DATA state, and the counter wdata_cnt also records the number of write data bits.

[0102] (15) When the value of alt_cnt is equal to the number of alternating byte bits alt_bits, it indicates that the alternating byte sampling is completed. At this time, if the number of empty cycles dummy_num is equal to 0, the read / write flag is_write is equal to 0, and the number of read data bits rdata_bits is not equal to 0, the state machine jumps to the READ_DATA state, and the counter rdata_cnt also records the number of read data bits.

[0103] (16) When the value of alt_cnt is equal to the number of alternate byte bits alt_bits, it means that the alternate byte sampling is completed. At this time, if the number of empty cycles dummy_num is equal to 0, the number of write data bits wdata_bits is equal to 0, and the number of read data bits rdata_bits is equal to 0, the state machine jumps to the IDLE state.

[0104] (17) When the value of dummy_cnt is equal to the number of empty cycles dummy_num, it means that the sampling of the empty cycle stage is completed. At this time, if the read / write flag is_write is equal to 1 and the number of write data bits wdata_bits is not equal to 0, the state machine jumps to the WRITE_DATA state, and the counter wdata_cnt also records the number of write data bits.

[0105] (18) When the value of dummy_cnt is equal to the number of empty cycles dummy_num, it means that the sampling of the empty cycle stage is completed. At this time, if the read / write flag is_write is equal to 0 and the number of read data bits rdata_bits is not equal to 0, the state machine jumps to the READ_DATA state, and the counter rdata_cnt also records the number of read data bits.

[0106] (19) When the value of dummy_cnt is equal to the number of empty cycles dummy_num, it means that the sampling of the empty cycle stage is completed. At this time, if the number of write data bits wdata_bits is equal to 0 and the number of read data bits rdata_bits is equal to 0, the state machine jumps to the IDLE state.

[0107] (20) When the value of wdata_cnt is equal to the number of write data bits wdata_bits, it means that the sampling of the write data phase is completed. At this time, the state machine jumps to the IDLE state.

[0108] (21) When the value of rdata_cnt is equal to the number of read data bits rdata_bits, it means that the sampling of the read data phase is completed. At this time, the state machine jumps to the IDLE state.

[0109] Taking the INSTRUCTION state as an example, some of the codes in the QSPI monitor are as follows:

[0110] @posedge(vif.qspi_sck) begin

[0111] case(state)

[0112] ………

[0113] INSTRUCTION: begin

[0114] vld_bit_cnt = 0;

[0115] sample_data[0] = vif.IO[0]; / / Sampling data on QSPI signal line

[0116] sample_data[1] = vif.IO[1];

[0117] sample_data[2] = vif.IO[2];

[0118] sample_data[3] = vif.IO[3];

[0119] if(vif.IO_en[0]) vld_bit_cnt = vld_bit_cnt+1; / / Judge the valid bit

[0120] if(vif.IO_en[1]) vld_bit_cnt = vld_bit_cnt+1;

[0121] if(vif.IO_en[2]) vld_bit_cnt = vld_bit_cnt+1;

[0122] if(vif.IO_en[3]) vld_bit_cnt = vld_bit_cnt+1;

[0123] instruction = instruction << vld_bit_cnt;

[0124] for (int i = 0; i < vld_bit_cnt; i++) begin / / Convert serial data into parallel data

[0125] instruction[i] = sample_data[i];

[0126] end

[0127] instruction_cnt = instruction_cnt + vld_bit_cnt; / / Record the number of sampled bits

[0128] if(instruction_cnt == cfg.instruction_bits) begin / / Judge whether sampling is completed

[0129] instruction_cnt == 0;

[0130] if(cfg.addr_bits != 0) state == ADDR; / / jump to ADDR state

[0131] else if(cfg.alt_bits != 0) state = ALT; / / jump to ALT state

[0132] else if(cfg.dummy_num !=0 ) state = DUMMY; / / Jump to DUMMY state

[0133] else if(cfg.wdata_bits != 0 && cfg.is_write == 1)

[0134] state = WRITE_DATA; / / jump to WRITE_DATA state

[0135] else if(cfg.rdata_bits != 0 && cfg.is_write == 0)

[0136] state = READ_DATA; / / jump to READ_DATA state

[0137] else begin

[0138] qspi_tx.instruction = instruction;

[0139] qspi_tx.addr = 0;

[0140] qspi_tx.alt = 0;

[0141] qspi_tx.dum_num = 0;

[0142] state = IDLE; / / jump to IDLE state

[0143] mon_ap.wrtie(qspi_tx); / / Send transaction to other components

[0144] end

[0145] end

[0146] end

[0147] As shown in the code above, when the QSPI monitor is in the INSTRUCTION state, it first samples the data on the four IO signal lines. Based on the IO enable signal on the interface, it determines which signal lines have valid bits. Then, through serial-to-parallel conversion, the data on the IO signal lines is stored in the variable instruction. When the sampled bit count equals instruction_bits, QSPI_Monitor determines the next state to jump to based on the number of bits in the other phases. If the number of bits in the other phases is all 0, it means that the serial data stream only has the instruction phase. The state machine jumps to the IDLE state and places the sampled data into the Transaction, which is sent to other components in the verification platform through TLM_port.

[0148] In this way, the QSPI monitor of the present application can identify each stage from the serial data stream of the QSPI, accurately sample the data of each stage, and convert the serial data into parallel data. Therefore, it can be integrated into the verification platform to check whether the data transmitted by the QSPI controller is correct, thereby accelerating the construction of the verification platform.

[0149] See also Figure 6 As shown, the embodiment of the present application discloses a QSPI bus data transmission verification device, which is applied to a preset QSPI monitor, and the device includes:

[0150] The bit number acquisition module 11 is used to obtain the number of bits required to be transmitted in each phase of the test case from a preset global configuration database; wherein each phase includes, in the target order, the instruction phase, the address phase, the alternating byte phase, the empty instruction cycle phase, and the data phase;

[0151] The state machine control module 12 is configured to control the local state machine to execute a state jump operation based on each bit number to obtain each post-jump state, and to enter a data sampling process of a corresponding stage based on each post-jump state to sample first QSPI data from the output of the QSPI controller. The local state machine is pre-set with states corresponding to different stages. If the number of bits corresponding to the current stage is non-zero, the local state machine is controlled to jump to the first state corresponding to the current stage. Otherwise, a target stage corresponding to the next non-zero number of bits is determined based on a target sequence, and the local state machine is controlled to jump to a second state corresponding to the target stage.

[0152] The comparison module 13 is configured to send the first QSPI data to a preset checker so that the checker compares the consistency between the first QSPI data and the second QSPI data and obtains a verification result; wherein the second QSPI data is data sampled from the input end of the QSPI controller.

[0153] As can be seen, the QSPI monitor in this application first needs to obtain the number of bits required to be transmitted at each stage of the test case from a preset global configuration database, and then control the local state machine to perform state jump operations based on the bit number to obtain each post-jump state. Based on each post-jump state, the data sampling process of the corresponding stage is entered to sample the first QSPI data from the output of the QSPI controller. In other words, the number of bits can be used to accurately control the post-jump data sampling process of the state machine according to specific test requirements. Considering that different test cases may have different requirements for the number of bits in each stage, this method can ensure that the expected amount of data is accurately collected at each stage, avoiding deviations in verification results due to inaccurate sampling. In addition, this application covers the instruction stage, address stage, alternating byte stage, empty instruction cycle stage, and data stage of QSPI bus data transmission. Through the state jump operation of the state machine, data at each stage can be sampled, ensuring that the verification process fully covers the entire QSPI data transmission process, thereby more accurately detecting potential problems. In addition, through the automatic state jump operation of the local state machine, automatic control of data sampling at each stage is achieved, without the need for manual intervention in the switching of each stage, reducing human errors in the verification process and improving verification efficiency. Furthermore, the present application samples the data of each stage separately, and compares the consistency of the first QSPI data sampled from the output end with the second QSPI data sampled from the input end, and obtains a verification result. If inconsistency is found during the comparison process, it can be easily determined which stage of the data has a problem, thereby quickly locating the fault point and facilitating debugging and repair. In this way, the present application can accurately check whether the data transmitted at each stage in the data stream sent by the QSPI controller is correct, so as to reduce the risk of missed detection.

[0154] Since the embodiments of the device part correspond to the above embodiments, the embodiments of the device part please refer to the description of the embodiments of the method part, and will not be repeated here.

[0155] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Specifically, the device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps of the QSPI bus data transmission verification method performed by the electronic device disclosed in any of the aforementioned embodiments.

[0156] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0157] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0158] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0159] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, enabling the processor 21 to calculate and process the massive amount of data 223 in the memory 22. The operating system 221 can be Windows, Unix, Linux, etc. In addition to including a computer program capable of implementing the QSPI bus data transmission verification method disclosed in any of the aforementioned embodiments and executed by the electronic device 20, the computer program 222 may further include computer programs capable of performing other specific tasks. The data 223 may include not only data received by the electronic device from external devices but also data collected by its own input / output interface 25.

[0160] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the steps of the verification method for QSPI bus data transmission disclosed in any of the aforementioned embodiments are implemented.

[0161] An embodiment of the present invention further discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the QSPI bus data transmission verification method disclosed in any of the aforementioned embodiments.

[0162] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0163] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0164] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0165] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0166] The above is a detailed introduction to the QSPI bus data transmission verification method, device, equipment and storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only intended to help understand the method and core concept of the present invention. At the same time, for those skilled in the art, according to the concept of the present invention, there may be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for verifying QSPI bus data transmission, characterized in that: Applied to a preset QSPI monitor, the method includes: Obtaining the number of bits required to be transmitted in each phase of the test case from a preset global configuration database; wherein the phases include, in a target order, an instruction phase, an address phase, an alternating byte phase, an empty instruction cycle phase, and a data phase; Controlling a local state machine to perform a state jump operation based on each of the bit numbers to obtain each post-jump state, and entering a data sampling process of a corresponding stage based on each of the post-jump states to sample first QSPI data from an output end of the QSPI controller; wherein the local state machine is pre-set with states corresponding to different stages, and if the number of bits corresponding to a current stage is a non-zero value, controlling the local state machine to jump to a first state corresponding to the current stage; otherwise, determining a target stage corresponding to the next non-zero number of bits based on the target sequence, and controlling the local state machine to jump to a second state corresponding to the target stage; The first QSPI data is sent to a preset checker so that the checker compares the consistency between the first QSPI data and the second QSPI data and obtains a verification result; wherein the second QSPI data is data sampled from the input end of the QSPI controller.

2. The verification method of QSPI bus data transmission according to claim 1, wherein The data sampling process of entering the corresponding stage based on each of the jump states to sample the first QSPI data from the output end of the QSPI controller includes: Entering a data sampling process of a corresponding phase based on the current post-jump state, and starting a counter corresponding to the current post-jump state; Sampling QSPI data from an output terminal of the QSPI controller, and using the counter to count the number of bits of the currently sampled QSPI data to obtain a counter value; When the counter value is the same as the number of bits of the corresponding stage obtained from the global configuration database, stopping the data sampling operation corresponding to the current post-jump state, and obtaining the first QSPI data based on the currently sampled QSPI data; Determine the next post-jump state, and use the next post-jump state as the current post-jump state, then jump again to the step of executing the data sampling process of entering the corresponding stage based on the current post-jump state until the data sampling processes corresponding to each post-jump state are completed.

3. The verification method of QSPI bus data transmission according to claim 2, wherein The number of bits required to be transmitted at each stage includes the number of instruction bits, the number of address bits, the number of alternating byte bits, the number of empty cycles and the number of data bits; Accordingly, the controlling of the local state machine to perform a state jump operation based on each of the bit numbers to obtain each post-jump state includes: If the instruction bit number is a non-zero value, controlling the local state machine to jump from an initial state to an instruction state corresponding to the instruction phase, and performing a data sampling operation of the instruction phase; If the number of address bits is a non-zero value, after executing the data sampling operation of the instruction phase, controlling the local state machine to jump from the instruction state to the address state corresponding to the address phase, and executing the data sampling operation of the address phase; If the number of alternating byte bits is a non-zero value, after executing the data sampling operation of the address phase, controlling the local state machine to jump from the address state to the alternating byte state corresponding to the alternating byte phase, and executing the data sampling operation of the alternating byte phase; If the number of empty cycles is a non-zero value, after executing the data sampling operation in the alternating byte phase, the local state machine is controlled to jump from the alternating byte state to the empty instruction cycle state corresponding to the empty instruction cycle phase, and execute the data sampling operation in the empty instruction cycle phase; If the number of data bits is a non-zero value, after executing the data sampling operation of the empty instruction cycle phase, the local state machine is controlled to jump from the empty instruction cycle state to the data state corresponding to the data phase, and the data sampling operation of the data phase is executed. Then, after executing the data sampling operation of the data phase, the local state machine is controlled to jump from the empty instruction cycle state to the initial state.

4. The verification method of QSPI bus data transmission according to claim 3, wherein The data phase includes a data writing phase and a data reading phase, and the number of data bits includes a number of write data bits and a number of read data bits; Correspondingly, if the number of data bits is a non-zero value, controlling the local state machine to jump from the idle instruction cycle state to the data state corresponding to the data phase after executing the data sampling operation in the idle instruction cycle phase includes: If the preset read / write flag is a first preset value and the number of write data bits is a non-zero value, controlling the local state machine to jump from the idle instruction cycle state to the write data state corresponding to the write data phase after executing the data sampling operation in the idle instruction cycle phase; If the preset read / write flag is a second preset value and the number of read data bits is a non-zero value, then after executing the data sampling operation of the empty instruction cycle phase, the local state machine is controlled to jump from the empty instruction cycle state to the read data state corresponding to the read data phase.

5. The verification method of QSPI bus data transmission according to claim 2, wherein The output end of the QSPI controller includes four input and output signal lines; Accordingly, sampling QSPI data from the output end of the QSPI controller includes: Obtaining an input / output enable signal sent by the QSPI controller through a target interface; Determining a target input / output signal line currently used by the QSPI controller based on the input / output enable signal; wherein the target input / output signal line is any one, any two, or four of the four input / output signal lines; The QSPI data is sampled from the target input and output signal lines of the QSPI controller through the target interface.

6. The verification method of QSPI bus data transmission according to claim 1, wherein The sending the first QSPI data to a preset checker includes: Converting the first QSPI data from a serial data format to a parallel data format to obtain converted first QSPI data; The converted first QSPI data is encapsulated into a transaction object, and the transaction object is sent to a preset checker through a transaction-level modeling port.

7. The method for verifying QSPI bus data transmission according to any one of claims 1 to 6, wherein: The QSPI monitor and the checker are located in a preset verification platform, and the preset verification platform further includes an AHB master device verification component; wherein the AHB master device verification component and the QSPI monitor are respectively connected to the checker, and the AHB master device verification component includes a driver and a monitor; Accordingly, the process of the checker acquiring the second QSPI data includes: The driver in the AHB master device verification component writes the second QSPI data to the register in the QSPI monitor through the target interface; The monitor in the AHB master device verification component sends the second QSPI data to the checker.

8. A QSPI bus data transmission verification device, characterized in that: Applicable to a preset QSPI monitor, the device comprises: A bit number acquisition module is used to obtain the number of bits required to be transmitted in each phase of the test case from a preset global configuration database; wherein the phases include, in the target order, the instruction phase, the address phase, the alternating byte phase, the empty instruction cycle phase, and the data phase; a state machine control module, configured to control a local state machine to perform a state jump operation based on each of the bit numbers to obtain each post-jump state, and to enter a data sampling process of a corresponding stage based on each of the post-jump states to sample first QSPI data from an output of the QSPI controller; wherein the local state machine is pre-set with states corresponding to different stages, and if the number of bits corresponding to a current stage is a non-zero value, the local state machine is controlled to jump to a first state corresponding to the current stage; otherwise, a target stage corresponding to the next non-zero number of bits is determined based on the target sequence, and the local state machine is controlled to jump to a second state corresponding to the target stage; A comparison module is configured to send the first QSPI data to a preset checker so that the checker compares the consistency between the first QSPI data and second QSPI data and obtains a verification result; wherein the second QSPI data is data sampled from an input end of the QSPI controller.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the QSPI bus data transmission verification method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that Used to store a computer program; wherein, when the computer program is executed by a processor, the steps of the QSPI bus data transmission verification method according to any one of claims 1 to 7 are implemented.

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