A verification method, device and equipment for QSPI bus data transmission and a medium

Abstract

The application discloses a QSPI bus data transmission verification method and device, equipment and medium, and relates to the chip verification technical field, which comprises the following steps: acquiring the number of bits required to be transmitted in each stage of a test case; controlling a state machine to perform a state jump operation based on the number of bits, entering a data sampling process corresponding to each state after jumping to sample first QSPI data from the output end of a QSPI controller; the state machine is provided with states corresponding to different stages in advance, if the number of bits corresponding to the current stage is a non-zero value, jumping to a first state corresponding to the current stage, otherwise determining a target stage corresponding to the number of bits of the next non-zero value to jump to a second state corresponding to the target stage; sending the first QSPI data to a checker to obtain a verification result by comparing the consistency between the first QSPI data and second QSPI data; and the second QSPI data is sampled from the input end of the QSPI controller.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip verification, and in particular to a QSPI bus data transmission verification method and device, equipment and medium. BACKGROUND

[0002] In the chip development process, chip verification is a key link to guarantee the quality and performance of the chip, and its core task is to check the logical function accuracy of the DUT (Device Under Test, Device Under Test) design code and the reliability of the chip performance. Chip verification personnel need to deeply study design documents and architecture documents in the early and middle stages of development, accurately grasp the module function, role in the subsystem or system on a chip, and the interaction with other devices, and then develop a comprehensive verification plan.

[0003] QSPI (Quad Serial Peripheral Interface, Quad Serial Peripheral Interface) as a serial data transmission protocol is widely used in data interaction between system on a chip and external flash devices. QSPI supports transmitting 4-bit data in a single clock cycle, and is compatible with single-line and double-line working modes. The data flow specified by the QSPI protocol covers five stages: instruction, address, alternating byte, null instruction cycle, and data. In actual application, some stages can be skipped according to requirements, but at least one of the instruction, address, alternating byte, or data stages must be included. To achieve communication with external Flash devices, system on a chip usually integrates a QSPI controller, which is mainly used to complete read and write operations on Flash by sending and receiving QSPI data streams.

[0004] When verifying the QSPI controller, it is crucial to ensure that the data written and read by the QSPI controller to the Flash is consistent with the expected value. The traditional verification method is to first let the QSPI controller write data to the Flash, then read it out and compare whether they are consistent. However, this method only indirectly verifies the data consistency and cannot directly monitor the data on the QSPI four serial data transmission lines. It cannot determine whether the data transmitted in each stage of the data stream sent by the QSPI controller is completely consistent with the configuration data, thereby bringing risks to the correctness of the verification result, which may cause data transmission errors and other problems in the actual use of the chip, affecting the overall performance and reliability of the chip.

[0005] In summary, how to accurately check whether the data transmitted in each stage of the data stream sent by the QSPI controller is correct to reduce the risk of missed detection is a problem to be solved at present. SUMMARY

[0006] In view of this, the purpose of the present application is to provide a QSPI bus data transmission verification method, device, equipment and medium, which can accurately check whether the data transmitted in each stage of the data stream sent by the QSPI controller is correct, so as to reduce the risk of missed detection. The specific scheme is as follows:

[0007] In the first aspect, the present application discloses a QSPI bus data transmission verification method, applied to a preset QSPI monitor, comprising:

[0008] Obtain the number of bits required for transmission in each stage of the test case from the preset global configuration database; wherein each stage includes an instruction stage, an address stage, an alternating byte stage, an empty instruction period stage and a data stage in turn according to the target order;

[0009] Control the local state machine to perform state jump operation based on the number of bits to obtain each state after jumping, and enter the data sampling process of the corresponding stage based on each state after jumping to sample the first QSPI data from the output end of the QSPI controller; wherein the local state machine is pre-set with states corresponding to different stages, if the number of bits corresponding to the current stage is a non-zero value, control the local state machine to jump to the first state corresponding to the current stage, otherwise determine the target stage corresponding to the next non-zero value based on the target order, to control the local state machine to jump to the second state corresponding to the target stage;

[0010] Send the first QSPI data to the preset checker, so that the checker compares the consistency between the first QSPI data and the second QSPI data and obtains the verification result; wherein the second QSPI data is the data sampled from the input end of the QSPI controller.

[0011] Optionally, based on each state after jumping, enter the data sampling process of the corresponding stage to sample the first QSPI data from the output end of the QSPI controller, comprising:

[0012] Enter the data sampling process of the corresponding stage based on the current state after jumping, and start the counter corresponding to the current state after jumping;

[0013] Sample the QSPI data from the output end of the QSPI controller, and use the counter to count the number of bits of the currently sampled QSPI data to obtain the counter value;

[0014] When the counter value is the same as the number of bits of the corresponding stage obtained from the global configuration database, stop the data sampling operation corresponding to the current state after jumping, and obtain the first QSPI data based on the currently sampled QSPI data;

[0015] determining a next post-jump state, taking the next post-jump state as a current post-jump state, and re-jumping to perform a step of executing a data sampling process based on the current post-jump state into a corresponding phase until the data sampling processes corresponding to all post-jump states are executed completely.

[0016] Optionally, the number of bits required for transmission in each phase includes a number of instruction bits, a number of address bits, a number of alternating byte bits, a number of empty cycles, and a number of data bits.

[0017] Correspondingly, the local state machine is controlled to perform state jump operations based on the numbers of bits to obtain the post-jump states, including:

[0018] If the number of instruction bits is a non-zero value, the local state machine is controlled to jump from an initial state to an instruction state corresponding to an instruction phase, and perform a data sampling operation of the instruction phase.

[0019] If the number of address bits is a non-zero value, the local state machine is controlled to jump from the instruction state to an address state corresponding to an address phase after the data sampling operation of the instruction phase is performed, and perform a data sampling operation of the address phase.

[0020] If the number of alternating byte bits is a non-zero value, the local state machine is controlled to jump from the address state to an alternating byte state corresponding to an alternating byte phase after the data sampling operation of the address phase is performed, and perform a data sampling operation of the alternating byte phase.

[0021] If the number of empty cycles is a non-zero value, the local state machine is controlled to jump from the alternating byte state to an empty instruction cycle state corresponding to an empty instruction cycle phase after the data sampling operation of the alternating byte phase is performed, and perform a data sampling operation of the empty instruction cycle phase.

[0022] If the number of data bits is a non-zero value, the local state machine is controlled to jump from the empty instruction cycle state to a data state corresponding to a data phase after the data sampling operation of the empty instruction cycle phase is performed, and perform a data sampling operation of the data phase, and then the local state machine is controlled to jump from the empty instruction cycle state to the initial state after the data sampling operation of the data phase is performed.

[0023] Optionally, the data phase includes a write data phase and a read data phase, and the number of data bits includes a number of write data bits and a number of read data bits.

[0024] Correspondingly, if the number of data bits is a non-zero value, the local state machine is controlled to jump from the empty instruction cycle state to the data state corresponding to the data phase after the data sampling operation of the empty instruction cycle phase is performed, including:

[0025] If the preset read-write flag is the first preset value and the number of write data bits is a non-zero value, the local state machine is controlled to jump from the empty instruction cycle state to a write data state corresponding to the write data stage after the data sampling operation in the empty instruction cycle stage is performed.

[0026] If the preset read-write flag is the second preset value and the number of read data bits is a non-zero value, the local state machine is controlled to jump from the empty instruction cycle state to a read data state corresponding to the read data stage after the data sampling operation in the empty instruction cycle stage is performed.

[0027] Optionally, the output end of the QSPI controller includes four input and output signal lines.

[0028] Correspondingly, the QSPI data is sampled from the output end of the QSPI controller, including:

[0029] The input and output enable signal sent by the QSPI controller through the target interface is acquired;

[0030] The target input and output signal line currently used by the QSPI controller is determined based on the input and output enable signal; wherein the target input and output signal line is any one, any two or four of the four input and output signal lines;

[0031] The QSPI data is sampled from the target input and output signal line of the QSPI controller through the target interface.

[0032] Optionally, sending the first QSPI data to the preset checker includes:

[0033] Converting the first QSPI data from a serial data format to a parallel data format to obtain converted first QSPI data;

[0034] Packaging the converted first QSPI data into a transaction object, and sending the transaction object to the preset checker through a transaction-level modeling port.

[0035] Optionally, the QSPI monitor and the checker are located in a preset verification platform, and the preset verification platform further includes an AHB master verification component; wherein the AHB master verification component and the QSPI monitor are respectively connected with the checker, and the AHB master verification component includes a driver and a monitor;

[0036] Correspondingly, the process of the checker acquiring the second QSPI data includes:

[0037] The driver in the AHB master verification component writes the second QSPI data to the register in the QSPI monitor through the target interface;

[0038] The monitor in the AHB master verification component sends the second QSPI data to the checker.

[0039] In a second aspect, the application discloses a verification device for QSPI bus data transmission, applied to a preset QSPI monitor, and the device comprises:

[0040] a bit number acquisition module, configured to acquire bit numbers required for transmission of test cases in each stage from a preset global configuration database; wherein each stage comprises an instruction stage, an address stage, an alternating byte stage, a null instruction cycle stage and a data stage in a target order;

[0041] a state machine control module, configured to control a local state machine to perform a state jump operation based on the bit numbers, so as to obtain each post-jump state, and based on each post-jump state, enter a data sampling process of a corresponding stage, so as to sample first QSPI data from an output end of a QSPI controller; wherein the local state machine is pre-set with states corresponding to different stages, if a bit number corresponding to a current stage is a non-zero value, the local state machine is controlled to jump to a first state corresponding to the current stage, otherwise, a target stage corresponding to a next non-zero value bit number is determined based on the target order, so as to control the local state machine to jump to a second state corresponding to the target stage;

[0042] a comparison module, configured to send the first QSPI data to a preset checker, so that the checker compares consistency between the first QSPI data and second QSPI data and obtains a verification result; wherein the second QSPI data is data sampled from an input end of the QSPI controller.

[0043] In a third aspect, the application discloses an electronic device, comprising:

[0044] a memory, configured to save a computer program;

[0045] a processor, configured to execute the computer program, so as to realize steps of the verification method for QSPI bus data transmission disclosed above.

[0046] In a fourth aspect, the application discloses a computer readable storage medium, configured to store a computer program; wherein the computer program is executed by a processor to realize steps of the verification method for QSPI bus data transmission disclosed above.

[0047] It can be seen that the QSPI monitor in the application obtains the number of bits required for transmission of the test case at each stage from the preset global configuration database; wherein each stage includes an instruction stage, an address stage, an alternating byte stage, a null instruction cycle stage and a data stage in turn according to the target order; based on the number of bits, a local state machine is controlled to perform a state jump operation to obtain each state after jumping, and based on each state after jumping, a data sampling process of the corresponding stage is entered to sample first QSPI data from the output end of the QSPI controller; wherein the local state machine is pre-set with states corresponding to different stages, if the number of bits corresponding to the current stage is a non-zero value, the local state machine is controlled to jump to a first state corresponding to the current stage, otherwise, based on the target order, a target stage corresponding to the number of bits of the next non-zero value is determined to control the local state machine to jump to a second state corresponding to the target stage; the first QSPI data is sent to a preset checker so that the checker compares the consistency between the first QSPI data and second QSPI data and obtains a verification result; wherein the second QSPI data is data sampled from the input end of the QSPI controller.

[0048] Beneficial effects: The QSPI monitor in the present application first needs to obtain the number of bits required for transmission in each phase of the test case from the preset global configuration database, to control the state jump operation of the local state machine based on the number of bits, to obtain each jump state, and to enter the data sampling process of the corresponding phase based on each jump state, to sample the first QSPI data from the output end of the QSPI controller. That is, the number of bits can accurately control the jump data sampling process of the state machine according to the specific test requirements. Considering that different test cases may have different requirements for the number of bits in each phase, this way can ensure that the expected amount of data is accurately collected in each phase, avoiding deviations in the verification result due to inaccurate sampling. And the present application covers the instruction phase, address phase, alternating byte phase, empty instruction cycle phase and data phase of the QSPI bus data transmission, through the state jump operation of the state machine, the data of each phase can be sampled, ensuring the comprehensive coverage of the verification process on the whole QSPI data transmission process, so as to more accurately detect possible problems. In addition, through the automatic state jump operation of the local state machine, the automatic control of data sampling in each phase is realized, without manual intervention in the switching of each phase, reducing human errors in the verification process and improving the verification efficiency. Further, the present application samples the data of each phase respectively, and compares the first QSPI data sampled from the output end with the second QSPI data sampled from the input end for consistency, and obtains the verification result. If inconsistencies are found in the comparison process, it can be easily determined which phase has a problem, so as to quickly locate the fault point and facilitate debugging and repair. In this way, the present application can accurately check whether the data transmitted in each phase of the data stream transmitted by the QSPI controller is correct, so as to reduce the risk of missing detection. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0050] Figure 1 A QSPI bus data transmission verification method flowchart disclosed by the present application;

[0051] Figure 2 A UVM-based QSPI controller verification platform schematic diagram disclosed by the present application;

[0052] Figure 3 A schematic diagram corresponding to different phases in the QSPI data transmission process;

[0053] Figure 4 A method flow chart of data sampling disclosed by the present application;

[0054] Figure 5 A state jump schematic diagram in a state machine disclosed by the present application;

[0055] Figure 6 A verification device structure schematic diagram of QSPI bus data transmission disclosed by the present application;

[0056] Figure 7 An electronic device structure diagram disclosed by the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0058] When verifying the QSPI controller, it is crucial to ensure that the data written and read by the QSPI controller to the Flash is consistent with the expectation. The traditional verification method is to let the QSPI controller write data to the Flash first, and then read out and compare whether the two are consistent. However, this method only indirectly verifies the data consistency, cannot directly monitor the data on the four serial data transmission lines of the QSPI, and cannot judge whether the data transmitted in each stage of the data stream sent by the QSPI controller is completely consistent with the configuration data, thereby bringing risks to the correctness of the verification result, which may cause problems such as data transmission errors in actual use of the chip, and affect the overall performance and reliability of the chip. Therefore, the embodiments of the present application disclose a verification method, device, equipment and medium for QSPI bus data transmission, which can accurately check whether the data transmitted in each stage of the data stream sent by the QSPI controller is correct, so as to reduce the risk of missed detection.

[0059] Referring to Figure 1 The embodiments of the present application disclose a verification method for QSPI bus data transmission, applied to a preset QSPI monitor, which comprises the following steps:

[0060] Step S11: acquiring the number of bits required to be transmitted in each stage of the test case from a preset global configuration database; wherein each stage includes an instruction stage, an address stage, an alternating byte stage, a null instruction cycle stage and a data stage in a target order in turn.

[0061] The embodiment discloses a QSPI monitor (i.e., QSPI_Monitor) for collecting QSPI data based on a data stream format of QSPI and a universal verification methodology (UVM) and integrates the QSPI monitor into a verification platform as shown in Figure 2 In the verification platform, the QSPI controller is a device under test (DUT), and an output port signal of the QSPI controller is connected with a flash memory. When a write instruction is received, the flash memory can store data output on an input / output (I / O) line of the QSPI controller. When a read instruction is received, the flash memory can drive stored data to the I / O line according to a timing sequence defined by QSPI.

[0062] The QSPI monitor needs to obtain bit numbers required for transmission in each stage of a test case from a preset global configuration database. The stages include, in a target order, an instruction stage, an address stage, an alternating byte stage, a dummy instruction cycle stage and a data stage. Figure 3 FIG. 2 is a schematic diagram of QSPI data transmission corresponding to different stages.

[0063] It is noted that the embodiment of the application uses a uvm_config_db mechanism to pass the bit numbers of serial data in each stage to the QSPI monitor in a test case at a top level, so that the QSPI monitor determines the number of subsequent sampling times according to the bit numbers of data in each stage. The uvm_config_db is a global configuration database used to dynamically pass configuration parameters between different components.

[0064] In step S12, a state jump operation of a local state machine is controlled based on the bit numbers, to obtain states after the jumps, and a data sampling process in a corresponding stage is entered based on each state after the jumps, to sample first QSPI data from an output terminal of the QSPI controller. The local state machine is previously set with states corresponding to different stages. If the bit number corresponding to a current stage is a non-zero value, the local state machine is controlled to jump to a first state corresponding to the current stage. Otherwise, a target stage corresponding to a bit number of a next non-zero value is determined based on a target order, to control the local state machine to jump to a second state corresponding to the target stage.

[0065] In this embodiment, the number of bits obtained can be used to accurately control the data sampling process after the state machine jumps according to specific test requirements. Considering that different test cases may have different requirements for the number of bits in each phase, this method can ensure that the expected amount of data is accurately collected in each phase, avoiding deviations in the verification results due to inaccurate sampling. Therefore, this embodiment needs to control the local state machine to perform a state jump operation based on the number of bits to obtain each post-jump state, and enter the data sampling process of the corresponding phase based on each post-jump state to sample the first QSPI data from the output end of the QSPI controller.

[0066] Furthermore, the embodiments of the present application cover the instruction phase, address phase, alternating byte phase, null instruction cycle phase and data phase of QSPI bus data transmission. Through the state jump operation of the state machine, the data of each phase can be sampled, ensuring comprehensive coverage of the entire QSPI data transmission process in the verification process, thereby more accurately detecting possible problems. In addition, through the automatic state jump operation of the local state machine, automatic control of data sampling in each phase is realized, without the need for manual intervention in each phase switching, reducing human errors in the verification process and improving verification efficiency.

[0067] In the specific implementation, as shown in Figure 4 the data sampling process of the corresponding phase based on each post-jump state to sample the first QSPI data from the output end of the QSPI controller includes the following steps:

[0068] Step S121: Enter the data sampling process of the corresponding phase based on the current post-jump state, and start the counter corresponding to the current post-jump state.

[0069] In this embodiment, for each post-jump state, the data sampling process of the corresponding phase needs to be entered, and each post-jump state is provided with a corresponding counter. Therefore, after entering the data sampling process of the corresponding phase of the current post-jump state, the counter corresponding to the current post-jump state needs to be started.

[0070] Step S122: Sample QSPI data from the output end of the QSPI controller, and use the counter to count the number of bits of the currently sampled QSPI data to obtain the counter value.

[0071] In this embodiment, QSPI data is sampled from the output end of the QSPI controller, and the counter is used to count the number of bits of the currently sampled QSPI data to obtain the counter value.

[0072] Step S123: When the counter value is the same as the number of bits of the corresponding stage obtained from the global configuration database, stop the data sampling operation corresponding to the current jump state, and obtain the first QSPI data based on the currently sampled QSPI data.

[0073] In this embodiment, when the counter value is equal to the number of bits of the corresponding stage obtained from the global configuration database, it indicates that the data sampling operation of the stage corresponding to the current jump state has been completed, and the QSPI data collected at this time is recorded as the first QSPI data.

[0074] Step S124: Determine the next post-jump state and use the next post-jump state as the current post-jump state. Then, jump back to the step of executing the data sampling process that enters the corresponding stage based on the current post-jump state, until the data sampling process corresponding to each post-jump state is completed.

[0075] In this embodiment, after completing the data sampling of the stage corresponding to the current jump state, the next jump state is determined and used as the current jump state. Then, the process jumps back to the step of executing the data sampling process based on the current jump state to enter the corresponding stage, until the data sampling process corresponding to each jump state is completed.

[0076] It should be noted that the output of the QSPI controller includes four input / output signal lines. Correspondingly, sampling QSPI data from the output of the QSPI controller includes: acquiring the input / output enable signal sent by the QSPI controller through the target interface; determining the target input / output signal lines currently used by the QSPI controller based on the input / output enable signal; wherein the target input / output signal lines can be any one, any two, or all four of the four input / output signal lines; and sampling QSPI data from the target input / output signal lines of the QSPI controller through the target interface. That is, the QSPI controller can transmit the input / output enable signal of the IO lines to the QSPI monitor through the target interface, and the QSPI monitor can determine the target input / output signal lines currently used by the QSPI controller based on the input / output enable signal, thereby sampling QSPI data from the target input / output signal lines of the QSPI controller through the target interface; wherein the target input / output signal lines can be any one, any two, or all four of the four input / output signal lines. In other words, this embodiment can utilize this input / output enable signal to simultaneously support single-line, dual-line, and four-line sampling. When the required number of bits is 8, it takes 8 clock cycles in single-wire mode, i.e., 1 bit is sampled per cycle, and 2 clock cycles in four-wire mode, i.e., 4 bits are sampled per cycle.

[0077] Specifically, the number of bits required to be transmitted at each stage includes the number of instruction bits, address bits, alternating byte bits, number of empty cycles, and number of data bits. Correspondingly, based on each bit count, the local state machine is controlled to perform state transition operations to obtain the state after each transition, including: if the number of instruction bits is non-zero, the local state machine is controlled to transition from the initial state to the instruction state corresponding to the instruction stage, and the data sampling operation of the instruction stage is performed; if the number of address bits is non-zero, after performing the data sampling operation of the instruction stage, the local state machine is controlled to transition from the instruction state to the address state corresponding to the address stage, and the data sampling operation of the address stage is performed; if the number of alternating byte bits is non-zero, after performing the data sampling operation of the address stage, the local state machine is controlled to transition from the instruction state to the address state corresponding to the address stage, and the data sampling operation of the address stage is performed; if the number of alternating byte bits is non-zero, after performing the data sampling operation of the address stage, the local state machine is controlled to transition from the instruction state to the address state, and the data sampling operation of the address stage is performed. The local state machine jumps from the address state to the alternating byte state corresponding to the alternating byte stage and performs data sampling operations for the alternating byte stage. If the number of empty cycles is non-zero, after performing data sampling operations for the alternating byte stage, the local state machine is controlled to jump from the alternating byte state to the empty instruction cycle state corresponding to the empty instruction cycle stage and performs data sampling operations for the empty instruction cycle stage. If the number of data bits is non-zero, after performing data sampling operations for the empty instruction cycle stage, the local state machine is controlled to jump from the empty instruction cycle state to the data state corresponding to the data stage and performs data sampling operations for the data stage. Then, after performing data sampling operations for the data stage, the local state machine is controlled to jump from the empty instruction cycle state to the initial state.

[0078] The data phase includes a write data phase and a read data phase, and the number of data bits includes the number of write data bits and the number of read data bits. Accordingly, if the number of data bits is non-zero, after the data sampling operation of the empty instruction cycle phase is completed, the local state machine is controlled to jump from the empty instruction cycle state to the data state corresponding to the data phase. This includes: if the preset read / write flag is a first preset value and the number of write data bits is non-zero, then after the data sampling operation of the empty instruction cycle phase is completed, the local state machine is controlled to jump from the empty instruction cycle state to the write data state corresponding to the write data phase; if the preset read / write flag is a second preset value and the number of read data bits is non-zero, then after the data sampling operation of the empty instruction cycle phase is completed, the local state machine is controlled to jump from the empty instruction cycle state to the read data state corresponding to the read data phase.

[0079] First, it's important to note that a complete data stream on the QSPI bus consists of five stages: instruction, address, alternating byte, no-instruction cycle, and data. In some cases, there may be fewer than these five stages. For example, when a write enable instruction is sent to Flash, the serial data stream only contains the instruction stage. Furthermore, QSPI supports single-wire, two-wire, and four-wire transmission. This necessitates that the QSPI monitor accurately identify each data stage from the serial data stream, sample data from each stage, and support single-wire, two-wire, and four-wire sampling. To achieve these functions, this embodiment incorporates a state machine within the QSPI monitor. The state machine includes six states: initial state (IDLE), instruction state (INSTRUCTION) corresponding to the instruction phase, address state (ADDR) corresponding to the address phase, alternating byte state (ALT) corresponding to the alternating byte phase, empty instruction cycle state (DUMMY) corresponding to the empty instruction cycle phase, write data state (WRITE_DATA) corresponding to the write data phase, and read data state (READ_DATA) corresponding to the read data phase. Controlling the state machine's transitions ensures that the QSPI monitor can correctly sample data from each phase.

[0080] First, the local state machine is in the initial state. If the number of instruction bits, address bits, alternating byte bits, empty cycle count, and data bits are all non-zero, the local state machine is first controlled to jump from the initial state to the instruction state and perform data sampling operations in the instruction phase. Next, the local state machine is controlled to jump from the instruction state to the address state and perform data sampling operations in the address phase. Then, the local state machine is controlled to jump from the address state to the alternating byte state and perform data sampling operations in the alternating byte phase. Next, the local state machine is controlled to jump from the alternating byte state to the empty instruction cycle state and perform data sampling operations in the empty instruction cycle phase. Finally, the local state machine is controlled to jump from the empty instruction cycle state to the data state and perform data sampling operations in the data phase. After completing the data sampling operations in the data phase, the local state machine is finally controlled to return to the initial state from the empty instruction cycle state. The data phase can specifically include a data writing phase and a data reading phase, and the corresponding data bit count includes the number of data writing bits and the number of data reading bits. In this embodiment, a preset read / write flag is_write is set. If the read / write flag is_write is equal to the first preset value 1 and the number of data writing bits is not equal to 0, the local state machine is controlled to jump to the data writing state. If the read / write flag is_write is equal to the second preset value 0 and the number of data reading bits is not equal to 0, the local state machine is controlled to jump to the data reading state.

[0081] Step S13: Send the first QSPI data to a preset checker so that the checker can compare the consistency between the first QSPI data and the second QSPI data and obtain the verification result; wherein, the second QSPI data is the data sampled from the input terminal of the QSPI controller.

[0082] In this embodiment, data from each stage is sampled separately, and the consistency of the first QSPI data sampled from the output end and the second QSPI data sampled from the input end is compared to obtain the verification result. If an inconsistency is found during the comparison, it is easy to determine which stage of the data has a problem, thereby quickly locating the fault point and facilitating debugging and repair. In this way, this application can accurately check whether the data transmitted in each stage of the data stream sent by the QSPI controller is correct, thereby reducing the risk of missed detections.

[0083] When data from multiple stages is collected, corresponding first QSPI data is collected for each stage. Therefore, depending on the verification requirements and design complexity, one of the following two schemes can be adopted to send the first QSPI data to the checker. In the first scheme, after data from each stage is collected, the corresponding first QSPI data is sent to the checker for comparison. This scheme is suitable for scenarios with high real-time requirements, quickly detecting errors in specific stages (such as instructions or addresses) without waiting for the complete data stream to finish. Furthermore, the stages are highly independent, and the correctness of each stage's data can be verified independently; for example, errors in the instruction stage can be immediately reported without affecting subsequent data. In the second scheme, after data from all stages is collected, the first QSPI data from each stage is aggregated and sent to the checker for comparison. This scheme is suitable for scenarios with strong inter-stage correlation, verifying the correctness of multi-stage combinations as a whole, such as the complete transmission of the instruction stage + address stage + data stage. It is also suitable for protocol integrity checks; for example, QSPI read / write operations must ensure consistency across all stages, such as the written address and data needing to match completely.

[0084] In a specific implementation, sending the first QSPI data to a preset checker includes: converting the first QSPI data from a serial data format to a parallel data format to obtain converted first QSPI data; encapsulating the converted first QSPI data into a transaction object; and sending the transaction object to the preset checker through a transaction-level modeling port. That is, the QSPI monitor in this embodiment can collect data from the instruction phase, address phase, alternating byte phase, null instruction phase, and data phase of the QSPI serial data stream. Then, it converts the collected first QSPI data from a serial data format to a parallel data format to obtain converted first QSPI data. Finally, it encapsulates the converted first QSPI data into a transaction object and sends the transaction object to the checker in the preset verification platform through a transaction-level modeling port (TLM_port) to compare whether the data at each stage of the QSPI serial data stream is consistent with the expected data.

[0085] It should also be noted that the QSPI monitor and checker are located on a preset verification platform, which also includes an AHB master device verification component. The AHB master device verification component and the QSPI monitor are connected to the checker, and the AHB master device verification component includes a driver and a monitor. Accordingly, the process by which the checker acquires the second QSPI data includes: the driver in the AHB master device verification component writes the second QSPI data to the register in the QSPI monitor through the target interface; the monitor in the AHB master device verification component sends the second QSPI data to the checker. It is understood that, as... Figure 2 As shown, the verification environment contains three main components: the AHB Master Verification Component (AHB_MASTER), the Checker, and the QSPI Monitor. The AHB Master Verification Component and the QSPI Monitor are connected to the Checker. The driver in the AHB Master Verification Component can write the instructions, addresses, and data to be sent into the QSPI controller's registers via the target interface, denoted as the second QSPI data. The monitor in the AHB Master Verification Component can then transmit this second QSPI data to the Checker. The QSPI Monitor is responsible for collecting the serial data from the four QSPI I / O lines via the target interface, i.e., the aforementioned first QSPI data, and sending it to the Checker to compare whether the data input to the QSPI controller and the data output to the QSPI controller are consistent.

[0086] As can be seen, the QSPI monitor in this application first needs to obtain the number of bits required to be transmitted in each stage of the test case from a preset global configuration database. Based on the number of bits, it controls the local state machine to perform state transition operations to obtain the state after each transition. Then, based on each state after the transition, it enters the data sampling process of the corresponding stage to sample the first QSPI data from the output of the QSPI controller. That is, the number of bits can be used to precisely control the data sampling process after the state machine transition according to specific test requirements. Considering that different test cases may have different requirements for the number of bits in each stage, this method can ensure that the expected amount of data is accurately collected in each stage, avoiding deviations in the verification results due to inaccurate sampling. Furthermore, this application covers the instruction stage, address stage, alternating byte stage, empty instruction cycle stage, and data stage of QSPI bus data transmission. Through the state transition operations of the state machine, data in each stage can be sampled, ensuring that the verification process fully covers the entire QSPI data transmission process, thereby more accurately detecting potential problems. Furthermore, by implementing automatic state transitions through the local state machine, automated control of data sampling at each stage is achieved, eliminating the need for manual intervention in stage switching, reducing human error during verification, and improving verification efficiency. Further, this application samples data from each stage separately and compares the consistency of the first QSPI data sampled from the output with the second QSPI data sampled from the input to obtain the verification result. If inconsistencies are found during the comparison, it is easy to determine which stage's data has a problem, thus quickly locating the fault point and facilitating debugging and repair. In this way, this application can accurately check the correctness of data transmitted at each stage in the data stream sent by the QSPI controller, reducing the risk of missed detections.

[0087] Figure 5 This is a schematic diagram of state transitions in a state machine disclosed in this application. The conditions for transitions between states are as follows, wherein the following numbers (1) to (21) are related to... Figure 5 The serial numbers in the table correspond one-to-one:

[0088] (1) The initial state of the state machine is IDLE. When the instruction bit count instruction_bits is not equal to 0, the state machine jumps to INSTRUCTION and starts sampling instruction data. At the same time, the counter instruction_cnt will also record the number of instruction bits sampled.

[0089] (2) When the value of instruction_cnt is equal to the number of instruction bits, it means that the instruction stage sampling is completed. At this time, if the number of address bits, addr_bits, is not equal to 0, the state machine jumps to the ADDR state and starts sampling address data. At the same time, the counter addr_cnt will also record the number of address bits sampled.

[0090] (3) When the value of instruction_cnt is equal to the number of instruction bits, it means that the instruction stage sampling is completed. At this time, if the number of address bits, addr_bits, is equal to 0 and the number of alternating byte bits, alt_bits, is not equal to 0, the state machine jumps to the ALT state and starts sampling alternating byte data. At the same time, the counter alt_cnt will also record the number of alternating byte bits sampled.

[0091] (4) When the value of instruction_cnt is equal to the number of instruction bits, it means that the sampling of the instruction stage is completed. At this time, if the number of address bits, addr_bits, is equal to 0, the number of alternating byte bits, alt_bits, is equal to 0, and the number of empty cycles, dummy_num, is not equal to 0, the state machine jumps to the DUMMY state. At the same time, the counter dummy_cnt will also record the number of empty cycles.

[0092] (5) When the value of instruction_cnt is equal to the number of instruction bits, it means that the instruction phase sampling is complete. At this time, if the number of address bits, addr_bits, is equal to 0, the number of alternating byte bits, alt_bits, is equal to 0, the number of empty cycles, dummy_num, is equal to 0, the read / write flag is_write is equal to 1, and the number of write data bits, wdata_bits, is not equal to 0, then the state machine jumps to the WRITE_DATA state, and the counter wdata_cnt will also record the number of write data bits.

[0093] (6) When the value of instruction_cnt is equal to the number of instruction bits, it means that the instruction phase sampling is complete. At this time, if the number of address bits, addr_bits, is equal to 0, the number of alternating byte bits, alt_bits, the number of empty cycles, dummy_num, is_write, is_write, and the number of read data bits, rdata_bits, is not equal to 0, the state machine jumps to the READ_DATA state, and the counter rdata_cnt will also record the number of read data bits.

[0094] (7) When the value of instruction_cnt is equal to the number of instruction bits, it means that the sampling of the instruction stage is completed. At this time, if the number of address bits, addr_bits, alt_bits, dummy_num, wdata_bit, and rdata_bits are equal to 0, the state machine jumps to the IDLE state.

[0095] (8) When the value of addr_cnt is equal to the number of address bits addr_bits, it means that the address phase sampling is completed. At this time, if the number of alternating byte bits alt_bits is not equal to 0, the state machine jumps to the ALT state and starts sampling alternating byte data. At the same time, the counter alt_cnt will also record the number of alternating byte bits sampled.

[0096] (9) When the value of addr_cnt is equal to the number of address bits addr_bits, it means that the address phase sampling is completed. At this time, if the number of alternating byte bits alt_bits is equal to 0 and the number of empty cycles dummy_num is not equal to 0, the state machine jumps to the DUMMY state. At the same time, the counter dummy_cnt will also record the number of empty cycles.

[0097] (10) When the value of addr_cnt is equal to the number of address bits addr_bits, it means that the address phase sampling is complete. At this time, if the number of alternating byte bits alt_bits is equal to 0, the number of empty cycles dummy_num is equal to 0, the read / write flag is_write is equal to 1, and the number of written data bits wdata_bits is not equal to 0, then the state machine jumps to the WRITE_DATA state, and the counter wdata_cnt will also record the number of written data bits.

[0098] (11) When the value of addr_cnt is equal to the number of address bits addr_bits, it means that the address phase sampling is completed. At this time, if the number of alternating byte bits alt_bits is equal to 0, the number of empty cycles dummy_num is equal to 0, the read / write flag is_write is equal to 0, and the number of read data bits rdata_bits is not equal to 0, then the state machine jumps to the READ_DATA state, and the counter rdata_cnt will also record the number of read data bits.

[0099] (12) When the value of addr_cnt is equal to the number of address bits addr_bits, it means that the address phase sampling is completed. At this time, if the number of alternating byte bits alt_bits is equal to 0, the number of empty cycles dummy_num is equal to 0, the number of write data bits wdata_bit is equal to 0, and the number of read data bits rdata_bits is equal to 0, then the state machine jumps to the IDLE state.

[0100] (13) When the value of alt_cnt is equal to the number of alternating byte bits alt_bits, it means that the alternating byte sampling is complete. At this time, if the number of empty cycles dummy_num is not equal to 0, the state machine jumps to the DUMMY state, and the counter dummy_cnt will also record the number of empty cycles.

[0101] (14) When the value of alt_cnt is equal to the number of alternating byte bits alt_bits, it means that the alternating byte sampling is complete. At this time, if the number of empty cycles dummy_num is equal to 0, the read / write flag is_write is equal to 1, and the number of written data bits wdata_bits is not equal to 0, the state machine jumps to the WRITE_DATA state. At the same time, the counter wdata_cnt will also record the number of written data bits.

[0102] (15) When the value of alt_cnt is equal to the number of alternating byte bits alt_bits, it means that the alternating byte sampling is complete. At this time, if the number of empty cycles dummy_num is equal to 0, the read / write flag is_write is equal to 0, and the number of read data bits rdata_bits is not equal to 0, the state machine jumps to the READ_DATA state. At the same time, the counter rdata_cnt will also record the number of read data bits.

[0103] (16) When the value of alt_cnt is equal to the number of alternating byte bits alt_bits, it means that the alternating byte sampling is complete. At this time, if the number of empty cycles dummy_num is equal to 0, the number of write data bits wdata_bits is equal to 0, and the number of read data bits rdata_bits is equal to 0, then the state machine jumps to the IDLE state.

[0104] (17) When the value of dummy_cnt is equal to the number of empty cycles dummy_num, it means that the sampling of the empty cycle stage is completed. At this time, if the read / write flag is_write is equal to 1 and the number of written data bits wdata_bits is not equal to 0, the state machine jumps to the WRITE_DATA state. At the same time, the counter wdata_cnt will also record the number of written data bits.

[0105] (18) When the value of dummy_cnt is equal to the number of empty cycles dummy_num, it means that the sampling of the empty cycle stage is completed. At this time, if the read / write flag is_write is equal to 0 and the number of read data bits rdata_bits is not equal to 0, the state machine jumps to the READ_DATA state, and the counter rdata_cnt will also record the number of read data bits.

[0106] (19) When the value of dummy_cnt is equal to the number of empty cycles dummy_num, it means that the sampling of the empty cycle stage is completed. At this time, if the number of written data bits wdata_bits is equal to 0 and the number of read data bits rdata_bits is equal to 0, the state machine jumps to the IDLE state.

[0107] (20) When the value of wdata_cnt is equal to the number of data bits to be written wdata_bits, it means that the data writing phase sampling is completed. At this time, the state machine jumps to the IDLE state.

[0108] (21) When the value of rdata_cnt is equal to the number of data bits to be read, rdata_bits, it means that the data reading stage sampling is completed. At this time, the state machine jumps to the IDLE state.

[0109] Taking the INSTRUCTION state as an example, part of the code in the QSPI monitor is as follows:

[0110] @posedge(vif.qspi_sck) begin

[0111] case(state)

[0112] ………

[0113] INSTRUCTION: begin

[0114] vld_bit_cnt = 0;

[0115] sample_data[0] = vif.IO[0]; / / Sample data on the QSPI signal line

[0116] sample_data[1] = vif.IO[1];

[0117] sample_data[2] = vif.IO[2];

[0118] sample_data[3] = vif.IO[3];

[0119] if(vif.IO_en[0]) vld_bit_cnt = vld_bit_cnt+1; / / Determine the valid bits

[0120] if(vif.IO_en[1]) vld_bit_cnt = vld_bit_cnt+1;

[0121] if(vif.IO_en[2]) vld_bit_cnt = vld_bit_cnt+1;

[0122] if(vif.IO_en[3]) vld_bit_cnt = vld_bit_cnt+1;

[0123] instruction = instruction << vld_bit_cnt;

[0124] for (int i = 0; i < vld_bit_cnt; i++) begin / / Convert serial data to parallel data

[0125] instruction[i] = sample_data[i];

[0126] end

[0127] instruction_cnt = instruction_cnt + vld_bit_cnt; / / Record the number of bits sampled.

[0128] if(instruction_cnt == cfg.instruction_bits) begin / / Determine if sampling has ended

[0129] instruction_cnt == 0;

[0130] if (cfg.addr_bits != 0) state == ADDR; / / Jump to ADDR state

[0131] else if (cfg.alt_bits != 0) state = ALT; / / Jump to ALT state

[0132] else if (cfg.dummy_num != 0 ) state = DUMMY; / / Jump to the DUMMY state

[0133] else if(cfg.wdata_bits != 0 && cfg.is_write == 1)

[0134] state = WRITE_DATA; / / Jump to the WRITE_DATA state

[0135] else if(cfg.rdata_bits != 0 && cfg.is_write == 0)

[0136] state = READ_DATA; / / Jump to the READ_DATA state

[0137] else begin

[0138] qspi_tx.instruction = instruction;

[0139] qspi_tx.addr = 0;

[0140] qspi_tx.alt = 0;

[0141] qspi_tx.dum_num = 0;

[0142] state = IDLE; / / Jump to the IDLE state

[0143] mon_ap.wrtie(qspi_tx); / / Send transaction to other components

[0144] end

[0145] end

[0146] end

[0147] As shown in the code above, when the QSPI monitor is in the INSTRUCTION state, it first samples the data on the four I / O signal lines. Based on the I / O enable signal on the interface, it determines which signal lines contain valid bits. Then, it converts the serial-to-parallel data on the I / O signal lines and stores it in the variable `instruction`. When the sampled bit count equals `instruction_bits`, the QSPI_Monitor determines the next state the state machine should transition to based on the bit counts of other stages. If the bit counts of other stages are all 0, it indicates that the serial data stream only has the instruction stage. The state machine will then transition to the IDLE state, place the sampled data in the Transaction, and send it to other components in the verification platform via the TLM_port.

[0148] In this way, the QSPI monitor of this application can identify each stage from the serial data stream of QSPI, accurately sample the data of each stage, and convert the serial data into parallel data. Therefore, it can be integrated into the verification platform to check whether the data transmitted by the QSPI controller is correct, thereby accelerating the construction of the verification platform.

[0149] See Figure 6 As shown in the figure, this application discloses a verification device for QSPI bus data transmission, applied to a preset QSPI monitor. The device includes:

[0150] The bit acquisition module 11 is used to obtain the number of bits required to be transmitted by the test case in each stage from the preset global configuration database; wherein, each stage includes the instruction stage, address stage, alternating byte stage, empty instruction cycle stage and data stage in the target order.

[0151] The state machine control module 12 is used to control the local state machine to perform state transition operations based on each bit number to obtain each transition state, and to enter the corresponding stage of the data sampling process based on each transition state to sample the first QSPI data from the output of the QSPI controller; wherein, the local state machine is pre-set with states corresponding to different stages. If the bit number corresponding to the current stage is non-zero, the local state machine is controlled to jump to the first state corresponding to the current stage. Otherwise, the target stage corresponding to the next non-zero bit number is determined based on the target sequence, and the local state machine is controlled to jump to the second state corresponding to the target stage.

[0152] The comparison module 13 is used to send the first QSPI data to a preset checker so that the checker can compare the consistency between the first QSPI data and the second QSPI data and obtain a verification result; wherein, the second QSPI data is data sampled from the input terminal of the QSPI controller.

[0153] As can be seen, the QSPI monitor in this application first needs to obtain the number of bits required to be transmitted in each stage of the test case from a preset global configuration database. Based on the number of bits, it controls the local state machine to perform state transition operations to obtain the state after each transition. Then, based on each state after the transition, it enters the data sampling process of the corresponding stage to sample the first QSPI data from the output of the QSPI controller. That is, the number of bits can be used to precisely control the data sampling process after the state machine transition according to specific test requirements. Considering that different test cases may have different requirements for the number of bits in each stage, this method can ensure that the expected amount of data is accurately collected in each stage, avoiding deviations in the verification results due to inaccurate sampling. Furthermore, this application covers the instruction stage, address stage, alternating byte stage, empty instruction cycle stage, and data stage of QSPI bus data transmission. Through the state transition operations of the state machine, data in each stage can be sampled, ensuring that the verification process fully covers the entire QSPI data transmission process, thereby more accurately detecting potential problems. Furthermore, by implementing automatic state transitions through the local state machine, automated control of data sampling at each stage is achieved, eliminating the need for manual intervention in stage switching, reducing human error during verification, and improving verification efficiency. Further, this application samples data from each stage separately and compares the consistency of the first QSPI data sampled from the output with the second QSPI data sampled from the input to obtain the verification result. If inconsistencies are found during the comparison, it is easy to determine which stage's data has a problem, thus quickly locating the fault point and facilitating debugging and repair. In this way, this application can accurately check the correctness of data transmitted at each stage in the data stream sent by the QSPI controller, reducing the risk of missed detections.

[0154] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.

[0155] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the verification method for QSPI bus data transmission performed by the electronic device disclosed in any of the foregoing embodiments.

[0156] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0157] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0158] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored on it include operating system 221, computer program 222 and data 223, etc., and the storage method can be temporary storage or permanent storage.

[0159] The operating system 221 manages and controls the various hardware devices on the electronic device 20 and the computer program 222 to enable the processor 21 to perform calculations and processing on the massive amount of data 223 in the memory 22. The operating system 221 can be Windows, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of performing the QSPI bus data transmission verification method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, may further include computer programs capable of performing other specific tasks. The data 223 may include data received by the electronic device from external devices, as well as data collected by its own input / output interface 25.

[0160] Furthermore, embodiments of this application also disclose a computer-readable storage medium storing a computer program. When the computer program is loaded and executed by a processor, it implements the verification method steps for QSPI bus data transmission disclosed in any of the foregoing embodiments.

[0161] This invention also discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the QSPI bus data transmission verification method disclosed in any of the foregoing embodiments.

[0162] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0163] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0164] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0165] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0166] The present invention provides a detailed description of a QSPI bus data transmission verification method, apparatus, device, and storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A verification method for QSPI bus data transmission, characterized in that, Applied to a preset QSPI monitor, the method includes: The number of bits required to be transmitted for each stage of the test case is obtained from the preset global configuration database; wherein, the stages are ordered in the following order: instruction stage, address stage, alternating byte stage, empty instruction cycle stage, and data stage. Based on the number of bits, the local state machine is controlled to perform state transition operations to obtain each transition state, and based on each transition state, the corresponding stage's data sampling process is entered to sample the first QSPI data from the output of the QSPI controller; wherein, the local state machine is pre-set with states corresponding to different stages. If the number of bits corresponding to the current stage is non-zero, the local state machine is controlled to transition to the first state corresponding to the current stage; otherwise, based on the target sequence, the next non-zero number of bits corresponding to the target stage is determined, and the local state machine is controlled to transition to the second state corresponding to the target stage. The first QSPI data is sent to a preset checker so that the checker compares the consistency between the first QSPI data and the second QSPI data and obtains a verification result; wherein, the second QSPI data is data sampled from the input terminal of the QSPI controller; The data sampling process based on each state after the transition to the corresponding stage, to sample the first QSPI data from the output of the QSPI controller, includes: The data sampling process enters the corresponding stage based on the current jump state, and the counter corresponding to the current jump state is started; The QSPI data is sampled from the output of the QSPI controller, and the counter is used to count the number of bits of the currently sampled QSPI data to obtain the counter value; When the counter value is the same as the number of bits of the corresponding stage obtained from the global configuration database, the data sampling operation corresponding to the current jump state is stopped, and the first QSPI data is obtained based on the currently sampled QSPI data. Determine the next post-jump state and use it as the current post-jump state. Then, jump back to the step of executing the data sampling process that enters the corresponding stage based on the current post-jump state, until the data sampling process corresponding to each post-jump state is completed.

2. The verification method for QSPI bus data transmission according to claim 1, characterized in that, The number of bits required to be transmitted in each stage includes the number of instruction bits, the number of address bits, the number of alternating byte bits, the number of empty cycles, and the number of data bits; Accordingly, the step of controlling the local state machine to perform state transition operations based on each of the stated bit counts to obtain each transitioned state includes: If the number of instruction bits is non-zero, then the local state machine is controlled to jump from the initial state to the instruction state corresponding to the instruction stage, and the data sampling operation of the instruction stage is executed; If the number of address bits is non-zero, then after the data sampling operation of the instruction stage is completed, the local state machine is controlled to jump from the instruction state to the address state corresponding to the address stage, and the data sampling operation of the address stage is executed. If the number of alternating byte bits is non-zero, then after the data sampling operation of the address stage is completed, the local state machine is controlled to jump from the address state to the alternating byte state corresponding to the alternating byte stage, and the data sampling operation of the alternating byte stage is executed. If the number of empty cycles is non-zero, then after the data sampling operation of the alternating byte phase is completed, the local state machine is controlled to jump from the alternating byte state to the empty instruction cycle state corresponding to the empty instruction cycle phase, and the data sampling operation of the empty instruction cycle phase is executed. If the number of data bits is non-zero, after the data sampling operation of the empty instruction cycle phase is completed, the local state machine is controlled to jump from the empty instruction cycle state to the data state corresponding to the data phase, and the data sampling operation of the data phase is executed. Then, after the data sampling operation of the data phase is completed, the local state machine is controlled to jump from the empty instruction cycle state to the initial state.

3. The verification method for QSPI bus data transmission according to claim 2, characterized in that, The data phase includes a data writing phase and a data reading phase, and the number of data bits includes the number of data writing bits and the number of data reading bits; Accordingly, if the number of data bits is non-zero, then after completing the data sampling operation of the empty instruction cycle phase, controlling the local state machine to jump from the empty instruction cycle state to the data state corresponding to the data phase includes: If the preset read / write flag is a first preset value and the number of write data bits is non-zero, then after the data sampling operation of the empty instruction cycle phase is completed, the local state machine is controlled to jump from the empty instruction cycle state to the write data state corresponding to the write data phase. If the preset read / write flag is a second preset value and the number of read data bits is non-zero, then after the data sampling operation of the empty instruction cycle phase is completed, the local state machine is controlled to jump from the empty instruction cycle state to the read data state corresponding to the read data phase.

4. The verification method for QSPI bus data transmission according to claim 1, characterized in that, The output of the QSPI controller includes four input / output signal lines; Accordingly, sampling QSPI data from the output of the QSPI controller includes: Obtain the input / output enable signals sent by the QSPI controller through the target interface; The target input / output signal line currently used by the QSPI controller is determined based on the input / output enable signal; wherein, the target input / output signal line is any one, any two, or all four of the four input / output signal lines; QSPI data is sampled from the target input / output signal lines of the QSPI controller through the target interface.

5. The verification method for QSPI bus data transmission according to claim 1, characterized in that, Sending the first QSPI data to a preset checker includes: The first QSPI data is converted from serial data format to parallel data format to obtain the converted first QSPI data; The converted first QSPI data is encapsulated into a transaction object, and the transaction object is sent to a preset checker through a transaction-level modeling port.

6. The verification method for QSPI bus data transmission according to any one of claims 1 to 5, characterized in that, The QSPI monitor and the inspector are located on a preset verification platform, which also includes an AHB master device verification component; wherein the AHB master device verification component and the QSPI monitor are respectively connected to the inspector, and the AHB master device verification component includes a driver and a monitor; Accordingly, the process by which the inspector acquires the second QSPI data includes: The driver in the AHB master device verification component writes the second QSPI data to the register in the QSPI monitor through the target interface; The monitor in the AHB master device verification component sends the second QSPI data to the inspector.

7. A verification device for QSPI bus data transmission, characterized in that, The device, applied to a pre-defined QSPI monitor, includes: The bit count acquisition module is used to obtain the number of bits required to be transmitted by the test case at each stage from a preset global configuration database; wherein, the stages are ordered in the target order as follows: instruction stage, address stage, alternating byte stage, empty instruction cycle stage and data stage. A state machine control module is used to control a local state machine to perform state transition operations based on the number of bits, so as to obtain each transition state, and to enter the corresponding stage of the data sampling process based on each transition state, so as to sample the first QSPI data from the output of the QSPI controller; wherein, the local state machine is pre-set with states corresponding to different stages. If the number of bits corresponding to the current stage is non-zero, the local state machine is controlled to jump to the first state corresponding to the current stage; otherwise, the target stage corresponding to the next non-zero number of bits is determined based on the target sequence, so as to control the local state machine to jump to the second state corresponding to the target stage. A comparison module is used to send the first QSPI data to a preset checker, so that the checker compares the consistency between the first QSPI data and the second QSPI data and obtains a verification result; wherein, the second QSPI data is data sampled from the input terminal of the QSPI controller; Specifically, the state machine control module is used to enter the data sampling process of the corresponding stage based on the current jump state, and start the counter corresponding to the current jump state; sample QSPI data from the output of the QSPI controller, and use the counter to count the number of bits of the currently sampled QSPI data to obtain the counter value; when the counter value is the same as the number of bits of the corresponding stage obtained from the global configuration database, stop the data sampling operation corresponding to the current jump state, and obtain the first QSPI data based on each of the currently sampled QSPI data; determine the next jump state, and use the next jump state as the current jump state, and then jump back to the step of executing the data sampling process of entering the corresponding stage based on the current jump state, until the data sampling process corresponding to each jump state is completed.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the verification method for QSPI bus data transmission as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, Used to store a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the verification method for QSPI bus data transmission as described in any one of claims 1 to 6.

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