Test device, test method and test system for integrated circuit communication bus

Abstract

The application discloses a test device, a test method and a test system of an integrated circuit communication bus, relates to the technical field of computer communication and electronic testing, and comprises a microcontroller and a bus expansion module which are electrically connected. The microcontroller sends a test control signal to the bus expansion module. The bus expansion module generates a bus abnormal signal and inputs the bus abnormal signal into a device to be tested. The device to be tested generates test data according to the bus abnormal signal. The bus abnormal signal at least comprises an abnormal interrupt signal. The microcontroller dynamically adjusts the test control signal according to the test data fed back by the device to be tested to continue the test. By introducing a multi-channel bus expansion module with special programmable control capability and combining the intelligent judgment capability of the microcontroller, the polling test of the multi-channel is realized, and a plurality of bus abnormal signals, especially interrupt signals, can be accurately and timely generated and injected, so that the robustness and other characteristics of the device to be tested can be comprehensively evaluated.

Description

Technical Field

[0001] This application relates to the fields of computer communication and electronic testing technology, and in particular to a testing device, a testing method, and a testing system for an integrated circuit communication bus. Background Technology

[0002] With the increasing demands for stability and reliability of the I2C bus in modern electronic devices such as servers, smart hardware, and industrial control systems, comprehensive and efficient testing of the I2C bus has become crucial. However, existing I2C bus testing methods generally suffer from the following shortcomings:

[0003] 1. Low testing efficiency and limited coverage: Traditional I2C bus testing often relies on manual intervention or static settings, resulting in a lengthy and inefficient testing process. Especially when simulating abnormal operating conditions, the test scenario coverage is incomplete, making it difficult to discover potential design defects and compatibility issues.

[0004] 2. Insufficient ability to simulate anomalies: Existing methods struggle to accurately simulate complex anomalies that may occur on the I2C bus during actual operation, such as microsecond-level timing violations, waveform distortion caused by voltage fluctuations, or signal glitches caused by transient interference. In particular, they often fail to actively and dynamically generate and inject non-standard I2C communication signals (such as precisely controlled clock stretching timeouts, data setup / hold time violations) or interrupt signals of non-standard durations.

[0005] 3. Difficulty in fault diagnosis and location: After abnormal equipment behavior is discovered, traditional methods are often unable to quickly and accurately diagnose the cause of the fault and locate the problem point, relying heavily on the engineer's experience and time-consuming manual troubleshooting. Summary of the Invention

[0006] This application provides a test apparatus, a test method, and a test system for an integrated circuit communication bus, to at least solve the problems in related technologies where bus testing lacks comprehensive scenario coverage and cannot accurately inject abnormal signals, leading to inaccurate bus robustness assessment.

[0007] This application provides a testing device for an integrated circuit communication bus, comprising: a microcontroller, configured to generate a test control signal and dynamically adjust the test control signal according to test data fed back by the device under test (DUT) to determine the test result of the DUT; and a bus expansion module electrically connected to the microcontroller, the bus expansion module being configured to generate at least one bus abnormal signal according to the test control signal sent by the microcontroller, and input the bus abnormal signal to the DUT, so that the DUT generates the test data according to the bus abnormal signal, wherein the bus abnormal signal is a simulated bus abnormal signal of the DUT, and the bus abnormal signal includes at least an abnormal interrupt signal.

[0008] This application also provides a testing method for an integrated circuit communication bus, applicable to a microcontroller in any of the aforementioned integrated circuit communication bus testing devices. The method includes: determining multiple test scenarios and, based on the test scenarios, determining corresponding test control signals; sending the test control signals to a bus expansion module, causing the bus expansion module to generate at least one bus abnormal signal based on the test control signals, and causing the bus expansion module to input the bus abnormal signal to the device under test (DUT), wherein the bus abnormal signal is a simulated bus abnormal signal of the DUT, and the bus abnormal signal includes at least an abnormal interrupt signal; receiving test data fed back from the DUT, and dynamically adjusting the test control signals based on the test data to determine the test results of the DUT.

[0009] This application also provides a test system for an integrated circuit communication bus, comprising: a device under test (DUT); a test device for any of the aforementioned integrated circuit communication buses, electrically connected to the DUT; an oscilloscope, electrically connected to the DUT, for real-time detection of the bus waveform of the DUT; and a host computer, communicatively connected to the test device for the integrated circuit communication bus, for displaying the test results of the DUT.

[0010] This application describes a microcontroller that sends test control signals to a bus expansion module. The bus expansion module generates bus abnormal signals and inputs these signals to the device under test (DUT). The DUT generates test data based on the bus abnormal signals, which include at least an interrupt signal. The microcontroller dynamically adjusts the test control signals based on the test data from the DUT to continue testing. By introducing a multi-channel bus expansion module with special programmable control capabilities, combined with the microcontroller's intelligent interpretation capabilities, multi-channel polling testing is achieved. This allows for the accurate and real-time generation and injection of various bus abnormal signals, especially interrupt signals, enabling a comprehensive evaluation of the DUT's robustness and other characteristics. This solves the problem in related technologies where bus testing lacks comprehensive scenario coverage and cannot accurately inject abnormal signals, leading to inaccurate bus robustness evaluation. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of the structure of a test device for an integrated circuit communication bus provided in an embodiment of this application;

[0013] Figure 2 A schematic diagram of the interface structure of a test device for an integrated circuit communication bus provided in an embodiment of this application;

[0014] Figure 3 A schematic diagram of the interface structure of another integrated circuit communication bus test device provided in an embodiment of this application;

[0015] Figure 4 A schematic diagram of the structure of a real integrated circuit communication bus test device provided for embodiments of this application;

[0016] Figure 5 This is a schematic diagram of the structure of a device under test provided in an embodiment of this application;

[0017] Figure 6 A schematic diagram of the structure of another integrated circuit communication bus test device provided in an embodiment of this application;

[0018] Figure 7 A flowchart illustrating a testing method for an integrated circuit communication bus provided in an embodiment of this application;

[0019] Figure 8A schematic diagram of an I2C bus communication anomaly detection and processing flow provided in this application embodiment;

[0020] Figure 9 A flowchart illustrating an interrupt handling mechanism in I2C bus communication provided in an embodiment of this application;

[0021] Figure 10 This is a schematic diagram of the structure of a test system for an integrated circuit communication bus provided in an embodiment of this application.

[0022] The above figures include the following reference numerals:

[0023] 01. Test device for integrated circuit communication bus; 02. Device under test; 03. Oscilloscope; 04. Host computer; 10. Microcontroller; 11. Main control interface; 12. General purpose input / output pins; 20. Bus expansion module; 21. Abnormal signal input interface; 22. Interrupt signal input interface; 23. Abnormal signal output interface; 231. Bus output interface; 2311. Clock signal output interface; 2312. Data signal output interface; 232. Interrupt signal output interface. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0025] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0026] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] The specific application environment architecture or specific hardware architecture on which the test method for integrated circuit communication buses depends is described here.

[0028] Embodiments of this application provide a test apparatus 01 for an integrated circuit communication bus, such as... Figure 1 As shown, the device includes a microcontroller 10 and a bus expansion module 20. The microcontroller 10 generates test control signals and dynamically adjusts the test control signals according to the test data fed back by the device under test (DUT) 02 to determine the test results of the DUT 02. The bus expansion module 20 is electrically connected to the microcontroller 10 and generates at least one bus abnormal signal according to the test control signals sent by the microcontroller 10. The bus abnormal signal is then input to the DUT 02 so that the DUT 02 generates test data based on the bus abnormal signal. The bus abnormal signal is a simulated abnormal signal of the bus of the DUT 02, and the bus abnormal signal includes at least an abnormal interrupt signal.

[0029] The microcontroller unit (MCU) generates a series of signals to control the test process, guiding the bus expansion module to transmit normal or abnormal communication signals. Test control signals include specific test instructions, such as read / write operations, interrupt signal generation, and the type and parameter settings of abnormal signals. The MCU can dynamically adjust subsequent test control signals in real time based on data fed back by the Device Under Test (DUT) during testing. This means that if the DUT performs poorly under specific abnormal signals, the MCU can adjust the strength, type, or frequency of the abnormal signals to further test the robustness and fault tolerance of the device. The MCU analyzes the received feedback data to determine whether the DUT can correctly respond to various normal and abnormal communication signals. If the DUT maintains communication stability and data accuracy under abnormal signals, it indicates good robustness; otherwise, it may indicate design flaws or compatibility issues.

[0030] The bus expansion module is an I2C (Inter-Integrated Circuit) bus expansion module. It receives test control signals from the MCU and generates and injects at least one bus exception signal into the DUT according to instructions. These exception signals simulate various non-ideal communication conditions that the DUT may encounter in real-world applications, such as abnormal interruptions, timing errors, and signal glitches, to test the DUT's response and processing capabilities. The bus expansion module inputs the generated exception signal into the DUT's communication bus, forcing the DUT to generate feedback data under abnormal conditions. For example, when simulating an abnormal interrupt signal, the DUT, upon receiving the interrupt, may need to reinitialize communication, record an error log, or execute an error recovery procedure; its response will be reflected in the feedback data.

[0031] The device under test (DUT) is any electronic device with multiple I2C buses and associated interrupt input pins.

[0032] In digital communication, interrupt signals are typically used to notify the receiver of an event, such as data readiness or an abnormal condition. In this test setup, abnormal interrupt signals refer to those that do not conform to the communication protocol standard, such as interrupts that last too long, interrupts that are triggered at the wrong time, or interrupt signal level changes that do not meet protocol requirements. By injecting these abnormal interrupt signals, the DUT's response and handling capabilities in the face of non-standard interrupt situations can be tested.

[0033] The MCU automatically interprets the feedback data from the DUT, not only to determine whether the communication was successful, but more importantly, to analyze the specific behavior patterns of the DUT under abnormal conditions (e.g., whether it restarts immediately, suspends, experiences data transmission errors, or is able to self-recover and log errors).

[0034] The MCU combines its own recorded anomaly injection information (when and what type of anomaly was injected into which channel) with the DUT's response to perform preliminary fault localization and cause analysis. For example, if a specific channel frequently fails under a certain anomaly injection, the MCU can mark that channel as "anomaly sensitive" or point out possible hardware / software design flaws.

[0035] In the aforementioned integrated circuit communication bus testing apparatus of this application, the microcontroller sends a test control signal to the bus expansion module. The bus expansion module generates a bus abnormal signal and inputs the bus abnormal signal to the device under test (DUT). The DUT generates test data based on the bus abnormal signal, which includes at least an abnormal interrupt signal. The microcontroller dynamically adjusts the test control signal based on the test data fed back by the DUT to continue testing. By introducing a multi-channel bus expansion module with special programmable control capabilities, combined with the intelligent interpretation capabilities of the microcontroller, multi-channel polling testing is achieved. It can accurately and in real-time generate and inject various bus abnormal signals, especially interrupt signals, thereby comprehensively evaluating the robustness and other characteristics of the DUT. This solves the problem in related technologies where bus testing scenarios are not fully covered and abnormal signals cannot be accurately injected, leading to inaccurate bus robustness evaluation.

[0036] The above embodiments can solve the problems of low efficiency, insufficient abnormal simulation capability, and difficulty in fault diagnosis in existing I2C bus testing methods. By introducing a multi-channel I2C bus expansion module with special programmable control capability and combining it with the intelligent judgment capability of microcontroller, parallel, independent or synchronous testing of multiple I2C buses and their accompanying interrupt signals can be realized. It can also accurately and in real time generate and inject various I2C bus abnormal signals, thereby comprehensively evaluating the robustness and other characteristics of the device under test.

[0037] In some embodiments, such as Figure 2As shown, the microcontroller 10 further includes: at least one main control interface 11, electrically connected to the bus expansion module 20, for sending control commands and receiving test data, wherein the control command is a signal that controls the bus expansion module 20 to generate a bus abnormal signal; and at least one general-purpose input / output pin 12, electrically connected to the bus expansion module 20, for sending first abnormal information and second abnormal information, wherein the first abnormal information includes information about the bus abnormal signal generated by the bus expansion module 20 (which is not an abnormal interrupt signal), and the second abnormal information includes information about the abnormal interrupt signal generated by the bus expansion module 20.

[0038] The main control interface 11 is an I2C master control interface, used as an I2C master controller to communicate data and control commands with the I2C bus expansion module. One or more general purpose input / output (GPIO) pins 12 are used to send (or simulate) reference interrupt signals or other auxiliary test control signals to the I2C bus expansion module. The microcontroller also has an embedded control program used to generate I2C test signals according to test requirements, precisely control the I2C bus timing and interrupt signal output, and automatically interpret the received test data. Alternatively, the microcontroller can be replaced with a central processing unit (CPU). The microcontroller can precisely control the bus expansion module to generate and inject various non-standard I2C communication signals and / or interrupt signals of non-standard durations in real time on a specified I2C channel according to preset or dynamically adjusted test scenarios. Furthermore, the microcontroller can automatically interpret the feedback data from the device under test (DUT) and perform preliminary fault behavior pattern analysis and fault location based on the injected anomaly type, time, and DUT response.

[0039] The microcontroller 10 sends detailed control commands to the bus expansion module 20 via the main control interface 11. These commands include specific parameters for generating specific types of bus fault signals, such as the magnitude of timing deviations and the duration of signal glitches. In this way, the bus expansion module 20 can accurately simulate various abnormal operating conditions according to the microcontroller's commands, increasing the accuracy and complexity of the test. The main control interface 11 is also used to receive test data returned from the device under test (DUT) 02. This data reflects the DUT's processing results after experiencing bus fault signals, including but not limited to data integrity, error codes, and communication status. The microcontroller uses this data to determine whether the DUT's response meets expectations, thereby evaluating its robustness and compatibility. Furthermore, the MCU has built-in algorithms or logic that can generate composite faults of specific patterns, such as injecting clock stretch timeouts accompanied by injecting transient glitches on the data lines, simulating more complex bus fault scenarios.

[0040] In addition to sending control commands via the main control interface 11, the microcontroller can also directly send first and second exception information to the bus expansion module 20 via general-purpose input / output pins 12. These signals contain additional information about the bus exception signal, such as the duration of the interrupt signal or the triggering condition for injecting the exception signal at a specific timing point. In this way, the microcontroller can more finely control the exception simulation process, ensuring the diversity and accuracy of the test scenarios. By using general-purpose input / output pins 12 to send first and second exception information, the test system can cover a wider range of more complex abnormal operating conditions. This includes not only exceptions within the protocol's allowed range but also extreme cases beyond the protocol's limitations, greatly enriching the test scenarios and improving the comprehensiveness of the test. The injection of first and second exception information helps to evaluate the robustness of the DUT under non-standard or extreme conditions, that is, its ability to maintain stable operation and data integrity when faced with various communication anomalies. This evaluation is crucial for ensuring the reliability of the device in real-world application environments (such as those with noise or timing deviations).

[0041] In other words, the microcontroller can actively simulate and inject I2C communication signals with abnormal timing, including but not limited to clock stretching timeouts, data setup / hold time violations, signal glitches, or transient interference. It can also generate abnormal interrupt signals whose duration exceeds the threshold specified by the I2C bus protocol (e.g., specified as 20ms, set to 25ms). The microcontroller (MCU) works in conjunction with the I2C bus expansion module to achieve the precise generation and injection of these abnormal signals.

[0042] By combining the microcontroller's main control interface 11 and general-purpose input / output pins 12, the entire test system achieves refined simulation and intelligent control of integrated circuit communication bus anomalies. This highly integrated and programmable testing method can comprehensively and efficiently detect and verify the behavior and performance of the DUT under various non-ideal communication environments. Furthermore, it promotes the automation of fault diagnosis, reduces the time and resources required for manual troubleshooting, and improves the overall efficiency and quality of testing.

[0043] As the main control unit, the MCU's embedded control program can precisely control the I2C bus timing and interrupt signal output, thereby achieving accurate simulation of abnormal signals. The MCU also has the ability to automatically interpret the received test data, improving testing efficiency and objectivity. Furthermore, it can generate I2C test signals according to test requirements, including normal read / write and exception injection.

[0044] In some embodiments, such as Figure 2As shown, the test control signal includes first abnormal information and second abnormal information. The first abnormal information includes information about the bus abnormal signal, which is a non-abnormal interrupt signal generated by the bus expansion module 20. The second abnormal information includes information about the abnormal interrupt signal generated by the bus expansion module 20. The bus expansion module 20 includes:

[0045] The abnormal signal input interface 21 is electrically connected to the microcontroller 10 and is used to receive the first abnormal information.

[0046] Interrupt signal input interface 22 is electrically connected to microcontroller 10 and is used to receive second abnormal information;

[0047] Multiple sets of abnormal signal output interfaces 23 are used to electrically connect to the device under test 02. Each set of abnormal signal output interfaces 23 includes multiple bus output interfaces 231 and one interrupt signal output interface 232. The bus output interfaces 231 are used to output bus abnormal signals that are not abnormal interrupt signals, and the interrupt signal output interface 232 is used to output abnormal interrupt signals.

[0048] The I2C bus expansion module connects to the microcontroller's I2C master interface and has an exception signal input interface 21, an interrupt signal input interface 22, several independent bus output interfaces 231, and several independent interrupt signal output interfaces 232. The exception signal input interface can be considered as an I2C input interface, and the bus output interface can be considered as an I2C output interface.

[0049] The I2C bus expansion module can be programmed and controlled by a microcontroller to independently enable / disable the bus output interface 231 and several independent interrupt signal output interfaces 232, perform independent address routing, and independently or synchronously send test signals and simulate interrupt signals. More importantly, in conjunction with the microcontroller, it can actively and precisely generate and inject various I2C bus abnormal signals on specific channels among the several bus output interfaces and terminal signal output interfaces.

[0050] The first anomaly information includes bus anomaly signal information related to non-abnormal interrupt signals. This information guides the bus expansion module on how to simulate and generate bus-level anomalies during normal communication, such as data setup time violations, hold time errors, signal glitches, and clock stretching timeouts. In this way, the test device can meticulously examine the response of the device under test (DUT) 02 outside of standard communication bus signals, and evaluate its stability and data integrity under non-ideal communication environments.

[0051] The second type of anomaly information specifically relates to the generation of abnormal interrupt signals. It includes information such as the non-standard timing, duration, and level of the interrupt signal, aiming to test the behavior and robustness of the device under test (DUT) when handling abnormal interrupt requests. Injecting abnormal interrupt signals helps evaluate the device's interrupt management mechanism, including interrupt response efficiency and the ability to handle long-duration interrupts, which is crucial for ensuring the stability and safety of the device in the face of unexpected situations.

[0052] Through the abnormal signal input interface 21 and the interrupt signal input interface 22, the bus expansion module 20 can independently receive and process two types of abnormal information. This means it can simultaneously generate and inject two different types of abnormal signals, providing more complex and realistic test scenarios. This separate design improves testing flexibility, allowing testers to conduct more in-depth analysis and verification for specific abnormal situations. Each set of abnormal signal output interfaces 23 includes multiple bus output interfaces 231 and one interrupt signal output interface 232. This design allows the bus expansion module 20 to poll and output abnormal signals on multiple independent bus channels, thereby enabling testing of the integrated circuit's anti-interference capability and resource allocation efficiency in multi-channel communication. This architecture allows each set of abnormal signal output interfaces to independently control the output of bus abnormal signals and interrupt abnormal signals, allowing testers to set unique test scenarios and abnormal conditions for each channel. This highly customizable testing capability helps to discover weaknesses in individual devices or specific channels, ensuring the robust operation of the entire system under various abnormal conditions.

[0053] In some embodiments, such as Figure 3 As shown, a set of abnormal signal output interfaces 23 includes multiple bus output interfaces, namely a clock signal output interface 2311 and a data signal output interface 2312. The communication addresses of any two sets of abnormal signal output interfaces 23 are different.

[0054] Different abnormal signal output interfaces correspond to different communication channels. These interfaces are designed to be accessible via test fixtures or connectors for flexible connection to multiple I2C buses and their corresponding interrupt GPIO interfaces on the circuit board under test (DUT).

[0055] The microcontroller can control the selection of different I2C channels (i.e. a set of abnormal signal output interfaces) for testing. Through the programmable multi-channel I2C bus expansion module, efficient and automated polling testing of multiple I2C bus channels can be achieved without frequent manual switching, which greatly shortens the test cycle and reduces test costs and manpower requirements.

[0056] By separating the clock signal output interface and the data signal output interface into two independent interfaces, the test device can independently control and simulate anomalies for the clock signal (SCL) and the data signal (SDA). This means that anomalies such as clock stretching timeout and clock signal glitches can be injected separately into the clock line, and anomalies such as data setup time violation and data hold time violation can be injected separately into the data line, or composite anomalies can be generated in combination between the two, providing more refined and customized test scenarios.

[0057] Any two sets of abnormal signal output interfaces have different communication addresses, meaning that each set of interfaces can communicate independently with a specific communication channel of the device under test (DUT) without interfering with each other. In I2C bus communication, different devices are identified by a unique address. Therefore, abnormal signal output interfaces with different addresses can accurately locate different DUTs or channels, enabling multi-channel selective polling testing and improving the targeting and automation of the test.

[0058] Since the communication addresses of each set of abnormal signal output interfaces are independent, testers can simulate complex communication sequences and observe the response of the device under test by sending abnormal signals to abnormal signal output interfaces with different communication addresses one by one or in a specific sequence. This is very important for discovering potential communication sequence dependency problems, timing sensitivity problems, and interaction problems between devices.

[0059] When a communication problem is found in a specific channel during testing, the unique communication address of each interface group allows for quick identification of which channel or device is faulty, eliminating the need for additional diagnostic steps to determine which device is affected and greatly simplifying the troubleshooting process.

[0060] By injecting abnormal signals individually or jointly on channels with different communication addresses, the testing device can comprehensively evaluate the robustness and compatibility of the device under test under normal communication and various abnormal conditions, ensuring that the device can maintain stable operation in complex and variable environments.

[0061] In some embodiments, the bus expansion module is used to output an abnormal interrupt signal to the device under test through an interrupt signal output interface. The abnormal interrupt signal is a low-level pulse signal with a duration of a first duration, which is longer than the duration of the interrupt signal that enables the device under test to maintain normal communication.

[0062] Specifically, generating abnormal interrupt signals involves generating interrupt signals of non-standard duration. This means actively generating and outputting interrupt signals with a duration exceeding the I2C bus protocol threshold (e.g., 25ms). This verifies the response and robustness of the device under test (DUT) in situations exceeding the I2C bus standard specifications or encountering abnormal disturbances. The I2C bus expansion module can be programmed via the MCU to output a low-level pulse on a specified INTx pin with a duration (e.g., 25ms) longer than the standard I2C device interrupt signal (e.g., 10ms), testing the DUT's response to abnormal interrupts.

[0063] By outputting an abnormally long low-level pulse signal as an interrupt signal, the bus expansion module can simulate extreme conditions beyond the standard or normal operating range. Injecting this abnormal interrupt signal is crucial for testing the response mechanism and recovery capability of the device under test (DUT) in the face of prolonged interruptions. Prolonged abnormal interrupt signals help verify the fault tolerance mechanism and recovery strategy of the DUT. Under normal circumstances, the device should have a certain interruption tolerance, meaning it can automatically resume communication after a short interruption. However, when the interrupt signal duration exceeds the normal range, the device's recovery mechanism will face challenges, and the test results can evaluate the device's fault tolerance performance under extreme conditions.

[0064] Different devices or designs may have varying tolerances for the duration of interrupt signals. By injecting interrupt signals with a duration exceeding the normal range, the compatibility between the device under test (DUT) and different standards or devices can be evaluated, especially in multi-device or complex systems.

[0065] By outputting a low-level pulse signal with an abnormally long duration as an interrupt signal, the bus expansion module can perform in-depth testing of the robustness of the device under test (DUT) under extreme conditions, including identifying interrupt sensitivity, verifying fault tolerance mechanisms, evaluating compatibility, and promoting robustness improvement. This testing strategy plays a crucial role in ensuring that devices can maintain normal operation under various non-ideal communication scenarios, thereby improving the overall system stability and reliability.

[0066] In some embodiments, bus abnormal signals include clock timeout signals, abnormal timing signals, interference signals, and circuit fault signals. A clock timeout signal is a signal whose low level lasts for more than the maximum time threshold of the bus protocol. An abnormal timing signal is a data signal or clock signal whose timing causes the device under test to misidentify data. A circuit fault signal is a bus open circuit signal or a bus short circuit signal.

[0067] A clock timeout signal refers to a clock signal (SCL) on the bus remaining low for a duration exceeding the maximum time threshold specified by the bus protocol. For example, in the I2C bus, if the clock signal is held low for a significantly longer period than the standard timing, it will be considered a clock timeout. By simulating this clock timeout situation that exceeds protocol limits, the response capability and robustness of the device under test (DUT) under extreme conditions are tested. This determines whether the device can maintain normal communication functions when the clock signal is pulled low for an extended period, or whether it can perform appropriate error handling and recovery actions upon timeout.

[0068] Abnormal timing signals include situations where data or clock signals do not follow fixed or protocol-defined timing rules during transmission, leading to misreading or inability to parse data by the device under test (DUT). For example, the data line SDA may not stabilize before the rising edge of the clock line, or may change its state too quickly after the falling edge, violating setup and hold time requirements. By testing the DUT's performance under abnormal timing signals, the device's sensitivity to timing can be verified, especially its behavior under timing edge conditions.

[0069] Interference signals refer to unexpected, transient voltage fluctuations or pulses injected into data or clock lines, simulating real-world electromagnetic interference, power fluctuations, and other conditions to assess the interference immunity of the communication bus. The response mechanism of the device under test (DUT) in the face of circuit faults (such as open circuits or short circuits) is examined to determine whether it can detect the fault and take appropriate protection or error recovery measures.

[0070] By injecting the above four types of bus anomaly signals, the test device can comprehensively evaluate the robustness, compatibility, anti-interference capability, and fault response mechanism of the integrated circuit communication bus under various abnormal and extreme conditions. The above embodiments not only verify the normal read and write functions of the I2C bus, but also accurately simulate and inject abnormal timing and states of I2C bus communication or interrupt signals (such as interrupt time exceeding limits, timing distortion, and signal interference), thereby systematically evaluating the robustness of the device under test under non-ideal conditions. This enables the discovery of potential design defects and compatibility issues that are difficult to detect using traditional testing methods, comprehensively improving test coverage. It allows for flexible configuration and testing of potential interference or contention issues under multi-channel parallel communication, ensuring the stability of I2C communication in complex systems.

[0071] In some embodiments, the bus expansion module is used to generate a low-level signal, the duration of which exceeds the maximum time threshold of the bus protocol, to generate a clock timeout signal, wherein the clock signal is a signal of the serial clock signal line; the bus expansion module is used to generate a clock signal with a first abnormal timing sequence, and / or to generate a data signal with a second abnormal timing sequence, to generate an abnormal timing signal, wherein the data signal is a signal of the serial data signal line; the bus expansion module is used to inject pulses of a preset width and preset amplitude into the serial clock signal line and / or the serial data signal line to generate an interference signal.

[0072] The clock signal line provides a clock signal to synchronize data transmission between all devices on the I2C bus. The master device generates this clock signal, while the slave devices use this clock signal to synchronize the reception and transmission of data.

[0073] Therefore, by maintaining a specific low-level state on the clock signal line for a duration exceeding the maximum threshold specified by the I2C protocol (e.g., injecting a 25ms clock stretch timeout, while the protocol specifies 20ms), the clock stretch timeout situation on the serial clock signal line (SCL) is accurately simulated, and a clock timeout signal is obtained.

[0074] Test the device under test's response to prolonged clock stretch timeouts. Ideally, the device should be able to detect this anomaly and take appropriate action, such as error handling, communication retry, or entering a safe mode. By observing the device's handling mechanism, the robustness and fault tolerance of the design can be evaluated, and optimizations can be made as necessary, such as enhancing the timeout detection logic or improving the error recovery strategy.

[0075] Specifically, the MCU sends instructions to the I2C bus expansion module. The module's internal logic or programmable GPIO takes over control of the SCL line for a specific channel. During data transmission, the module forcibly pulls the SCL line low and holds it for a preset duration exceeding the maximum clock pull time allowed by the I2C protocol (e.g., 25ms) before releasing the SCL line. The DUT's response to this non-standard clock pull (such as suspension, timeout error, or communication anomaly) will be recorded and analyzed by the MCU.

[0076] Data is transmitted on a separate line, the Serial Data Line (SDA), but its validity is tied to the state of the SCL line. Typically, data on the SDA can only change when SCL is low, and must remain stable when SCL is high. This timing control ensures proper data reading and writing.

[0077] Therefore, abnormal timing signals are actually non-compliant data setup or hold times. These are intentionally created by precisely adjusting the relative timing of the serial data lines and the SCL signal, resulting in setup or hold times that do not meet the requirements of the I2C protocol. The device's data reception capability under timing abnormalities is tested, including deviations in key timing parameters such as setup time and hold time. This ensures the device can communicate correctly with other devices or systems that have slight timing deviations.

[0078] Interference signals are short-lived voltage pulses or drops injected into the SDA or SCL lines to simulate physical noise or interference. Checking whether pulses on the signal lines affect data integrity, and whether the device can identify and filter out these interferences to maintain communication quality, reflects the accuracy of data transmission and communication recovery capabilities of the test equipment after experiencing transient interference.

[0079] Specifically, each I2C channel of the I2C bus expansion module can integrate a controllable instantaneous voltage generator or a high-speed switch controlled by an MCU to briefly inject a pulse of preset width (e.g., tens of nanoseconds to a few microseconds) and amplitude onto the SDA or SCL lines to simulate transient interference.

[0080] For circuit fault signals, the SDA / SCL signal lines are forcibly pulled low or left floating to simulate a short circuit or open circuit fault on the bus, thus obtaining the circuit fault signal.

[0081] By injecting clock timeout, abnormal timing, and interference signals, the bus expansion module can comprehensively test the performance of the communication bus in the face of various software anomalies and physical interference. It can realize in-depth testing of integrated circuit communication buses under complex and extreme conditions, promote the optimization of device design, and improve the communication quality and reliability of the device.

[0082] In the event of a violation of the analog data setup and hold time, the bus expansion module 20 is used to change the state of the data signal within a first preset duration before the rising edge of the clock signal to generate an abnormal timing signal. The first preset duration is less than the data stabilization duration, which is the duration for which the data signal stabilizes. And / or, the bus expansion module 20 changes the state of the data signal within a second preset duration after the falling edge of the clock signal to generate an abnormal timing signal. The second preset duration is less than the duration for which the data of the data signal is completely acquired.

[0083] Specifically, the MCU uses an I2C bus expansion module to precisely control the switching timing of the SDA and SCL signals for a specific channel. For example, before the rising edge of the SCL signal, the settling time of the SDA signal can be advanced or delayed, causing it to fail to meet the setup time requirements specified by the I2C protocol; or after the falling edge of the SCL signal, the state of the SDA signal can be changed too early or too late, causing it to fail to meet the hold time requirements. The module can have a built-in programmable delay unit or use high-speed GPIO to precisely control these microsecond-level timings.

[0084] Within a first preset duration before the rising edge of the clock signal (SCL), the bus expansion module 20 changes the state of the data signal (SDA). This first preset duration is intentionally set shorter than the data settling time (i.e., the shortest time during which the data must remain unchanged until the rising edge of the clock signal arrives), causing instability in the data signal during setup. The test device's data reception and processing capabilities are assessed under conditions of data setup time violation. The device should be able to identify such errors and take appropriate response measures, such as retrying communication, logging errors, or implementing other fault-tolerant strategies.

[0085] Within a second preset duration following the falling edge of the clock signal, the bus extension module 20 changes the state of the data signal. This second preset duration is shorter than the time required for the data signal to be fully acquired (i.e., the data must remain unchanged until the end of the clock signal's falling edge), causing instability in the data signal during the hold period. This tests verify whether the device can correctly transmit and interpret data even with a shortened data hold time. Such tests are crucial for ensuring device compatibility and data integrity under timing edge conditions.

[0086] By deliberately introducing anomalies in data setup and retention timing, test setups can provide in-depth assessments of the timing sensitivity of the device under test (DUT), particularly its performance under high-speed communication or timing-critical conditions. These tests expose potential design weaknesses, prompting development teams to optimize the device's timing management strategies and improve its robustness to timing variations. Verifying the DUT's ability to correctly handle data signals at the edge of the I2C protocol standard is crucial for ensuring compatibility with various standard and non-standard devices in real-world applications.

[0087] By deliberately violating standards in data setup and hold timing, the abnormal timing signals generated by the bus extension module can perform detailed testing on the integrated circuit communication bus, helping developers evaluate the timing robustness and data transmission quality of the device, while promoting design improvement and optimization, and ensuring that the device can operate stably in complex and ever-changing communication environments.

[0088] In some embodiments, the microcontroller is also used to determine the target abnormal signal output interface of the bus expansion module, wherein the bus output interface in the target abnormal signal output interface is the interface that actually outputs the bus abnormal signal (non-abnormal interrupt signal) to the device under test, and the interrupt signal output interface in the target abnormal signal output interface is the interface that actually outputs the abnormal interrupt signal to the device under test, and there are one or more target abnormal signal output interfaces.

[0089] The microcontroller intelligently selects and controls the target abnormal signal output interface in the bus expansion module, ensuring that abnormal signals are accurately injected into the intended communication path of the device under test. Testers can precisely send abnormal signals to specific I2C channels or interrupt lines, avoiding redundancy and unnecessary complexity that can result from indiscriminate testing across the entire range. Through the microcontroller's intelligent decision-making, selective abnormal signal injection significantly accelerates the testing process and reduces unnecessary waiting time and resource waste.

[0090] The microcontroller can dynamically adjust the target anomaly signal output interface according to test needs. This means that testing can be performed not only on a single channel but also seamlessly switched to other channels, and even anomaly signal injection can be performed on multiple channels simultaneously, enhancing the flexibility and coverage of the test. Utilizing the parallel characteristics of the target anomaly signal output interface, anomaly signal injection tests can be performed simultaneously on multiple I2C channels, greatly improving the parallel processing capability of the test and shortening the overall test cycle. By injecting anomaly signals synchronously or asynchronously on multiple channels, the test device can evaluate the robustness and anti-interference capability of the device under test at the entire system level, ensuring stable operation of the device even in complex multi-device communication environments.

[0091] During testing, the microcontroller records the anomaly type, injection time, and duration of each target abnormal signal output interface, as well as the response of the device under test, providing detailed data support for subsequent fault analysis and repair. Because the microcontroller can clearly record the specific injection path and time of each abnormal signal, testers can more accurately pinpoint the exact location and time of the fault, accelerating the problem diagnosis process.

[0092] In some embodiments, the bus expansion module 20 includes a bus multiplexer and / or an integrated circuit switch.

[0093] The bus expansion module utilizes readily available I2C bus multiplexers or integrated circuit switches to achieve independent control and routing of multi-channel I2C buses. This module not only provides multiple I2C outputs, but more importantly, it is programmed and controlled by the MCU to independently enable / disable each channel, route addresses independently, and inject abnormal signals onto specific channels.

[0094] The bus multiplexer and integrated circuit switch enable independent control and switching of multiple I2C bus channels, allowing the test system to perform parallel testing on multiple devices or multiple interfaces of a single device simultaneously. This significantly improves testing efficiency, as manual switching of test devices or channels is eliminated, saving considerable test preparation and switching time. The bus multiplexer and integrated circuit switch can be programmed and controlled by a microcontroller 10, enabling fine-grained management and routing of I2C bus signals (including clock signal SCL and data signal SDA). This means the test system can freely choose which signals pass through which channels and when to route signals to specific I2C lines, greatly enhancing the customizability and controllability of the test.

[0095] The use of bus multiplexers and integrated circuit switches makes the hardware design of the bus expansion module 20 more compact and efficient. This modular architecture not only facilitates maintenance and upgrades but also simplifies the overall design of the test equipment, reduces the required external wiring, and lowers system complexity. The combined use of bus multiplexers and integrated circuit switches allows the test system to dynamically inject abnormal signals into a specified I2C channel at any time without interrupting the entire test process.

[0096] Figure 4 This is a schematic diagram of the structure of a test device for a real integrated circuit communication bus. Figure 4 As shown, the microcontroller is connected to a positive power supply and outputs clock, data, reset, and interrupt signals to the bus expansion module via general-purpose pins. The signals output by the microcontroller to the bus expansion module include channel information for which an exception signal needs to be output, as well as the type and parameters of the exception signal to be output. Figure 4 The bus expansion module shown supports four channels. It receives clock, data, reset, and interrupt signals from the microcontroller via general-purpose pins. The first clock, first data, and first interrupt signals are the clock, data, and interrupt signals output by the first channel, respectively. The second clock, second data, and second interrupt signals are the clock, data, and interrupt signals output by the second channel, respectively. The third clock, third data, and third interrupt signals are the clock, data, and interrupt signals output by the third channel, respectively. The fourth clock, fourth data, and fourth interrupt signals are the clock, data, and interrupt signals output by the fourth channel, respectively. Each channel can connect to one device under test (DUT), and multiple channels can be polled to perform polling tests on multiple DUTs. The microcontroller can be configured to enable specific channels and the activation order of multiple channels. Figure 5 This is a schematic diagram of the structure of a device under test, such as... Figure 5As shown, the device under test (DUT) includes a DUT motherboard, which has a smart board management controller. The smart board management controller has a clock signal input interface, a data signal input interface, and an interrupt signal input interface. The DUT receives abnormal bus signals sent by the bus expansion module through the clock signal input interface, the data signal input interface, and the interrupt signal input interface.

[0097] Figure 6 This is a schematic diagram of the structure of a test device for another real integrated circuit communication bus. (Example:) Figure 6 As shown, the integrated circuit communication bus test setup has a Universal Serial Interface (USB) input, which connects to a microcontroller and a bus expansion module. The test setup also includes a DC-DC converter module, power connectors, a 3.3V regulated power supply, and six 12V power outputs. The number and voltage of the power supplies can be adjusted according to actual needs. The bus expansion module has four channels: a first bus channel, a second bus channel, a third bus channel, and a fourth bus channel. An abnormal bus signal is transmitted to a device under test (DUT) motherboard through one of these four channels. Each channel can connect to a DUT motherboard for testing.

[0098] In the above embodiments, the core I2C bus expansion module can be flexibly replaced according to the actual needs of the number of buses under test (e.g., from 4 channels to ICs with more channels). The microcontroller, as the main control unit, can be adapted to different test scenarios and I2C bus configuration requirements through firmware programming. Adopting a modular design, it can be adapted to different models of I2C bus expansion modules, and the MCU firmware can also be flexibly configured and easily extended to other serial communication protocols. Without increasing additional hardware costs or structural complexity, the hardware characteristics of existing microcontrollers and multi-channel I2C bus switch chips are integrated through software programming, achieving powerful anomaly simulation and testing functions, avoiding large-scale modifications to the existing test architecture or the introduction of expensive dedicated hardware.

[0099] Furthermore, the above embodiments are not limited to robustness testing of the I2C bus; their core principles and architecture can be flexibly extended to the following areas to achieve a wider range of feature injection and detection:

[0100] 1. Robustness and compatibility testing of other serial communication protocols:

[0101] SPI (Serial Peripheral Interface): Analog clock phase / polarity abnormalities, data sampling timing violations, multi-master contention conflicts, etc.

[0102] UART (Universal Asynchronous Receiver / Transmitter): This addresses issues such as baud rate deviation, start / stop bit loss or error, parity error, and frame error.

[0103] CAN (Controller Area Network): Analog bit error, stuffing error, CRC error, ACK error and other network layer anomalies.

[0104] RS-232 / RS-485: Analog voltage level abnormalities, data misalignment, noise interference, etc.

[0105] Low-level Ethernet (physical layer): Simulates physical layer anomalies such as signal attenuation, crosstalk, packet loss, and delay to detect the robustness of the PHY chip.

[0106] 2. General hardware / firmware robustness and performance testing:

[0107] Power Management IC (PMIC) Testing: Simulate anomalies in the PMIC control bus (such as PMBus, SMBus) to test its stability and protection mechanisms under non-standard inputs.

[0108] Sensor interface testing: For digital sensor interfaces such as I2C and SPI, abnormal signals are injected to evaluate the data accuracy and reliability of the sensors in harsh environments.

[0109] Fault injection in safety-critical systems: In fields such as aerospace, medical equipment, and automotive electronics, I2C bus faults are injected to verify the effectiveness of the system's safety mechanisms (such as fault isolation and fault tolerance) under fault conditions.

[0110] Inter-processor communication (IPC) testing: Simulates anomalies in I2C or SPI communication between different processors to evaluate the communication robustness of multi-core or distributed systems.

[0111] Peripheral driver development and verification: When developing new hardware drivers, actively injecting I2C exceptions accelerates the error handling logic and robustness verification of the drivers.

[0112] 3. Product manufacturing testing and quality assurance:

[0113] In the final inspection or online testing of the product production line, standard, boundary condition I2C anomalies are quickly injected to screen out devices with marginalized I2C interface performance or potential defects, thereby improving the quality of products leaving the factory.

[0114] Embodiments of this application also provide a testing method for an integrated circuit communication bus, applicable to the microcontroller in any integrated circuit communication bus testing device, such as... Figure 7 As shown, the method includes the following steps:

[0115] Step S101: Determine multiple test scenarios and, based on the test scenarios, determine the corresponding test control signals;

[0116] Step S102: Send the test control signal to the bus expansion module so that the bus expansion module generates at least one bus abnormal signal according to the test control signal, and inputs the bus abnormal signal to the device under test. The bus abnormal signal is a simulated bus abnormal signal of the device under test, and the bus abnormal signal includes at least an abnormal interrupt signal.

[0117] Step S103: Receive test data fed back by the device under test, and dynamically adjust the test control signal according to the test data to determine the test result of the device under test.

[0118] Before testing, the MCU, I2C bus expansion module, device under test (DUT), and test result display and analysis unit need to be electrically connected. The MCU controls the I2C bus expansion module via programming, selecting the I2C channel to be tested and setting communication parameters. The I2C bus module and the DUT's I2C are connected via cable, and then the MCU sends commands through the I2C bus module to select or switch the I2C channel for communication with the DUT's I2C channel.

[0119] Before conducting tests, one or more test scenarios need to be preset in the microcontroller, including normal communication tests and at least one I2C bus anomaly verification condition. I2C bus anomaly verification condition refers to specific test parameters designed to evaluate the robustness of the device under test (DUT) to non-ideal I2C bus behavior.

[0120] According to the preset test program, the microcontroller sends test commands (such as data read / write and register configuration) to the target I2C bus of the electronic device under test through the I2C bus expansion module.

[0121] The microcontroller receives feedback data from the electronic device under test (DUT) and performs automated interpretation to determine whether the read data meets expectations and whether the DUT's response to injected abnormal signals meets its robustness design goals.

[0122] The test results display and analysis unit (oscilloscope) displays the SDA / SCL waveforms of the I2C bus in real time, allowing testers to perform intuitive timing verification and signal quality analysis, especially when abnormal simulations occur, to observe waveform changes and device responses.

[0123] The microcontroller also performs comprehensive fault diagnosis and precise location assessment based on automated data interpretation results and waveform analysis to determine whether the I2C bus design under test strictly follows standard specifications, as well as its reliability and robustness under various complex or abnormal conditions.

[0124] The testing method described in this application involves a microcontroller sending a test control signal to a bus expansion module. The bus expansion module generates a bus abnormality signal and inputs it to the device under test (DUT). The DUT generates test data based on the bus abnormality signal, which includes at least an interrupt signal. The microcontroller dynamically adjusts the test control signal based on the test data from the DUT to continue the test. By introducing a multi-channel bus expansion module with special programmable control capabilities, combined with the microcontroller's intelligent interpretation capabilities, multi-channel polling testing is achieved. This allows for the accurate and real-time generation and injection of various bus abnormal signals, especially interrupt signals, thus comprehensively evaluating the robustness and other characteristics of the DUT. This solves the problem in related technologies where bus testing lacks comprehensive scenario coverage and cannot accurately inject abnormal signals, leading to inaccurate bus robustness assessments.

[0125] In some embodiments, the test control signal includes first abnormal information and second abnormal information. The first abnormal information includes information about a bus abnormal signal that is not an abnormal interrupt signal generated by the bus expansion module, and the second abnormal information includes information about an abnormal interrupt signal generated by the bus expansion module. The corresponding test control signal is determined based on the test scenario, and includes at least one of the following:

[0126] In the case of a clock timeout test scenario, determine the duration of the low level of the clock timeout signal to obtain the first abnormal information, which is that the duration exceeds the maximum time threshold of the bus protocol of the device under test.

[0127] In the case of an abnormal timing scenario during testing, the first abnormal timing of the clock signal and the second abnormal timing of the data signal are determined to obtain the first abnormal information. The clock signal is the signal of the serial clock signal line, and the data signal is the signal of the serial data signal line.

[0128] In a test scenario with interference, the preset width and preset amplitude of the interference pulse are determined to obtain the first abnormal information;

[0129] In the case of a circuit fault scenario during the test, determine the signal type of the circuit fault signal and obtain the first abnormal information. The signal type is either a bus open circuit signal or a bus short circuit signal.

[0130] In a test scenario where the signal is interrupted, the abnormal interruption signal is determined to be a low-level pulse signal with a duration of a first duration, and the second abnormal information is obtained. The first duration is greater than the duration of the interruption signal that enables the device under test to maintain normal communication.

[0131] Specifically, when executing test scenarios that include abnormal verification conditions, the MCU precisely controls the I2C bus expansion module to generate and inject simulated I2C bus abnormal signals (such as clock stretch timeout, signal glitches, data setup / hold time violations) or interrupt signals of non-standard durations in real time on specific I2C channels.

[0132] Among them, simulating complex interrupt timing anomalies involves setting the microcontroller to apply non-standard interrupt signal timing to the interrupt input interface of the device under test through the I2C bus expansion module. For example, generating a simulated interrupt signal with a duration exceeding the I2C bus specification threshold (e.g., 25ms).

[0133] Alternatively, simulate subtle I2C communication waveform anomalies by precisely injecting brief interference into the I2C data or clock lines, forcibly pulling the signal low, or fine-tuning the timing to place it at the edge of the protocol (e.g., intentionally creating data setup / hold time violations).

[0134] By setting non-abnormal interrupt signals (i.e., standard interrupt signals) generated by the bus expansion module and clock timeout signals exceeding the maximum time threshold of the I2C protocol, the processing mechanism and robustness of the DUT under conditions of excessively long clock pull-low (SCL low-level hold time is too long) can be tested. This verifies the effectiveness of the DUT's clock timeout protection mechanism and whether it can correctly restore communication under extreme clock timeout conditions, avoiding system deadlock or abnormal suspension.

[0135] Precisely configures abnormal timing of clock and data signals, i.e., deviations of the serial clock line (SCL) and serial data line (SDA) from the behavior specified in the normal protocol. It can detect the sensitivity of the DUT to timing violations, including setup time and hold time anomalies, and assess its stability and compatibility under timing edge conditions.

[0136] Generate interference pulses with preset width and amplitude to simulate physical layer noise or transient disturbances. Test the DUT's immunity to interference, ensuring it maintains communication accuracy even when encountering minor interference in a real-world environment.

[0137] Simulate bus open or short circuit faults to test the DUT's fault detection and handling capabilities at the hardware level. Verify the DUT's robustness under circuit fault conditions, such as its ability to identify faults and take appropriate measures to prevent data corruption or system crashes.

[0138] Define interrupt signals with non-standard durations, such as low-level pulse signals whose duration exceeds the threshold that the DUT can normally handle. Evaluate the DUT's response to abnormal interrupt signals, especially its ability to handle excessively long interrupt signals, to ensure that it can maintain communication continuity and system stability under non-standard interrupt conditions.

[0139] These tests systematically verify and optimize the performance of the Design Under Test (DUT) under complex or abnormal operating conditions, ensuring stable operation in real-world application environments and meeting expected robustness and compatibility requirements. This testing method not only improves testing efficiency but also expands test coverage, enabling timely detection and correction of design flaws, thereby enhancing the overall quality and reliability of the product.

[0140] In some embodiments, the test control signal includes a control command. The corresponding test control signal is determined according to the test scenario, including: determining at least one test channel of the device under test according to the test scenario, obtaining the control command, wherein the communication addresses of any two test channels are different, and the control command is used to control the bus expansion module to output a bus abnormal signal using the target abnormal signal output interface corresponding to the test channel.

[0141] In other words, exception injection can be tested independently for a single channel, or it can be tested by polling multiple channels.

[0142] Based on a pre-defined test scenario, the microcontroller (MCU) can identify at least one test channel of the device under test (DUT) and generate corresponding control commands. This enables precise control of a specific I2C channel, allowing for the injection of abnormal signals into that channel without interfering with normal communication on other channels, thus testing its robustness and anomaly handling capabilities.

[0143] Multiple test channels operate independently, with a microcontroller controlling multiple channels to poll for testing, thus improving the level of test automation.

[0144] The MCU selects the target abnormal signal output interface corresponding to the test channel through control commands and outputs the bus abnormal signal. It provides a flexible testing strategy, capable of dynamically adjusting the type, intensity, and channel of the abnormal signal according to different test scenarios, achieving a more comprehensive and detailed robustness assessment.

[0145] After receiving control commands, the bus expansion module outputs preset bus abnormal signals through the target abnormal signal output interface, such as clock stretching timeout, data setup / hold time violation, signal glitches, etc. This can simulate various abnormal situations that the I2C bus may encounter in actual operation, verify the performance of the device under test under non-standard communication conditions, and help discover potential design flaws or compatibility issues.

[0146] In summary, by using control commands to dynamically configure and operate the bus expansion module, this embodiment can effectively perform accurate abnormal signal simulation and robustness testing on different I2C channels, thereby significantly improving the efficiency, accuracy, and flexibility of testing. It provides a comprehensive testing solution for the I2C bus design of electronic devices, contributing to the improvement of product quality and reliability.

[0147] In some embodiments, dynamically adjusting the test control signal based on test data includes: adjusting the signal type, signal strength, occurrence time, and number of bus abnormal signals based on test data to obtain updated abnormal signals, thereby dynamically adjusting the test control signal.

[0148] The MCU can dynamically adjust the type, intensity, timing, and action channel of anomaly injection based on real-time feedback from the device under test (DUT) or a preset test sequence. For example, if the DUT exhibits instability in response to a specific anomaly, the MCU can automatically adjust the anomaly parameters or switch to other related anomaly types to conduct more in-depth testing and simulate complex chain reactions in real-world scenarios.

[0149] Test data collected during the testing process (including DUT response, error rate, communication latency, etc.) is used to analyze the current robustness and anomaly sensitivity of the device under test. Based on the feedback from the test data, the MCU can intelligently adjust the parameters of the anomaly signals, including signal type (such as clock stretching, data glitches), signal strength (such as voltage fluctuation amplitude), occurrence time (when the anomaly is injected), and signal quantity (number of injections within the test cycle), to more accurately evaluate the DUT's performance under various specific anomaly conditions. This adaptive testing strategy enables more precise and in-depth testing of the DUT's weaknesses or specific anomaly scenarios, helping to discover problems that are difficult to expose under fixed test conditions, further optimizing test efficiency and quality.

[0150] By continuously adjusting the parameters of abnormal signals and gradually approaching the extreme operating conditions of the DUT, it is possible to more quickly identify which signal types and intensities are the key factors causing DUT performance degradation or failure. This accelerates the problem localization process, reduces invalid testing, and allows engineers to focus on abnormal conditions that truly affect system stability and reliability, thereby speeding up problem analysis and resolution.

[0151] Dynamically adjusting anomaly signals means that multiple anomaly types and intensities can be covered in a single test. This is more comprehensive than using only preset fixed anomaly signals, enabling a more systematic check of the DUT's robustness. It significantly enhances the comprehensiveness and depth of testing, avoids testing blind spots, ensures that the DUT can be fully verified during the design phase, and reduces potential quality issues after entering the production phase.

[0152] The method of dynamically adjusting test control signals not only improves the flexibility and efficiency of testing, but also greatly enriches the test scenarios, which helps to verify the robustness of the I2C bus of electronic devices more comprehensively and in-depth, and provides strong support for product quality control and design optimization.

[0153] In some specific test experiments, the test platform is first set up, and the MCU, I2C bus expansion module, and multiple DUTs (such as I2C sensors, non-volatile memory EEPROM, and power management integrated circuit PMIC) are connected and powered on. The PC host computer software loads the test firmware to the MCU.

[0154] Next, configure the abnormal test scenario. On the PC host computer interface, the user selects the I2C channels to be tested (e.g., channel A and channel C) and configures the abnormal injection type, for example: "Channel A: Clock stretch timeout (25ms); Channel C: SDA signal glitches (100ns width)". Simultaneously, it can be set whether the MCU automatically switches to the next abnormal scenario or repeats the injection of the current abnormality after detecting a DUT communication error.

[0155] The automated testing process then begins. The MCU starts sending normal I2C read / write commands to the DUT on channel A. At a specific moment or when a condition is triggered, the MCU instructs the I2C bus extension module to precisely inject a 25ms clock stretch timeout on channel A. Simultaneously, the MCU begins sending commands to the DUT on channel C, and randomly or periodically injects 100ns glitches into the SDA line during communication. An oscilloscope is triggered to capture the I2C waveform during the injection anomaly for manual analysis.

[0156] Finally, the MCU monitors the responses of each DUT in real time. If the DUT of channel A can still respond correctly after the clock stretch timeout, but the timeout error is recorded in the internal log, it is judged as "good robustness, anomaly can be recorded". If it cannot respond, it is judged as "poor robustness". If the DUT of channel C has data errors or no response after glitch injection, the MCU will record the error type and time, display the error information on the PC interface, and mark the DUT of channel C as "sensitive to SDA glitch". The PC host computer software will summarize all test results and generate a report, including key indicators such as the anomaly injection type, number of injections, DUT response, and error rate for each channel.

[0157] Figure 8 This is a schematic diagram of an I2C bus communication anomaly detection and handling process. Figure 8 As shown, the process first confirms the master-slave transmission of the inter-integrated circuit bus, then prepares for data transmission, sends the slave address, enables and waits for an interrupt (enable clock signal low-level timeout), and then checks if the inter-integrated circuit bus has timed out. If so, the return value is set to inter-integrated circuit bus_error_retry, i.e., an error return. If not, it checks if the device has been woken up from the clock signal low-level timeout. If so, the bus is reset, and the return value is confirmed to be inter-integrated circuit bus_error_retry, i.e., an error return. If not, a normal return is confirmed.

[0158] The above process ensures the security and integrity of communication during I2C data transmission by detecting and responding to clock low timeouts.

[0159] Figure 9 This is an interrupt handling mechanism in I2C bus communication, used to monitor and ensure successful data transmission, especially in the event of potential communication anomalies. For example... Figure 9 As shown, the inter-integrated circuit bus interrupt handler first checks if data transmission and reception are normal. If so, it processes the next batch of data or completes the transmission (waking up the host). If not, it checks if the data is incorrect. If so, it wakes up the host to transmit. If not, it checks if the clock signal low level has timed out. If so, it wakes up the host to transmit; otherwise, it returns from the interrupt.

[0160] The above process is a key step in ensuring data transmission quality and system stability in I2C bus communication. By monitoring the communication status in real time and responding quickly to anomalies, it improves the overall communication efficiency and reliability, providing a solid guarantee for high-performance communication of electronic devices.

[0161] Embodiments of this application also provide a testing system for an integrated circuit communication bus, such as... Figure 10 As shown, it includes: a device under test (DUT) 02; a test device 01 for any type of integrated circuit communication bus, electrically connected to the DUT 02; an oscilloscope 03, electrically connected to the DUT 02, used to detect the bus waveform of the DUT 02 in real time; and a host computer 04, communicatively connected to the test device 01 for displaying the test results of the DUT 02.

[0162] The MCU's firmware is responsible for generating the I2C test logic, controlling the I2C bus expansion module, interpreting test results, and communicating with the user interface. When the MCU precisely injects a specific anomaly, it can trigger an external oscilloscope to capture the waveform synchronously, allowing engineers to simultaneously observe the anomaly injection point and the DUT's response waveform details, greatly accelerating the fault diagnosis and debugging process.

[0163] The device under test (DUT) has several I2C bus interfaces and interrupt input interfaces (usually GPIO) associated with the I2C bus function. The corresponding interfaces of the DUT are connected to the corresponding output interfaces of the I2C bus expansion module.

[0164] The oscilloscope is connected to the I2C bus interface of the DUT to monitor the I2C bus waveform, timing and signal quality in real time, especially during abnormal injection, and can synchronously capture and display waveform details.

[0165] The PC debugging terminal / host computer software communicates with the MCU via interfaces such as UART, USB, or Ethernet. It is used to load test programs, display test results, logs, and error information, and allows users to configure test parameters and exception injection strategies.

[0166] Indicator lights on the I2C bus expansion module can display the real-time operating status of each communication channel. The system also includes a power module and mechanical structure / housing to provide a stable power supply and encapsulate all components.

[0167] The combination of the microcontroller's automated data interpretation capabilities and the real-time waveform monitoring of the test result display unit enables faster and more accurate isolation of problems, whether they originate from a specific I2C channel, slave device, or a specific timing anomaly or bus fault. This accelerates product debugging and problem resolution. Furthermore, the integration of the MCU's automated data interpretation and real-time waveform monitoring allows for faster diagnosis of fault causes and precise location of problems, reducing the difficulty of troubleshooting.

[0168] The integrated circuit communication bus test system integrates multiple components such as the device under test (DUT), integrated circuit communication bus test device, oscilloscope, and host computer, forming a comprehensive test platform. The system can comprehensively evaluate the performance and robustness of the integrated circuit communication bus from aspects such as hardware signal waveforms, software data interaction, and protocol compliance. Using the integrated circuit communication bus test device, various abnormal signals can be precisely controlled and injected to simulate different fault scenarios, thereby gaining a deeper understanding of the potential problems of the DUT.

[0169] By using an oscilloscope to monitor and display the bus waveforms of the device under test (DUT) in real time, engineers can intuitively observe signal quality and timing characteristics, and quickly diagnose communication problems. The host computer can not only display test results but also perform in-depth data analysis, such as calculating error rates and identifying abnormal patterns, helping engineers quickly understand the behavioral characteristics of the DUT.

[0170] The testing system can automatically execute pre-set test sequences, including normal communication and anomaly injection scenarios, reducing manual operation and improving testing efficiency. The system can combine waveform information and test data to analyze the cause of faults from multiple perspectives, thereby more accurately locating the problem. Based on the fault diagnosis results, the testing device can dynamically adjust testing strategies, for example, by selectively repeating or enhancing specific types of anomaly injections until the device's response mechanism is fully understood.

[0171] The system described above can be used to inject normal signals that conform to the I2C protocol but are under boundary conditions (e.g., the minimum / maximum communication rate allowed by the protocol, the minimum / maximum packet length, or the longest / shortest clock stretch time within the protocol range) to evaluate the compatibility and stability of the DUT for various compliant but extreme I2C communication scenarios.

[0172] Under continuous injection of specific anomalies or high-intensity communication loads, the above system can measure key performance indicators of the DUT, such as I2C communication throughput, response latency, or error rate. For example, under frequent signal glitches, the degree of decrease in I2C communication rate can be used as a quantitative indicator of performance degradation.

[0173] The aforementioned system can integrate with or coordinate with external power consumption measurement modules to monitor the real-time power consumption performance of the DUT while performing anomaly injection. By analyzing the power consumption changes of the DUT under abnormal conditions, its energy efficiency management strategy and energy consumption characteristics under fault conditions can be evaluated.

[0174] For I2C devices involving security-sensitive data, the above system can simulate malicious or unauthorized I2C command injection (e.g., injecting incorrect device addresses, forged read / write commands, or illegal data packets) to test the effectiveness of the DUT's I2C communication security protection mechanism, such as whether it can identify and reject illegal operations or whether it will trigger a security alarm.

[0175] For example, by using MCU software programming and combining the hardware characteristics of the I2C bus expansion module, non-standard / abnormal behaviors of the I2C bus and interrupt signals can be "actively simulated and injected".

[0176] This combination of hardware and software enables a systematic evaluation of the robustness of the device under test under non-ideal conditions, which is difficult to achieve with traditional testing methods.

[0177] Furthermore, by leveraging the multi-channel characteristics of the I2C bus expansion module, parallel or efficient automated polling tests of multiple I2C bus channels were achieved, significantly improving testing efficiency.

[0178] By coordinating programmable MCUs and I2C bus expansion modules, various "non-standard" or "abnormal" I2C communication signals and interrupt signals are actively and accurately simulated and injected on multi-channel I2C buses, thereby systematically evaluating the robustness of the electronic device under test under harsh conditions.

[0179] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0180] Embodiments of this application also provide a microcontroller, including: a determining unit, a transmitting unit, and a receiving unit. The determining unit is used to determine multiple test scenarios and, based on the test scenarios, determine corresponding test control signals. The transmitting unit is used to transmit the test control signals to a bus expansion module, so that the bus expansion module generates at least one bus abnormal signal based on the test control signals, and inputs the bus abnormal signal to the device under test (DUT). The bus abnormal signal is a simulated bus abnormal signal of the DUT, and the bus abnormal signal includes at least an abnormal interrupt signal. The receiving unit is used to receive test data fed back by the DUT and dynamically adjust the test control signals based on the test data to determine the test results of the DUT.

[0181] The microcontroller described in this application sends test control signals to a bus expansion module. The bus expansion module generates bus abnormal signals and inputs these signals to the device under test (DUT). The DUT generates test data based on the bus abnormal signals, which include at least an interrupt signal. The microcontroller dynamically adjusts the test control signals based on the test data fed back from the DUT to continue testing. By introducing a multi-channel bus expansion module with special programmable control capabilities, combined with the microcontroller's intelligent interpretation capabilities, multi-channel polling testing is achieved. This allows for the accurate and real-time generation and injection of various bus abnormal signals, especially interrupt signals, thereby comprehensively evaluating the robustness and other characteristics of the DUT. This solves the problem in related technologies where bus testing lacks comprehensive scenario coverage and cannot accurately inject abnormal signals, leading to inaccurate bus robustness assessments.

[0182] In some embodiments, the test control signal includes first abnormal information and second abnormal information. The first abnormal information includes information about a bus abnormal signal that is not an abnormal interrupt signal generated by the bus expansion module. The second abnormal information includes information about an abnormal interrupt signal generated by the bus expansion module. The determining unit includes a first determining module, a second determining module, a third determining module, a fourth determining module, and a fifth determining module. The first determining module is used to determine the duration of the low level of the clock timeout signal to obtain the first abnormal information when the test scenario is a clock timeout scenario. The duration exceeds the maximum time threshold of the bus protocol of the device under test. The second determining module is used to determine the first abnormal timing of the clock signal and the second abnormal timing of the data signal when the test scenario is an abnormal timing scenario. The test involves several modules: a first abnormality information module (DUT) and a second abnormality information module (DUT). The first module determines the first abnormality information by identifying the clock signal (serial clock signal) and data signal (serial data signal). The second module determines the DUT's handling mechanism and robustness in the event of an excessively long clock pull-down (SCL low-level hold time). The third module determines the preset width and amplitude of the interference pulse in an interference scenario, thus obtaining the first abnormality information. The fourth module determines the signal type of the circuit fault signal in a circuit fault scenario, thus obtaining the first abnormality information. The signal type is either a bus open-circuit signal or a bus short-circuit signal. The fifth module determines the abnormal interruption signal as a low-level pulse signal with a duration of a first duration in a signal interruption scenario, thus obtaining the second abnormality information. The first duration is greater than the duration of the interruption signal that allows the DUT to maintain normal communication. By setting the non-abnormal interruption signal (i.e., the standard interrupt signal) generated by the bus expansion module and the clock timeout signal exceeding the maximum time threshold of the I2C protocol, the DUT's handling mechanism and robustness in the event of an excessively long clock pull-down (SCL low-level hold time too long) can be tested.

[0183] In some embodiments, the test control signal includes control instructions, and the determining unit includes a sixth determining module, used to determine at least one test channel of the device under test (DUT) according to the test scenario, and obtain control instructions. The communication addresses of any two test channels are different. The control instructions are used to control the bus expansion module to output a bus abnormal signal using the target abnormal signal output interface corresponding to the test channel. The microcontroller (MCU) can determine at least one test channel of the DUT and generate corresponding control instructions. This achieves precise control of a specific I2C channel, enabling the injection of abnormal signals into the channel independently without interfering with the normal communication of other channels, thus testing its robustness and abnormal handling capabilities.

[0184] In some embodiments, the receiving unit includes an adjustment module for adjusting the signal type, signal strength, occurrence time, and number of bus abnormal signals based on test data to obtain updated abnormal signals, thereby dynamically adjusting the test control signals. By continuously adjusting the abnormal signal parameters and gradually approaching the extreme operating conditions of the DUT, it is possible to more quickly identify which signal types and strengths are the key factors causing DUT performance degradation or failure.

[0185] For a description of the features in the embodiment corresponding to the microcontroller, please refer to the relevant description of the embodiment corresponding to the test method of the integrated circuit communication bus, which will not be repeated here.

[0186] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above-described test method embodiments for an integrated circuit communication bus.

[0187] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described test method embodiments for integrated circuit communication buses when running.

[0188] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0189] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described test method embodiments for integrated circuit communication buses.

[0190] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described integrated circuit communication bus test method embodiments.

[0191] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0192] The foregoing has provided a detailed description of the testing apparatus, method, and system for an integrated circuit communication bus provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A test apparatus for an integrated circuit communication bus, characterized by The test device comprises a microcontroller, a bus expansion module and a bus. The microcontroller is configured to generate a test control signal and dynamically adjust the test control signal according to test data fed back by the device under test, so as to determine a test result of the device under test. The bus expansion module is electrically connected to the microcontroller and is configured to generate at least one bus exception signal according to the test control signal sent by the microcontroller, and input the bus exception signal into the device under test, so that the device under test generates the test data according to the bus exception signal. The bus exception signal is an analog exception signal of a bus of the device under test, and at least comprises an exception interrupt signal which is an interrupt signal not conforming to a communication protocol standard.

2. The test apparatus of the integrated circuit communication bus according to claim 1, wherein, The test control signal comprises first exception information and second exception information. The first exception information comprises information of the bus exception signal of a non-exception interrupt signal generated by the bus expansion module. The second exception information comprises information of the exception interrupt signal generated by the bus expansion module. The bus expansion module comprises an exception signal input interface, an interrupt signal input interface and a plurality of groups of exception signal output interfaces.

3. The test apparatus of the integrated circuit communication bus according to claim 2, wherein, The exception signal input interface is electrically connected to the microcontroller and is configured to receive the first exception information.

4. The test apparatus of claim 2, wherein, The interrupt signal input interface is electrically connected to the microcontroller and is configured to receive the second exception information.

5. The test apparatus of claim 2, wherein, Each group of the exception signal output interfaces comprises a plurality of bus output interfaces and an interrupt signal output interface. The bus output interfaces are configured to output the bus exception signal of the non-exception interrupt signal. The interrupt signal output interface is configured to output the exception interrupt signal. The plurality of bus output interfaces of one group of the exception signal output interfaces respectively comprise a clock signal output interface and a data signal output interface. The communication addresses of any two groups of the exception signal output interfaces are different. The bus expansion module is configured to output the exception interrupt signal to the device under test through the interrupt signal output interface. The exception interrupt signal is a low-level pulse signal with a first duration, and the first duration is greater than a duration of an interrupt signal enabling the device under test to maintain normal communication. The bus exception signal comprises a clock timeout signal, an exception timing signal, an interference signal and a circuit fault signal. The clock timeout signal is a signal with a low-level duration exceeding a maximum time threshold of a bus protocol. The exception timing signal is a data signal or a clock signal with a timing enabling the device under test to incorrectly identify data. The circuit fault signal is a bus open circuit signal or a bus short circuit signal.

6. The test device of the integrated circuit communication bus according to claim 5, wherein The bus extension module is configured to generate a low-level signal, and a duration of the low-level signal exceeds a maximum time threshold of the bus protocol to generate the clock timeout signal, the clock signal being a signal of a serial clock signal line; The bus extension module is configured to generate a clock signal with a first abnormal timing, and / or generate a data signal with a second abnormal timing to generate the abnormal timing signal, the data signal being a signal of a serial data signal line; The bus extension module is configured to inject a pulse with a preset width and a preset amplitude on the serial clock signal line and / or the serial data signal line to generate the interference signal.

7. The test device for the integrated circuit communication bus according to claim 6, wherein The bus extension module is configured to change a state of the data signal within a first preset time period before a rising edge of the clock signal to generate the abnormal timing signal, the first preset time period being less than a data stabilization time period, the data stabilization time period being a time period for stabilizing the data signal; and / or The bus extension module is configured to change the state of the data signal within a second preset time period after a falling edge of the clock signal to generate the abnormal timing signal, the second preset time period being less than a time period for completely collecting data of the data signal.

8. The test device for the integrated circuit communication bus according to claim 2, wherein The microcontroller is further configured to determine a target abnormal signal output interface of the bus extension module, the bus output interface in the target abnormal signal output interface being an interface for actually outputting the bus abnormal signal that is a non-abnormal interrupt signal to the device under test, an interrupt signal output interface in the target abnormal signal output interface being an interface for actually outputting the abnormal interrupt signal to the device under test, and the target abnormal signal output interface being one or more.

9. The test apparatus of the integrated circuit communication bus according to claim 1, wherein, The bus extension module comprises a bus multiplexer and / or an integrated circuit switch.

10. The test device for the integrated circuit communication bus according to claim 2, wherein The microcontroller further comprises: at least one master interface, which is electrically connected to the bus extension module, and is configured to send a control instruction and receive the test data, the control instruction being a signal for controlling the bus extension module to generate the bus abnormal signal; at least one general-purpose input / output pin, which is electrically connected to the bus extension module, and is configured to send first abnormal information and second abnormal information, the first abnormal information including information of the bus abnormal signal that is a non-abnormal interrupt signal generated by the bus extension module, and the second abnormal information including information of an abnormal interrupt signal generated by the bus extension module.

11. A method of testing an integrated circuit communication bus, characterized by, The microcontroller applied to the test device for the integrated circuit communication bus according to any one of claims 1 to 10, the method comprising: determining a plurality of test scenarios, and determining corresponding test control signals according to the test scenarios; sending the test control signal to the bus extension module, so that the bus extension module generates at least one bus exception signal according to the test control signal, and so that the bus extension module inputs the bus exception signal into the device under test, the bus exception signal being an analog exception signal of a bus of the device under test, the bus exception signal at least including an exception interrupt signal, the exception interrupt signal being an interrupt signal that does not conform to a communication protocol standard; receiving test data fed back by the device under test, and dynamically adjusting the test control signal according to the test data to determine a test result of the device under test; dynamically adjusting the test control signal according to test data fed back by the device under test, including: adjusting a signal type, a signal strength, a time of occurrence, and a signal quantity of the bus exception signal according to the test data to obtain an updated exception signal, so as to dynamically adjust the test control signal.

12. The method of testing an integrated circuit communication bus of claim 11, wherein, The test control signal includes first exception information and second exception information, the first exception information including information of a non-exception interrupt signal of the bus exception signal generated by the bus extension module, and the second exception information including information of an exception interrupt signal generated by the bus extension module, and determining a corresponding test control signal according to the test scenario includes at least one of the following: In a case where the test scenario is a clock timeout scenario, determining a duration of a low level of a clock timeout signal to obtain the first exception information, the duration exceeding a maximum time threshold of a bus protocol of the device under test; In a case where the test scenario is an exception timing scenario, determining a first exception timing of a clock signal and a second exception timing of a data signal to obtain the first exception information, the clock signal being a signal of a serial clock signal line, and the data signal being a signal of a serial data signal line; In a case where the test scenario is an interference scenario, determining a preset width and a preset amplitude of an interference pulse to obtain the first exception information; In a case where the test scenario is a circuit fault scenario, determining a signal type of a circuit fault signal to obtain the first exception information, the signal type being a bus open circuit signal or a bus short circuit signal; In a case where the test scenario is a signal interrupt scenario, determining that the exception interrupt signal is a low level pulse signal with a first duration, to obtain the second exception information, the first duration being greater than a duration of an interrupt signal that enables the device under test to maintain normal communication.

13. The method of testing an integrated circuit communication bus of claim 11, wherein, The test control signal includes a control instruction, and determining a corresponding test control signal according to the test scenario includes: According to the test scenario, determining at least one test channel of the device under test to obtain the control instruction, a communication address of any two test channels being different, and the control instruction being used to control the bus extension module to output the bus exception signal by using a target exception signal output interface corresponding to the test channel.

14. A test system for an integrated circuit communication bus, characterized by The device under test; The integrated circuit communication bus testing device of any one of claims 1 to 10, in electrical connection with the device under test; ​ An oscilloscope, which is electrically connected with the device under test, is used for detecting the bus waveform of the device under test in real time. A host computer, which is in communication connection with the test device of the integrated circuit communication bus, is used for displaying the test result of the device under test.

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