A TSI system OC bus layout method and system

Abstract

The present invention relates to the technical field of steam turbine safety monitoring, and in particular to a method and system for arranging the OC bus of a TSI system, comprising: dividing the OC bus into three independent main channels at the physical layout layer: a data acquisition bus, a communication bus, and an address and operating condition bus; according to the signal characteristics of the three independent channels, a grounding design with separated analog and digital grounds and a resistor buffer circuit are provided to form a multi-layer anti-interference system, with different buses arranged in layers; the hardware redundancy layer relies on the independent channels reserved in the physical layout to construct a dual-phase hard-wired redundant channel, combining relays and control nodes to form a fault switching mechanism, and the redundant channel is physically isolated from the main channel; the intelligent algorithm layer constructs a state space based on the address bus and power channel status in the physical layout layer, combines the fault feedback signal of the hardware redundancy layer, and iteratively optimizes the algorithm decision through a dynamic allocation model. This solution adopts a three-layer progressive structure to arrange the OC bus to improve transmission reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of steam turbine safety monitoring, and in particular to a method and system for arranging an OC bus of a TSI system. Background Art

[0002] The OC bus in traditional TSI systems faces significant technical challenges in implementation. They employ a hybrid wiring approach, routing data acquisition, communication, and control signals onto the same transmission channel. This approach results in significant crosstalk between different signal types. Field measurements show that this crosstalk can increase vibration monitoring data errors by over 25%, directly impacting the accuracy of turbine fault diagnosis and potentially leading to delayed equipment maintenance or misdiagnosis of fault types. Traditional solutions rely on digital buses for transmission of critical signals such as speed and key phase, which are crucial for safe turbine operation. However, bus failures account for 32% of TSI system failures, with digital bus failures accounting for a staggering 78%. Once a failure occurs, it can easily cause the protection system to malfunction or fail to operate, posing the risk of an emergency turbine shutdown or even a more serious safety incident. Regarding bus resource allocation, the traditional OC bus utilizes a fixed bandwidth allocation strategy, which is unable to dynamically adjust to varying operating conditions, such as turbine startup, stable operation, and shutdown. For example, during startup, the conflict between the large amount of transient data transmission demand and the fixed bandwidth can easily lead to bus congestion. However, during normal operation, when data volume decreases, bandwidth resources become idle. This supply-demand mismatch severely reduces overall system efficiency. Summary of the Invention

[0003] The present invention adopts a three-layer progressive structure to arrange the OC bus, thereby improving transmission reliability, real-time performance and resource utilization.

[0004] The technical solution proposed by the present invention is: a method for arranging an OC bus of a TSI system, the method comprising:

[0005] At the physical layout layer, the OC bus is divided into three independent main channels: data acquisition bus, communication bus, and address and working condition bus. Based on the signal characteristics of the three independent channels, a grounding design with separate analog and digital grounds and a resistor buffer circuit are set up to form a multi-layer anti-interference system. Different buses are arranged in layers, and the analog and digital grounds are connected at a single point.

[0006] The hardware redundancy layer relies on independent channels reserved in the physical layout to build dual-phase hard-wired redundant channels. Relays and control nodes form a fault switching mechanism, and the redundant channels are physically isolated from the main channels.

[0007] The intelligent algorithm layer constructs a state space based on the address bus and power channel status in the physical layout layer. Combined with the fault feedback signals from the hardware redundancy layer, it iteratively optimizes the algorithm decisions through a dynamic allocation model. The optimized algorithm decisions are then applied to the hardware pins in real time.

[0008] Preferably, the main channel division method is as follows:

[0009] The data acquisition bus consists of 26 pins and is directly connected to the vibration monitoring module and the speed monitoring module. The wiring spacing between the data acquisition bus and the other main channels is greater than 50 mils; the communication bus is designed in accordance with the RS-485 communication standard and is transmitted through differential signals. In terms of bus topology, a trunk-branch structure is adopted, and the branch length of each node is ≤30 cm; the address and working condition bus includes an 8-pin address bus and an 8-pin working condition bus. The two types of buses constitute an independent control link. The wiring spacing between the address bus, the working condition bus and the data acquisition bus is greater than 20 mils, and the address and working condition bus and the data acquisition bus are isolated by the power supply layer.

[0010] Preferably, the specific construction process of the multi-layer anti-interference system is as follows:

[0011] The data acquisition bus transmits analog signals, the analog circuit is connected to the analog ground, and the analog ground plane is covered with a complete copper foil; the communication bus and the address and working condition bus transmit digital signals, the digital circuit is connected to the digital ground, and the digital ground plane is divided into independent areas; the analog ground and the digital ground are interconnected at a single point through a 0Ω resistor; in the data acquisition bus, a resistor buffer circuit is constructed using a 3K resistor, which is connected in series with the signal transmission path and placed close to the signal source; when the signal frequency exceeds 1MHz, the 3K resistor adjusts the equivalent impedance to 110-130Ω.

[0012] Preferably, the specific content of the hardware redundancy layer is as follows:

[0013] Relying on the independent channels reserved in the physical layout layer, dual-phase hard-wired redundant channels are constructed; the redundant channels are linked to the control nodes through relays to form a fault switching mechanism; the pin spacing between the redundant channels and the main channels is ≥20mil, an independent grounding path is set, and the wiring length is less than 5cm; a resistor buffer circuit with the same standard as the main channel is used; when a bus fails, the hardware redundancy layer performs channel switching through the redundancy mechanism.

[0014] Preferably, the redundancy mechanism includes the following:

[0015] During the normal operation phase, key signals are transmitted via the communication bus. The data format is Modbus RTU frame, which includes a 16-bit CRC check code. The relay is in the normally closed state, the dual-phase hard-wired redundant channel is disconnected from the signal source, the control node outputs a low level, and the relay is not triggered. In this phase, the dual-phase hard-wired redundant channel outputs a high level, and the system displays the working status of each channel through the status indicator light. During the fault detection phase, the status bus monitors the working status of the communication bus in real time. The monitoring parameters include bit error rate and communication interruption time. When the communication bus bit error rate exceeds 0.5% or 5 consecutive data packets are lost, the system will automatically detect the fault. The status bus sends a high-level signal to the control node. The resistor network in the control node divides and filters the input level, and the fault detection algorithm calculates the bit error rate. During the redundant switching phase, after the control node receives the high-level signal, it drives the relay to switch to the normally open state. The switching time is less than 0.5ms. The key signal is immediately switched to the 4-pin double-phase hard-wired channel for transmission. The signal type is changed from a differential digital signal to a single-ended pulse signal. The system sends a bus fault alarm signal to the monitoring interface. The alarm information includes the fault type and the switching timestamp. During the switching process, the signal transmission delay is reduced from 8ms to 0.5ms of the hard-wired channel.

[0016] Preferably, the intelligent algorithm layer constructs a 128-dimensional state space based on the address bus and power channel status in the physical layout layer, combines the fault feedback signal of the hardware redundancy layer, and adopts a dynamic allocation model based on the Q-Learning algorithm to perform bandwidth allocation, priority setting and transmission path selection to form an optimized algorithm decision. The optimized algorithm decision realizes bandwidth control through PWM signals and realizes switching through relay modules. When the action is executed, the algorithm must ensure the compatibility of bandwidth allocation and transmission path.

[0017] Preferably, the specific operation process of the dynamic allocation model is as follows:

[0018] The system reads the current hardware state; queries the Q-value table to select an action, considering the exploration-exploitation balance to discover the optimal strategy; obtains the bit error rate and delay, and calculates the utilization rate through the current monitoring resistor; updates the Q-value using the Q-Learning formula to increase the priority of the corresponding state-action pair in the Q-value table, and the algorithm subsequently selects this action under the same working conditions; after every 100 iterations, it performs strategy aggregation, clustering similar actions in the same state in the Q-value table, retaining the top three strategies with the highest Q values, and eliminating strategies with Q values ​​20% below the average level. The optimized strategy is then written to the Flash memory via the SPI interface.

[0019] The present invention also provides a TSI system OC bus layout system, which is used to execute the TSI system OC bus layout method.

[0020] The present invention also provides a computer-readable storage medium storing a computer program. The computer program is executed by a processor to implement the method for arranging an OC bus of a TSI system.

[0021] Beneficial effects of the present invention:

[0022] 1. By dividing the OC bus into three independent physical channels: data acquisition, 485 communication, and address and operating conditions, coupled with wiring spacing of at least 50 mils, differential signal transmission (CMRR ≥ 80dB), and distributed grounding (DGND) technology, crosstalk is suppressed from three dimensions: spatial isolation, signal transmission, and grounding system. Tests have shown that this design reduces vibration signal crosstalk from 28% to 9.5% and improves analog signal-to-noise ratio by 15dB (55dB to 70dB), meeting the noise suppression requirements of the API 670 standard and providing a low-interference hardware foundation for subsequent redundancy mechanisms and algorithm optimization.

[0023] 2. Construct a 4-pin dual-phase hard-wired channel (KEY1 / KEY2 pins), cooperate with Omron relays (switching time < 0.5ms) and 74HC86 XOR gate phase check, to achieve the signal transmission delay in the event of a fault from 8ms of the 485 bus to 0.5ms, and the bit error rate from 0.08% to < , meeting the SIL3 safety integrity level. In a project case, this mechanism reduced the speed signal measurement error of a 300MW unit from ±0.1% to ±0.03%, reducing unplanned shutdowns by 2-3 times per year.

[0024] 3. A reinforcement learning model is constructed using a 128-dimensional state space (address bus and power state) and a 36-dimensional action space (bandwidth / priority / path). The strategy is dynamically optimized using a comprehensive reward function based on bit error rate (weight 0.4), latency (0.4), and utilization (0.2). Field tests show that the algorithm improves bus efficiency by 22%, achieving a bit error rate of less than 0.05% and latency of less than 4ms under 95% of operating conditions. When redundant channels are switched, the algorithm automatically increases the hard-wired bandwidth from 30% to 50%, forming a closed loop of "hardware failure-algorithm adaptation-efficiency optimization," enabling self-evolving management of bus resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flow chart of a method for arranging an OC bus of a TSI system according to the present invention;

[0026] Figure 2 An OC bus signal exchange circuit diagram of a TSI system OC bus arrangement method according to the present invention;

[0027] Figure 3 A control signal transfer circuit diagram of a TSI system OC bus arrangement method according to the present invention;

[0028] Figure 4 A voltage-dividing sampling circuit diagram of a TSI system OC bus arrangement method according to the present invention;

[0029] Figure 5 This is a state signal conditioning circuit diagram of a TSI system OC bus arrangement method of the present invention. DETAILED DESCRIPTION

[0030] The following description is intended to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are for illustrative purposes only, and those skilled in the art will readily appreciate other obvious variations. The basic principles of the present invention defined in the following description may be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0031] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the elements may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0032] like Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 or Figure 5As shown, this solution divides the OC bus into three independent physical channels based on function: a 26-pin independent data acquisition bus, a 10-pin 485 communication bus, and an 8-pin address bus and an 8-pin operating condition bus. The 26-pin independent data acquisition bus utilizes pin groups A1-A10 and B1-B10 for direct connection to vibration and speed monitoring modules. Pins A1 / A2 are differential inputs for the X-axis vibration signal of bearing 1 (A1 is positive phase, A2 is negative phase). Pins B1-B4 connect to a magnetoresistive speed sensor (outputting a 5V square wave signal), and pins B5-B8 connect to an eddy-current speed sensor (outputting a -24V to 0V sawtooth signal). This design utilizes physical isolation principles to strictly control the wiring spacing between the data acquisition bus and other signal types to at least 50 mils. Differential signal transmission (common-mode rejection ratio CMRR ≥ 80dB) effectively minimizes crosstalk interference with the original monitoring signal. From the perspective of the signal transmission link, the weak charge signal (about 10mV) output by the vibration sensor is converted into a voltage signal by the charge amplifier and then directly connected to the A1-A10 pins, avoiding sharing the wiring channel with the digital signal and reducing the risk of interference at the source. The 10-pin 485 communication bus uses the CH1_485A / B (located at the A2 / C2 pin) and CH2_485A / B (located at the C4 / A4 pin) interfaces and follows the RS-485 communication standard design. Differential signal transmission (the voltage difference between V+ and V- is ≥ 200mV) makes it highly resistant to common-mode interference, and can achieve a bit error rate of ≤ 100kbps within a transmission distance of 1200 meters. Reliable data transmission is suitable for the exchange of spectrum data and alarm signals between monitoring modules. The communication protocol utilizes Modbus RTU. Data frames include a CRC checksum field, and hardware differential transmission further enhances long-distance communication reliability. The bus topology adopts a trunk-branch structure, with branch lengths of ≤30cm at each node to ensure acceptable signal reflections. The 8-pin address bus and 8-pin operating bus utilize pins IPA_adr1-4 for the address bus. A 4-bit encoding can define 16 module addresses (e.g., IPA_adr = 1010 corresponds to a key phase detector module). The operating bus utilizes pins Working 1-4, transmitting real-time unit status via TTL levels (high level ≥ 2.4V, low level ≤ 0.4V) (e.g., Working 2 = 1 indicates grid-connected status). These two buses form independent control links, adhering to the principle of "separation of data and control" to prevent control signals from interfering with data transmission timing and improve control system response speed. The address bus and operating status bus maintain a minimum spacing of 20 mils from the data acquisition bus on the PCB layout and are isolated by a power plane to prevent high-frequency noise from the control signals from coupling into the data channels. Pins 97, 98, 11, and 12 connect to the controller chip, which controls overall circuit operation. IPA_buf1-4 are used for buffering data or signals.

[0033] To further enhance the OC bus's interference immunity, sophisticated isolation and buffering designs were incorporated into the physical layout. These features directly correspond to the bus board's hardware circuitry, forming a multi-level interference mitigation system. A split-point DGND grounding design was implemented, with pins A29 and B29 designated as digital ground (DGND), and pins A30 and B30 as analog ground (AGND). These two are connected at a single point near pins C16-C18 via a 0Ω resistor (±1% accuracy). This design, using separate ground planes, isolates ground noise from analog circuits (such as vibration signal conditioning amplifiers) and digital circuits (such as MCUs). This has been shown to improve the analog signal-to-noise ratio from 55dB to over 70dB, meeting the API 670 noise suppression requirements. Regarding the grounding system design, the analog ground plane is fully copper-clad, while the digital ground plane is segmented into separate areas, connected only at a single point via a 0Ω resistor to prevent ground loop currents and reduce common-mode interference. Several 3K resistors form a 3K resistor buffer circuit. A tri-state 1-8 buffer circuit is constructed using resistors R301-R308 (1 / 8W, ±5% precision resistors). R301 is connected in series with the tri-state 1 pin (labeled "3K tri-state 1"). When signal frequencies exceed 1MHz, the mismatch between the bus characteristic impedance (approximately 120Ω) and the load impedance (1kΩ) can easily cause reflections. The 3K resistors adjust the equivalent impedance to 110-130Ω, keeping the reflection coefficient below 0.1. This ensures a rise time of less than 50ns for high-speed signals (such as tachometer pulses, which can reach frequencies up to 100kHz), thus preventing waveform distortion. The buffer circuit's topology uses series termination, with the resistors placed close to the signal source. This effectively suppresses reflections at the source while not affecting the signal level at the receiver, ensuring proper sampling by subsequent circuits.

[0034] The physical layout was implemented using a systematic engineering approach, with each step closely aligned from requirements analysis to simulation verification to ensure the feasibility and reliability of the design. First, a detailed signal characteristics analysis was conducted on the signal types, data rates, and reliability requirements of each monitoring module in the TSI system. This determined which signals needed to be connected to the data acquisition bus, which needed to be transmitted via the communication bus, and which signals were control signals. The vibration monitoring module outputs a 0-10V voltage signal with a frequency range of 0-10kHz and a sampling rate of ≥20kHz, and must be connected to pins A1-A8 of the 26-pin data acquisition bus. The speed monitoring module collects the 5V square wave (1-10kHz) output of the magnetoresistive sensor and the -24V to 0V sawtooth wave (0-50kHz) output of the eddy current sensor, and must be connected to pins B1-B8. The communication module must comply with the RS-485 standard with a data transmission rate of 115.2kbps and must be connected to pins CH1_485A / B. The address coding signal in the control module is a TTL level, and the operating condition indication signal is a switch quantity, and must be connected to pins IPA_adr1-4 and work 1-4. By establishing a signal characteristic database, a basis is provided for subsequent pin assignment and PCB layout, ensuring the rational allocation of various types of signals on the physical channels. Assign pins A1-A10, B1-B10, etc. to the data acquisition bus. Each pin group corresponds to an independent signal channel, and the connection relationship between the pins and the sensor is clearly marked on the bus board schematic. Assign pins such as CH1_485A / B to the 485 communication bus. CH1_485A / B is used for the main communication link, and CH2_485A / B is used as the backup link. The connection between the pins and the communication chip (such as SN75176) must meet the RS-485 electrical characteristics requirements. Assign pins such as IPA_adr1-4 and Work 1-4 to the address and working condition bus. IPA_adr1-4 is directly connected to the module address DIP switch, and Work 1-4 is connected to the PLC input module. The pin output level must meet the PLC input specification (24VDC). During the pin assignment process, special attention must be paid to signal compatibility. For example, digital signal and analog signal pins must be arranged in partitions to avoid crosstalk caused by adjacent wiring.In printed circuit board (PCB) design, adhere to the following principles to ensure signal integrity and anti-interference capabilities: The spacing between the data acquisition bus and the 485 communication bus should be ≥20 mils to prevent electric field coupling. The spacing between analog signal pins (such as A1-A8) and digital signal pins (such as IPA_adr1-4) should be ≥30 mils and isolated by a ground plane. The analog and digital grounds should be connected via a ferrite bead or 0Ω resistor to form a single-point ground. The ground via diameter should be ≥12 mils, and the ground plane copper foil thickness should be ≥1 oz to ensure a low-impedance ground path. Buffer resistors should be placed as close to the signal source as possible to achieve optimal buffering effect. Buffer resistors such as R301-R308 should be placed close to the signal source, ≤5 mm away, for optimal matching. The resistor package should be 0805 to balance heat dissipation and parasitic parameter control. A four-layer PCB design is used, with the top layer being the data acquisition bus, the second layer being the analog ground plane, the third layer being the digital ground plane, and the bottom layer being the 485 communication bus. The control bus is distributed on the top and bottom layers and isolated by the power layer. Using simulation tools such as HyperLynx, signal integrity simulations were performed on the PCB layout to verify whether crosstalk, reflections, and other indicators met design requirements. Based on the simulation results, the layout was optimized until the desired results were achieved. Simultaneous transmission of a vibration signal (10kHz sine wave) and a 485 communication signal (115.2kbps square wave) was set. If the simulation results showed a crosstalk amplitude of less than 5%, the design requirements were met. Transmission line simulations were performed on the speed signal (50kHz square wave). After buffering with a 3K resistor, the reflection coefficient was required to be less than 0.1, and the rise time was controlled within 50ns. The potential difference between the analog and digital grounds was required to be less than 50mV, and the power plane fluctuation was required to be less than 100mV to ensure stable power supply for the analog circuits. Any issues identified in the simulations were addressed by adjusting wiring spacing and optimizing termination resistor values ​​until all indicators met the standards.

[0035] For example, the aforementioned physical layout design was adopted in a 300MW steam turbine TSI system retrofit project. Eight eddy-current vibration sensors (±200μm range) were connected to pins A1-A8, and four speed sensors (three magnetoresistive and one eddy-current) were connected to pins B1-B8. The vibration signal transmission line utilizes twisted-pair shielded cable, with the shield grounded at one end (to the bus board AGND) to reduce spatial magnetic field interference. The speed signal transmission line utilizes coaxial cable with a characteristic impedance of 50Ω, which, along with the matching resistors (3kΩ) on the bus board pins, completes the transmission chain. The CH1_485A / B pins connect the vibration monitoring module to the PLC, with a communication distance of approximately 80 meters. A 120Ω matching resistor is connected to the bus terminal to ensure acceptable signal reflections. The communication protocol utilizes Modbus RTU. The data frame contains 8 bytes of vibration spectrum data, with a transmission period of 20ms and a measured bit error rate of less than 0.01%. IPA_adr1-4 pins set the vibration module address to 0011. Working pins 1-4 connect to the unit's DCS system, transmitting real-time status signals for startup (Working 1 = 1), grid connection (Working 2 = 1), full load (Working 3 = 1), and shutdown (Working 4 = 1). Control signal transmission lines and data acquisition lines are routed separately to prevent interference and malfunction. Post-modification test data shows a significant reduction in vibration signal crosstalk from 28% to 9.5%, and a reduction in speed signal measurement error from ±0.1% to ±0.03%, meeting the highest accuracy level required by the API 670 standard. This case demonstrates the effectiveness of the physical layout design and lays a solid hardware foundation for the subsequent implementation of redundancy mechanisms and intelligent algorithms.

[0036] The physical layout layer provides a solid hardware foundation for the subsequent redundancy layer. Independent channel configuration enables redundant switching. Since the data acquisition bus, communication bus, and control bus are independent, if a bus fails, the redundancy mechanism can selectively switch to the corresponding backup channel without affecting the transmission of other signals. For example, if the 485 communication bus (CH1_485A / B) experiences excessive bit error rates due to interference, the redundancy mechanism can switch critical signals (such as speed) to the hardwired channel (KEY1 / KEY2 pins), while the vibration signal continues to be transmitted normally via the data acquisition bus, ensuring signal integrity of the non-faulty channel. Isolation design improves the reliability of the redundant channel. The DGND split point and buffer circuit design apply not only to the main channel but also to the redundant channel, ensuring high-quality redundant signal transmission. The KEY1 / KEY2 pins of the hardwired channel are buffered with R801-R804 (3kΩ) (similar to the buffer design of the data acquisition bus) and utilize independent ground paths to isolate them from the main channel's ground system, preventing ground noise from the faulty channel from affecting the redundant signal. During the physical layout design phase, necessary pin resources were reserved for redundancy, such as dual-phase pins like KEY1 and KEY2. These pins were placed close to the relay module mounting location on the PCB, with a wiring length of less than 5 cm, ensuring a transmission delay of less than 1 ns for the hard-wired channel. The reserved pins were spaced ≥ 20 mils from the main channel pins and isolated with ground vias to prevent signal coupling under normal operating conditions.

[0037] The transmission reliability of key signals such as speed and key phase in the TSI system is directly related to the safe operation of the steam turbine. These signals are used to calculate key parameters such as shaft vibration intensity and critical speed. Their transmission delay must be less than 5ms and the bit error rate must be less than 0.01%. Otherwise, the emergency trip system (ETS) may malfunction or refuse to operate, causing a major safety accident. Statistics show that the bit error rate of the traditional 485 bus can rise to 1% in a strong electromagnetic interference environment (such as when the inverter is running), while the bit error rate of the hard-wired redundant channel designed in this solution is less than 0.01%. , meeting SIL3 safety integrity level requirements.

[0038] From an engineering perspective, the response time for steam turbine trip protection must be ≤10ms, of which signal transmission delay must account for ≤50% (i.e., ≤5ms). Under worst-case conditions (long-distance transmission and strong interference), the traditional 485 bus can experience delays of up to 8-10ms, failing to meet this requirement. However, through direct physical connections, hardwired channels can reduce delays to less than 0.5ms. Combined with rapid relay switching, the overall fault response time is less than 1ms, fully meeting the real-time requirements of the protection system.

[0039] The hard-wired redundant channel includes three core parts: a 4-pin dual-phase hard-wired channel, a relay module, and a CS1-CS4 control node. The 4-pin dual-phase hard-wired channel uses pins such as KEY1 and KEY2 to form a dual-phase hard-wired channel. KEY1 transmits positive-phase speed pulses, and KEY2 transmits reverse-phase pulses (phase difference of 180°). The receiving end detects the validity of the signal through the 74HC86 XOR gate circuit next to the C2-C3 pins. When the KEY1 / KEY2 signal is lost or the phase difference is greater than 90°, the ERR_KEY1 / 2 pin outputs a 3.3V high-level alarm. The advantage of the dual-phase design is that the authenticity of the signal is determined by the phase difference. When one of the signals is interfered and distorted, the other signal can still remain normal, and the XOR gate output remains unchanged, ensuring that the receiving end samples correctly. The relay module uses high-reliability electromagnetic relays, such as the Omron G6K series, with a switching time of less than 0.5ms and a contact life of up to The REL1 pin is driven by a 2N3906 PNP transistor (with a 10kΩ current-limiting resistor in series with the base). The relay contacts and hard-wired channels are connected in the C5-C8 area via 20mil-wide traces, with an on-resistance of less than 100mΩ and a signal attenuation of less than 0.1dB at 10kHz. A 1N4007 diode (D101) is connected in parallel across the relay coil to suppress back EMF when the coil is de-energized, protecting the driver circuit. The CS1-CS4 control nodes are constructed using 3kΩ resistors such as R501-R504 and the 24-pin status bus. These nodes are linked to the 24-pin channel status bus to control relay switching. When Status 5 = 0 (data acquisition channel 5 fault) and CS3 = 1, R503 divides the voltage with the Status 5 pin to output a 3.3V high level, triggering the relay toggling. The input impedance of the control node is designed to be 10kΩ, matching the output impedance of the status bus (approximately 500Ω) to ensure accurate level conversion. The role of the resistor here is to limit the current and divide the voltage to ensure that the level of the control signal meets the driving requirements of the relay.

[0040] The hard-wired redundancy mechanism can be divided into three stages. In the normal operation stage, key signals (such as speed and key phase) are transmitted through the 485 communication bus (CH2_485A / B pins). The data format is Modbus RTU frame, including 16-bit CRC check code. The relay is in the normally closed state, the hard-wired channel (KEY1 / KEY2 pins) is disconnected from the signal source and is in standby state. The CS1-CS4 control nodes output a low level (≤0.4V) and do not trigger the relay action. In this stage, the ERR_KEY1 / 2 pins of the hard-wired channel output a high level (≥2.4V), indicating that the redundant channel is in normal standby state. The system displays the working status of each channel through the status indicator (LED1-LED4); in the fault detection stage, the 24-pin channel status bus (status 1-status 8 pins) monitors the working status of the 485 communication bus in real time. The monitoring parameters include bit error rate (calculated by the number of CRC check failures, with a threshold of 0.1%) and communication interruption time (five consecutive data packets are lost, which is determined to be a bus fault). When the communication bus bit error rate exceeds 0.5% or five consecutive packets are lost, the system will automatically shut down. When a data packet is lost, the status bus sends a high-level signal (≥3.3V) to the CS1-CS4 control nodes. The R501-R504 resistor network within the control nodes divides and filters the input voltage to prevent false triggering. The fault detection algorithm uses a sliding window mechanism with a window size of 100 data packets. The bit error rate calculation is updated every 10 received data packets to ensure accurate and real-time detection. During the redundant switching phase, after receiving the high-level signal, the CS1-CS4 control nodes drive the relays through the REL1-REL3 pins to switch to the normally open state. The switching time is less than 0.5ms. The critical signal is immediately switched to the 4-pin dual-phase hard-wired channel (KEY1 / KEY2 pins) for transmission. The signal type is converted from differential digital signal to single-ended pulse signal. The system sends a bus fault alarm signal to the monitoring interface via working pins 1-4. The alarm information includes the fault type (such as the 485 bus bit error rate exceeds the standard) and the switching timestamp. During the switching process, the signal transmission delay is reduced from 8ms for the 485 bus to 0.5ms for the hard-wired channel, ensuring the real-time response of the protection system.

[0041] The specific implementation process of the redundancy mechanism involves using FMEA (Failure Mode and Effects Analysis) methods, combined with turbine protection logic, to determine which signals are critical and require hard-wired redundant channels. These typically include the turbine speed signal (three independent measurements for two-out-of-three protection logic), the key phase detector signal (one for shaft phase reference), the axial displacement signal (two for rotor axial position monitoring), and the differential expansion signal (one for monitoring the clearance between moving and static components). During this stage, a critical signal importance matrix is ​​established, and the redundancy level is determined based on the impact of signal loss on unit safety. Design the relay module's installation location, maximizing proximity to the signal source and receiver. Install the relay module in a separate metal shielded box near the bus board, ≤30 cm from the source and receiver to minimize transmission delay. Plan the hardwired channel routing, avoiding high-voltage cables (such as power cables) and ensuring a 90° or greater angle of intersection with these cables to minimize magnetic field coupling. Determine the connection method between the CS1-CS4 control nodes and the channel status bus. Use shielded twisted-pair cables with grounded shields at both ends to improve interference immunity. Write a channel status monitoring program, set fault determination thresholds, and design relay driver logic to ensure reliable switching and implement fault alarm and logging. Implement the channel status monitoring program using interrupts, with the highest interrupt priority, to ensure real-time fault detection. The relay driver logic includes anti-jitter processing, ensuring a 100ms or greater interval between switching operations to prevent false trips. Fault alarm and logging functions record the time, cause, and recovery status of each switching event, with a storage depth of ≥1000 records. The programming environment uses embedded C language, and the compiler optimization level is set to -O2 to ensure code execution efficiency. Simulate 485 communication bus failures, test redundant switching time, verify signal continuity during the switching process, conduct long-term stability tests, and verify the reliability of the redundancy mechanism. Use an oscilloscope to measure the time from the occurrence of a 485 bus failure to the activation of the hard-wired channel, which must be ≤1ms. Use a data recorder to compare the signal waveforms before and after switching, requiring the signal loss time during the switching process to be less than 50μs. Run continuously for 1000 hours, simulate 50 fault switchings, and require no switching failures or signal anomalies. During the test, it is necessary to record parameters such as ambient temperature and humidity to ensure that the test conditions are consistent with actual operating conditions.

[0042] For example, in the TSI system of a 600 MW supercritical steam turbine unit, the aforementioned hard-wired redundancy mechanism was applied to collect turbine speed (three independent measurements for two-out-of-three protection logic, reluctance type, 60 teeth) and key phase detector signals (one independent measurement for two-out-of-three protection logic, eddy current type, 1 tooth). The KEY1 and KEY2 pins formed a dual interphase channel, using coaxial cable (characteristic impedance 50Ω). The Omron G6K-2F-Y12V relay, with a coil voltage of 12 VDC and a switching time of 0.3 ms, was used. Tests showed a bus fault switching time of 0.5 ms (from fault detection on the Status 7 pin to relay activation on the REL1 pin). The maximum speed signal fluctuation during the switching process was 0.02% (corresponding to a speed measurement error of ±0.6 rpm). Fault-free switching was achieved during 1000 hours of continuous operation, and 32 simulated fault switching attempts were completed without a single failure. The ERR_KEY1 pin alarm had 100% accuracy. The results show that the hardwired redundancy mechanism effectively improves the reliability of critical signal transmission, meeting the safe operation requirements of large steam turbine units. This redundancy mechanism successfully resolved the unit's original TSI system's speed signal nuisance tripping caused by 485 bus interference, reducing unplanned downtime by 2-3 times annually and generating direct economic benefits of approximately 5 million yuan. Furthermore, the high reliability of the hardwired channel provides a stable hardware environment for subsequent intelligent algorithm optimization.

[0043] The redundancy mechanism layer provides a reliable hardware environment for the intelligent allocation algorithm layer. The redundancy mechanism and intelligent algorithm layers do not operate independently, but rather form a deep synergy through hardware status and control signals to jointly improve system reliability and efficiency. The intelligent allocation algorithm uses the bus fault status detected by the redundancy mechanism as a key input parameter. When a bus fault is detected and a switchover is completed, the algorithm automatically adjusts the bandwidth allocation strategy, for example, increasing the bandwidth of the hardwired channel from 30% to 50% to prioritize the bandwidth requirements of the hardwired redundant channel. Status information is transmitted to the intelligent algorithm layer via the following pins: IPB_adr1-4 pins transmit code 0001, indicating that the hardwired channel is currently in use; the +24V_3 pin outputs a high level, indicating that the relay power is on; and the status 7 pin outputs a high level, indicating a 485 bus fault. During the redundancy switching process, the signal transmission path changes from the 485 bus (CH1_485A / B pins) to the hard-wired channel (KEY1 / KEY2 pins). The change in the signal transmission path will cause changes in transmission delay and bit error rate. The intelligent allocation algorithm can perceive these changes in real time and adjust the bus allocation plan accordingly to ensure the stability of data transmission. For example, if the delay is reduced from 8ms to 0.5ms, the algorithm will reduce the reward weight for the delay accordingly ( The coefficient is temporarily reduced from 0.4 to 0.3); the bit error rate is reduced from 0.08% to 0, and the algorithm will increase the reward weight for the bit error rate ( The coefficient is temporarily increased from 0.4 to 0.5); this dynamic adjustment ensures that the algorithm always adapts to the current transmission environment and maintains the optimal allocation strategy. The high reliability requirements of the hard-wired redundancy mechanism prompt the intelligent allocation algorithm to pay more attention to reliability indicators when allocating bandwidth, such as prioritizing bandwidth to signals that use redundant transmission, thereby improving the reliability level of the entire system. Reliability indicators include prioritizing bandwidth to signals that use redundant transmission (such as speed and key phase); avoiding the transmission of non-critical data (such as historical data queries) on hard-wired channels; and automatically triggering the data compression algorithm to reduce the transmission volume when the bandwidth utilization of the hard-wired channel exceeds 80%. The algorithm memorizes these optimization strategies through the Q-value table. When the same working conditions reappear, the optimal strategy can be directly called to shorten the decision-making time.

[0044] The intelligent allocation algorithm layer uses a dynamic bus allocation algorithm based on reinforcement learning. It incorporates the Q-Learning algorithm to construct a dynamic allocation model. Its state space and action space are designed to strictly map to the bus board hardware parameters. The state variables in the 128-dimensional state space are composed of address bus (IPB_adr1-4, corresponding to pins B4-B7) and power supply channels (+24V_1-3, corresponding to pins C31-C32). For example, IPB_adr = 0001 corresponds to the address code of the vibration monitoring module, IPB_adr = 0010 corresponds to the speed monitoring module, and +24V_1 = 101 indicates that both +24V_1 and +24V_3 are enabled. Each dimension of the state space directly corresponds to a physical pin on the bus board, ensuring real-time synchronization between the algorithm state and the hardware state. The action space (36 dimensions) includes three policy combinations: bandwidth allocation ratio, priority setting, and transmission path selection. Bandwidth allocation is divided into six levels (10%-60%) at 10% granularity. For example, 50% bandwidth corresponds to data transmission priority on pins A1-A10. Bandwidth control is achieved through PWM signals on pins CS1-CS4. Priority levels are divided into three levels: high (protection signal), medium (status monitoring), and low (diagnostic data). High priority corresponds to interrupt request signals on pins Status 1-Status 8. The transmission path includes CH1_485A or CH2_485B (corresponding to pins A2 / C2 and C4 / A4), switched via the relay module (pins REL1-REL3). During action execution, the algorithm must ensure compatibility between bandwidth allocation and transmission path to avoid logical conflicts. The algorithm interacts with the hardware through the following bus board pins: input pins include IPB_adr1-4 (address), +24V_1-3 (power status), and status 1-status 8 (channel status); output pins include CS1-CS4 (bandwidth control), REL1-REL3 (path switching), and work 1-4 (operating condition indication). The interface design follows the TTL level standard to ensure reliable signal transmission.

[0045] The comprehensive reward function is defined as:

[0046] ;

[0047] in: is the bit error rate bonus, , when the bit error rate When the threshold is 0.1%, 10 points will be awarded for every 0.01% decrease; is the transmission delay reward term, ,Delay 4 points will be awarded for every 1ms reduction (meeting the delay requirement of the turbine protection system ≤ 5ms); is the bus utilization bonus, ,Utilization Linear rewards are given between 60% and 80%, and 5 points are deducted for every 10% deviation outside the range to balance the bus load.

[0048] Based on the principle of security first, the bit error rate (0.4) with delay The sum of the coefficients (0.4) accounts for 80%, reflecting the core requirements of the TSI system for "data accuracy" and "real-time response". For example, when the 485 bus bit error rate exceeds the standard ( =0.15%), =-50, even if the utilization rate reaches the target ( =70%), the comprehensive reward is still negative, forcing the algorithm to adjust its strategy. Through bus board hardware test data fitting: In the 300MW unit TSI system, different coefficient combinations were set for 1000 iterations. When the coefficients of bit error rate, transmission delay, and bus utilization were set to 0.4, 0.4, and 0.2 respectively, the bus efficiency increased by 22%, and the bit error rate was less than 0.05% and the delay was less than 4ms under 95% of the working conditions. Low weight Avoid excessive pursuit of utilization and neglect of reliability by the algorithm. For example, in the case of turbine tripping, even if the bus utilization is only 50%, the high-weight / Priority remains given to protecting signal transmission.

[0049] For example, when the turbine load is increased to 70%, the collected data is IPB_adr=0101 (vibration module address, from pins B5-B8), +24V_2=1 (485 communication bus power supply, from pin C32). Real-time monitoring shows that the amount of vibration signal data has increased by 3 times, and the 485 bus bit error rate has increased to 0.08% (R401-R404 resistor monitoring end). When selecting an action, the bandwidth is increased from 30% to 40%, the priority is set to high, the path is switched to CH2_485B, and the relay REL2 is driven to attract through the CS3 pin (R503 resistor), switching to the backup 485 channel. After adjustment, the bit error rate is reduced to 0.04% ( =60), the delay dropped from 6ms to 4.5ms ( =22), utilization rate 75% ( =22.5). Comprehensive rewards =0.4×60+0.4×22+0.2×22.5=38.3. After the Q value is updated, the strategy priority under this working condition increases by 20%.

[0050] The specific operation process of the dynamic allocation model includes the following steps: First, state perception is performed. The algorithm reads the current hardware status through pins IPB_adr1-4 and +24V_1-3. For example, IPB_adr = 0101 (corresponding to pins B5-B8) indicates that the vibration module data is currently being processed, and +24V_2 = 1 (corresponding to pin C32) indicates that the 485 communication bus power supply is normal. The state reading cycle is 1ms to ensure real-time perception of hardware changes. Then, dynamic decision-making is performed. The Q value table is consulted to select an action, considering the exploration-exploitation balance ( - Greedy strategy, = 0.1), with a 90% probability of selecting the action with the highest Q value (exploitation) and a 10% probability of randomly selecting an action (exploration) to discover a better strategy. When executing an action, bandwidth allocation is controlled via pins CS1-CS4, and the transmission path is switched via pins REL1-REL3. Reward calculation is performed. Bit error rate e and delay d are obtained via pins State 1-State 8, and utilization u is calculated using the current monitoring resistor. For example, when e = 0.04%, =100×(0.1%-0.04%) / 0.1%=60, when d=4.5ms, =20×(5ms-4.5ms) / 5ms=2, when u=75%, =30×(75%-60%) / 20%=22.5, the total reward R=0.4×60+0.4×2+0.2×22.5=33.3. Then update the Q value. Update the Q value according to the Q-Learning formula. The formula is , where the learning rate , discount factor For example, the original Q value = 20, the reward R = 33.3, and the maximum future reward = 25, and the new Q value = 20 + 0.3 × (33.3 + 0.9 × 25 - 20) = 20 + 0.3 × (33.3 + 22.5 - 20) = 20 + 0.3 × 35.8 = 20 + 10.74 = 30.74. This update increases the priority of the corresponding state-action pair in the Q value table, making the algorithm more likely to select this action under the same subsequent working conditions. Finally, policy iterative optimization is performed. After every 100 iterations, the algorithm performs policy aggregation, clustering similar actions in the same state in the Q value table. The top three policies with the highest Q values ​​are retained, and policies with Q values ​​below 20% of the average are eliminated to reduce invalid decisions. The optimized policies are then written to the Flash memory via the SPI interface (pins C1-C2) for power-off retention.

[0051] For example, under typical operating conditions with a 600MW steam turbine load increased to 70%, the dynamic bus allocation algorithm executes as follows: the address bus status is IPB_adr = 0101 (corresponding to pins B5-B8, pointing to the vibration monitoring module), the power channel status is +24V_2 = 1 (the 485 communication bus is functioning normally, and pin C32 outputs a high level). Real-time monitoring data shows a threefold increase in vibration signal volume compared to full load, the 485 bus bit error rate rises to 0.08% (feedback from the monitoring terminals of the R401-R404 resistors), and the transmission delay is 6ms. The algorithm queries the Q value table and finds that the "40% bandwidth + high priority + CH2_485B path" has the highest Q value (Q = 28.5) in the current state. Pin CS3 (the R503 resistor divider network) outputs a high level, driving relay REL2 to energize, switching the transmission path to the backup 485 channel CH2_485B and increasing the bandwidth of this channel from 30% to 40%. The relay switching time is 0.3ms (Omron G6K-2F-Y12V relay characteristics). After the path is switched, the hardware status is that the CH2_485B pin (C4 pin) is activated, and the bit error rate monitoring value of the state 7 pin (connected in series with the tri-state 7 resistor) begins to decrease. The performance index after adjustment is the bit error rate e=0.04% ( =100×(0.1%-0.04%) / 0.1%=60), transmission delay d=4.5ms ( =20×(5ms-4.5ms) / 5ms=2), bus utilization u=75% ( =30×(75%-60%) / 20%=22.5), the total reward R=0.4×60+0.4×2+0.2×22.5=33.3, the original Q(s,a)=28.5, the new Q value=28.5+0.3×(33.3+0.9× -28.5), assuming =30, the new Q = 30.8, and the priority of this action is increased by 20%. After 100 iterations of the algorithm under similar operating conditions, it generated an optimized policy: "When IPB_adr = 0101 and +24V_2 = 1, prioritize 40% of the bandwidth to the CH2_485B path." This policy was written into the configuration registers of CS1-CS4, solidifying the policy at the hardware level. Subsequently, under similar operating conditions, the decision time was reduced from 1ms to 0.3ms.

[0052] When the redundancy mechanism switches to the hardwired channel, the algorithm automatically executes and the status is updated, IPB_adr = 0001 (hardwired address), +24V_3 = 1 (relay power on, C31 pin). Increase the hardwired channel bandwidth from 30% to 50%, / The weights are temporarily increased to 0.5 / 0.5 to ensure error-free transmission. If 10 consecutive switches trigger a high reward, the algorithm generates a new rule: "When +24V_3 = 1, prioritize the CH2_485B path." This rule is written into the configuration registers of CS1-CS4. This two-way feedback mechanism between hardware and algorithms enables continuous system optimization during operation, ultimately achieving the performance goals of a 22% increase in bus efficiency and a 15% reduction in critical data latency.

[0053] The embodiments disclosed in the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. The embodiments disclosed in the present invention include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part, and / or installed from a removable medium. When the computer program is executed by the central processing unit (CPU), the above-mentioned functions defined in the method of the present application are executed. It should be noted that the computer-readable medium mentioned above in the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, but not limited to, a system, device or device of an electrical, magnetic, optical, electromagnetic, infrared segment or semiconductor, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wire segments, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take a variety of forms, including, but not limited to, an electromagnetic signal, an optical signal, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to wireless, electrical wire, optical fiber cable, RF, etc., or any suitable combination thereof.

[0054] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or portion of code that contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two boxes shown in succession can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified functions or operations, or can be implemented using a combination of dedicated hardware and computer instructions.

[0055] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are only examples and do not limit the present invention. The objectives of the present invention have been fully and effectively achieved. The functional and structural principles of the present invention have been demonstrated and explained in the embodiments. Without departing from the principles, the implementation methods of the present invention may be subject to any deformation or modification.

Claims

1. A method for arranging an OC bus of a TSI system, characterized in that: The method comprises: In the physical layout layer, the OC bus is divided into three independent main channels: data acquisition bus, communication bus, and address and working condition bus. Based on the signal characteristics of the three independent channels, a grounding design with separate analog and digital grounds and a resistor buffer circuit are set up to form a multi-layer anti-interference system. Different buses are arranged in layers, and the analog and digital grounds are connected at a single point. The hardware redundancy layer uses independent channels reserved in the physical layout to build dual-phase hard-wired redundant channels. Relays and control nodes are combined to form a fault switching mechanism. The redundant channels are physically isolated from the primary channels. When a bus fails, the hardware redundancy layer uses the redundancy mechanism to switch channels. In the intelligent algorithm layer, the state space is constructed using the address bus and power channel states in the physical layout layer. Combined with the fault feedback signals from the hardware redundancy layer, the algorithm decision is iteratively optimized through a dynamic allocation model. The optimized algorithm decision is then applied to the hardware pins in real time. The redundancy mechanism includes the following: During the normal operation phase, key signals are transmitted via the communication bus. The data format is a Modbus RTU frame containing a 16-bit CRC checksum. The relay is in the normally closed state, the dual-phase hard-wired redundant channel is disconnected from the signal source, and the control node outputs a low level, which does not trigger the relay. During this phase, the dual-phase hard-wired redundant channel outputs a high level, and the system displays the working status of each channel through the status indicator light. During the fault detection phase, the status bus monitors the working status of the communication bus in real time. The monitoring parameters include the bit error rate and communication interruption time. When it is detected that the communication bus bit error rate exceeds 0.5% or five consecutive data packets are lost, the status bus sends a high-level signal to the control node. The resistor network in the control node divides and filters the input level, and the fault detection algorithm calculates the bit error rate. During the redundancy switching phase, after the control node receives a high-level signal, it drives the relay to switch to the normally open state. The switching time is less than 0.5ms, and the critical signal is immediately switched to the 4-pin dual-phase hard-wired channel for transmission. The signal type changes from a differential digital signal to a single-ended pulse signal. The system sends a bus fault alarm signal to the monitoring interface. The alarm information includes the fault type and the switching timestamp. During the switching process, the signal transmission delay is reduced from 8ms to 0.5ms of the hard-wired channel. The intelligent algorithm layer constructs a 128-dimensional state space based on the address bus and power channel status in the physical layout layer. Combined with the fault feedback signal of the hardware redundancy layer, it adopts a dynamic allocation model based on the Q-Learning algorithm to perform bandwidth allocation, priority setting, and transmission path selection to form an optimized algorithm decision. The optimized algorithm decision implements bandwidth control through PWM signals and switching through relay modules. When the action is executed, the algorithm must ensure the compatibility of bandwidth allocation and transmission path.

2. The method for arranging the OC bus of a TSI system according to claim 1, characterized in that: The main channel division method is as follows: The data acquisition bus consists of 26 pins and is directly connected to the vibration monitoring module and the speed monitoring module. The wiring distance between the data acquisition bus and other main channels is greater than 50 mils. The communication bus is designed in accordance with the RS-485 communication standard and uses differential signal transmission. In terms of bus topology, it adopts a trunk-branch structure, and the length of each node branch is ≤30cm. The address and working condition bus includes an 8-pin address bus and an 8-pin working condition bus. The two types of buses constitute an independent control link. The wiring spacing between the address bus, the working condition bus and the data acquisition bus is greater than 20mil. The address and working condition bus and the data acquisition bus are isolated by the power layer.

3. The method for arranging the OC bus of a TSI system according to claim 2, characterized in that: The specific construction process of the multi-layer anti-interference system is as follows: The data acquisition bus transmits analog signals, the analog circuit is connected to the analog ground, and the analog ground plane is covered with complete copper foil; The communication bus and the address and working condition bus transmit digital signals, the digital circuit is connected to the digital ground, and the digital ground plane is divided into independent areas; The analog ground and digital ground are connected at a single point through a 0Ω resistor. In the data acquisition bus, a resistor buffer circuit is constructed using a 3K resistor, which is connected in series with the signal transmission path and placed close to the signal source. When the signal frequency exceeds 1MHz, the 3K resistor adjusts the equivalent impedance to 110-130Ω.

4. The method for arranging the OC bus of a TSI system according to claim 3, characterized in that: The specific contents of the hardware redundancy layer are as follows: Relying on the independent channels reserved in the physical layout layer, a dual-phase hard-wired redundant channel is constructed. The redundant channel is linked to the control node through relays to form a fault switching mechanism. The pin spacing between the redundant channel and the main channel is ≥20mil, an independent ground path is set, and the wiring length is less than 5cm; a resistor buffer circuit with the same standard as the main channel is used.

5. The method for arranging the OC bus of a TSI system according to claim 4, characterized in that: The specific operation process of the dynamic allocation model is as follows: Read the current hardware status; query the Q value table to select an action, consider the exploration-exploitation balance, and find the best strategy; obtain the bit error rate and latency, and calculate the utilization rate through the current monitoring resistor; The Q-Learning formula updates the Q value to increase the priority of the corresponding state-action pair in the Q value table. The algorithm then selects this action under the same working conditions. After every 100 iterations, strategy aggregation is performed to cluster similar actions under the same state in the Q value table. The top three strategies with the highest Q values ​​are retained, and strategies with Q values ​​20% below the average level are eliminated. The optimized strategies are then written to the Flash memory via the SPI interface.

6. A TSI system OC bus layout system, characterized in that: The system is used to execute the TSI system OC bus arrangement method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method for arranging an OC bus of a TSI system according to any one of claims 1 to 5.

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