GOA driving circuit and display device

Abstract

A GOA drive circuit and a display device belong to the technical field of display, and invert the voltage of a pull-up control node through an inverter module to output a pull-down control signal to a pull-down control node; the pull-down adjustment module adjusts the pull-down control signal according to the pull-down adjustment signal; wherein the starting time of the adjusted pull-down control signal is advanced; the pull-down maintaining module maintains the pull-up control node and the output end of the GOA driving circuit at low level according to the adjusted pull-down control signal; no pulling exists between the potential of the grid electrode of the transistor in the pull-down maintaining module and the potential of the pull-up control node, the possibility that large current or the potential of the pull-up control node cannot rise is reduced, and then the possibility that GOA fails is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a GOA driving circuit and a display device. Background Art

[0002] The gate driver on array (GOA) circuit is integrated into the display panel's gate driver circuit on a glass substrate, forming a scanning drive for the display panel. Compared to traditional drive technologies using gate chips, GOA driving technology can significantly reduce manufacturing costs and reduce the left and right bezels of the display panel. Each level of GOA driver module outputs a scan signal for each row, which is used to drive the pixel cells in a row. Multiple levels of GOA driver modules are cascaded to form a GOA driver circuit, achieving progressive scanning of the display panel.

[0003] The output signal of the inverter module in the related GOA driving circuit is a signal opposite to Qn, which causes a pull between the gate potential Kn / Pn of the transistor in the pull-down holding module and the potential Qn of the pull-up control node. Therefore, a large current may occur or the potential Qn of the pull-up control node may not be able to rise, resulting in GOA failure.

[0004] Therefore, there is potential pull in the related GOA driving circuit, which causes GOA failure. Summary of the Invention

[0005] The purpose of the present application is to provide a GOA driving circuit and a display device, aiming to solve the problem that the related GOA driving circuit has potential pulling, thereby causing GOA failure.

[0006] The embodiment of the present application provides a GOA driving circuit, including a pull-up module, an input module, a pull-down module, a pull-down maintaining module, an inverter module and a pull-down adjustment module;

[0007] The input module is connected to the first input signal terminal and the pull-up control node;

[0008] The pull-up module is connected to the clock signal end, the pull-up control node and the output end of the GOA driving circuit;

[0009] The inverter module is connected to the pull-up control node and the pull-down control node, and is used to invert the voltage of the pull-up control node to output a pull-down control signal to the pull-down control node;

[0010] The pull-down adjustment module is connected to the pull-down control node and the pull-down adjustment signal terminal, and is used to adjust the pull-down control signal according to the pull-down adjustment signal; wherein the start time of the adjusted pull-down control signal is advanced;

[0011] The pull-down maintaining module is connected to the pull-down control node, the pull-up control node and the output end of the GOA driving circuit, and is used to maintain the pull-up control node and the output end of the GOA driving circuit at a low level according to the adjusted pull-down control signal;

[0012] The pull-down module is connected to the pull-up control node and the second input signal terminal.

[0013] An embodiment of the present invention further provides a display device, which includes the above-mentioned GOA driving circuit.

[0014] Compared with the prior art, the embodiments of the present invention have the following advantages: since the voltage of the pull-up control node is inverted by the inverter module to output the pull-down control signal to the pull-down control node; the pull-down adjustment module adjusts the pull-down control signal according to the pull-down adjustment signal; wherein the start time of the adjusted pull-down control signal is advanced; the pull-down maintaining module maintains the output end of the pull-up control node and the GOA driving circuit at a low level according to the adjusted pull-down control signal; there is no pull between the gate potential of the transistor in the pull-down maintaining module and the potential of the pull-up control node, thereby reducing the possibility of large current or the potential Qn of the pull-up control node failing to increase, thereby reducing the possibility of GOA failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical inventions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 A schematic structural diagram of a GOA driving circuit provided in one embodiment of the present application;

[0017] Figure 2 A waveform diagram of various signals of the GOA driving circuit provided in one embodiment of the present application;

[0018] Figure 3 Another structural diagram of a GOA driving circuit provided in one embodiment of the present application;

[0019] Figure 4 A partial exemplary circuit schematic diagram of a GOA driving circuit provided in one embodiment of the present application;

[0020] Figure 5 Another partial exemplary circuit schematic diagram of a GOA driving circuit provided in one embodiment of the present application;

[0021] Figure 6Another waveform diagram of various signals of the GOA driving circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0023] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0024] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0026] Figure 1 The structure diagram of the GOA driving circuit provided by the preferred embodiment of the present application is shown. For ease of explanation, only the part related to this embodiment is shown, which is described in detail as follows:

[0027] The GOA driving circuit includes a pull-up module 10 , an input module 20 , a pull-down module 30 , a pull-down maintaining module 40 , an inverter module 50 and a pull-down adjusting module 60 .

[0028] The input module 20 is connected to the first input signal terminal and the pull-up control node.

[0029] The pull-up module 10 is connected to the clock signal terminal, the pull-up control node and the output terminal of the GOA driving circuit.

[0030] The inverter module 50 is connected to the pull-up control node and the pull-down control node, and is used to invert the voltage of the pull-up control node to output a pull-down control signal to the pull-down control node.

[0031] The pull-down adjustment module 60 is connected to the pull-down control node and the pull-down adjustment signal terminal, and is used to adjust the pull-down control signal according to the pull-down adjustment signal; wherein the start time of the adjusted pull-down control signal is advanced.

[0032] The pull-down maintaining module 40 is connected to the pull-down control node, the pull-up control node and the output end of the GOA driving circuit, and is used to maintain the pull-up control node and the output end of the GOA driving circuit at a low level according to the adjusted pull-down control signal.

[0033] The pull-down module 30 is connected to the pull-up control node and the second input signal terminal.

[0034] In one embodiment, the input module 20 is used to access a first input signal and transmit the first input signal to a pull-up control node; the pull-up module 10 is used to access a clock signal and, in response to a high-level clock signal and a high-level signal of the pull-up control node, output a high-level output signal from the output end of the GOA driving circuit; the pull-down module 30 is used to access a second input signal and, in response to a high-level second input signal, pull the pull-up control node down to a low level.

[0035] The pull-down adjustment signal is the output signal Gn-m of the GOA driving circuit of the upper m rows, the stage transmission signal STn-m of the GOA driving circuit of the upper m rows, or the signal Qn-m of the pull-up control node of the GOA driving circuit of the upper m rows; the first input signal is the output signal of the GOA driving circuit of the upper k rows; the second input signal is the output signal of the GOA driving circuit of the lower k rows, where k is a positive integer and m is a positive integer less than 2k.

[0036] It should be noted that, in one embodiment, m is equal to k.

[0037] It should be noted that the pull-up module 10 in the present application also outputs a level transmission signal STn that is the same as the output signal Gn. The output signals of the GOA driving circuits at each level input in the present application can be replaced by the level transmission signals of the GOA driving circuits at each level; for example, the pull-down adjustment signal ADJ can be replaced by the output signal Gn-m of the GOA driving circuit of the upper k rows with the level transmission signal STn-m of the GOA driving circuit of the upper k rows.

[0038] It is worth emphasizing that the pull-down adjustment signal ADJ can also be replaced by the output signal Qn-m of the GOA driving circuit of the upper k rows and the signal Qn-m of the pull-up control node of the GOA driving circuit of the upper k rows.

[0039] The pull-down adjustment signal and the first input signal can be set to be the same signal, thereby simplifying the circuit of the display device.

[0040] Figure 2 A waveform diagram of each signal of the GOA driving circuit is shown below. Figure 2 right Figure 1 The principle of the GOA driving circuit shown is further explained:

[0041] In the stage before A, the pull-down adjustment signal ADJ, the reset signal RESET, the clock signal CLK, the first input signal Gn-k and the second input signal Gn+k are all at low levels; the pull-down module 30 is closed according to the low-level second input signal Gn+k, the input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn, the pull-up control node Qn is at a low level, the inverter module 50 inverts the low-level signal of the pull-up control node Qn, and outputs the inverted signal (high level) to the pull-down control node Kn. At the same time, the reset module 70 is closed according to the low-level reset control signal, the pull-down adjustment module 60 is closed according to the low-level pull-down adjustment signal ADJ, the pull-down control node Kn is at a high level, so that the pull-down maintaining module 4040 is in the open state, and maintains the pull-up control node Qn and the output end of the GOA driving circuit at a low level according to the high-level signal, and the output end of the GOA driving circuit outputs a low-level output signal Gn.

[0042] During the A to B phase, the pull-down adjustment signal ADJ is at a high level, and the reset signal RESET, the clock signal CLK, the first input signal Gn-k, and the second input signal Gn+k are all at a low level. The pull-down module 30 is turned off according to the low-level second input signal Gn+k, and the input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn. The pull-up control node Qn is at a low level. The inverter module 50 inverts the low-level signal of the pull-up control node Qn and outputs the inverted signal (high level) to the pull-down control node Kn. At the same time, the reset module 70 is turned off according to the low-level reset control signal, and the pull-down adjustment module 60 is turned on according to the low-level pull-down adjustment signal ADJ and advances the start time of the pull-down control signal. The pull-down control node Kn is at a low level, so that the pull-down maintaining module 4040 is in a closed state and maintains the pull-up control node Qn and the output end of the GOA driving circuit in a floating state according to the low-level signal. The output end of the GOA driving circuit outputs a low-level output signal Gn.

[0043] In phases B to C, the first input signal Gn-k is at a high level, the reset signal RESET, the first clock signal CLK, and the second input signal Gn+k are all at a low level, and the pull-down adjustment signal ADJ jumps from a high level to a low level; the pull-down module 3030 is closed according to the low-level second input signal Gn+k, and the input module 2020 transmits the high-level first input signal Gn-k to the pull-up control node Qn. Since the pull-up control node Qn is in a floating state, it quickly rises to a high level (first voltage). The inverter module 5050 inverts the high-level signal of the pull-up control node Qn. And the inverted signal (low level) is output to the pull-down control node Kn. At the same time, the reset module 70 is turned off according to the low-level reset control signal, and the pull-down adjustment module 60 is turned off according to the pull-down adjustment signal ADJ. The pull-down control node Kn is low level, so that the pull-down maintenance module 4040 is in the off state. The pull-up module 1010 is connected to the low-level clock signal CLK, and in response to the high-level signal of the pull-up control node Qn, the low-level clock signal CLK is transmitted to the output end of the GOA drive circuit, and the output end of the GOA drive circuit outputs a low-level output signal Gn.

[0044] In the C to D phase, the clock signal CLK is at a high level, the pull-down adjustment signal ADJ, the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all at a low level; the pull-down module 30 is turned off according to the low-level second input signal Gn+k, the input module 20 is turned off according to the low-level first input signal Gn-k, the pull-up control node Qn maintains a high level, the inverter module 5050 inverts the high-level signal of the pull-up control node Qn, and outputs the inverted signal (low level) to the pull-down control node Kn. At the same time, the reset module 70 is turned off according to the low-level reset control signal. The pull-down adjustment module 60 is turned off according to the low-level pull-down adjustment signal ADJ, and the pull-down control node Kn is at a low level, so that the pull-down maintaining module 4040 is in a closed state. The pull-up module 1010 is connected to the high-level clock signal CLK, and in response to the high-level signal of the pull-up control node Qn, the high-level clock signal CLK is transmitted to the output end of the GOA driving circuit. It is worth noting that due to the bootstrap effect of the capacitor in the pull-up module 10, the high level maintained by the pull-up control node Qn is a second voltage, wherein the second voltage is greater than the first voltage, and the output end of the GOA driving circuit outputs a high-level output signal Gn.

[0045] In the D to E phase, the pull-down adjustment signal ADJ, the second input signal Gn+k, the reset signal RESET, the clock signal CLK and the first input signal Gn-k are all at low levels; the pull-down module 30 is closed according to the low-level second input signal Gn+k, the input module 2020 is closed according to the low-level first input signal Gn-k, the pull-up control node Qn maintains a high level, the inverter module 5050 inverts the high-level signal of the pull-up control node Qn, and outputs the inverted signal (low level) to the pull-down control node Kn. At the same time, the reset module 70 is closed according to the low-level reset control The control signal is turned off, the pull-down adjustment module 60 is turned off according to the low-level pull-down adjustment signal ADJ, the pull-down control node Kn is at a low level, so that the pull-down maintaining module 4040 is in a closed state, and the pull-up module 1010 is connected to the low-level clock signal CLK, and in response to the high-level signal of the pull-up control node Qn, the low-level clock signal CLK is transmitted to the output end of the GOA driving circuit. It is worth noting that since the capacitor in the pull-up module 10 is no longer bootstrapped, the high level maintained by the pull-up control node Qn is the first voltage, and the output end of the GOA driving circuit outputs a low-level output signal Gn.

[0046] In phases E to F, the second input signal Gn+k is at a high level, and the pull-down adjustment signal ADJ, the reset signal RESET, the clock signal CLK, and the first input signal Gn-k are all at a low level. The input module 20 transmits the low-level first input signal Gn-k to the pull-up control node Qn. The pull-down module 30 receives the high-level second input signal Gn+k and pulls the pull-up control node Qn down to a low level in response to the high-level second input signal Gn+k. The inverter module 50 inverts the low-level signal of the pull-up control node Qn and outputs the inverted signal (high level) to the pull-down control node Kn. At the same time, the reset module 70 is turned off according to the low-level reset control signal, and the pull-down adjustment module 60 is turned off according to the low-level pull-down adjustment signal ADJ. The pull-down control node Kn is at a high level, so that the pull-down maintaining module 4040 is in an on state and maintains the pull-up control node Qn and the output end of the GOA driving circuit at a low level according to the high-level signal. The output end of the GOA driving circuit outputs the low-level output signal Gn.

[0047] In the F to G phase, the operating principle of the GOA driving circuit is the same as that in the phase before A, and will not be repeated here.

[0048] In the G to H phase, the reset signal RESET is at a high level, the pull-down adjustment signal ADJ, the clock signal CLK, the first input signal Gn-k and the second input signal Gn+k are at a low level; the pull-down module 30 is closed according to the low-level second input signal Gn+k, the input module 2020 transmits the low-level first input signal Gn-k to the pull-up control node Qn, the pull-up control node Qn is at a low level, the inverter module 5050 inverts the low-level signal of the pull-up control node Qn, and outputs the inverted signal (high level) to the pull-down control node Kn, and at the same time The reset module 70 is turned on according to the high-level reset control signal, the pull-down adjustment module 60 is turned off according to the low-level pull-down adjustment signal ADJ, the pull-down control node Kn is at a high level, so that the pull-down maintaining module 4040 is in the turned-on state, and the pull-up control node Qn and the output end of the GOA driving circuit are both maintained at a low level according to the high-level signal, and the output end of the GOA driving circuit outputs a low-level output signal Gn; the reset module 70 is in the turned-on state, the pull-up control node Qn is effectively reset, and the output end of the GOA driving circuit outputs a low-level output signal Gn.

[0049] like Figure 3 As shown, the GOA driving circuit further includes a reset module 70 .

[0050] The reset module 70 is connected to the reset signal terminal and the pull-up control node, and is used to receive the reset signal and pull down the pull-down control node to a low level according to the reset signal.

[0051] It should be noted that the reset signal is located before the output signal Gn-k of the GOA driving circuit of the upper k rows, and is located after the output signal Gn+k of the GOA driving circuit of the lower k rows.

[0052] The reset signal RESET is set between the output signal Gn-k of the GOA driving circuit of the upper k rows and the output signal Gn+k of the GOA driving circuit of the lower k rows, so that the GOA driving circuit is reset during the scanning interval, thereby releasing the excess charge in the GOA driving circuit, allowing the GOA driving circuit to enter a certain state where it can operate stably, thereby improving the stability and reliability of the GOA driving circuit.

[0053] like Figure 4 As shown, the inverter module 50 includes a first inverter unit 51 and a second inverter unit 52, the pull-down maintaining module 40 includes a first pull-down maintaining unit 41 and a second pull-down maintaining unit 42, and the pull-down adjusting module 60 includes a first pull-down adjusting unit 61 and a second pull-down adjusting unit 62;

[0054] The first inverter unit 51 and the second inverter unit 52 are used to alternately output a first pull-down control signal and a second pull-down control signal respectively;

[0055] The first pull-down adjustment unit 61 and the second pull-down adjustment unit 62 are used to adjust the first pull-down control signal and the second pull-down control signal respectively; wherein the start time of the adjusted first pull-down control signal and the start time of the adjusted second pull-down control signal are both advanced;

[0056] The first pull-down maintaining unit 41 and the second pull-down maintaining unit 42 are configured to alternately operate with the adjusted first pull-down control signal and the adjusted second pull-down control signal, respectively, to pull down both the pull-up control node and the output end of the GOA driving circuit to a low level.

[0057] By providing two inverter units, two pull-down maintaining units and two pull-down adjusting units, and making the two identical circuit units work alternately, the possibility of the device being turned on for a long time is reduced, thereby reducing the possibility of device degradation and extending the life of the device.

[0058] Figure 4 FIG. 4 shows a partial exemplary circuit structure of a GOA driving circuit provided by an embodiment of the present invention. Figure 5 A partial exemplary circuit structure of a GOA driving circuit provided by an embodiment of the present invention is shown. For ease of illustration, only the portion related to the embodiment of the present invention is shown, which is described in detail as follows:

[0059] like Figure 4 and Figure 5 As shown, the input module 20 includes a first transistor T1 .

[0060] The drain of the first transistor T1 and the gate of the first transistor T1 are connected to the first input signal terminal; the source of the first transistor T1 is connected to the pull-up control node.

[0061] like Figure 4 and Figure 5 As shown, the pull-up module 10 includes a second transistor T2 and a bootstrap capacitor.

[0062] The gate of the second transistor T2 and the first end of the bootstrap capacitor are commonly connected to the pull-up control node; the source of the second transistor T2 and the second end of the bootstrap capacitor are commonly connected to the output end of the GOA driving circuit; the drain of the second transistor T2 is connected to the clock signal end to receive the clock signal.

[0063] like Figure 5 As shown, the pull-down maintaining module 40 includes a third transistor T3 and a fourth transistor T4.

[0064] The drain of the third transistor T3 is connected to the output end of the GOA driving circuit, the drain of the fourth transistor T4 is connected to the pull-up control node, the gate of the third transistor T3 and the gate of the fourth transistor T4 are commonly connected to the pull-down control node, the source of the third transistor T3 is connected to the second low-voltage source, and the source of the fourth transistor T4 is connected to the first low-voltage source, wherein the output voltage of the first low-voltage source is less than the output voltage of the second low-voltage source.

[0065] like Figure 5 As shown, the inverter module 50 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9.

[0066] The drain of the fifth transistor T5, the gate of the fifth transistor T5, and the drain of the seventh transistor T7 are commonly connected to a high voltage source; the gate of the sixth transistor T6 and the gate of the eighth transistor T8 are commonly connected to a pull-up control node; the source of the ninth transistor T9, the gate of the sixth transistor T6, and the gate of the eighth transistor T8 are commonly connected to a first low voltage source; the source of the fifth transistor T5 is connected to the drain of the ninth transistor T9, the drain of the sixth transistor T6, and the gate of the seventh transistor T7; the source of the seventh transistor T7 and the drain of the eighth transistor T8 are commonly connected to a pull-down control node; and the gate of the ninth transistor T9 serves as a pull-down adjustment signal input terminal of the inverter module 50 to receive the pull-down adjustment signal.

[0067] like Figure 5 As shown, the pull-down adjustment module 60 includes a tenth transistor T10.

[0068] The drain of the tenth transistor T10 is connected to the pull-down control node; the gate of the tenth transistor T10 serves as the pull-down adjustment signal input terminal of the pull-down adjustment module 60 to receive the pull-down adjustment signal; the source of the tenth transistor T10 is connected to the first low voltage source.

[0069] like Figure 4 As shown, the first pull-down sustaining unit 41 includes an eleventh transistor T11 and a twelfth transistor T12.

[0070] The drain of the eleventh transistor T11 is connected to the output terminal of the GOA driving circuit, the drain of the twelfth transistor T12 is connected to the pull-up control node, the gate of the eleventh transistor T11 and the gate of the twelfth transistor T12 are commonly connected to the first pull-down control node, the source of the eleventh transistor T11 is connected to the second low voltage source, and the source of the twelfth transistor T12 is connected to the first low voltage source, wherein the output voltage of the first low voltage source is less than the output voltage of the second low voltage source;

[0071] The second pull-down sustaining unit 42 includes a thirteenth transistor T13 and a fourteenth transistor T14 .

[0072] The drain of the thirteenth transistor T13 is connected to the output end of the GOA driving circuit, the drain of the fourteenth transistor T14 is connected to the pull-up control node, the gate of the thirteenth transistor T13 and the gate of the fourteenth transistor T14 are commonly connected to the second pull-down control node, the source of the thirteenth transistor T13 is connected to the first low-voltage source, and the source of the fourteenth transistor T14 is connected to the second low-voltage source.

[0073] like Figure 4 As shown, the first inverter unit 51 includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19.

[0074] The drain of the fifteenth transistor T15, the gate of the fifteenth transistor T15, and the drain of the seventeenth transistor T17 are connected and together constitute a low-frequency clock signal input terminal of the first inverter unit 51 to receive the first low-frequency clock signal; the gate of the sixteenth transistor T16 and the gate of the eighteenth transistor T18 are commonly connected to the pull-up control node; the source of the nineteenth transistor T19, the gate of the sixteenth transistor T16, and the gate of the eighteenth transistor T18 are commonly connected to the first low voltage source; the source of the fifteenth transistor T15 is connected to the drain of the nineteenth transistor T19, the drain of the sixteenth transistor T16, and the gate of the seventeenth transistor T17; the source of the seventeenth transistor T17 and the drain of the eighteenth transistor T18 are commonly connected to the pull-down control node; the gate of the nineteenth transistor T19 serves as a pull-down adjustment signal input terminal of the first inverter unit 51 to receive the pull-down adjustment signal;

[0075] The second inverter unit 52 includes a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, and a twenty-fourth transistor T24.

[0076] The drain of the 20th transistor T20, the gate of the 20th transistor T20, and the drain of the 22nd transistor T22 are connected and together constitute a low-frequency clock signal input terminal of the second inverter unit 52 for receiving the second low-frequency clock signal; the gate of the 21st transistor T21 and the gate of the 23rd transistor T23 are commonly connected to the pull-up control node; the source of the 24th transistor T24, the gate of the 21st transistor T21, and the gate of the 23rd transistor T23 are commonly connected to the first low voltage source; the source of the 20th transistor T20 is connected to the drain of the 24th transistor T24, the drain of the 21st transistor T21, and the gate of the 22nd transistor T22; the source of the 22nd transistor T22 and the drain of the 23rd transistor T23 are commonly connected to the pull-down control node; the gate of the 24th transistor T24 serves as a pull-down adjustment signal input terminal of the second inverter unit 52 for receiving the pull-down adjustment signal;

[0077] The first low-frequency clock signal and the second low-frequency clock signal have opposite polarities.

[0078] like Figure 4 As shown, the first pull-down adjustment unit 61 includes a twenty-fifth transistor T25 .

[0079] The drain of the twenty-fifth transistor T25 is connected to the first pull-down control node; the gate of the twenty-fifth transistor T25 serves as the pull-down adjustment signal input terminal of the pull-down adjustment module 60 to receive the pull-down adjustment signal; the source of the twenty-fifth transistor T25 is connected to the first low voltage source.

[0080] The second pull-down adjustment unit 62 includes a twenty-sixth transistor T26; the drain of the twenty-sixth transistor T26 is connected to the second pull-down control node; the gate of the twenty-sixth transistor T26 serves as the pull-down adjustment signal input terminal of the pull-down adjustment module 60 to receive the pull-down adjustment signal; and the source of the twenty-sixth transistor T26 is connected to the first low voltage source.

[0081] like Figure 5 and Figure 6 As shown, the reset module 70 includes a twenty-seventh transistor T27;

[0082] The gate of the twenty-seventh transistor T27 constitutes the reset signal terminal of the reset module 70 to receive the reset signal; the source of the twenty-seventh transistor T27 is connected to the first low voltage source; and the drain of the twenty-seventh transistor T27 is connected to the pull-up control node.

[0083] like Figure 4 and Figure 5 As shown, the pull-down module 30 includes a twenty-eighth transistor T28 .

[0084] The drain of the twenty-eighth transistor T28 is connected to the pull-down control node; the drain of the twenty-eighth transistor T28 is connected to the first low voltage source; and the gate of the twenty-eighth transistor T28 is connected to the second input signal terminal to receive the second input signal.

[0085] It should be noted that the above transistors may all be NMOS transistors.

[0086] The following combination Figure 2 right Figure 5 The working principle shown is further explained:

[0087] In the stage before A, the pull-down adjustment signal ADJ, the reset signal RESET, the clock signal CLK, the first input signal Gn-k and the second input signal Gn+k are all at a low level; the twenty-eighth transistor T28 is turned off according to the low-level second input signal Gn+k, the gate of the fifth transistor T5 is connected to the high-level signal output by the high-voltage source VGH, the drain of the fifth transistor T5 transmits the high-level signal output by the high-voltage source VGH to the source of the fifth transistor T5, the gate of the first transistor T1 is connected to the low-level first input signal Gn-k, the first transistor T1 is turned off, and the pull-up control node Qn is at a low level, so the ninth transistor T9, the sixth transistor T6 and the eighth transistor T8 is turned off, the seventh transistor T7 is turned on and the seventh transistor T7 outputs the high-level signal output by the high voltage source VGH to the pull-down control node Kn. At the same time, the tenth transistor T10 is turned off according to the low-level pull-down adjustment signal ADJ, the gate of the twenty-ninth transistor T10 is connected to the low-level reset signal RESET, the twenty-ninth transistor T29 is turned off, and the pull-down control node Kn is at a high level, so that the third transistor T3 and the fourth transistor T4 are in the turned-on state, so that the pull-up control node Qn is connected to the first low voltage source VSSQ and the output end of the GOA driving circuit is connected to the second low voltage source VSSG, and the output end of the GOA driving circuit outputs a low-level output signal Gn.

[0088] In the A to B phase, the pull-down adjustment signal ADJ is at a high level, the reset signal RESET, the clock signal CLK, the first input signal Gn-k and the second input signal Gn+k are all at a low level; the twenty-eighth transistor T28 is turned off according to the low-level second input signal Gn+k, the gate of the fifth transistor T5 is connected to the high-level signal output by the high-voltage source VGH, the drain of the fifth transistor T5 transmits the high-level signal output by the high-voltage source VGH to the source of the fifth transistor T5, the gate of the first transistor T1 is connected to the low-level first input signal Gn-k, the first transistor T1 is turned off, and the pull-up control node Q n is at a low level, so the ninth transistor T9 is turned on, the sixth transistor T6 and the eighth transistor T8 are turned off, and the seventh transistor T7 is turned off. At the same time, the tenth transistor T10 is turned on according to the high-level pull-down adjustment signal ADJ to make the pull-down control node Kn a low level, and the gate of the twenty-ninth transistor T29 is connected to the low-level reset signal RESET, and the twenty-ninth transistor T29 is turned off, so that the third transistor T3 and the fourth transistor T4 are in a turned-off state, so that the pull-up control node Qn and the output end of the GOA driving circuit are in a floating state, and the output end of the GOA driving circuit outputs a low-level output signal Gn.

[0089] In phases B to C, the pull-down adjustment signal ADJ jumps from a high level to a low level, the first input signal Gn-k is at a high level, the reset signal RESET, the first clock signal CLK, and the second input signal Gn+k are all at a low level; the twenty-eighth transistor T28 is turned off according to the low-level second input signal Gn+k, the gate of the fifth transistor T5 is connected to the high-level signal output by the high-voltage source VGH, the drain of the fifth transistor T5 transmits the high-level signal output by the high-voltage source VGH to the source of the fifth transistor T5, the ninth transistor T9 changes from an on state to an off state, and the seventh transistor T7 changes from an off state to an on state; the gate of the first transistor T1 is connected to the high-level first input signal Gn-k, the drain of the first transistor T1 transmits the high-level first input signal Gn-k to the drain of the first transistor T1. The input signal Gn-k is transmitted to the source of the first transistor T1, the pull-up control node Qn is at a high level (first voltage) and the bootstrap capacitor C1 is charged, so the sixth transistor T6 and the eighth transistor T8 are turned on to pull the pull-down control node Kn to a low level, and the tenth transistor T10 is changed from on to off. At the same time, the gate of the twenty-ninth transistor T29 is connected to the low-level reset signal RESET, and the twenty-ninth transistor T29 is turned off, so that the third transistor T3 and the fourth transistor T4 are in the off state. The second transistor T2 is turned on according to the high-level signal of the pull-up control node Qn, and the low-level clock signal CLK is transmitted to the output end of the GOA drive circuit, and the output end of the GOA drive circuit outputs the low-level output signal Gn.

[0090] In the C to D phase, the clock signal CLK is at a high level, the pull-down adjustment signal ADJ, the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all at a low level; the twenty-eighth transistor T28 is turned off according to the low-level second input signal Gn+k, the drain of the fifth transistor T5 transmits the high-level signal output by the high voltage source VGH to the source of the fifth transistor T5, the ninth transistor T9 is turned off, and the seventh transistor T7 is turned off; the gate of the first transistor T1 is connected to the low-level first input signal Gn-k, the first transistor T1 is turned off, and since the bootstrap capacitor C1 is charged and stores energy in the previous phase, the pull-up control node Qn is at a high level, so the sixth transistor T6 and the seventh transistor T7 are turned off. The eighth transistor T8 is turned on to pull down the pull-down control node Kn to a low level. At the same time, the tenth transistor T10 is turned off, and the gate of the twenty-ninth transistor T29 is connected to the low-level reset signal RESET. The twenty-ninth transistor T29 is turned off, so that the third transistor T3 and the fourth transistor T4 are in an off state. The second transistor T2 is turned on according to the high-level signal of the pull-up control node Qn, and transmits the high-level first clock signal CLK to the output end of the GOA drive circuit. Due to the bootstrap effect of the bootstrap capacitor C1, the pull-up control node Qn is raised to a high level of the second voltage, wherein the second voltage is greater than the first voltage, and the output end of the GOA drive circuit outputs a high-level output signal Gn.

[0091] In the D to E phase, the pull-down adjustment signal ADJ, the clock signal CLK, the first input signal Gn-k, the reset signal RESET, and the second input signal Gn+k are all at a low level; the twenty-eighth transistor T28 is turned off according to the low-level second input signal Gn+k, the drain of the fifth transistor T5 transmits the high-level signal output by the high-voltage source VGH to the source of the fifth transistor T5, the ninth transistor T9 is turned off, and the seventh transistor T7 is turned on; the gate of the first transistor T1 is connected to the low-level first input signal Gn-k, the first transistor T1 is turned off, and due to the energy storage of the bootstrap capacitor C1 in the previous phase, the pull-up control node Qn is at a high level, so the sixth transistor T6 and the eighth transistor T8 are turned on to pull the pull-down control node Kn down to a low level. At the same time, The tenth transistor T10 is turned off, the gate of the twenty-ninth transistor T29 is connected to the low-level reset signal RESET, and the twenty-ninth transistor T29 is turned off, so that the third transistor T3 and the fourth transistor T4 are turned on according to the high-level signal of the pull-up control node Qn, so that the pull-up control node Qn is connected to the first low voltage source VSSQ and the output end of the GOA drive circuit is connected to the second low voltage source VSSG, and the second transistor T2 is turned on according to the high-level signal of the pull-up control node Qn, and transmits the low-level first clock signal CLK to the output end of the GOA drive circuit. Since the bootstrap capacitor C1 is no longer bootstrapped at this time, the pull-up control node Qn is at a high level of the first voltage, and the output end of the GOA drive circuit outputs a low-level output signal Gn.

[0092] In the E to F phase, the second input signal Gn+k is at a high level, the pull-down adjustment signal ADJ, the reset signal RESET, the clock signal CLK, and the first input signal Gn-k are all at a low level; the drain of the fifth transistor T5 transmits the high-level signal output by the high voltage source VGH to the source of the fifth transistor T5, the gate of the first transistor T1 is connected to the low-level first input signal Gn-k, the first transistor T1 is turned off, the twenty-eighth transistor T28 is turned on according to the high-level second input signal Gn+k, and the pull-up control node Qn is pulled down to a low level, so the sixth transistor T6 and the eighth transistor T8 are turned off. , the seventh transistor T7 is turned on and outputs the high-level signal output by the high voltage source VGH to the pull-down control node Kn. At the same time, the gate of the twenty-ninth transistor T29 is connected to the low-level reset signal RESET, the twenty-ninth transistor T29 is turned off, and the pull-down control node Kn jumps from the low level to the high level, so that the third transistor T3 and the fourth transistor T4 are in the turned-on state, so that the pull-up control node Qn is connected to the first low voltage source VSSQ and the output end of the GOA driving circuit is connected to the second low voltage source VSSG, and the output end of the GOA driving circuit outputs the low-level output signal Gn.

[0093] In the F to G phase, the operating principle of the GOA driving circuit is the same as that in the phase before A, and will not be repeated here.

[0094] In the G to H phase, the reset signal RESET is at a high level, the pull-down adjustment signal ADJ, the clock signal CLK, the first input signal Gn-k and the second input signal Gn+k are at a low level; the twenty-eighth transistor T28 is turned off according to the low-level second input signal Gn+k, the drain of the fifth transistor T5 transmits the high-level signal output by the high-voltage source VGH to the source of the fifth transistor T5, the gate of the first transistor T1 is connected to the low-level first input signal Gn-k, the first transistor T1 is turned off, the pull-up control node Qn is at a low level, so the sixth transistor T6 and the eighth transistor T8 are turned off, the ninth transistor T9 is turned off, the seventh transistor T7 is turned on and the seventh transistor T7 transmits the high-level signal output by the high-voltage source VGH to the source of the fifth transistor T5. The pull-up signal is output to the pull-down control node Kn, and the tenth transistor T10 is turned off. At the same time, the gate of the twenty-ninth transistor T29 is connected to the high-level reset signal RESET. The twenty-ninth transistor T29 pulls down the pull-up control node to a low level, and the pull-down control node Kn is at a high level, so that the third transistor T3 and the fourth transistor T4 are in a strongly turned-on state, so that the pull-up control node Qn is connected to the first low voltage source VSSQ and the output end of the GOA driving circuit is connected to the second low voltage source VSSG. Since the third transistor T3 and the fourth transistor T4 are in the strongly turned-on state, the pull-up control node Qn and the output end of the GOA driving circuit are effectively reset, and the output end of the GOA driving circuit outputs a low-level output signal Gn.

[0095] It should be noted that Figure 6 Another waveform diagram of each signal of the GOA driving circuit is shown below. Figure 6 right Figure 4 The principle of the GOA driving circuit shown is similar to Figure 5 The difference in the principle of the GOA driving circuit shown is further explained:

[0096] The first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 have opposite polarities, so that two identical circuit units (two inverter units, two pull-down holding units and two pull-down adjustment units) work alternately, reducing the possibility of the device being turned on for a long time, thereby reducing the possibility of device degradation and extending the life of the device.

[0097] An embodiment of the present invention further provides a display device, which includes the above-mentioned GOA driving circuit.

[0098] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0099] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A GOA driving circuit, characterized in that: It includes a pull-up module, an input module, a pull-down module, a pull-down maintaining module, an inverter module and a pull-down adjustment module; The input module is connected to the first input signal terminal and the pull-up control node; The pull-up module is connected to the clock signal end, the pull-up control node and the output end of the GOA driving circuit; The inverter module is connected to the pull-up control node and the pull-down control node, and is used to invert the voltage of the pull-up control node to output a pull-down control signal to the pull-down control node; The pull-down adjustment module is connected to the pull-down control node and the pull-down adjustment signal terminal, and is used to adjust the pull-down control signal according to the pull-down adjustment signal; wherein the start time of the adjusted pull-down control signal is advanced; The pull-down maintaining module is connected to the pull-down control node, the pull-up control node and the output end of the GOA driving circuit, and is used to maintain the pull-up control node and the output end of the GOA driving circuit at a low level according to the adjusted pull-down control signal; The pull-down module is connected to the pull-up control node and the second input signal terminal.

2. The GOA driving circuit according to claim 1, wherein: The input module is used to receive a first input signal and transmit the first input signal to the pull-up control node; The input module includes a first transistor; The drain of the first transistor and the gate of the first transistor are connected to the first input signal terminal; A source of the first transistor is connected to the pull-up control node.

3. The GOA driving circuit according to claim 1, wherein: The pull-up module is used to access the clock signal, and in response to the high-level clock signal and the high-level signal of the pull-up control node, output a high-level output signal from the output end of the GOA driving circuit; The pull-up module includes a second transistor and a bootstrap capacitor; The gate of the second transistor and the first end of the bootstrap capacitor are commonly connected to the pull-up control node; The source of the second transistor and the second end of the bootstrap capacitor are commonly connected to the output end of the GOA driving circuit; The drain of the second transistor is connected to the clock signal terminal to receive the clock signal.

4. The GOA driving circuit according to claim 1, wherein: The pull-down maintaining module includes a third transistor and a fourth transistor; The drain of the third transistor is connected to the output end of the GOA driving circuit, the drain of the fourth transistor is connected to the pull-up control node, the gate of the third transistor and the gate of the fourth transistor are commonly connected to the pull-down control node, the source of the third transistor is connected to the second low voltage source, and the source of the fourth transistor is connected to the first low voltage source, wherein the output voltage of the first low voltage source is less than the output voltage of the second low voltage source.

5. The GOA driving circuit according to claim 1, wherein: The inverter module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor; The drain of the fifth transistor, the gate of the fifth transistor and the drain of the seventh transistor are commonly connected to a high voltage source; The gate of the sixth transistor and the gate of the eighth transistor are commonly connected to the pull-up control node; The source of the ninth transistor, the gate of the sixth transistor and the gate of the eighth transistor are commonly connected to a first low voltage source; The source of the fifth transistor is connected to the drain of the ninth transistor, the drain of the sixth transistor, and the gate of the seventh transistor; The source of the seventh transistor and the drain of the eighth transistor are commonly connected to the pull-down control node; The gate of the ninth transistor serves as the pull-down adjustment signal input terminal of the inverter module to receive the pull-down adjustment signal.

6. The GOA driving circuit according to claim 1, wherein: The pull-down adjustment module includes a tenth transistor; The drain of the tenth transistor is connected to the pull-down control node; The gate of the tenth transistor serves as a pull-down adjustment signal input terminal of the pull-down adjustment module to receive the pull-down adjustment signal; A source of the tenth transistor is connected to a first low voltage source.

7. The GOA driving circuit according to claim 1, wherein: The inverter module includes a first inverter unit and a second inverter unit, the pull-down maintaining module includes a first pull-down maintaining unit and a second pull-down maintaining unit, and the pull-down adjusting module includes a first pull-down adjusting unit and a second pull-down adjusting unit; The first inverter unit and the second inverter unit are used to alternately output a first pull-down control signal and a second pull-down control signal respectively; The first pull-down adjustment unit and the second pull-down adjustment unit are used to adjust the first pull-down control signal and the second pull-down control signal respectively; wherein the start time of the adjusted first pull-down control signal and the start time of the adjusted second pull-down control signal are both advanced; The first pull-down maintaining unit and the second pull-down maintaining unit are used to alternately operate the adjusted first pull-down control signal and the adjusted second pull-down control signal respectively to pull down the pull-up control node and the output end of the GOA driving circuit to a low level.

8. The GOA driving circuit according to claim 7, wherein: The first pull-down adjustment unit includes a twenty-fifth transistor; a drain of the twenty-fifth transistor connected to the first pull-down control node; The gate of the twenty-fifth transistor serves as a pull-down adjustment signal input terminal of the pull-down adjustment module to receive the pull-down adjustment signal; The source of the twenty-fifth transistor is connected to the first low voltage source; The second pull-down adjustment unit includes a twenty-sixth transistor; The drain of the twenty-sixth transistor is connected to the second pull-down control node; The gate of the twenty-sixth transistor serves as a pull-down adjustment signal input terminal of the pull-down adjustment module to receive the pull-down adjustment signal; A source of the twenty-sixth transistor is connected to a first low voltage source.

9. The GOA driving circuit according to any one of claims 1 to 8, wherein: The pull-down adjustment signal is an output signal of the GOA driving circuit of the upper m rows, a level transmission signal of the GOA driving circuit of the upper m rows, or a signal of a pull-up control node of the GOA driving circuit of the upper m rows; The first input signal is the output signal of the GOA driving circuit of the upper k rows; the second input signal is the output signal of the GOA driving circuit of the lower k rows, where k is a positive integer and m is a positive integer less than 2k.

10. A display device, characterized in that: The display device comprises the GOA driving circuit according to any one of claims 1 to 9.

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