Array substrate and display device

Abstract

The invention provides an array substrate and a display device.The array substrate comprises a plurality of pixel circuits, each pixel circuit comprises an amplitude modulation sub-circuit and a pulse width modulation sub-circuit, and the array substrate further comprises a first type of gate drive circuit, a second type of gate drive circuit and an electrostatic shielding unit; the first type of gate drive circuit is used for transmitting a control signal to the pulse width modulation sub-circuit, and the second type of gate drive circuit is used for transmitting a control signal to the amplitude modulation sub-circuit. The first voltage line and the second voltage line transmit high-voltage signals to the first type of gate drive circuit and the second type of gate drive circuit respectively, or the first voltage line and the second voltage line transmit low-voltage signals to the first type of gate drive circuit and the second type of gate drive circuit respectively. At least part of the electrostatic shielding units are connected between the first voltage line and the second voltage line, and the voltage transmitted by the first voltage line is different from the voltage transmitted by the second voltage line.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to an array substrate and a display device. Background Art

[0002] With the development of science and technology, the display field has also made great progress and achieved diversified development. On this basis, people's requirements for display devices are also increasing day by day. How to improve the reliability of display devices while meeting performance requirements has become one of the research directions of manufacturers. Summary of the Invention

[0003] Embodiments of the present application provide an array substrate and a display device, which can improve the reliability of a display panel.

[0004] In a first aspect, an embodiment of the present application provides an array substrate, the array substrate includes a plurality of pixel circuits, the pixel circuit includes an amplitude modulation sub-circuit and a pulse width modulation sub-circuit, the array substrate also includes a first type of gate drive circuit, a second type of gate drive circuit and an electrostatic shielding unit, the first type of gate drive circuit is used to transmit a control signal to the pulse width modulation sub-circuit, and the second type of gate drive circuit is used to transmit a control signal to the amplitude modulation sub-circuit.

[0005] The first voltage line and the second voltage line transmit high-voltage signals to the first type of gate drive circuit and the second type of gate drive circuit, respectively, or the first voltage line and the second voltage line transmit low-voltage signals to the first type of gate drive circuit and the second type of gate drive circuit, respectively. At least a portion of the electrostatic shielding unit is connected between the first voltage line and the second voltage line, and the voltage transmitted by the first voltage line is different from the voltage transmitted by the second voltage line.

[0006] In a second aspect, an embodiment of the present application provides a display device, which includes the array substrate in any of the aforementioned embodiments.

[0007] An embodiment of the present application provides an array substrate and a display device, which have added virtual registers, and at least part of the electrostatic shielding unit is connected between the first voltage line and the second voltage line, so that at least part of the electrostatic shielding unit can discharge abnormal charges generated by static electricity on the first voltage line and the second voltage line, thereby achieving static electricity discharge between the first voltage line and the second voltage line, improving the reliability of signal transmission on the first voltage line and the second voltage line, reducing the abnormal problems of control signals output by the first type gate drive circuit and the second type gate drive circuit due to static electricity, enhancing the operating reliability of the pixel circuit, and meeting the normal display needs of the display device.

[0008] In addition, by setting the voltage transmitted by the first voltage line and the voltage transmitted by the second voltage line to be different, a voltage difference is created between the two, thereby reducing the risk of direct conduction between the first voltage line and the second voltage line due to the electrostatic shielding unit. This design can achieve the electrostatic protection function while improving the independent operation reliability of the first type of gate drive circuit and the second type of gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0010] Figure 1 This is a schematic diagram of a simplified partial structure of an array substrate provided in an embodiment of the present application;

[0011] Figure 2 This is a schematic diagram of a simplified partial structure of another array substrate provided in an embodiment of the present application;

[0012] Figure 3 This is a schematic diagram of a simplified partial structure of another array substrate provided in an embodiment of the present application;

[0013] Figure 4 yes Figure 1 Schematic diagram of the enlarged structure at the middle area Q;

[0014] Figure 5a and Figure 5b This is a simplified circuit diagram of two pixel circuits in an array substrate provided by an embodiment of the present application;

[0015] Figure 6 is a schematic cross-sectional structural diagram of a display device provided in an embodiment of the present application;

[0016] Figure 7 This is a simplified circuit diagram of a shift register in a first type of gate driving circuit in an array substrate provided by an embodiment of the present application;

[0017] Figure 8 This is a simplified circuit diagram of an electrostatic shielding unit in an array substrate provided in an embodiment of the present application;

[0018] Figure 9 This is a structural schematic diagram of an electrostatic shielding unit in another array substrate provided in an embodiment of the present application;

[0019] Figure 10 This is a schematic diagram of a simplified partial structure of another array substrate provided in an embodiment of the present application;

[0020] Figure 11 This is a schematic diagram of a simplified partial structure of another array substrate provided in an embodiment of the present application;

[0021] Figure 12 This is a schematic diagram of a simplified partial structure of another array substrate provided in an embodiment of the present application;

[0022] Figure 13 A display device provided in an embodiment of the present application is Figure 12 Schematic diagram of the cross-sectional structure at AA in the middle;

[0023] Figure 14 This is a schematic diagram of a simplified partial structure of another array substrate provided in an embodiment of the present application;

[0024] Figure 15 This is a schematic diagram of a simplified partial structure of another array substrate provided in an embodiment of the present application;

[0025] Figure 16 This is a simplified circuit diagram of a shift register and a fourth shielding unit in an array substrate provided by an embodiment of the present application;

[0026] Figure 17a and Figure 17b This is a schematic diagram of a simplified partial structure of another array substrate provided in an embodiment of the present application.

[0027] Marking Description:

[0028] 100. Array substrate; 200. Display device;

[0029] 11. First type gate drive circuit; 12. Second type gate drive circuit;

[0030] 21, first voltage line; 211, first sub-segment; 212, third sub-segment; 22, second voltage line; 221, second sub-segment; 222, fourth sub-segment; 23, third voltage line; 231, fifth sub-segment; 24, fourth voltage line; 241, sixth sub-segment;

[0031] 30. Electrostatic shielding unit; 31. First shielding unit; 32. Second shielding unit; 33. Third shielding unit; 34. Fourth shielding unit; 341. First subunit; 3411. First transistor; 342. Second subunit; 3421. Second transistor; 35. Fifth shielding unit; 351. Third subunit; 352. Fourth subunit;

[0032] 40. Transistor; 41. First electrode; 42. Second electrode; 43. Control electrode;

[0033] 51. First discharge pattern; 52. Second discharge pattern;

[0034] 60, first electrode; 61, last electrode row;

[0035] 71. First category signal line; 72. Second category signal line;

[0036] 81. Light-emitting portion; 82. First pole portion; 83. Second pole portion;

[0037] D1, first end; D2, second end; D3, third end; D4, connection end; D5, discharge end;

[0038] P, pixel circuit; P1, pulse width modulation subcircuit; P2, amplitude modulation subcircuit; P3, last row circuit; F, light emitting element;

[0039] V. Shift register;

[0040] X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0041] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0042] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0043] There are many types of display devices. Micro-luminescent displays have attracted widespread attention due to their advantages, such as higher brightness and wider color gamut. Micro-luminescent displays use micro-devices such as micro-light-emitting diodes (Micro LEDs) or sub-millimeter light-emitting diodes (Mini LEDs) as light-emitting elements to achieve luminous display functions. The pixel circuits of micro-luminescent displays are often divided into two circuit structures, each driven by different control signals. However, the control signals corresponding to the two circuit structures are prone to poor transmission due to factors such as static electricity, which can affect the normal display of the micro-luminescent display.

[0044] Regarding the above issues, please refer to Figures 1 to 6 An embodiment of the present application provides an array substrate 100, which includes a plurality of pixel circuits P. The pixel circuit P includes an amplitude modulation sub-circuit P2 and a pulse width modulation sub-circuit P1. The array substrate 100 also includes a first-type gate driving circuit 11, a second-type gate driving circuit 12, and an electrostatic shielding unit 30. The first-type gate driving circuit 11 is used to transmit a control signal to the pulse width modulation sub-circuit P1, and the second-type gate driving circuit 12 is used to transmit a control signal to the amplitude modulation sub-circuit P2.

[0045] The first voltage line 21 and the second voltage line 22 transmit high voltage signals to the first type gate drive circuit 11 and the second type gate drive circuit 12, respectively, or the first voltage line 21 and the second voltage line 22 transmit low voltage signals to the first type gate drive circuit 11 and the second type gate drive circuit 12, respectively. At least part of the electrostatic shielding unit 30 is connected between the first voltage line 21 and the second voltage line 22, and the voltage transmitted by the first voltage line 21 is different from the voltage transmitted by the second voltage line 22. Figure 1 The electrostatic shielding unit 30 is not shown.

[0046] The array substrate 100 is a key component for the subsequent formation of the display device 200. The display device 200 is a device for displaying images. In addition to the array substrate 100, the display device 200 also includes a light-emitting element F. The light-emitting element F is a main component for realizing the light-emitting function. In the embodiment of the present application, the light-emitting element F may be a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a sub-millimeter light-emitting diode (Mini Light Emitting Diode, MiniLED) and other micro light-emitting elements F. Among them, the light-emitting element F can have a variety of structural forms. For example, the light-emitting element F can be a flip-chip, or a face-mounted chip, or a vertical chip. The embodiment of the present application does not limit this. Among them, Figures 1 to 4 The light emitting element F is not shown in FIG. 5 , but the light emitting element F and the pixel circuit P for driving and controlling the light emitting element F are shown. Figure 6 1 and 2 show a light emitting element F and a transistor 40 in the pixel circuit P.

[0047] A pixel circuit P is disposed within the array substrate 100. There are multiple pixel circuits P, each of which controls a different light-emitting element F to achieve a light-emitting function. The projections of the pixel circuits P and the corresponding light-emitting element F in the thickness direction Z of the display device 200 can overlap or be relatively offset, and this is not limited in the present embodiment. The thickness direction Z of the display device 200, the thickness direction Z of the array substrate 100, and the thickness direction Z of the film layer within the array substrate 100 are all arranged in parallel. For ease of understanding, the thickness directions Z are all illustrated as being in the same direction in the accompanying drawings.

[0048] The pixel circuit P includes at least two circuit structures, including a pulse width modulation subcircuit P1 and an amplitude modulation subcircuit P2. The pulse width modulation subcircuit P1 is configured to control the pulse width of the driving current provided to the light-emitting element F based on a pulse width modulation data voltage, that is, to control the light-emitting duration of the light-emitting element F. The amplitude modulation subcircuit P2 is configured to control the amplitude of the driving current provided to the light-emitting element F based on a pulse amplitude modulation data voltage. The pulse width of the driving current can be understood as the duration of the driving current, and the amplitude of the driving current can be understood as the current value of the driving current.

[0049] Specifically, the light-emitting element F includes a first electrode 82, a second electrode 83, and a light-emitting portion 81. The first electrode 82 and the second electrode 83 work together to enable the light-emitting portion 84 to achieve a light-emitting display function. The pixel circuit P generates a drive current under the control of an amplitude modulation subcircuit P2 and a pulse width modulation subcircuit P1. The amplitude modulation subcircuit P2 can be used to control the amplitude of the drive current, while the pulse width modulation subcircuit P1 can be used to adjust the pulse width of the voltage applied to the first electrode 41 of the light-emitting element F.

[0050] The pulse width modulation sub-circuit P1 adjusts the actual emission period of the drive current applied to the light-emitting element F by adjusting the pulse width of the voltage applied to the first electrode 82 of the light-emitting element F. At the same time, the drive current applied to the light-emitting element F is maintained at a constant level to adjust the grayscale or brightness displayed by the light-emitting element F, rather than adjusting the grayscale or brightness displayed by the light-emitting element F by adjusting the magnitude of the drive current applied to the light-emitting element F. Thus, the amplitude modulation sub-circuit P2 can provide a drive current to the light-emitting element F so that the light-emitting element F is driven with optimal luminous efficiency. Furthermore, the pulse width modulation sub-circuit P1 adjusts the light emission duty cycle of the light-emitting element F (i.e., the emission period of the light-emitting element F) to adjust the grayscale or brightness displayed by the light-emitting element F. The output terminal of the pulse width modulation sub-circuit P1 can be directly connected to the control terminal of a driving transistor in the amplitude modulation sub-circuit P2 or indirectly controlled via a capacitor structure. That is, the electrical signal output by the output terminal of the pulse width modulation sub-circuit P1 can be directly written to the control terminal of the driving transistor, or written to the capacitor structure to control the control terminal of the driving transistor, thereby adjusting the amplitude of the drive current.

[0051] Furthermore, the embodiments of the present application do not limit the specific circuit configuration of the pulse width modulation sub-circuit P1 and the amplitude modulation sub-circuit P2. Figure 5a As shown, the pulse width modulation sub-circuit P1 includes a first drive transistor M3, a first gate reset transistor M5, a first data write transistor M2, a first compensation transistor M4, a first control transistor M1, a second control transistor M6, and a storage capacitor Cst. The first control transistor M1 is connected between the first power supply voltage PWM-vdd and the first electrode of the first drive transistor M3, and the second control transistor M6 is connected between the second electrode of the first drive transistor M3 and the first node N1. The first data write transistor M2 is connected to the first data signal PWM-data and the first electrode of the first drive transistor M3, the first compensation transistor M4 is connected to the second electrode and the control electrode of the first drive transistor M3, and the first gate reset transistor M5 is connected to the control electrode of the first drive transistor M3. The first plate of the storage capacitor Cst is connected to the control electrode of the first drive transistor M3, and the second plate of the storage capacitor Cst is connected to the sweep signal SWEEP. The control electrode of the first gate reset transistor M5 receives the first scan signal PWM-S1, and the control electrodes of the first data write transistor M2 and the first compensation transistor M4 receive the second scan signal PWM-S2. Control terminals of the first control transistor M1 and the second control transistor M6 receive a first light emitting control signal PWM-EM.

[0052] The amplitude modulation sub-circuit P2 includes a second drive transistor M9, a second gate reset transistor M11, a second data write transistor M8, a second compensation transistor M10, a third control transistor M7, a fourth control transistor M12, and an electrode reset transistor M13. The third control transistor M7 is connected between the second power supply voltage PAM-vdd and the first electrode of the second drive transistor M9. The fourth control transistor M12 is connected between the second electrode of the second drive transistor M9 and the light-emitting element F. The second drive transistor M9 is configured to generate a drive current under the control of its control electrode voltage, i.e., the voltage of the first node N1. The second data write transistor M8 is connected to the second data signal PAM-data and the first electrode of the second drive transistor M9. The second compensation transistor M10 is connected to the second electrode and the control electrode of the second drive transistor M9. The second gate reset transistor M11 is connected to the control electrode of the second drive transistor M9. The electrode reset transistor M13 is connected to the second electrode of the light-emitting element F. The fourth control transistor M12 is also connected to the first electrode of the light-emitting element F. The second electrode of the light-emitting element F is connected to the third power supply voltage PVEE. The control electrode of the second gate reset transistor M11 receives the third scan signal PAM-S1; the control electrodes of the second data write transistor M8, the second compensation transistor M10, and the electrode reset transistor M13 receive the fourth scan signal PAM-S2; and the control electrodes of the third control transistor M7 and the fourth control transistor M12 receive the second light emission control signal PAM-EM.

[0053] Or as Figure 5b As shown, both the amplitude modulation subcircuit P2 and the pulse width modulation subcircuit P1 include an initialization unit 111' / 121', a data writing unit 112 / 122', a threshold compensation unit 113 / 123', a light emitting control unit 114 / 124, storage capacitors C1, C2, and C3, a compensation module 115, an electrode reset module 116, a voltage stabilization module 125, and a driving transistor PAM-DR / PWM-DR. The amplitude modulation subcircuit P2 includes the initialization unit 111', the data writing unit 112, the threshold compensation unit 113, the light emitting control unit 114, the storage capacitor C2, the voltage stabilization module 125, and the driving transistor PAM-DR; the pulse width modulation subcircuit P1 includes the initialization unit 121', the data writing unit 122', the threshold compensation unit 123', the light emitting control unit 124, the storage capacitors C2 and C3, the compensation module 115, the electrode reset module 116, and the driving transistor PWM-DR. The storage capacitor C3 is located in the compensation module 115 , and the supplement module 115 further includes a plurality of transistors.

[0054] The initialization unit 111' / 121' is electrically connected between the initialization signal VREF and the first node N1 / N2. The initialization unit 111' / 121' is used to provide the initialization signal VREF to the first node N1 and the second node N2 during the initialization phase (the initialization signal provided by the initialization signal terminal of the amplitude modulation sub-circuit P2 may have the same value as or different from the initialization signal of the pulse width modulation sub-circuit P1. Figure 5b Schematic diagram showing the case where the initialization signal VREF includes PAM-REF and PWM-REF, respectively. A data write unit 112 / 122' is electrically connected between the data signal PAM-DATA / PWM-DATA and the first electrode of the driving transistor PAM-DR / PWM-DR. The control electrode of the driving transistor PAM-DR / PWM-DR and the first plate of the storage capacitor C2 / C1 are electrically connected to the first node N1 and the second node N2. The data write unit 112 / 122' is configured to provide the data signal PAM-DATA / PWM-DATA to the first node N1 and the second node N2 via the driving transistor PAM-DR / PWM-DR during the data write phase. A threshold compensation unit 113 / 123' is electrically connected to the second electrode of the driving transistor PAM-DR / PWM-DR. The threshold compensation unit 113 / 123' is configured to compensate the threshold voltage of the driving transistor PAM-DR / PWM-DR to the first node N1 and the second node N2. The electrode reset module 116 is electrically connected between the second reset signal PAM-INIT and the first electrode 41 of the light-emitting element F. During the initialization phase, the electrode reset module 116 is configured to provide the first electrode with the second reset signal PAM-REF to reset the first electrode. The compensation module 115 is electrically connected to the second plate of the storage capacitor C2 to provide compensation and reduce voltage drops in the pixel circuit P. The voltage stabilization module 125 is electrically connected between the second plate 42 of the storage capacitor C1 and the voltage stabilization signal SWEEP-GND. The voltage stabilization module 125 is configured to stabilize the potential of the second node N2 when the sweep signal SWEEP is not active.

[0055] In addition to the pixel circuit P, the array substrate 100 also includes a first-type gate driver circuit 11 and a second-type gate driver circuit 12. The first-type gate driver circuit 11 is used to provide corresponding control signals to the control terminals of the transistors in the pulse width modulation sub-circuit P1, and the second-type gate driver circuit 12 is used to transmit corresponding control signals to the control terminals of the transistors in the amplitude modulation sub-circuit P2. For example, the first-type gate driver circuit 11 can be used to transmit one of the first scanning signal PWM-S1, the second scanning signal PWM-S2, the first light-emitting control signal PWM-EM, and the sweep signal line SWEEP. The second-type gate driver circuit 12 can be used to transmit one of the third scanning signal PAM-S1, the fourth scanning signal PAM-S2, and the second light-emitting control signal PAM-EM.

[0056] The specific positional relationship between the first type gate driving circuit 11 and the second type gate driving circuit 12 relative to the pixel circuit P is not limited in the present embodiment. Taking the first type gate driving circuit 11 as an example, Figure 1 As shown, the first type of gate driving circuit 11 can be arranged at the same side area of ​​all pixel circuits, or considering that the array substrate 100 provided in the embodiment of the present application is used to form a display device 200 using micron light emitting diodes or sub-millimeter light emitting diodes as light emitting elements F, as shown in FIG. Figure 2 As shown, the first type of gate driving circuit 11 can be set between adjacent pixel circuits P to facilitate achieving a nearly borderless display effect. On this basis, the first type of gate driving circuit 11 can be set between adjacent circuit rows or between adjacent circuit columns.

[0057] Both the first-type gate drive circuit 11 and the second-type gate drive circuit 12 include multiple shift registers V arranged in cascade. The shift register V is a sequential logic circuit primarily used to store and transmit specific signals. The output end of the shift register V in the first-type gate drive circuit 11 is electrically connected to the control end of the transistor in the pulse modulation subcircuit via a specific signal trace to transmit the control signal to the pulse modulation subcircuit. The output end of the shift register V in the second-type gate drive circuit 12 is electrically connected to the control end of the transistor in the amplitude modulation subcircuit P2 via a specific signal trace to transmit the control signal to the amplitude modulation subcircuit P2.

[0058] The specific circuit structure of the shift register is not limited in the present embodiment. Figure 7Taking the shift register V in the first type of gate drive circuit 11 as an example, the shift register V includes a first output module K1, a second output module K2, a first control module K3, and a second control module K4. The first output module K1 is connected between the second clock signal PWM-XCKSS and the shift output terminal GOUT. The control terminal of the first output module K1 is connected to the third node N3. The potential of the third node N3 controls the on-off state of the first output module K1. The first output module K1 includes a transistor structure T8 and a capacitor C4. The control electrode of the transistor structure T8 is connected to the third node N3. The first electrode and the second electrode are respectively connected to the second clock signal PWM-XCKSS and the shift output terminal GOUT. The two plates of the capacitor C4 are respectively connected to the second clock signal PWM-XCKSS and the shift output terminal GOUT.

[0059] The second output module K2 is connected between the first high-voltage signal PWM-VGH and the shift output terminal GOUT. The control electrode of the second output module K2 is connected to the fourth node N4. The potential of the fourth node N4 controls the on / off state of the second output module K2. The second output module K2 includes a transistor structure T7 and a capacitor C5. The control electrode of the transistor structure T7 is connected to the fourth node N4. The first electrode and the second electrode are respectively connected to the first high-voltage signal PWM-VGH and the shift output terminal GOUT. The two plates of the capacitor C5 are respectively connected to the first high-voltage signal PWM-VGH and the shift output terminal GOUT.

[0060] The first control module K3 is connected to the third node N3 and is used to control the on / off state of the first output module K1. The first control module K3 includes a transistor structure T1, a transistor structure T4, a transistor structure T5, and a transistor structure T6. The control electrode of the transistor structure T1 is connected to the first clock signal PWM-CKSS, and the first and second electrodes are respectively connected to the first start signal PWM-STV and the fifth node N5. The control electrode of the transistor structure T4 is connected to the second clock signal PWM-XCKSS, and the first and second electrodes are respectively connected to the fifth node N5 and the transistor structure T5. The control electrode of the transistor structure T5 is connected to the fourth node N4, and the first and second electrodes are respectively connected to the transistor structure T4 and the first high-voltage signal PWM-VGH. The control electrode of the transistor structure T6 is connected to the first low-voltage signal PWM-VGL, and the first and second electrodes are respectively connected to the fifth node N5 and the third node N3.

[0061] The second control module K4 is connected to the fourth node N4 and is used to control the on / off state of the second output module K2. The second control module K4 includes a transistor structure T2 and a transistor structure T3. The control terminal of the transistor structure T2 is connected to the fifth node N5, and the first and second terminals are respectively connected to the first clock signal PWM-CKSS and the fourth node N4. The control base of the transistor structure T3 is connected to the first clock signal PWM-CKSS, and the first and second terminals are respectively connected to the first low-voltage signal PWM-VGL and the fourth node N4.

[0062] The first voltage line 21 and the second voltage line 22 can be used to transmit high-voltage signals to the first type gate drive circuit 11 and the second type gate drive circuit 12, respectively. For example, the first voltage line 21 is used to transmit the first high-voltage signal PWM-VGH, and the second voltage line 22 is used to transmit the second high-voltage signal PAM-VGH. The first voltage line 21 and the second voltage line 22 can also be used to transmit low-voltage signals to the first type gate drive circuit 11 and the second type gate drive circuit 12, respectively. For example, the first voltage line 21 is used to transmit the first low-voltage signal PWM-VGL, and the second voltage line 22 is used to transmit the second low-voltage signal PAM-VGL. For ease of understanding, the embodiments of the present application will be described below using the example of the first voltage line 21 being used to transmit the first high-voltage signal PWM-VGH and the second voltage line 22 being used to transmit the second high-voltage signal PAM-VGH.

[0063] It should be noted that the above description is merely one circuit structure of the shift register V in the first type of gate drive circuit and does not limit the circuit structure of the shift register V. Depending on actual needs, the shift register V may also adopt other circuit structures. Furthermore, the circuit structure of the shift register V in the second type of gate drive circuit 12 may be the same as or different from the above description.

[0064] In addition, the embodiment of the present application does not limit the connection form of the first voltage line 21 and the second voltage line 22 relative to the first type gate drive circuit 11 and the second type gate drive circuit 12. Figure 1 As shown, the first voltage line 21 may include a side trace located on one side of the first type gate driving circuit 11 along the second direction Y, a top trace located on one side of the first type gate driving circuit 11 along the first direction X, and an overlapping trace extending along the first direction X and overlapping with the first type gate driving circuit 11, the overlapping trace being connected to the side trace and the top trace at both ends of the second direction Y. Or as Figure 3As shown, the first voltage line 21 includes side lines but does not include top lines and overlapping lines. On this basis, the first voltage line 21 also includes connecting lines extending along the second direction. There are multiple connecting lines and they are connected to the multiple shift registers V in the first type of gate drive circuit 11.

[0065] In addition to the aforementioned structures, the array substrate 100 also includes an electrostatic shielding unit 30. This unit can provide electrostatic protection to reduce damage to the circuit caused by electrostatic discharge. The electrostatic shielding unit 30 can have various forms, such as a diode structure or a specific discharge pattern.

[0066] One or more electrostatic shielding units 30 may be provided, and at least part of the electrostatic shielding units 30 are connected between the first voltage line 21 and the second voltage line 22. In this way, at least part of the electrostatic shielding units 30 can discharge the abnormal charges generated by static electricity on the first voltage line 21 and the second voltage line 22, thereby realizing the electrostatic discharge between the first voltage line 21 and the second voltage line 22, improving the reliability of signal transmission on the first voltage line 21 and the second voltage line 22, reducing the abnormal problems of the control signals output by the first type gate drive circuit 11 and the second type gate drive circuit 12 due to static electricity, enhancing the operation reliability of the pixel circuit P, and meeting the normal display needs of the display device 200.

[0067] In the related art, the first high-voltage signal PWM-VGH and the second high-voltage signal PAM-VGH may have the same or similar potential voltages. Considering that a diode structure often allows unidirectional movement of current, if a diode structure is provided between the signal traces corresponding to the two signals to implement an electrostatic protection function, the signal traces corresponding to the two signals will be directly connected through the diode structure, thereby affecting the normal operation of the gate drive circuit and causing display abnormalities.

[0068] In view of this, the embodiment of the present application also sets the voltage transmitted by the first voltage line 21 to be different from the voltage transmitted by the second voltage line 22, so that there is a voltage difference between the two. Taking the case where the voltage transmitted by the first voltage line 21 is greater than the voltage transmitted by the second voltage line 22 as an example, by setting the electrostatic shielding unit 30 to only allow current to flow to the first voltage line 21 via the second voltage line 22, while the current itself cannot flow from the high-voltage side to the low-voltage side, the current under this design cannot flow from the second voltage line 22 to the first voltage line 21 through the electrostatic shielding unit 30, thereby reducing the risk of direct conduction between the first voltage line 21 and the second voltage line 22 due to the electrostatic shielding unit 30. This design can improve the independent operation reliability of the first type gate drive circuit 11 and the second type gate drive circuit 12 while achieving the electrostatic protection function.

[0069] In some embodiments, see Figure 4 and Figure 8 The electrostatic shielding unit 30 has a first end D1 and a second end D2. One of the first end D1 and the second end D2 is electrically connected to the first voltage line 21, and the other is electrically connected to the second voltage line 22. The electrostatic shielding unit 30 includes a transistor 40. The transistor 40 includes a first electrode 41, a second electrode 42, and a control electrode 43. The control electrode 43 controls the conduction or disconnection of the first electrode 41 and the second electrode 42. The first electrode 41 and the control electrode 43 are electrically connected. The control electrodes 43 of at least some of the transistors 40 are electrically connected to the first end D1, and the second electrodes 42 of at least some of the transistors 40 are electrically connected to the second end D2.

[0070] The electrostatic shielding unit 30 includes two ends for connecting to the first voltage line 21 and the second voltage line 22. For ease of understanding, the present embodiment uses an example in which the first end D1 is electrically connected to the lower voltage of the first and second voltage lines 21, 22, and the second end D2 is electrically connected to the higher voltage of the first and second voltage lines 21, 22. In addition to the first and second ends D1, D2, the electrostatic shielding unit 30 also includes a third end D3, which is connected to ground.

[0071] Transistor 40 is a core component of electrostatic shielding unit 30. Transistor 40 itself is a triode structure, with control electrode 43 controlling the conduction or disconnection of first electrode 41 and second electrode 42. However, in the present embodiment, by electrically connecting first electrode 41 and control electrode 43, transistor 40 can be made equivalent to a diode structure, thereby achieving electrostatic protection. Specifically, transistor 40 in electrostatic shielding unit 30 can allow current to flow from first terminal D1 to second terminal D2, while preventing current from second terminal D2 to first terminal D1.

[0072] Under this design, when the first voltage line 21 and the second voltage line 22 are operating normally, the current tends to flow from the second end D2 to the first end D1, but in the direction from the second end D2 to the first end D1, the transistor 40 is in a high-resistance state, and the current cannot flow from the second end D2 to the first end D1. Therefore, it hardly affects the independent transmission of the respective signal voltages of the first voltage line 21 and the second voltage line 22, as well as the normal operation of the first type gate drive circuit 11 and the second type gate drive circuit 12. However, once an electrostatic discharge event occurs, the voltage of the first end D1 and the second end D2 will rise rapidly. When this voltage exceeds the threshold voltage of the transistor 40 itself, the transistor 40 will change from a high-resistance state to a low-resistance state, forming a conductive path, thereby quickly bypassing the energy of the electrostatic pulse to the ground, realizing the electrostatic discharge between the first voltage line 21 and the second voltage line 22, reducing the adverse effects of static electricity on the corresponding signal transmission between the first voltage line 21 and the second voltage line 22, improving the operating reliability of the first type gate drive circuit 11 and the second type gate drive circuit 12 and the reliability of the corresponding transmitted control signals, and enhancing the display effect and display accuracy of the display device 200.

[0073] It should be noted that the electrostatic shielding unit 30 may include multiple transistors 40, and different transistors 40 may be connected in a variety of ways. Figure 8 FIG2 shows a connection method between multiple transistors 40 in the electrostatic shielding unit 30. As shown in the figure, the electrostatic shielding unit 30 may include two transistors 40, wherein the first electrode 41 and the control electrode 43 of one transistor 40 are both electrically connected to the first terminal D1, and the second electrode 42 is electrically connected to the third terminal D3. The first electrode 41 and the control electrode 43 of the other transistor 40 are both electrically connected to the third terminal D3, and the second electrode 42 is electrically connected to the second terminal D2.

[0074] In some embodiments, see Figure 2 and Figure 9 The electrostatic shielding unit 30 includes a first discharge pattern 51 and a second discharge pattern 52. Each of the first and second discharge patterns 51 and 52 includes a connecting end D4 and a discharging end D5. The width of the discharge pattern gradually decreases from the connecting end D4 toward the discharging end D5. The connecting end D4 of the first discharge pattern 51 is electrically connected to the first voltage line 21, while the connecting end D4 of the second discharge pattern 52 is electrically connected to the second voltage line 22.

[0075] The first discharge pattern 51 and the second discharge pattern 52 are both made of conductive material. They each include a connection end D4 and a discharge end D5, which are electrically connected to the first voltage line 21 and the second voltage line 22, respectively, via the corresponding connection end D4. The discharge end D5 is the primary area of ​​the discharge pattern for achieving electrostatic discharge. The width of the discharge pattern decreases gradually in the direction from the connection end D4 to the discharge end D5. The "width" mentioned here refers to the dimension of the discharge pattern perpendicular to the direction from the connection end D4 to the discharge end D5. The discharge end D5 is the sharp end of the discharge pattern.

[0076] The first discharge pattern 51 and the second discharge pattern 52 use the tip discharge principle to achieve electrostatic discharge. The tip discharge principle is the phenomenon of concentrated release of the electric field on a sharp object. When a conductor has a sharp point, the charge density in this area is high and the electric field strength is large, resulting in discharge. Under electrostatic equilibrium, the charge on the surface of the conductor is evenly distributed. According to Gauss's theorem, it can be known that the field strength near the surface of the conductor is only related to the surface charge density. Therefore, the charge density at the discharge end D5 is large and the electric field strength is strong, which easily triggers the discharge phenomenon. When the discharge end D5 discharges, the electric field strength causes ions in the air to move, collide with air molecules, and the air is broken down, achieving electrostatic discharge, thereby realizing the electrostatic protection function.

[0077] The present embodiment of the present application does not restrict the specific material composition of the first discharge pattern 51 and the second discharge pattern 52. Optionally, the first discharge pattern 51 and the second discharge pattern 52 can be provided on the same layer, i.e., they can be made of the same material and fabricated together in the same patterning process. Furthermore, the present embodiment of the present application does not restrict the specific dimensions and morphology of the two discharge patterns, as long as both include a pointed discharge end D5. Optionally, the projections of the first discharge pattern 51 and the second discharge pattern 52 in the thickness direction Z can both be triangular.

[0078] In some embodiments, see Figure 1 and Figure 10 The array substrate 100 further includes a third voltage line 23 and a fourth voltage line 24. The first voltage line 21 and the second voltage line 22 transmit high-voltage signals to the first type gate driver circuit 11 and the second type gate driver circuit 12, respectively. The third voltage line 23 and the fourth voltage line 24 transmit low-voltage signals to the first type gate driver circuit 11 and the second type gate driver circuit 12, respectively. The voltage transmitted by the third voltage line 23 is different from the voltage transmitted by the fourth voltage line 24. The multiple electrostatic shielding units 30 include a first shielding unit 31 and a second shielding unit 32. The first shielding unit 31 is connected between the first voltage line 21 and the second voltage line 22, and the second shielding unit 32 is connected between the third voltage line 23 and the fourth voltage line 24.

[0079] The first voltage line 21 is used to transmit the first high voltage signal PWM-VGH, the second voltage line 22 is used to transmit the second high voltage signal PAM-VGH, the third voltage line 23 is used to transmit the first low voltage signal PWM-VGL, and the fourth voltage line 24 is used to transmit the second low voltage signal PAM-VGL.

[0080] The first shielding unit 31 and the second shielding unit 32 are different electrostatic shielding units 30. The first shielding unit 31 is connected between the first voltage line 21 and the second voltage line 22 to discharge abnormal charges generated by static electricity on the first voltage line 21 and the second voltage line 22, thereby achieving static electricity discharge between the first voltage line 21 and the second voltage line 22, and improving the reliability of the transmission of the first high-voltage signal PWM-VGH and the second high-voltage signal PAM-VGH. The second shielding unit 32 is connected between the third voltage line 23 and the fourth voltage line 24 to discharge abnormal charges generated by static electricity on the third voltage line 23 and the fourth voltage line 24, thereby achieving static electricity discharge between the third voltage line 23 and the fourth voltage line 24, and improving the reliability of the transmission of the first low-voltage signal PWM-VGL and the second low-voltage signal PAM-VGL.

[0081] Furthermore, similar to the first voltage line 21 and the second voltage line 22, the embodiment of the present application also sets the voltage transmitted by the third voltage line 23 to be different from the voltage transmitted by the fourth voltage line 24, so that there is a voltage difference between the two, thereby reducing the risk of the third voltage line 23 and the fourth voltage line 24 being directly connected due to the second shielding unit 32. This design can improve the independent operation reliability of the first type gate drive circuit 11 and the second type gate drive circuit 12 while realizing the electrostatic protection function.

[0082] In summary, in the embodiment of the present application, in addition to providing a first shielding unit 31 for electrostatic protection of the first voltage line 21 and the second voltage line 22, a second shielding unit 32 is also provided for electrostatic protection of the third voltage line 23 and the fourth voltage line 24, thereby simultaneously improving the reliability of the high-voltage signal and the low-voltage signal transmitted to the first type gate driver circuit 11, and simultaneously improving the reliability of the high-voltage signal and the low-voltage signal transmitted to the second type gate driver circuit 12. This design can further improve the operational reliability of the first type gate driver circuit 11 and the second type gate driver circuit 12, reduce abnormal problems of the control signal line caused by static electricity, and improve the display effect and display accuracy of the display device 200.

[0083] In some embodiments, as Figure 8 and Figure 10As shown, the electrostatic shielding unit 30 includes a first end D1 and a second end D2. The electrostatic shielding unit 30 is configured to allow current to flow from the first end D1 to the second end D2 and to prevent current from flowing from the second end D2 to the first end D1. The voltage transmitted by the first voltage line 21 is greater than the voltage transmitted by the second voltage line 22. The first end D1 of the first shielding unit 31 is electrically connected to the second voltage line 22, and the second end D2 of the first shielding unit 31 is electrically connected to the first voltage line 21.

[0084] When the electrostatic shielding unit 30 includes a diode structure or is equivalent to a diode structure through the transistor 40, the electrostatic shielding unit 30 only allows current to flow in one direction, that is, it allows current to flow from the first end D1 to the second end D2. In the direction from the second end D2 to the first end D1, the electrostatic shielding unit 30 is in a high-impedance state.

[0085] The voltage transmitted by the first voltage line 21 is greater than the voltage transmitted by the second voltage line 22. Therefore, when both the first voltage line 21 and the second voltage line 22 are connected to the first shielding unit 31, the current on the first voltage line 21 tends to flow from the first shielding unit 31 to the second voltage line 22. Based on this, the embodiment of the present application electrically connects the first end D1 of the first shielding unit 31 to the second voltage line 22, and the second end D2 to the first voltage line 21. In this way, during the normal operation of the first voltage line 21 and the second voltage line 22, the current is blocked from flowing from the first voltage line 21 to the second voltage line 22, thereby meeting the independent transmission requirements of the signal voltages of the first voltage line 21 and the second voltage line 22.

[0086] Similarly, in some embodiments, the voltage transmitted by the third voltage line 23 is greater than the voltage transmitted by the fourth voltage line 24, the first end D1 of the second shielding unit 32 is electrically connected to the fourth voltage line 24, and the second end D2 of the second shielding unit 32 is electrically connected to the third voltage line 23. This design can prevent current from flowing from the third voltage line 23 to the fourth voltage line 24 during normal operation of the third voltage line 23 and the fourth voltage line 24, thereby meeting the needs of independent transmission of the signal voltages of the third voltage line 23 and the fourth voltage line 24.

[0087] Furthermore, in some optional embodiments, the voltage transmitted by the first voltage line 21 is greater than the voltage transmitted by the second voltage line 22, the first end D1 of the first shielding unit 31 is electrically connected to the second voltage line 22, and the second end D2 of the first shielding unit 31 is electrically connected to the first voltage line 21. Moreover, the voltage transmitted by the third voltage line 23 is greater than the voltage transmitted by the fourth voltage line 24, the first end D1 of the second shielding unit 32 is electrically connected to the fourth voltage line 24, and the second end D2 of the second shielding unit 32 is electrically connected to the third voltage line 23.

[0088] In some embodiments, the voltage transmitted by the first voltage line 21 and the voltage transmitted by the second voltage line 22 are both greater than 0V, and the voltage transmitted by the third voltage line 23 and the voltage transmitted by the fourth voltage line 24 are both less than 0V.

[0089] The present embodiment does not limit the specific values ​​of the voltage transmitted by the first voltage line 21 and the voltage transmitted by the second voltage line 22. For example, the voltage of the first high-voltage signal PWM-VGH transmitted by the first voltage line 21 can be 8V, and the voltage of the second high-voltage signal PAM-VGH transmitted by the second voltage line 22 can be 3V.

[0090] The present embodiment does not limit the specific values ​​of the voltage transmitted by the third voltage line 23 and the voltage transmitted by the fourth voltage line 24. For example, the voltage of the first ground voltage signal PWM-VGL transmitted by the third voltage line 23 can be -7V, and the voltage of the second low voltage signal PAM-VGL transmitted by the fourth voltage line 24 can be -12V.

[0091] In an embodiment of the present application, the voltage transmitted by the first voltage line 21 and the voltage transmitted by the second voltage line 22 are set to have the same polarity, so as to reduce the voltage difference between the first voltage line 21 and the second voltage line 22, thereby increasing the numerical difference between the voltage difference and the threshold voltage corresponding to the first shielding unit 31, reducing the adverse effect of the voltage difference between the first voltage line 21 and the second voltage line 22 on the electrostatic protection capability corresponding to the first shielding unit 31, and improving the reliability of electrostatic protection.

[0092] Similarly, the embodiment of the present application sets the voltage transmitted by the third voltage line 23 and the voltage transmitted by the fourth voltage line 24 to have the same polarity, thereby reducing the voltage difference between the third voltage line 23 and the fourth voltage line 24, thereby increasing the numerical difference between the voltage difference and the threshold voltage corresponding to the second shielding unit 32, reducing the adverse effect of the voltage difference between the third voltage line 23 and the fourth voltage line 24 on the corresponding electrostatic protection capability of the second shielding unit 32, and improving the reliability of electrostatic protection.

[0093] In some embodiments, the voltage difference between the first voltage line 21 and the second voltage line 22 is equal to the voltage difference between the third voltage line 23 and the fourth voltage line 24 .

[0094] In the embodiment of the present application, since the voltage difference between the two high-voltage signal lines is equal to the voltage difference between the two low-voltage signal lines, the first shielding unit 31 between the two high-voltage signal lines and the second shielding unit 32 between the two low-voltage signal lines can be set to have the same threshold voltage, thereby meeting the electrostatic protection needs of the two high-voltage signal lines and the two low-voltage signal lines. Furthermore, the first shielding unit 31 and the second shielding unit 32 can adopt the same structural design and the same material design, thereby reducing design difficulty and manufacturing cost.

[0095] In some embodiments, the voltage difference between the first voltage line 21 and the second voltage line 22 is C, where C satisfies 4V≤C≤6V. Alternatively, C is one of 4V, 4.5V, 5V, 5.5V, and 6V. Further, optionally, C is 5V.

[0096] In the embodiment of the present application, by setting the voltage difference C between the first voltage line 21 and the second voltage line 22 to no less than 4V, a certain voltage difference exists between the two, thereby reducing the risk of the voltage of the first voltage line 21 being lower than the voltage of the second voltage line 22 due to slight voltage fluctuations during normal operation of the first voltage line 21 and the second voltage line 22, thereby reducing the risk of abnormal conduction between the first voltage line 21 and the second voltage line 22 through the first shielding unit 31. At the same time, by setting the voltage difference C between the first voltage line 21 and the second voltage line 22 to no more than 6V, the impact of an excessive voltage difference on the first shielding unit 31 is reduced, thereby improving the electrostatic protection effect of the first shielding unit 31.

[0097] Similarly, in some optional embodiments, the voltage difference between the first voltage line 21 and the second voltage line 22 is D, and D satisfies 4V≤D≤6V. Optionally, D is one of 4V, 4.5V, 5V, 5.5V, and 6V.

[0098] In some embodiments, the voltage transmitted by the first voltage line 21 is greater than the voltage transmitted by the second voltage line 22, and the voltage transmitted by the third voltage line 23 is greater than the voltage transmitted by the fourth voltage line 24. The plurality of electrostatic shielding units 30 further include a third shielding unit 33, which is connected between the second voltage line 22 and the third voltage line 23.

[0099] The first shielding unit 31, the second shielding unit 32, and the third shielding unit 33 can all provide electrostatic protection. The first shielding unit 31, the second shielding unit 32, and the third shielding unit 33 can have the same structure or different structures, which is not limited in this embodiment of the present application. Optionally, the first shielding unit 31, the second shielding unit 32, and the third shielding unit 33 each include a transistor 40 equivalent to a diode structure.

[0100] In addition to the first shielding unit 31 and the second shielding unit 32, the embodiment of the present application further includes a third shielding unit 33, which is disposed between the second voltage line 22 and the third voltage line 23 to achieve electrostatic discharge between the second voltage line 22 and the third voltage line 23, thereby further improving the reliability of signal transmission on the second voltage line 22 and the third voltage line 23. Furthermore, the voltage transmitted by the second voltage line 22 is set different from the voltage transmitted by the third voltage line 23, so that there is a voltage difference between the two, thereby reducing the risk of direct conduction between the second voltage line 22 and the third voltage line 23 due to the third shielding unit 33. This design can improve the independent operation reliability of the first type gate drive circuit 11 and the second type gate drive circuit 12 while achieving the electrostatic protection function.

[0101] In some embodiments, see Figure 1 and Figure 11 The first type gate driving circuit 11 includes a plurality of shift registers V cascaded in a first direction X, the first voltage line 21 includes a first sub-segment 211 located on the same side of all pixel circuits P along the first direction X, the second voltage line 22 includes a second sub-segment 221 located on the same side of all pixel circuits P along the first direction X, and the electrostatic shielding unit 30 is connected to the first sub-segment 211 and the second sub-segment 221.

[0102] Multiple shift registers V are cascaded in a first direction X. In a display device, the first direction X may be a column direction. The first subsegment 211 is the portion of the first voltage line 21 located on the same side of all pixel circuits P in the first direction X. The second subsegment 221 is the portion of the second voltage line 22 located on the same side of all pixel circuits P in the first direction X. The first subsegment 211 and the second subsegment 221 may both extend along a second direction Y, with the first direction X, the second direction Y, and the thickness direction Z intersecting each other. Optionally, the first direction X, the second direction Y, and the thickness direction Z are perpendicular to each other.

[0103] The present embodiment does not limit the film layer position relationship between the first sub-segment 211 and the second sub-segment 221. For example, the first sub-segment 211 and the second sub-segment 221 can be provided in the same layer, i.e., they can be made of the same material and manufactured together in the same process. In other embodiments, the array substrate 100 includes a substrate, and the first sub-segment 211 can be located on the side of the second sub-segment 221 facing the substrate, or the first sub-segment 211 can be located on the side of the second sub-segment 221 facing away from the substrate.

[0104] In the embodiment of the present application, the electrostatic shielding unit 30 is connected between the first sub-segment 211 and the second sub-segment 221, so that the electrostatic shielding unit 30 can be located on the same side of all the pixel circuits P along the first direction X, thereby reducing the risk of physical interference between the electrostatic shielding unit 30 and the structures in the pixel circuit P and signal interference. In addition, the electrostatic shielding unit 30 under this design will not affect the relative arrangement between the multiple pixel circuits P, so it can be applied to the layout of conventional pixel circuits P and has strong practicality.

[0105] The embodiment of the present application does not limit the positional relationship of the electrostatic shielding unit 30 relative to the first sub-segment 211 and the second sub-segment 221. For example, the electrostatic shielding unit 30 can be located between the first sub-segment 211 and the second sub-segment 221, or the electrostatic shielding unit 30 can be located on the same side of the first sub-segment 211 and the second sub-segment 221 in the first direction X. Figure 11 FIG. 2 shows a situation where the electrostatic shielding unit 30 is located on the same side of the first sub-segment 211 and the second sub-segment 221 .

[0106] In other embodiments, Figure 1 and Figure 10 As shown, the first voltage line 21 includes a third sub-segment 212 located on the same side of all pixel circuits P along the second direction Y, the second voltage line 22 includes a fourth sub-segment 222 located on the same side of all pixel circuits P along the second direction Y, and the electrostatic shielding unit 30 is connected to the third sub-segment 212 and the fourth sub-segment 222.

[0107] In the display device, the second direction Y may be a row direction. The third sub-segment 212 is a portion of the first voltage line 21 located on the same side of all pixel circuits P in the second direction Y. The fourth sub-segment 222 is a portion of the second voltage line 22 located on the same side of all pixel circuits P in the second direction Y. The third sub-segment 212 and the fourth sub-segment 222 may both extend along the first direction X.

[0108] The present embodiment does not limit the film layer position relationship between the third sub-segment 212 and the fourth sub-segment 222. For example, the third sub-segment 212 and the fourth sub-segment 222 can be provided in the same layer, i.e., they can be made of the same material and manufactured together in the same process. In other embodiments, the array substrate 100 includes a substrate, and the third sub-segment 212 can be located on the side of the fourth sub-segment 222 facing the substrate, or the third sub-segment 212 can be located on the side of the fourth sub-segment 222 facing away from the substrate.

[0109] In addition, when the first voltage line 21 includes a first subsegment 211 and a third subsegment 212, the first subsegment 211 and the third subsegment 212 can be provided on the same layer, or they can be located in different film layers and connected by vias. When the second voltage line 22 includes a second subsegment 221 and a fourth subsegment 222, the second subsegment 221 and the fourth subsegment 222 can be provided on the same layer, or they can be located in different film layers and connected by vias.

[0110] In the embodiment of the present application, the electrostatic shielding unit 30 is connected between the third sub-segment 212 and the fourth sub-segment 222, so that the electrostatic shielding unit 30 can be located on the same side of all the pixel circuits P along the second direction Y, thereby reducing the risk of physical interference between the electrostatic shielding unit 30 and the structure in the pixel circuit P and signal interference. In addition, the electrostatic shielding unit 30 under this design will not affect the relative arrangement between multiple pixel circuits P, so it can be applied to the layout of conventional pixel circuits P and has strong practicality.

[0111] In some embodiments, see Figure 1 、 Figure 6 as well as Figure 12 The first voltage line 21 includes a first subsegment 211 located on the same side of all pixel circuits P along the first direction X. The second voltage line 22 includes a second subsegment 221 located on the same side of all pixel circuits P along the first direction X. The electrostatic shielding unit 30 is connected to the first subsegment 211 and the second subsegment 221. The plurality of pixel circuits P arranged in the second direction Y collectively constitute a circuit row. The array substrate 100 also includes a plurality of first electrodes 60 electrically connected to the plurality of pixel circuits P. The plurality of first electrodes 60 include a last electrode row 61 corresponding to the last circuit row P3. The electrostatic shielding unit 30 is located between the last electrode row 61 and the last circuit row P3.

[0112] The first direction X is the column direction, and the second direction Y is the row direction. Multiple pixel circuits P arranged in the second direction Y can together form a circuit row. The array substrate 100 includes multiple circuit rows, and the last circuit row P3 is the last circuit row among the multiple circuit rows and is located on the same side as the other circuit rows.

[0113] The first electrode 60 is a conductor structure on the array substrate 100 for bonding to the first electrode 41 of the light-emitting element F. Optionally, the array substrate 100 also includes a second electrode for bonding to the second electrode 42 of the light-emitting element F. The first electrode 60 is electrically connected to the pixel circuit P, while the second electrode transmits a third power supply voltage PVEE. The first electrode 41 of the light-emitting element F receives a signal voltage from the pixel circuit P via the first electrode 60, and the second electrode 42 receives the third power supply voltage PVEE via the second electrode. The first electrode 41 and the second electrode 42 jointly drive and control the light-emitting portion to achieve light emission.

[0114] The last electrode row 61 is a single electrode row composed of a plurality of first electrodes 60 arranged along the second direction Y, and the plurality of first electrodes 60 in the last electrode row 61 can be electrically connected to the plurality of pixel circuits P in the last circuit row P3 respectively, and can also be electrically connected to the first pole 41 portion of the last light-emitting element F, so as to realize the control needs of the last light-emitting element F corresponding to the last circuit row P3.

[0115] In an embodiment of the present application, the last electrode row 61 and the last circuit row P3 are spaced apart in the first direction X, and the electrostatic shielding unit 30 is located between the last electrode row 61 and the last circuit row P3. Normally, the position of the last electrode row 61 often corresponds to the position of the last light-emitting element F. Therefore, in the display device 200, the electrostatic shielding unit 30 will be located on the side of the last light-emitting element F facing the light-emitting elements F in other rows. In other words, the electrostatic shielding unit 30 will be located between adjacent rows of light-emitting elements F, rather than on the same side of all light-emitting elements F. This design enables the electrostatic shielding unit 30 to be integrated into the light-emitting area of ​​the display device 200, thereby reducing the impact of the electrostatic shielding unit 30 on the frame size and achieving a frameless display effect.

[0116] In some embodiments, see Figure 12 and Figure 13 The first voltage line 21 includes a first subsegment 211 located on the same side of all pixel circuits P along the first direction X. The second voltage line 22 includes a second subsegment 221 located on the same side of all pixel circuits P along the first direction X. The electrostatic shielding unit 30 connects the first subsegment 211 and the second subsegment 221. The first subsegment 211 and the second subsegment 221 are disposed adjacent to each other on the same layer. The term "adjacently disposed" here means that no other signal lines exist between the first subsegment 211 and the second subsegment 221 in the same film layer.

[0117] In the related art, the signal routing for transmitting the first high-voltage signal PWM-VGH and the signal routing for transmitting the first low-voltage signal PWM-VGL are often arranged adjacent to each other, and the signal routing for transmitting the second high-voltage signal PAM-VGH and the signal routing for transmitting the second low-voltage signal PAM-VGL are often arranged adjacent to each other.

[0118] However, in the embodiment of the present application, the first voltage line 21 for transmitting the first high-voltage signal PWM-VGH is not arranged adjacent to the third voltage line 23 for transmitting the first low-voltage signal PWM-VGL, and the second voltage line 22 for transmitting the second high-voltage signal PAM-VGH is not arranged adjacent to the fourth voltage line 24 for transmitting the second low-voltage signal PAM-VGL. In the embodiment of the present application, the first sub-segment 211 in the first voltage line 21 and the second sub-segment 221 in the second voltage line 22 are arranged adjacent to each other. This design helps to reduce the distance between the first voltage line 21 and the second voltage line 22, thereby reducing the difficulty of connecting the electrostatic shielding unit 30 relative to the first voltage line 21 and the second voltage line 22.

[0119] Similarly, in some other embodiments, the first voltage line 21 includes a third subsegment 212 located on the same side of all pixel circuits P along the second direction Y, the second voltage line 22 includes a fourth subsegment 222 located on the same side of all pixel circuits P along the second direction Y, and the electrostatic shielding unit 30 is connected to the third subsegment 212 and the fourth subsegment 222. The third subsegment 212 and the fourth subsegment 222 are disposed on the same layer and adjacent to each other.

[0120] In some embodiments, as Figure 12 and Figure 13 As shown, the array substrate 100 also includes a third voltage line 23 and a fourth voltage line 24. The first voltage line 21 and the second voltage line 22 transmit high-voltage signals to the first type of gate drive circuit 11 and the second type of gate drive circuit 12 respectively. The third voltage line 23 and the fourth voltage line 24 transmit low-voltage signals to the first type of gate drive circuit 11 and the second type of gate drive circuit 12 respectively. The voltage in the first voltage line 21 is greater than the voltage in the second voltage line 22, and the voltage transmitted by the third voltage line 23 is greater than the voltage transmitted by the fourth voltage line 24.

[0121] The multiple electrostatic shielding units 30 include a first shielding unit 31 and a second shielding unit 32. The first shielding unit 31 is connected between the first voltage line 21 and the second voltage line 22. The second shielding unit 32 is connected between the third voltage line 23 and the fourth voltage line 24. The third shielding unit 33 is connected between the second voltage line 22 and the third voltage line 23.

[0122] The third voltage line 23 includes a fifth subsegment 231 located on the same side of all pixel circuits P along the first direction X. The fourth voltage line 24 includes a sixth subsegment 241 located on the same side of all pixel circuits P along the first direction X. The second shielding unit 32 is connected to the fifth subsegment 231 and the sixth subsegment 241. The third shielding unit 33 is connected to the second subsegment 221 and the fifth subsegment 231. The first subsegment 211, the second subsegment 221, the fifth subsegment 231, and the sixth subsegment 241 are located on the same layer and are adjacent to each other in sequence along the first direction X.

[0123] The first subsegment 211 is used to transmit a first high-voltage signal PWM-VGH, the second subsegment 221 is used to transmit a second high-voltage signal PAM-VGH, the fifth subsegment 231 is used to transmit a first low-voltage signal PWM-VGL, and the sixth subsegment 241 is used to transmit a second low-voltage signal PAM-VGL. Typically, the first subsegment 211 and the fifth subsegment 231 are positioned adjacent to each other, and the second subsegment 221 and the sixth subsegment 241 are positioned adjacent to each other. However, in this embodiment, the positions of these four subsegments are adjusted so that the first subsegment 211, the second subsegment 221, the fifth subsegment 231, and the sixth subsegment 241 are positioned on the same layer and adjacent to each other in sequence along the first direction X. This helps reduce the distance between the first subsegment 211 and the second subsegment 221, thereby simplifying the connection between the first shielding unit 31 and the first and second subsegments 211 and 221. Furthermore, the distance between the fifth and sixth subsegments 231 and 241 is reduced, thereby simplifying the connection between the second shielding unit 32 and the fifth and sixth subsegments 231 and 241. At the same time, the distance between the second sub-segment 221 and the fifth sub-segment 231 is reduced, thereby reducing the difficulty of connecting the third shielding unit 33 relative to the second sub-segment 221 and the fifth sub-segment 231 .

[0124] Furthermore, since the first sub-segment 211 and the second sub-segment 221 are both located on the same side of the fifth sub-segment 231 and the sixth sub-segment 241 in the first direction X, the corresponding first shielding unit 31 and the second shielding unit 32 can be spaced apart in the first direction X, thereby reducing the risk of contact interference between the two. Furthermore, since the second sub-segment 221 and the fifth sub-segment 231 are both located between the first sub-segment 211 and the sixth sub-segment 241, the corresponding third shielding unit 33 can be located between the first shielding unit 31 and the second shielding unit 32 in the first direction X. This design can reduce contact interference between the three electrostatic shielding units 30 while allowing the first shielding unit 31, the third shielding unit 33, and the second shielding unit 32 to be arranged sequentially in the first direction X, thereby achieving a regular arrangement of the multiple electrostatic shielding units 30.

[0125] In some embodiments, see Figure 14The electrostatic shielding unit 30 includes an electrostatic shielding circuit, and the first sub-segment 211 and the second sub-segment 221 are both overlapped with the electrostatic shielding circuit in the thickness direction of the array substrate.

[0126] The electrostatic shielding circuit may be a circuit structure composed of multiple device structures. For example, the electrostatic shielding unit 30 may include a transistor 40. For example, Figure 8 As shown, the electrostatic shielding unit 30 may include two transistors 40, wherein the first electrode 41 and the control electrode 43 of one transistor 40 are both electrically connected to the first sub-segment 211, and the second electrode 42 is electrically connected to the ground. The first electrode 41 and the control electrode 43 of the other transistor 40 are both electrically connected to the ground, and the second electrode 42 is electrically connected to the second sub-segment 221.

[0127] Furthermore, in the embodiment of the present application, the first sub-segment 211 and the second sub-segment 221 are arranged to overlap with the electrostatic shielding circuit in the thickness direction of the array substrate, thereby reducing the difficulty of connecting the electrostatic shielding unit 30 relative to the first sub-segment 211 and the second sub-segment 221. Specifically, the transistor 40 connected to the first sub-segment 211 can overlap with the first sub-segment 211. This allows electrical connection between the two to be achieved through a short connecting trace, or through vias without any connecting traces, thereby simplifying the connection difficulty. Similarly, the transistor 40 connected to the second sub-segment 221 can overlap with the second sub-segment 221. This allows electrical connection between the two to be achieved through a short connecting trace, or through vias without any connecting traces, thereby simplifying the connection difficulty. This design can reduce the connection difficulty and shorten or even eliminate the connecting traces, thereby simplifying the wiring layout of the array substrate 100.

[0128] In some embodiments, see Figure 1 、 Figure 4 as well as Figure 15 The array substrate 100 further includes a third voltage line 23, a fourth voltage line 24, a first type of signal line 71, and a second type of signal line 72. The first type of signal line 71 is used to transmit a first type of control signal to the first type of gate drive circuit 11, and the second type of signal line 72 is used to transmit a second type of control signal to the second type of gate drive circuit 12. The first voltage line 21 and the second voltage line 22 transmit high-voltage signals to the first type of gate drive circuit 11 and the second type of gate drive circuit 12, respectively. The third voltage line 23 and the fourth voltage line 24 transmit low-voltage signals to the first type of gate drive circuit 11 and the second type of gate drive circuit 12, respectively.

[0129] The multiple electrostatic shielding units 30 include a first shielding unit 31 and a fourth shielding unit 34. The first shielding unit 31 is connected between the first voltage line 21 and the second voltage line 22. The fourth shielding unit 34 includes a first sub-unit 341 and a second sub-unit 342. The first sub-unit 341 is connected between the first voltage line 21 and the first type signal line 71, and the second sub-unit 342 is connected between the third voltage line 23 and the first type signal line 71. Alternatively, the first sub-unit 341 is connected between the second voltage line 22 and the second type signal line 72, and the second sub-unit 342 is connected between the fourth voltage line 24 and the second type signal line 72.

[0130] The first-type signal lines 71 transmit first-type control signals to the first-type gate drive circuit 11 to meet the operating requirements of the first-type gate drive circuit 11. The second-type signal lines 72 transmit second-type control signals to the second-type gate drive circuit 12 to meet the operating requirements of the second-type gate drive circuit 12. The specific types of the first-type control signals and the second-type control signals are not limited in this embodiment of the present application.

[0131] In addition to the electrostatic shielding unit 30 mentioned above, the embodiment of the present application may also be provided with a fourth shielding unit 34, which can reduce the adverse effects of static electricity on at least one of the first-class signal line 71 and the second-class signal line 72. Specifically, taking the fourth shielding unit 34 as an example of improving the electrostatic problem of the first-class signal line 71, considering that the first voltage line 21, the third voltage line 23 and the first-class signal line 71 are all electrically connected to the first-class gate drive circuit 11, the three signal lines are often arranged at a close distance. On this basis, if there is an electrostatic problem on the first voltage line 21 and the third voltage line 23, it is easy to have an adverse effect on the first-class signal line 71.

[0132] In view of this, in the embodiment of the present application, the fourth shielding unit 34 is configured to include a first sub-unit 341 and a second sub-unit 342. The first sub-unit 341 is connected between the first voltage line 21 and the first-class signal line 71 to achieve electrostatic discharge between the first voltage line 21 and the first-class signal line 71. The second sub-unit 342 is connected between the third voltage line 23 and the first-class signal line 71 to achieve electrostatic discharge between the third voltage line 23 and the first-class signal line 71. As a result, with the help of the first sub-unit 341 and the second sub-unit 342, the electrostatic protection effect of the first-class signal line 71 can be improved, the reliability of the signal transmission corresponding to the first-class signal line 71 can be enhanced, and the operation of the first-class gate driver circuit 11 and the display reliability of the display device 200 can be improved. The situation where the fourth shielding unit 34 is used to improve the electrostatic problem of the second-class signal line 72 is similar, and the embodiment of the present application will not be repeated.

[0133] In some alternative embodiments, see Figure 16 , the first subunit 341 and the second subunit 342 both include a transistor 40. On this basis, since the voltage transmitted by the first voltage line 21 is greater than the voltage transmitted by the first-class signal line 71, and the voltage transmitted by the first-class signal line 71 is greater than the voltage transmitted by the third-class signal line 23, the transistor 40 in the first subunit 341 can be configured to allow current to flow to the first-class signal line 71 via the third-class voltage line 23, and to prevent current from flowing to the third-class voltage line 23 via the first-class signal line 71, while the transistor 40 in the second subunit 342 can be configured to allow current to flow to the first-class signal line 21 via the first-class signal line 71, and to prevent current from flowing to the first-class signal line 71 via the first-class voltage line 21. In this way, while meeting the electrostatic protection requirements, the risk of the first-class signal line 71 being conductive between the first voltage line 21 and the third voltage line 23 in normal operation is reduced, thereby meeting the normal operation requirements of the first-class gate drive circuit 11.

[0134] In some embodiments, as Figure 1 、 Figure 4 as well as Figure 15 As shown, the multiple electrostatic shielding units 30 further include a fifth shielding unit 35, which includes a third sub-unit 351 and a fourth sub-unit 352. The first sub-unit 341 is connected between the first voltage line 21 and the first type signal line 71, and the second sub-unit 342 is connected between the third voltage line 23 and the first type signal line 71. The third sub-unit 351 is connected between the second voltage line 22 and the second type signal line 72, and the fourth sub-unit 352 is connected between the fourth voltage line 24 and the second type signal line 72.

[0135] The fourth shielding unit 34 is used to provide electrostatic protection for the first type signal line 71, and the fifth shielding unit 35 is used to provide electrostatic protection for the second type signal line 72. Similar to the fourth shielding unit 34, the fifth shielding unit 35 also includes two sub-unit structures. The third sub-unit 351 is connected between the second voltage line 22 and the second type signal line 72 to achieve electrostatic discharge between the second voltage line 22 and the second type signal line 72, and the fourth sub-unit 352 is connected between the fourth voltage line 24 and the second type signal line 72 to achieve electrostatic discharge between the fourth voltage line 24 and the second type signal line 72. With the help of the third sub-unit 351 and the fourth sub-unit 352, the electrostatic protection effect of the second type signal line 72 can be improved, the reliability of the corresponding signal transmission of the second type signal line 72 is enhanced, and the operation of the second type gate drive circuit 12 and the display reliability of the display device 200 are improved.

[0136] In the embodiment of the present application, the array substrate 100 is provided with a fourth shielding unit 34 and a fifth shielding unit 35, so that the electrostatic protection of the first type signal line 71 can be achieved with the help of the fourth shielding unit 34, and the electrostatic protection of the second type signal line 72 can be achieved with the help of the fifth shielding unit 35, thereby enhancing the reliability of the signal transmission of the first type signal line 71 and the second type signal line 72, further improving the operating reliability of the first type gate drive circuit 11 and the second type gate drive circuit 12, and enhancing the display accuracy and display effect of the display device 200.

[0137] In some embodiments, the first type of signal line 71 includes a first start line and a first clock line, the first start line is used to transmit a first start signal PWM-STV to the first type of gate drive circuit 11, and the first clock line is used to transmit a clock signal to the first type of gate drive circuit 11. And / or, the second type of signal line 72 includes a second start line and a second clock line, the second start line is used to transmit a second start signal PAM-STV to the first type of gate drive circuit 11, and the second clock line is used to transmit a clock signal to the first type of gate drive circuit 11.

[0138] The first start line and the second start line are respectively used to transmit corresponding start signals to the first type gate driver circuit 11 and the second type gate driver circuit 12, and the first clock line and the second start line are respectively used to transmit corresponding start and stop signals to the first type gate driver circuit 11 and the second type gate driver circuit 12. The first clock line can be used to transmit the first clock signal PWM-CKS or the second start and stop signal PWM-CKS, and the second clock line can be used to transmit the third clock signal PAM-CKS or the fourth clock signal PAM-XCKS, which is not limited in this embodiment of the present application.

[0139] In the embodiment of the present application, at least one of the first start line and the first clock line can be protected from electrostatic discharge by means of the fourth shielding unit 34, thereby improving the signal transmission reliability of at least one of the first start signal PWM-STV, the first clock signal PWM-CKS, and the second clock signal PWM-CKS. Furthermore, at least one of the second start line and the second clock line can be protected from electrostatic discharge by means of the fifth shielding unit 35, thereby improving the signal transmission reliability of at least one of the second start signal PAM-STV, the third clock signal PAM-CKS, and the fourth clock signal PAM-XCKS.

[0140] In some embodiments, see Figure 1 、 Figure 417 , the first type gate driving circuit 11 includes a plurality of shift registers V cascaded along a first direction X, and the fourth shielding unit 34 is located between adjacent shift registers V in the first type gate driving circuit 11 along the first direction X.

[0141] Part of the structure of the first type signal line 71 generally extends along the first direction X and is located on one side of the first type gate driving circuit 11 in the second direction Y. On this basis, as shown in FIG. Figure 17a As shown, in the embodiment of the present application, the fourth shielding unit 34 is disposed between adjacent shift registers V in the first-type gate driver circuit 11, so that the connection line between the fourth shielding unit 34 and the first-type signal line 71 does not need to cross the shift register V, thereby reducing the difficulty of connecting the fourth shielding unit 34 and the first-type signal line 71. Further optionally, there can be multiple fourth shielding units 34, and the multiple fourth shielding units 34 are located between different adjacent shift registers V in the first-type gate driver circuit 11.

[0142] In another embodiment, Figure 17b As shown, the fourth shielding unit 34 is located on one side of the first type gate driving circuit 11 along the second direction Y.

[0143] In the embodiment of the present application, the portion of the first-type signal line 71 extending along the first direction X and the fourth shielding unit 34 can be located on the same side of the first gate driver circuit in the second direction Y. In this way, the connection between the fourth shielding unit 34 and the first-type signal line 71 also does not need to cross the shift register V, thereby reducing the difficulty of connecting the fourth shielding unit 34 and the first-type signal line 71. Further optionally, there can be multiple fourth shielding units 34, and the multiple fourth shielding units 34 are located on the same side of the first-type gate driver circuit 11 in the second direction Y.

[0144] In some embodiments, as Figure 1 、 Figure 4 、 Figure 15 as well as Figure 16As shown, the first subunit 341 includes a first transistor 3411, and the second subunit 342 includes a second transistor 3421. The first electrode 41 and the control electrode 43 of the first transistor 3411 are both electrically connected to the first-type signal line 71, the second electrode 42 of the first transistor 3411 is both electrically connected to the second voltage line 22, the first electrode 41 and the control electrode 43 of the second transistor 3421 are both electrically connected to the first voltage line 21, and the second electrode 42 of the first transistor 3411 is both electrically connected to the first-type signal line 71. The active structures of at least some of the transistors 40 in the first-type gate drive circuit 11 are integrally connected to the active structures of the first transistor 3411; and / or the active structures of at least some of the transistors 40 in the first-type gate drive circuit 11 are integrally connected to the active structures of the second transistor 3421; and / or the active structures of the first transistor 3411 are integrally connected to the active structures of the second transistor 3421.

[0145] The first subunit 341 and the second subunit 342 in the fourth shielding unit 34 respectively include a first transistor 3411 and a second transistor 3421. The number of the first transistor 3411 and the second transistor 3421 can be multiple. For example, the control electrode 43 and the first electrode 41 of some first transistors 3411 are electrically connected to the third voltage line 23, and the second electrode 42 is electrically connected to the ground signal. The control electrode 43 and the first electrode 41 of other first transistors 3411 are electrically connected to the ground signal, and the second electrode 42 is electrically connected to the first type signal line 71. Thus, with the cooperation of the multiple first transistors 3411, static electricity discharge between the first type signal line 71 and the third voltage line 23 can be achieved. The multiple second transistors 3421 in the second subunit 342 can be similarly applied, and will not be further described in detail in the present embodiment.

[0146] For the case where both the first sub-unit 341 and the second sub-unit 342 include the transistor 40, the embodiment of the present application can selectively connect the active structure of the first transistor 3411 and the active structure of the second transistor 3421 into one, that is, the active structures of the two include the same material and are formed together in the same process, thereby simplifying the preparation difficulty of the first transistor 3411 and the second transistor 3421 and improving the preparation efficiency.

[0147] In addition, considering that the first type of gate drive circuit 11 also includes a transistor 40, the embodiment of the present application can also selectively set the active structure of the transistor 40 in the first type of gate drive circuit 11 to be connected to the active structure of the first transistor 3411 as an integral setting, or to be connected to the active structure of the second transistor 3421 as an integral setting. This simplifies the manufacturing difficulty and improves the manufacturing efficiency. Optionally, the active structure of the transistor 40 in the second type and the third type drive circuit can also be connected to the active structure of at least one of the first transistor 3411 and the second transistor 3421 as an integral setting.

[0148] Second, as Figure 6 As shown, an embodiment of the present application provides a display device 200 , which includes the array substrate 100 in any of the aforementioned embodiments.

[0149] It should be noted that the display device 200 provided in the embodiment of the present application has the beneficial effects of the array substrate 100 in any of the aforementioned embodiments. Please refer to the aforementioned description of the beneficial effects of the array substrate 100 for details, and the embodiment of the present application will not be repeated.

[0150] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit the present invention. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of protection of this application shall still be based on the scope defined by the appended claims.

[0151] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited to this. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the scope of protection of this application.

Claims

1. An array substrate, characterized in that: The array substrate includes a plurality of pixel circuits, each pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit, and the array substrate further includes: A first type gate drive circuit is used to transmit a control signal to the pulse width modulation sub-circuit; A second type of gate drive circuit, configured to transmit a control signal to the amplitude modulation sub-circuit; a first voltage line and a second voltage line, wherein the first voltage line and the second voltage line transmit high voltage signals to the first type of gate driving circuit and the second type of gate driving circuit, respectively, or the first voltage line and the second voltage line transmit low voltage signals to the first type of gate driving circuit and the second type of gate driving circuit, respectively; an electrostatic shielding unit, at least a portion of which is connected between the first voltage line and the second voltage line; The voltage transmitted by the first voltage line is different from the voltage transmitted by the second voltage line.

2. The array substrate according to claim 1, wherein: The electrostatic shielding unit has a first end and a second end, one of the first end and the second end is electrically connected to the first voltage line, and the other is electrically connected to the second voltage line; The electrostatic shielding unit includes a transistor, the transistor includes a first electrode, a second electrode and a control electrode, the control electrode controls the conduction or disconnection of the first electrode and the second electrode, and the first electrode and the control electrode are electrically connected; The control electrodes of at least some of the transistors are electrically connected to the first end, and the second electrodes of at least some of the transistors are electrically connected to the second end.

3. The array substrate according to claim 1, wherein: The electrostatic shielding unit includes a first discharge pattern and a second discharge pattern, wherein the first discharge pattern and the second discharge pattern each include a connecting end and a discharging end opposite to each other, and the width of the discharge pattern gradually decreases in a direction from the connecting end to the discharging end; The connection end of the first discharge pattern is electrically connected to the first voltage line, and the connection end of the second discharge pattern is electrically connected to the second voltage line.

4. The array substrate according to claim 1, wherein: The system further includes a third voltage line and a fourth voltage line, wherein the first voltage line and the second voltage line transmit high-voltage signals to the first type of gate drive circuit and the second type of gate drive circuit, respectively, and the third voltage line and the fourth voltage line transmit low-voltage signals to the first type of gate drive circuit and the second type of gate drive circuit, respectively, and the voltage transmitted by the third voltage line is different from the voltage transmitted by the fourth voltage line; The plurality of electrostatic shielding units include a first shielding unit and a second shielding unit, the first shielding unit is connected between the first voltage line and the second voltage line, and the second shielding unit is connected between the third voltage line and the fourth voltage line.

5. The array substrate according to claim 4, wherein: The electrostatic shielding unit includes a first end and a second end, and the electrostatic shielding unit is configured to allow current to flow toward the second end via the first end and to prevent current from flowing toward the first end via the second end; The voltage transmitted by the first voltage line is greater than the voltage transmitted by the second voltage line, the first end of the first shielding unit is electrically connected to the second voltage line, and the second end of the first shielding unit is electrically connected to the first voltage line; and / or, The voltage transmitted by the third voltage line is greater than the voltage transmitted by the fourth voltage line. The first end of the first shielding unit is electrically connected to the fourth voltage line, and the second end of the first shielding unit is electrically connected to the third voltage line.

6. The array substrate according to claim 5, wherein: The voltage transmitted by the first voltage line and the voltage transmitted by the second voltage line are both greater than 0V, and the voltage transmitted by the third voltage line and the voltage transmitted by the fourth voltage line are both less than 0V.

7. The array substrate according to claim 5, wherein: A voltage difference between the first voltage line and the second voltage line is equal to a voltage difference between the third voltage line and the fourth voltage line.

8. The array substrate according to claim 5, wherein: The voltage difference between the first voltage line and the second voltage line is C, and C satisfies 4v≤C≤6v.

9. The array substrate according to claim 4, wherein: The voltage transmitted by the first voltage line is greater than the voltage transmitted by the second voltage line, and the voltage transmitted by the third voltage line is greater than the voltage transmitted by the fourth voltage line; The plurality of electrostatic shielding units further include a third shielding unit connected between the second voltage line and the third voltage line.

10. The array substrate according to claim 1, wherein: The first type of gate driving circuit includes a plurality of shift registers cascaded in a first direction, the first voltage line includes a first subsegment located on a same side of all the pixel circuits along the first direction, the second voltage line includes a second subsegment located on a same side of all the pixel circuits along the first direction, and the electrostatic shielding unit is connected to the first subsegment and the second subsegment; or The first voltage line includes a third sub-segment located on the same side of all the pixel circuits along the second direction, the second voltage line includes a fourth sub-segment located on the same side of all the pixel circuits along the second direction, the electrostatic shielding unit is connected to the third sub-segment and the fourth sub-segment, and the first direction intersects with the second direction.

11. The array substrate according to claim 10, wherein: The first voltage line includes a first subsegment located on a same side of all the pixel circuits along the first direction, the second voltage line includes a second subsegment located on a same side of all the pixel circuits along the first direction, and the electrostatic shielding unit is connected to the first subsegment and the second subsegment; The plurality of pixel circuits arranged in the second direction together constitute a circuit row, the first direction intersects the second direction, the array substrate further comprises a plurality of first electrodes electrically connected to the plurality of pixel circuits, the plurality of first electrodes comprising a last electrode row corresponding to the last circuit row, and the electrostatic shielding unit is located between the last electrode row and the last circuit row.

12. The array substrate according to claim 10, wherein: The first voltage line includes a first subsegment located on a same side of all the pixel circuits along the first direction, the second voltage line includes a second subsegment located on a same side of all the pixel circuits along the first direction, and the electrostatic shielding unit is connected to the first subsegment and the second subsegment; The first sub-segment and the second sub-segment are on the same layer and are adjacent to each other.

13. The array substrate according to claim 12, wherein: The system further includes a third voltage line and a fourth voltage line, wherein the first voltage line and the second voltage line transmit high-voltage signals to the first type of gate drive circuit and the second type of gate drive circuit, respectively, and the third voltage line and the fourth voltage line transmit low-voltage signals to the first type of gate drive circuit and the second type of gate drive circuit, respectively, wherein the voltage in the first voltage line is greater than the voltage in the second voltage line, and the voltage transmitted by the third voltage line is greater than the voltage transmitted by the fourth voltage line; The plurality of electrostatic shielding units include a first shielding unit, a second shielding unit, and a third shielding unit, wherein the first shielding unit is connected between the first voltage line and the second voltage line, the second shielding unit is connected between the third voltage line and the fourth voltage line, and the third shielding unit is connected between the second voltage line and the third voltage line; The third voltage line includes a fifth subsegment located on a common side of all the pixel circuits along the first direction, the fourth voltage line includes a sixth subsegment located on a common side of all the pixel circuits along the first direction, the second shielding unit is connected to the fifth subsegment and the sixth subsegment, and the third shielding unit is connected to the second subsegment and the fifth subsegment; The first sub-segment, the second sub-segment, the fifth sub-segment and the sixth sub-segment are in the same layer and are arranged adjacent to each other in sequence along the first direction.

14. The array substrate according to claim 12, wherein: The electrostatic shielding unit includes an electrostatic shielding circuit, and the first sub-segment and the second sub-segment are both arranged to overlap with the electrostatic shielding circuit in a thickness direction of the array substrate.

15. The array substrate according to claim 1, wherein: The invention also includes a third voltage line, a fourth voltage line, a first type of signal line and a second type of signal line, wherein the first type of signal line is used to transmit a first type of control signal to the first type of gate drive circuit, and the second type of signal line is used to transmit a second type of control signal to the second type of gate drive circuit; The first voltage line and the second voltage line transmit high voltage signals to the first type gate driving circuit and the second type gate driving circuit respectively, and the third voltage line and the fourth voltage line transmit low voltage signals to the first type gate driving circuit and the second type gate driving circuit respectively; The plurality of electrostatic shielding units include a first shielding unit and a fourth shielding unit, the first shielding unit is connected between the first voltage line and the second voltage line, and the fourth shielding unit includes a first sub-unit and a second sub-unit; In which, the first sub-unit is connected between the first voltage line and the first type of signal line, and the second sub-unit is connected between the third voltage line and the first type of signal line; or, the first sub-unit is connected between the second voltage line and the second type of signal line, and the second sub-unit is connected between the fourth voltage line and the second type of signal line.

16. The array substrate according to claim 15, wherein: The plurality of electrostatic shielding units further include a fifth shielding unit, wherein the fifth shielding unit includes a third subunit and a fourth subunit; Among them, the first sub-unit is connected between the first voltage line and the first type of signal line, the second sub-unit is connected between the third voltage line and the first type of signal line; the third sub-unit is connected between the second voltage line and the second type of signal line, and the fourth sub-unit is connected between the fourth voltage line and the second type of signal line.

17. The array substrate according to claim 15, wherein: The first type of signal line includes a first start line and a first clock line, the first start line is used to transmit a first start signal to the first type of gate driving circuit, and the first clock line is used to transmit a clock signal to the first type of gate driving circuit; and / or, The second type of signal line includes a second start line and a second clock line. The second start line is used to transmit a second start signal to the first type of gate driving circuit, and the second clock line is used to transmit a clock signal to the first type of gate driving circuit.

18. The array substrate according to claim 15, wherein: The first type of gate driving circuit includes a plurality of shift registers cascaded along a first direction, and the fourth shielding unit is located between adjacent shift registers in the first type of gate driving circuit along the first direction; or, the fourth shielding unit is located on one side of the first type of gate driving circuit along a second direction, and the first direction intersects with the second direction.

19. The array substrate according to claim 15, wherein: The first subunit includes a first transistor, and the second subunit includes a second transistor, wherein a first electrode and a control electrode of the first transistor are both electrically connected to the first-type signal line, a second electrode of the first transistor is both electrically connected to the second voltage line, a first electrode and a control electrode of the second transistor are both electrically connected to the first voltage line, and a second electrode of the first transistor is both electrically connected to the first-type signal line; In which, the active structure of at least some transistors in the first type of gate drive circuit is connected to the active structure of the first transistor as an integral whole; and / or, the active structure of at least some transistors in the first type of gate drive circuit is connected to the active structure of the second transistor as an integral whole; and / or, the active structure of the first transistor is connected to the active structure of the second transistor as an integral whole.

20. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 19.

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