Decoding method and device based on error correction code and storage medium

Abstract

The invention discloses a decoding method and device based on an error correction code and a storage medium, and relates to the technical field of memorizers, and the method comprises the steps: determining a storage unit corresponding to a target code word as a first storage unit when the target code word which cannot be decoded exists, and determining a storage unit adjacent to the first storage unit as a second storage unit; determining a voltage difference between the first storage unit and the second storage unit according to the first state code word of the first storage unit and the second state code word of the second storage unit; if the voltage difference is greater than a preset voltage difference threshold, adjusting an initial log-likelihood ratio of the first storage unit to obtain a target log-likelihood ratio; and performing iterative decoding according to the target log-likelihood ratio and a preset error correction code algorithm to obtain a decoding result of the target code word. By reducing the log-likelihood ratio deviation, iterative decoding can be more effectively converged to correct code words, and the bit error rate is reduced.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a decoding method, device, and storage medium based on an error correction code. Background Art

[0002] When processing undecodable codewords, soft decoding is typically performed based on a log-likelihood ratio conversion table and an error correction code algorithm. Soft decoding uses the log-likelihood ratio to quantify the degree of match between the received signal and the expected state. The more accurate the log-likelihood ratio value, the more confident the decoder is in its judgment of the signal's reliability. However, when programming or reading adjacent memory cells, their voltage states can affect each other, causing the read voltage of the target cell to shift. This voltage shift can cause deviations in the log-likelihood ratio calculation. For example, if the actual voltage of the target cell is raised, the log-likelihood ratio may erroneously indicate that the cell is closer to a high voltage state, causing the decoding result to deviate from the actual state, thereby reducing decoding accuracy.

[0003] The above content is only used to assist in understanding the technical solution of this application and does not constitute an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of this application is to provide a decoding method, storage device and storage medium based on error correction code, aiming to solve the technical problem that the inter-unit interference phenomenon causes the soft decoding result to deviate from the true state, thereby reducing the decoding accuracy.

[0005] To achieve the above objectives, the present application proposes a decoding method based on an error correction code, the method comprising:

[0006] When there is a target codeword that cannot be decoded, the storage unit corresponding to the target codeword is determined as the first storage unit, and the storage unit adjacent to the first storage unit is determined as the second storage unit;

[0007] determining a voltage difference between the first storage unit and the second storage unit according to a first state code word of the first storage unit and a second state code word of the second storage unit;

[0008] If the voltage difference is greater than a preset voltage difference threshold, adjusting the initial log-likelihood ratio of the first storage unit to obtain a target log-likelihood ratio;

[0009] Iterative decoding is performed according to the target log-likelihood ratio and a preset error correction code algorithm to obtain a decoding result of the target codeword.

[0010] In one embodiment, the step of identifying the storage unit adjacent to the first storage unit as the second storage unit includes:

[0011] determining adjacent storage units of the first storage unit;

[0012] Adjacent storage units whose data writing order is later than the data writing order of the first storage unit are determined as second storage units, and the number of the second storage units is one or more.

[0013] In one embodiment, the step of determining the voltage difference between the first storage unit and the second storage unit according to the first state code word of the first storage unit and the second state code word of the second storage unit includes:

[0014] According to a preset conversion table, the first state codeword is mapped to a first voltage, and the second state codeword is mapped to a second voltage;

[0015] A voltage difference is determined based on the first voltage and the second voltage.

[0016] In one embodiment, the step of determining the voltage difference according to the first voltage and the second voltage includes:

[0017] When the number of the second storage units is greater than one, determining a weight coefficient of each second storage unit according to positions of the second storage unit and the first storage unit;

[0018] The voltage difference is determined according to the difference between the product of each second voltage and the corresponding weight coefficient and the first voltage.

[0019] In one embodiment, the step of determining the first state codeword of the first storage unit based on the soft decision result and likelihood information of the first storage unit includes:

[0020] In a first page state of a first memory cell, a first soft bit codeword is read according to a first left bias voltage value group and a first right bias voltage group, and a second soft bit codeword is read according to a second left bias voltage value group and a second right bias voltage group;

[0021] Obtaining first likelihood information in other page forms of the first storage unit;

[0022] Determining a high state, a middle state, and a low state of the first storage unit according to the first soft bit codeword, the second soft bit codeword, and the first likelihood information;

[0023] The high state, the middle state, and the low state are combined into a first state codeword.

[0024] In one embodiment, after the step of combining the high state, the middle state, and the low state into the first state codeword, the method further includes:

[0025] Sending a read command to the second storage unit to obtain a voltage value of the second storage unit;

[0026] Comparing the voltage value of the second storage unit with a preset voltage threshold, and determining a range of the voltage value of the second storage unit according to the comparison result;

[0027] A second state code word corresponding to the second storage unit is determined according to the range.

[0028] In one embodiment, the step of adjusting the initial log-likelihood ratio of the first storage unit to obtain the target log-likelihood ratio includes:

[0029] Obtaining a correction value corresponding to the voltage difference;

[0030] The target log-likelihood ratio is determined based on the initial log-likelihood ratio and the correction value.

[0031] In one embodiment, the step of adjusting the initial log-likelihood ratio of the first storage unit to obtain the target log-likelihood ratio includes:

[0032] When the voltage difference is negative and less than a preset first threshold, a target log-likelihood ratio is obtained according to the difference between the initial log-likelihood ratio and the corrected value;

[0033] When the voltage difference is positive and greater than a preset second threshold, a target log-likelihood ratio is obtained according to the sum of the initial log-likelihood ratio and the correction value.

[0034] In addition, to achieve the above-mentioned purpose, the present application also proposes a decoding device based on an error correction code, and the above-mentioned decoding device based on an error correction code includes: a memory, a processor, and a computer program stored on the above-mentioned memory and executable on the above-mentioned processor, and the above-mentioned computer program is configured to implement the steps of the decoding method based on the error correction code as described above.

[0035] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium. A computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the decoding method based on the error correction code as described above are implemented.

[0036] The present application provides a decoding method based on an error correction code, in which the storage unit corresponding to the target codeword that cannot be decoded is confirmed as the first storage unit, and the storage unit adjacent to the first storage unit is confirmed as the second storage unit. By obtaining the voltage difference between the first storage unit and the second storage unit, the degree of voltage offset caused by the inter-unit interference phenomenon is determined. If the voltage difference is greater than the preset voltage difference threshold, the log-likelihood ratio adjustment is triggered. By obtaining the voltage difference between the first storage unit and the second storage unit, the inter-unit interference phenomenon is converted into a measurable physical indicator. The larger the voltage difference, the stronger the charge coupling effect between adjacent units and the more serious the interference. When the voltage difference is greater than the preset voltage difference threshold, the log-likelihood ratio adjustment is triggered to correct the distorted log-likelihood ratio. The adjusted log-likelihood ratio can more accurately reflect the true signal state and reduce misjudgment caused by interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1 A flowchart of the first embodiment of the decoding method based on error correction code of the present application is provided;

[0040] Figure 2 A structural diagram of a flash memory device provided for the decoding method based on error correction codes of this application;

[0041] Figure 3 Another structural diagram of a flash memory device provided for the decoding method based on error correction code of this application;

[0042] Figure 4 A voltage distribution diagram provided for the decoding method based on error correction code of this application;

[0043] Figure 5 A flowchart of the second embodiment of the decoding method based on error correction code of the present application is provided;

[0044] Figure 6 A flowchart of the third embodiment of the decoding method based on error correction code of the present application is provided;

[0045] Figure 7 A corresponding relationship diagram of log-likelihood ratios provided for the decoding method based on error correction codes of this application;

[0046] Figure 8 Schematic diagram of the device structure of the hardware operating environment involved in the decoding method based on error correction code in the embodiment of the present application. DETAILED DESCRIPTION

[0047] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0048] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0049] The main solution of the embodiment of the present application is: when there is a target codeword that cannot be decoded, the storage unit corresponding to the target codeword is confirmed as the first storage unit, and the storage unit adjacent to the first storage unit is confirmed as the second storage unit; based on the first state codeword of the first storage unit and the second state codeword of the second storage unit, the voltage difference between the first storage unit and the second storage unit is determined; if the voltage difference is greater than a preset voltage difference threshold, the initial log-likelihood ratio of the first storage unit is adjusted to obtain a target log-likelihood ratio; iterative decoding is performed based on the target log-likelihood ratio and a preset error correction code algorithm to obtain a decoding result of the target codeword.

[0050] When processing undecodeable codewords, soft decoding is typically performed based on a log-likelihood ratio conversion table and an error correction code algorithm. Soft decoding uses the log-likelihood ratio to quantify the degree of match between the received signal and the expected state. The more accurate the log-likelihood ratio, the more confident the decoder is in its judgment of the signal's reliability. However, when programming or reading adjacent memory cells, their voltage states can affect each other, causing the read voltage of the target cell to shift. This voltage shift can cause deviations in the log-likelihood ratio calculation. For example, if the actual voltage of the target cell is raised, the log-likelihood ratio may erroneously indicate that the cell is closer to a high voltage state, causing the decoder's decoding result to deviate from the actual state, thereby reducing decoding accuracy.

[0051] In order to solve the above problems, the present application provides a decoding method based on an error correction code, in which the storage unit corresponding to the target codeword that cannot be decoded is confirmed as the first storage unit, and the storage unit adjacent to the first storage unit is confirmed as the second storage unit. By obtaining the voltage difference between the first storage unit and the second storage unit, the degree of voltage offset caused by the inter-unit interference phenomenon is determined. If the voltage difference is greater than the preset voltage difference threshold, the log-likelihood ratio adjustment is triggered. By obtaining the voltage difference between the first storage unit and the second storage unit, the inter-unit interference phenomenon is converted into a measurable physical indicator. The larger the voltage difference, the stronger the charge coupling effect between adjacent units and the more serious the interference. When the voltage difference is greater than the preset voltage difference threshold, the log-likelihood ratio adjustment is triggered to correct the distorted log-likelihood ratio. The adjusted log-likelihood ratio can more accurately reflect the true signal state and reduce misjudgment caused by interference.

[0052] It should be noted that the execution subject of this embodiment may be a computing service device with network communication and program execution functions, such as a tablet computer, personal computer, mobile phone, Nandflash and its corresponding controller, SSD and its corresponding controller, etc., or an electronic device or device capable of implementing the above functions. The controller of a flash memory storage device is used as an example to illustrate this embodiment and the following embodiments.

[0053] Based on this, the embodiment of the present application provides a decoding method based on error correction code, referring to Figure 1 , Figure 1 This is a flowchart of the first embodiment of the decoding method based on error correction code of the present application.

[0054] In this embodiment, the above-mentioned decoding method based on error correction code includes steps S10 to S40:

[0055] Step S10 : When there is a target codeword that cannot be decoded, the storage unit corresponding to the target codeword is identified as a first storage unit, and the storage unit adjacent to the first storage unit is identified as a second storage unit.

[0056] It should be noted that the target codeword that cannot be decoded refers to a storage unit data combination that cannot be restored to the original data through a normal decoding algorithm.

[0057] In this embodiment, the preset LLR conversion table is compensated according to the voltage difference between adjacent storage cells. When processing an undecodeable target codeword, the storage cells adjacent to it are first determined. The first storage cell and the second storage cell are adjacent in physical position inside the flash memory chip, which can be adjacent in the same page, adjacent in the same block, or adjacent in blocks. For example, please refer to Figure 2 , the red storage unit in the middle is the first storage unit, and the second storage unit includes: 9 storage units in the previous block (ex: Block1), the other 8 storage units in its own block (ex: Block2), and 9 storage units in the next block (ex: Block3), with a total of 25 adjacent storage units.

[0058] When determining adjacent storage units, first, a logical address (such as an address in the file system) is input. The physical address corresponding to the first storage unit is then searched through the FTL (Flash Translation Layer). For example, logical address LBA 1000 is mapped to physical address (Block 3, Page 12, Byte 512, Bit 0). Next, adjacent addresses are calculated based on the physical layout rules of the flash memory. For adjacent bits within the same page, the physical address bit is offset by +1 to obtain the adjacent bit address; the adjacent bit of the physical address (Block 3, Page 12, Byte 512, Bit 0) is (Block 3, Page 12, Byte 512, Bit 1). For adjacent pages within the same block, the physical address page number is increased by 1, and the byte offset is reset to 0. The adjacent page of the physical address (Block 3, Page 12, Byte 512, Bit 0) is (Block 3, Page 13, Byte 0, Bit 0).

[0059] In a preferred embodiment, step S10, when there is a target codeword that cannot be decoded, confirming the storage unit corresponding to the target codeword as the first storage unit, and confirming the storage unit adjacent to the first storage unit as the second storage unit includes the following steps: determining the adjacent storage units of the first storage unit; and determining the adjacent storage units whose data is written later than the first storage unit as the second storage units, where the number of the second storage units is one or more.

[0060] It's important to note that flash memory writes are sequential. Each time a single page or word line (WL) is written, it uses the Incremental Step Pulse Program (ISPP) write technique, which involves applying voltage, checking, then applying voltage again, and checking again to ensure that the current write reaches the correct voltage. Therefore, by the sixth write, the impact of the voltages from the first, second, third, and fifth writes is eliminated by the ISPP. However, previously written data will be affected by subsequent writes.

[0061] In this embodiment, the second storage unit is a storage unit adjacent to the first storage unit and has data written later than the first storage unit. The data writing order of the storage units can be obtained by analyzing the erase count of the physical block, tracking the mapping history of logical addresses to physical addresses, or using the write timestamp of the flash memory.

[0062] For example, please refer to Figure 3 , the first storage unit is Block2, WL[X], Cell[i]. The second storage unit is one or more of 2 Block2, WL[X], 3 Block3, WL[X], 3 Block1, WL[X+1], 3 Block2, WL[X+1], and 3 Block3, WL[X+1], a total of 15 adjacent storage units.

[0063] Optionally, the erase count of each physical block can be analyzed. Flash memory metadata can be read to obtain the erase count of each block. Pages in blocks with fewer erase counts are likely written earlier, while pages in blocks with more erase counts are likely written later.

[0064] Optionally, track the mapping history of logical addresses to physical addresses. Track changes in logical address mapping through FTL logs or snapshots. Export the FTL log through the debug interface or firmware update tool provided by the flash controller. Identify key events in the log, including: changes in the mapping of logical addresses to physical addresses, the time when the block was erased and the logical addresses involved, and operation records of page copying and block release. Sort the mapping update events by the timestamp in the log, track the time when each logical address was first mapped to the physical address, and infer the write order. Combine block erase and garbage collection at the same time, analyze block erase events, and determine the block usage cycle. Identify the impact of page copying and block release on the write order through garbage collection records. Establish a complete chain of logical address → physical address → write time.

[0065] Optionally, the data writing order is determined using the write timestamp of the flash memory. The metadata of the page or block is read to obtain the write timestamp, and the data is sorted according to the timestamp to determine the write order.

[0066] Step S20 , determining a voltage difference between the first storage unit and the second storage unit according to the first state code word of the first storage unit and the second state code word of the second storage unit.

[0067] It should be noted that the status code word (Status Code Word) is used to indicate the current status or error information of the storage unit.

[0068] In this embodiment, the state of the state code word of the storage cell is analyzed to calculate the voltage difference between the first storage cell and the second storage cell. If the voltage represented by the first code word of the first storage cell is lower than the voltage represented by the second state code word of the adjacent second storage cell, it indicates that the voltage value of the second storage cell is higher, and the actual value written to the second storage cell may be lower.

[0069] Step S30 : If the voltage difference is greater than the preset voltage difference threshold, the initial log-likelihood ratio of the first storage unit is adjusted to obtain a target log-likelihood ratio.

[0070] It should be noted that the cell-to-cell interference phenomenon in flash memory is closely related to the voltage state of adjacent cells. Figure 4When a memory cell has a low voltage (e.g., in the ER / A / B state) and an adjacent memory cell has a high voltage (e.g., in the E / F / G state), its own voltage will be slightly increased. Conversely, if a memory cell has a high voltage (e.g., in the E / F / G state) and an adjacent memory cell has a low voltage (e.g., in the ER / A / B state), its own voltage will be slightly decreased. This disturbance is treated as a direct error during hard decoding. However, if errors become frequent and soft decoding is used, cell-to-cell interference will affect the confidence of the soft decoding.

[0071] In addition, it should be noted that the log-likelihood ratio (LLR) value represents the log-likelihood ratio of a bit being 1 or 0 and is used in the soft decoding algorithm. The LLR table is a pre-calculated lookup table used to map the input soft message codeword to the corresponding LLR value.

[0072] In this embodiment, the preset voltage difference threshold can be determined based on the physical characteristics of the flash memory storage unit, or an inter-unit interference model can be established to analyze the impact of the adjacent storage unit operation on the current storage unit voltage. By experimentally measuring the voltage changes under different interference conditions, it is determined at what voltage difference the inter-unit interference begins to have a significant impact on the read data. When the voltage difference is less than or equal to the preset voltage difference threshold, it is considered that the voltage difference between the first storage unit and the second storage unit is not obvious. The inter-unit interference is relatively small, and the read voltage value can already well reflect the stored data. At this time, the initial log-likelihood ratio is not adjusted. When the voltage difference is greater than the preset voltage difference threshold, by adjusting the initial log-likelihood ratio, the error correction algorithm can reduce the read error rate to within the target range, thereby more accurately evaluating the degree of match between the received signal and different possible transmitted bits, thereby improving the accuracy of bit judgment.

[0073] Step S40 , performing iterative decoding according to the target log-likelihood ratio and a preset error correction code algorithm to obtain a decoding result of the target codeword.

[0074] In this embodiment, a target log-likelihood ratio is input into a variable node in an LDPC code (Error Correction Code) algorithm. Based on the target log-likelihood ratio and the connection relationship between its connected check nodes, the variable node calculates a message to be sent to each connected check node. These messages contain preliminary information about the variable node's own data bits, which is used in subsequent verification and error correction processes. After receiving the message from the connected variable node, the check node processes it according to a pre-set check equation. The check equation is a rule used in LDPC codes to verify data correctness, which specifies the specific relationship between the variable node and the check node. Based on the received message and the check equation, the check node calculates a message to be sent to each connected variable node. The check node analyzes the received message to determine whether the data bit represented by the variable node satisfies the check equation. If not, the check node generates a corresponding message based on the check equation, notifying the variable node of a possible error and providing information on how to correct the error. These messages are passed to the variable node as feedback for subsequent iterative updates. During each iteration, the variable node receives a new message from the connected check node. Based on these new messages and its previously stored log-likelihood ratio values, the variable node recalculates the message to be sent to the connected check node. It also updates its stored log-likelihood ratio values ​​based on the newly received messages. After multiple iterations, the log-likelihood ratio values ​​gradually stabilize, more accurately reflecting the likelihood of the data bits in the storage cells. Based on the final log-likelihood ratios, a hard decision is made. If the final log-likelihood ratio is positive, the data bit stored in that storage cell is determined to be 0; if the final log-likelihood ratio is negative, the data bit stored in that storage cell is determined to be 1. The decision results of all storage cells are combined to obtain the decoding result of the target codeword.

[0075] In this embodiment, the storage unit corresponding to the target codeword that cannot be decoded is identified as the first storage unit, and the storage unit adjacent to the first storage unit is identified as the second storage unit. By obtaining the voltage difference between the first storage unit and the second storage unit, the degree of voltage offset caused by the inter-unit interference phenomenon is determined. If the voltage difference is greater than the preset voltage difference threshold, the log-likelihood ratio adjustment is triggered. By obtaining the voltage difference between the first storage unit and the second storage unit, the inter-unit interference phenomenon is converted into a measurable physical indicator. The larger the voltage difference, the stronger the charge coupling effect between adjacent units and the more serious the interference. When the voltage difference is greater than the preset voltage difference threshold, the log-likelihood ratio adjustment is triggered to correct the distorted log-likelihood ratio. The adjusted log-likelihood ratio can more accurately reflect the true signal state and reduce misjudgment caused by interference.

[0076] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above embodiment 1 can be referred to the above introduction and will not be described in detail later. Figure 5 , step S20 may include steps S21 to S22:

[0077] Step S21 : According to a preset conversion table, the first state codeword is mapped to a first voltage, and the second state codeword is mapped to a second voltage.

[0078] Step S22: determining a voltage difference according to the first voltage and the second voltage.

[0079] In this embodiment, for non-volatile memories such as flash memory, state code words (e.g., L0, L1, L2, ..., L7) are typically used to represent different voltage states of a memory cell. Each state code word corresponds to a specific voltage range, which is predefined based on the design and process characteristics of the memory. The preset conversion table is a mapping relationship that maps the state code word to a specific voltage value or voltage range.

[0080] Alternatively, see Figure 4 Alternatively, the LX state voltage value may be set to X. If the voltage state of the first storage unit is L0 and the voltage state of the second storage unit is L7, the voltage difference may be represented by 0-7=-7.

[0081] In a feasible embodiment, step S22: when the number of second storage units is greater than one, determine the weight coefficient of each second storage unit according to the position of the second storage unit and the first storage unit; determine the voltage difference according to the difference between the product of each second voltage and the corresponding weight coefficient and the first voltage.

[0082] In this embodiment, when multiple adjacent storage cells are selected as second storage cells, a corresponding weight coefficient is set for each second storage cell, and multiple sets of voltage differences are obtained by multiplying them by the corresponding weight coefficients and then subtracting them from the first voltage to obtain a voltage difference.

[0083] Optionally, the weight coefficient is determined based on the physical distance between the first storage unit and the second storage unit. The closer the physical distance between the second storage unit and the first storage unit, the greater the impact of the voltage of the second storage unit on the same noise source (such as power supply fluctuations, thermal noise, coupling effects), and the higher the voltage correlation. The second storage unit with a closer distance is given a higher weight in the voltage difference calculation. The weight coefficient can be inversely proportional to the distance, the closer the distance, the higher the weight. The weight coefficient can also decay exponentially with distance, the farther the distance, the faster the weight decays.

[0084] Based on the first embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those in the above embodiment 1 can be referred to the above introduction and will not be described in detail later. Figure 6 Before determining the voltage difference between the first storage unit and the second storage unit according to the first state code word of the first storage unit and the second state code word of the second storage unit in step S20, the method may further include steps A10 to A40:

[0085] In one possible implementation, please refer to Figure 8 , step A10 may include steps A11 to A14:

[0086] In step A10 , in the first page state of the first memory cell, a first soft bit codeword is read according to the first left bias voltage value group and the first right bias voltage group, and a second soft bit codeword is read according to the second left bias voltage value group and the second right bias voltage group.

[0087] It should be noted that in flash memory, HD, SD1, SD2, LI1, and LI2 are input signals for flash memory soft decision decoding, which are used to indicate the state and confidence of the storage cell. HD (Hard Decision) is a hard bit codeword, which indicates the binary decision (0 or 1) when the storage cell is read. SD1 and SD2 (Soft Decision 1, Soft Decision 2) are soft bit codewords, which indicate the voltage level or signal strength when the storage cell is read, and are usually used for more precise error detection. SD1 and SD2 indicate the reading results under different reference voltages. LI1 and LI2 (Likelihood Information 1, Likelihood Information 2) are likelihood information, which indicate the confidence or reliability when the storage cell is read, and are usually related to SD1 and SD2, and are used to indicate the confidence of SD1 and SD2.

[0088] For example, please refer to Figure 7 When [HD,SD1,SD2,LI1,LI2]=[1,0,0,1,1], querying the LLRTable yields LLR=-7. When [HD,SD1,SD2,LI1,LI2]=[1,0,1,1,1], querying the LLR Table yields LLR=-4.

[0089] In addition, it should be noted that in flash memory, the page type refers to the programming and storage method of different bits in the memory cell. For MLC (Multi-Level Cell) or TLC (Triple-Level Cell) flash memory, there are usually Lower Page, Upper Page and possible Extra Page. In MLC or TLC flash memory, the Lower Page is the page that is first written to the memory cell during programming, corresponding to the least significant bit (LSB) of the memory cell state. The Upper Page is the page written after the Lower Page, corresponding to the other bits of the memory cell state (the most significant bit MSB in MLC, and may also include the middle bit in TLC). The Extra Page is the third page that may exist in TLC flash memory. The programming process usually follows the order of LP→UP→EP, that is, the Lower Page is written first, then the Upper Page, and finally the Extra Page.

[0090] In this embodiment, using TLC (triple-level cell) flash memory as an example, for an undecodeable target codeword, a pre-set first voltage offset value set is used in the first page type of the first memory cell where the target codeword is located to perform a read operation on the page containing the undecodeable codeword. The first page type is one of the following: Lower Page, Upper Page, and Extra Page. The first voltage offset value set is pre-calibrated based on the characteristics of the flash memory and is used to accurately read the voltage value of the memory cell.

[0091] The first left-biased voltage value group and the first right-biased voltage value group are obtained by fine-tuning the normal read voltage value. The left-biased voltage value group will make the reading result more inclined to a low voltage state, while the right-biased voltage value group will be more inclined to a high voltage state. The first left-biased voltage value group and the first right-biased voltage value group are used to read the page where the target codeword that cannot be decoded are located, and the read voltage values ​​are converted into binary codewords to obtain the first soft bit codeword SD1. The offsets of the second left-biased voltage value group and the second right-biased voltage value group are different from those of the first group, further expanding the range and accuracy of the voltage reading. Similarly, the second left-biased voltage value group and the second right-biased voltage value group are used for reading, and the voltage values ​​are converted into binary codewords to obtain the second soft bit codeword SD2.

[0092] Step A20: Obtain first likelihood information from other page forms of the first storage unit.

[0093] In this embodiment, in addition to the first page form, there are two other page forms in the TLC flash memory. The codewords of the other page forms are read as the first likelihood information (Level Indicator). A read command is sent to the other page forms through the read circuit of the flash memory. The read circuit detects the voltage value of the storage cell and converts these voltage values ​​into digital signal output. According to the voltage threshold rule of the flash memory, the read voltage value is converted into a binary codeword. If the voltage value is higher than a certain threshold, it is judged as a logic 1; if it is lower than the threshold, it is judged as a logic 0.

[0094] Step A30 : determining the high state, the middle state, and the low state of the first storage unit according to the first soft bit codeword, the second soft bit codeword, and the first likelihood information.

[0095] Step A40: combining the high state, the middle state, and the low state into a first state codeword.

[0096] In this embodiment, the previously acquired HD, SD1, SD2, LI1, and LI2 codewords are combined into a complete first soft message codeword in a specific order and format for subsequent state codeword combination. These codewords contain information under different read conditions, which helps to more comprehensively understand the state of the storage cell. Based on the page type represented by the HD bit, LI1 codeword, and LI2 codeword, a combination rule is determined between them. For example, if HD is L Page, LI1 is U Page, and LI2 is X Page, they are combined into L1, U1, and X1 state codewords according to a specific logic. According to the combination rule, the HD bit, LI1 codeword, and LI2 codeword are combined to obtain L1, U1, and X1 state codewords. These state codewords reflect the possible states of the storage cell under different page types.

[0097] In a feasible implementation manner, after step A40, steps A50 to A70 are further included:

[0098] Step A50: Send a read command to the second storage unit to obtain the voltage value of the second storage unit.

[0099] Step A60: Compare the voltage value of the second storage unit with a preset voltage threshold, and determine the range of the voltage value of the second storage unit according to the comparison result.

[0100] In this embodiment, taking TLC (Triple-Level Cell) flash memory as an example, each storage cell of TLC flash memory can store 3 bits of data, so there are 8 different status code words, corresponding to 8 different voltage ranges. These status code words can usually be represented by 3-bit binary numbers, such as 000, 001, 010, 011, 100, 101, 110, 111. The flash memory controller pre-sets 7 voltage thresholds to distinguish these 8 different voltage ranges. A read command is sent to the second storage cell to measure its voltage value. When reading the status code word of the second storage cell and the voltage offset value and the status code word of the first storage cell, the same voltage offset value is used, that is, the first voltage offset value group is used to perform a read operation on the second storage cell. The measured voltage value is compared with the 7 pre-set voltage thresholds. Based on the comparison result, the voltage range to which the voltage value belongs is determined.

[0101] Step A70: Determine the second state codeword corresponding to the second storage unit according to the range.

[0102] In this embodiment, the corresponding state code word is searched based on the voltage range to which the voltage value belongs. For example, if the voltage value is less than Vth1, the state code word is 000; if the voltage value is between Vth1 and Vth2, the state code word is 001; and so on, until the second state code word is determined.

[0103] Based on the first embodiment of the present application, in the fourth embodiment of the present application, the same or similar contents as those in the first embodiment above can be referred to above and will not be further described. On this basis, step S30, if the voltage difference is greater than the preset voltage difference threshold, adjusting the initial log-likelihood ratio of the first storage unit to obtain a target log-likelihood ratio may include the following steps: obtaining a correction value corresponding to the voltage difference; and determining the target log-likelihood ratio based on the initial log-likelihood ratio and the correction value.

[0104] In this implementation, the voltage differences are pre-grouped according to their absolute value ranges, with each range corresponding to a correction value. For example, if 0 <= absolute value of voltage difference < 1, the correction value is 0; 2 <= absolute value of voltage difference < 5, the correction value is +1 or -1; 5 <= absolute value of voltage difference <= 7, the correction value is +2 or -2. The adjusted target log-likelihood ratio can more accurately guide the decoding process of error-correcting codes (such as LDPC codes), thereby improving data reading accuracy.

[0105] In an optional embodiment, when the voltage difference is negative and less than a preset first threshold, the target log-likelihood ratio is obtained based on the difference between the initial log-likelihood ratio and the correction value; when the voltage difference is positive and greater than a preset second threshold, the target log-likelihood ratio is obtained based on the sum of the initial log-likelihood ratio and the correction value.

[0106] In this embodiment, the voltage difference is obtained by subtracting the voltage of the second state code word from the voltage of the first state code word. The first threshold and the second threshold are set based on the physical characteristics of the storage system, the noise level, the data reliability requirements, and the needs of the application scenario. The first threshold is a negative number, and the second threshold is a positive number. The numerical values ​​of the first threshold and the second threshold can be the same or different. For example, in some storage systems that have similar sensitivities to the effects of positive and negative voltage differences, using the same threshold can facilitate unified judgment and adjustment operations. In some storage media, negative voltage differences may be more likely to cause data errors, requiring stricter judgment criteria, that is, the numerical value of the first threshold is smaller, while the impact of the positive voltage difference is relatively small, and the numerical value of the second threshold is set larger.

[0107] When the voltage difference is negative and less than a first threshold, it indicates that the actual cell voltage is lower, indicating that the actual cell voltage is lower and the initial log-likelihood ratio needs to be reduced. For example, if the current LLR value is -4, the LLR value of the lower voltage value is -7, and the current LLR = -4 needs to be adjusted closer to -7; if the current LLR value is +4 and the LLR of the lower voltage value is -4, then the current LLR = +4 needs to be adjusted closer to -4. If the voltage difference is positive and greater than a second threshold, it indicates that the actual cell voltage should be higher and the initial log-likelihood ratio needs to be increased. For example, if the current LLR value is +4 and the LLR of the higher voltage value is +7, then the current LLR = +4 needs to be adjusted to +5 (or higher, closer to +7); if the current LLR value is -4 and the LLR of the higher voltage value is -7, then the current LLR = -4 needs to be adjusted to -5 (or lower, closer to -7).

[0108] The present application provides a storage device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the decoding method based on the error correction code in the above-mentioned embodiment 1.

[0109] Reference below Figure 8, which shows a schematic structural diagram of a decoding device based on an error correction code suitable for implementing embodiments of the present application. The decoding device based on an error correction code in the embodiments of the present application may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), and PADs (Portable Application Descriptions), as well as fixed terminals such as digital TVs and desktop computers. Figure 8 The storage device shown is only an example and should not limit the functions and scope of use of the embodiments of the present application.

[0110] like Figure 8 As shown, a decoding device based on an error correction code may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes based on a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. RAM 1004 also stores various programs and data required for the operation of the storage device. Processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input device 1007 including, for example, a touch screen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output device 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage device 1003 including, for example, a magnetic tape, hard disk, etc.; and communication device 1009. Communication device 1009 can allow storage device to carry out wireless or wired communication with other devices to exchange data. Although the figure shows storage device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have instead.

[0111] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program comprising program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0112] The storage device provided by this application utilizes the error-correcting code-based decoding method of the aforementioned embodiment, thereby resolving the technical problem that inter-unit interference causes soft decoding results to deviate from the true state, thereby reducing decoding accuracy. Compared with the prior art, the beneficial effects of the storage device provided by this application are the same as those of the error-correcting code-based decoding method of the aforementioned embodiment. Other technical features of this storage device are the same as those disclosed in the aforementioned embodiment and are not further described here.

[0113] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0114] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the above claims.

[0115] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, a computer program) stored thereon, wherein the computer-readable program instructions are used to execute the error correction code-based decoding method in the above embodiment.

[0116] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0117] The computer-readable storage medium may be included in a storage device, or may exist independently without being assembled into a storage device.

[0118] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the storage device, the flash memory storage device: when there is a target codeword that cannot be decoded, the storage unit corresponding to the target codeword is identified as the first storage unit, and the storage unit adjacent to the first storage unit is identified as the second storage unit; based on the first state codeword of the first storage unit and the second state codeword of the second storage unit, the voltage difference between the first storage unit and the second storage unit is determined; if the voltage difference is greater than a preset voltage difference threshold, the initial log-likelihood ratio of the first storage unit is adjusted to obtain a target log-likelihood ratio; and iterative decoding is performed based on the target log-likelihood ratio and a preset error correction code algorithm to obtain a decoding result of the target codeword.

[0119] Computer program code for performing the operations of the present application may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0120] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0121] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0122] The computer-readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described error-correction code-based decoding method. This computer-readable storage medium can address the technical problem of inter-unit interference causing soft decoding results to deviate from the true state, thereby reducing decoding accuracy. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the error-correction code-based decoding method provided in the above-described embodiment, and are not further elaborated here.

[0123] The above are only some embodiments of the present application and do not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A decoding method based on an error correction code, characterized in that: The decoding method based on the error correction code includes: When there is a target codeword that cannot be decoded, the storage unit corresponding to the target codeword is determined as a first storage unit, and the storage unit adjacent to the first storage unit is determined as a second storage unit; determining a voltage difference between the first storage unit and the second storage unit according to a first state code word of the first storage unit and a second state code word of the second storage unit; If the voltage difference is greater than a preset voltage difference threshold, adjusting the initial log-likelihood ratio of the first storage unit to obtain a target log-likelihood ratio; Iterative decoding is performed according to the target log-likelihood ratio and a preset error correction code algorithm to obtain a decoding result of the target codeword.

2. The decoding method based on error correction code according to claim 1, wherein: The step of identifying a storage unit adjacent to the first storage unit as a second storage unit comprises: determining an adjacent storage unit of the first storage unit; The adjacent storage unit that has data written later than the first storage unit is determined as the second storage unit, and the number of the second storage unit is one or more.

3. The decoding method based on error correction code according to claim 1, wherein: The step of determining the voltage difference between the first storage unit and the second storage unit according to the first state code word of the first storage unit and the second state code word of the second storage unit includes: According to a preset conversion table, mapping the first state codeword to a first voltage and mapping the second state codeword to a second voltage; The voltage difference is determined based on the first voltage and the second voltage.

4. The decoding method based on error correction code according to claim 3, wherein: The step of determining the voltage difference according to the first voltage and the second voltage includes: When the number of the second storage units is greater than one, determining a weight coefficient of each second storage unit according to positions of the second storage units and the first storage units; The voltage difference is determined according to a difference between the product of each second voltage and the corresponding weight coefficient and the first voltage.

5. The decoding method based on error correction code according to claim 1, wherein: Before the step of determining the voltage difference between the first storage unit and the second storage unit according to the first state code word of the first storage unit and the second state code word of the second storage unit, the method further includes: In a first page state of the first storage unit, the first soft bit codeword is read according to a first left bias voltage value group and a first right bias voltage group, and the second soft bit codeword is read according to a second left bias voltage value group and a second right bias voltage group; acquiring the first likelihood information in other page forms of the first storage unit; determining a high state, a middle state, and a low state of the first storage unit according to the first soft bit codeword, the second soft bit codeword, and the first likelihood information; The high state, the middle state, and the low state are combined into the first state codeword.

6. The decoding method based on error correction code according to claim 5, characterized in that: After the step of combining the high state, the middle state, and the low state into the first state codeword, the method further includes: Sending a read command to the second storage unit to obtain a voltage value of the second storage unit; comparing the voltage value of the second storage unit with a preset voltage threshold, and determining a range of the voltage value of the second storage unit according to the comparison result; The second state code word corresponding to the second storage unit is determined according to the range.

7. The decoding method based on error correction code according to claim 1, wherein: The step of adjusting the initial log-likelihood ratio of the first storage unit to obtain a target log-likelihood ratio includes: obtaining a correction value corresponding to the voltage difference; The target log-likelihood ratio is determined according to the initial log-likelihood ratio and the correction value.

8. The decoding method based on error correction code according to claim 7, characterized in that: The step of adjusting the initial log-likelihood ratio of the first storage unit to obtain a target log-likelihood ratio includes: When the voltage difference is negative and less than a preset first threshold, obtaining the target log-likelihood ratio according to the difference between the initial log-likelihood ratio and the correction value; When the voltage difference is positive and greater than a preset second threshold, the target log-likelihood ratio is obtained according to the sum of the initial log-likelihood ratio and the correction value, wherein the first threshold is a negative number and the second threshold is a positive number.

9. A decoding device based on an error correction code, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the error correction code-based decoding method according to any one of claims 1 to 8.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the decoding method based on error correction code according to any one of claims 1 to 8 are implemented.

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