Memory chip, chip stacking structure and memory

Abstract

The embodiment of the invention provides a memory chip, a chip stacking structure and a memory, the memory chip comprises a substrate and n conductive through hole groups, each conductive through hole group comprises first to fourth conductive through holes and first to fourth redistribution contact structures; the projection of the first redistribution contact structure and the projection of the first conductive through hole in the third direction are at least partially overlapped, and the first redistribution contact structure is electrically connected with the fourth conductive through hole; the projection of the second redistribution contact structure and the projection of the second conductive through hole in the third direction are at least partially overlapped and are electrically connected; the third redistribution contact structure is at least partially overlapped with the projection of the third conductive through hole along the third direction and is electrically connected with the third conductive through hole; the projection of the fourth redistribution contact structure and the projection of the fourth conductive through hole in the third direction are at least partially overlapped, and the first conductive through hole is electrically connected with the fourth redistribution contact structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory chip, a chip stacking structure, and a memory. Background Art

[0002] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limits of existing development technology, and limits of storage electron density. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit memory unit, bonding processes (such as hybrid bonding, bumping, and wire bonding) can be used to stack multiple chips to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affect the quality of signal transmission. Summary of the Invention

[0003] Embodiments of the present disclosure provide a memory chip, a chip stacking structure, and a memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a memory chip, comprising a substrate and n conductive via groups, where n is an even number and a positive integer;

[0005] The substrate has an active surface and an inactive surface facing each other; each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; the first conductive via, the second conductive via, the third conductive via, and the fourth conductive via all penetrate the substrate along a third direction, and the third direction is perpendicular to the active surface;

[0006] Each of the conductive via groups further includes a first redistribution contact structure, a second redistribution contact structure, a third redistribution contact structure, and a fourth redistribution contact structure;

[0007] The first redistribution contact structure at least partially overlaps with a projection of the first conductive via along the third direction, and the first redistribution contact structure and the first conductive via are electrically isolated, and the first redistribution contact structure and the fourth conductive via are electrically connected;

[0008] The second redistribution contact structure and the projection of the second conductive through hole along the third direction at least partially overlap, and the two are electrically connected;

[0009] The third redistribution contact structure and the projection of the third conductive via along the third direction at least partially overlap, and the two are electrically connected;

[0010] The fourth redistribution contact structure at least partially overlaps with a projection of the fourth conductive via along the third direction, and the fourth redistribution contact structure and the fourth conductive via are electrically isolated, and the first conductive via is electrically connected to the fourth redistribution contact structure.

[0011] In some embodiments, the ath conductive via group and the bth conductive via group are symmetrical about one of the symmetry axes of the active surface, and the symmetry axis is parallel to a side of the active surface; 1<a≤n / 2, n / 2<b≤n.

[0012] In some embodiments, the first conductive via in the ath conductive via group and the second conductive via in the bth conductive via group are symmetrical about the symmetry axis; the second conductive via in the ath conductive via group and the first conductive via in the bth conductive via group are symmetrical about the symmetry axis; the third conductive via in the ath conductive via group and the fourth conductive via in the bth conductive via group are symmetrical about the symmetry axis; the fourth conductive via in the ath conductive via group and the third conductive via in the bth conductive via group are symmetrical about the symmetry axis.

[0013] In some embodiments, the ath conductive via group and the bth conductive via group are symmetrical about the center point of the active surface; 1<a≤n / 2, n / 2<b≤n.

[0014] In some embodiments, the first conductive via in the ath conductive via group and the third conductive via in the bth conductive via group are symmetrical about the center point of the active surface; the second conductive via in the ath conductive via group and the fourth conductive via in the bth conductive via group are symmetrical about the center point of the active surface; the third conductive via in the ath conductive via group and the first conductive via in the bth conductive via group are symmetrical about the center point of the active surface; the fourth conductive via in the ath conductive via group and the second conductive via in the bth conductive via group are symmetrical about the center point of the active surface.

[0015] In some embodiments, the memory chip further includes a redistribution layer, which is disposed on the active surface or the inactive surface; the first conductive via and the fourth redistribution contact structure are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer, and the fourth conductive via and the first redistribution contact structure are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer.

[0016] In some embodiments, the second conductive via and the second redistribution contact structure are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer, and the third conductive via and the third redistribution contact structure are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer.

[0017] In some embodiments, the memory chip further includes n first driving circuits, which are coupled one-to-one with the first conductive vias in the n conductive via groups; the first driving circuits are used to send the signals transmitted by the corresponding coupled first conductive vias to the internal circuit of the memory chip; or, to send the signals generated by the internal circuit of the memory chip to the corresponding coupled first conductive vias.

[0018] In some embodiments, the conductive via is prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process, and different conductive vias in the same memory chip are electrically isolated from each other.

[0019] In a second aspect, an embodiment of the present disclosure provides a chip stacking structure, which includes at least one stacking unit stacked in sequence along a third direction, each stacking unit including a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along the third direction, and the third direction is perpendicular to the active surface of each memory chip; the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all memory chips as described in the first aspect; the ath conductive through-hole group of the first memory chip, the bth conductive through-hole group of the second memory chip, the ath conductive through-hole group of the third memory chip, and the bth conductive through-hole group of the fourth memory chip are aligned along the third direction; the bth conductive through-hole group of the first memory chip, the ath conductive through-hole group of the second memory chip, the bth conductive through-hole group of the third memory chip, and the ath conductive through-hole group of the fourth memory chip are aligned along the third direction; 1<a≤n / 2, n / 2<b≤n.

[0020] In some embodiments, each of the ath conductive via group and the bth conductive via group are symmetrical about the symmetry axis of the active surface, and adjacent memory chips are stacked back to back or face to face; the first conductive via in the ath conductive via group in each of the first memory chips, the second conductive via in the bth conductive via group in each of the second memory chips, the first conductive via in the ath conductive via group in each of the third memory chips, and the second conductive via in the bth conductive via group in each of the fourth memory chips are aligned along a third direction; the second conductive via in the ath conductive via group in each of the first memory chips, the first conductive via in the bth conductive via group in each of the second memory chips, the second conductive via in the ath conductive via group in each of the third memory chips, and the second conductive via in the bth conductive via group in each of the fourth memory chips are aligned along a third direction. The first conductive through-hole in the bth conductive through-hole group in the fourth storage chip is aligned along the third direction; the third conductive through-hole in the ath conductive through-hole group in each of the first storage chips, the fourth conductive through-hole in the bth conductive through-hole group in each of the second storage chips, the third conductive through-hole in the ath conductive through-hole group in each of the third storage chips, and the fourth conductive through-hole in the bth conductive through-hole group in each of the fourth storage chips are aligned along the third direction; the fourth conductive through-hole in the ath conductive through-hole group in each of the first storage chips, the third conductive through-hole in the bth conductive through-hole group in each of the second storage chips, the fourth conductive through-hole in the ath conductive through-hole group in each of the third storage chips, and the third conductive through-hole in the bth conductive through-hole group in each of the fourth storage chips are aligned along the third direction.

[0021] In some embodiments, the first conductive via and the fourth redistributed contact structure in the ath conductive via group in each of the first memory chips, the third redistributed contact structure and the third conductive via in the bth conductive via group in each of the second memory chips, the fourth conductive via and the first redistributed contact structure in the ath conductive via group in each of the third memory chips, and the second redistributed contact structure and the second conductive via in the bth conductive via group in each of the fourth memory chips are electrically connected to form a signal transmission channel; the second conductive via and the second redistributed contact structure in the ath conductive via group in each of the first memory chips, the first redistributed contact structure and the fourth conductive via in the bth conductive via group in each of the second memory chips, the third conductive via and the third redistributed contact structure in the ath conductive via group in each of the third memory chips, and the fourth redistributed contact structure and the first conductive via in the bth conductive via group in each of the fourth memory chips are electrically connected to form a signal transmission channel. transmission channel; the third conductive through-hole and the third redistributed contact structure in the ath conductive through-hole group in each of the first storage chips, the fourth redistributed contact structure and the first conductive through-hole in the bth conductive through-hole group in each of the second storage chips, the second conductive through-hole and the second redistributed contact structure in the ath conductive through-hole group in each of the third storage chips, and the first redistributed contact structure and the fourth conductive through-hole in the bth conductive through-hole group in each of the fourth storage chips are electrically connected to form a signal transmission channel; the fourth conductive through-hole and the first redistributed contact structure in the ath conductive through-hole group in each of the first storage chips, the second redistributed contact structure and the second conductive through-hole in the bth conductive through-hole group in each of the second storage chips, the first conductive through-hole and the fourth redistributed contact structure in the ath conductive through-hole group in each of the third storage chips, and the third redistributed contact structure and the third conductive through-hole in the bth conductive through-hole group in each of the fourth storage chips are electrically connected to form a signal transmission channel.

[0022] In some embodiments, the ath conductive through-hole group and the bth conductive through-hole group are symmetrical about the center point of the active surface; adjacent memory chips are stacked face to back; the first conductive through-hole in the ath conductive through-hole group in each of the first memory chips, the third conductive through-hole in the bth conductive through-hole group in each of the second memory chips, the first conductive through-hole in the ath conductive through-hole group in each of the third memory chips, and the third conductive through-hole in the bth conductive through-hole group in each of the fourth memory chips are aligned along a third direction; the second conductive through-hole in the ath conductive through-hole group in each of the first memory chips, the fourth conductive through-hole in the bth conductive through-hole group in each of the second memory chips, the second conductive through-hole in the ath conductive through-hole group in each of the third memory chips, and the fourth conductive through-hole in each of the fourth memory chips are aligned along a third direction. The fourth conductive through-hole in the bth conductive through-hole group in the memory chip is aligned along the third direction; the third conductive through-hole in the ath conductive through-hole group in each of the first memory chips, the first conductive through-hole in the bth conductive through-hole group in each of the second memory chips, the third conductive through-hole in the ath conductive through-hole group in each of the third memory chips, and the first conductive through-hole in the bth conductive through-hole group in each of the fourth memory chips are aligned along the third direction; the fourth conductive through-hole in the ath conductive through-hole group in each of the first memory chips, the second conductive through-hole in the bth conductive through-hole group in each of the second memory chips, the fourth conductive through-hole in the ath conductive through-hole group in each of the third memory chips, and the second conductive through-hole in the bth conductive through-hole group in each of the fourth memory chips are aligned along the third direction.

[0023] In some embodiments, the first conductive via and the fourth redistributed contact structure in the ath conductive via group in each of the first memory chips, the second conductive via and the second redistributed contact structure in the bth conductive via group in each of the second memory chips, the fourth conductive via and the first redistributed contact structure in the ath conductive via group in each of the third memory chips, and the third conductive via and the third redistributed contact structure in the bth conductive via group in each of the fourth memory chips form a signal transmission channel; the second conductive via and the second redistributed contact structure in the ath conductive via group in each of the first memory chips, the fourth conductive via and the first redistributed contact structure in the bth conductive via group in each of the second memory chips, the third conductive via and the third redistributed contact structure in the ath conductive via group in each of the third memory chips, and the first conductive via and the fourth redistributed contact structure in the bth conductive via group in each of the fourth memory chips form a signal transmission channel. transmission channel; the third conductive through-hole and the third redistributed contact structure in the ath conductive through-hole group in each of the first storage chips, the first conductive through-hole and the fourth redistributed contact structure in the bth conductive through-hole group in each of the second storage chips, the second conductive through-hole and the second redistributed contact structure in the ath conductive through-hole group in each of the third storage chips, the fourth conductive through-hole and the first redistributed contact structure in the bth conductive through-hole group in each of the fourth storage chips form a signal transmission channel; the fourth conductive through-hole and the first redistributed contact structure in the ath conductive through-hole group in each of the first storage chips, the third conductive through-hole and the third redistributed contact structure in the bth conductive through-hole group in each of the second storage chips, the first conductive through-hole and the fourth redistributed contact structure in the ath conductive through-hole group in each of the third storage chips, the second conductive through-hole and the second redistributed contact structure in the bth conductive through-hole group in each of the fourth storage chips form a signal transmission channel.

[0024] In some embodiments, for two chips connected face to face, the positions of the conductive vias in the two chips aligned along the third direction are electrically connected through a hybrid bonding process; for two chips connected back to back or for two chips connected back to face, the positions of the conductive vias in the two chips aligned along the third direction are electrically connected through a conductive bump bonding process; or, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the positions of the conductive vias in the two chips aligned along the third direction are electrically connected through the hybrid bonding process; or, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the positions of the conductive vias in the two chips aligned along the third direction are electrically connected through the conductive bump bonding process.

[0025] In a third aspect, an embodiment of the present disclosure provides a memory comprising a chip stacking structure as described in any one of the second aspects.

[0026] The embodiments of the present disclosure provide a memory chip, a chip stacking structure, and a memory. Conductive through-holes that are mirror-symmetrical (symmetrical about a certain symmetry axis) or center-point symmetrical are set in the memory chip. When stacked, adjacent memory chips are flipped or rotated in plane, thereby realizing spiral transmission of signals. Under the premise of low symmetry requirements, the number of drive circuits and data selectors set is reduced; only two conductive through-holes in each conductive through-hole group need to be connected in the horizontal direction, and the parasitic capacitance and parasitic resistance are relatively small. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of a through-hole structure of a semiconductor chip;

[0028] Figure 2 Schematic diagram of signal transmission for the first chip stacking structure;

[0029] Figure 3 Schematic diagram of signal transmission for the second chip stacking structure;

[0030] Figure 4A A schematic structural diagram of a memory chip provided in an embodiment of the present disclosure;

[0031] Figure 4B A schematic structural diagram of another memory chip provided in an embodiment of the present disclosure;

[0032] Figure 5 Schematic diagrams of first and second cross-sections of the active surface of a memory chip provided by an embodiment of the present disclosure;

[0033] Figure 6 A third cross-sectional schematic diagram of the active surface of the memory chip provided by an embodiment of the present disclosure;

[0034] Figure 7 A schematic diagram of a through-hole structure of another semiconductor chip provided in an embodiment of the present disclosure;

[0035] Figure 8 A schematic diagram of circuit connections of the active surface of a memory chip provided in an embodiment of the present disclosure;

[0036] Figure 9 A three-dimensional schematic diagram of a third chip stacking structure provided by an embodiment of the present disclosure;

[0037] Figure 10 A schematic diagram of through-hole alignment of a third chip stacking structure provided by an embodiment of the present disclosure;

[0038] Figure 11 A schematic diagram of through-hole alignment of a fourth chip stacking structure provided by an embodiment of the present disclosure;

[0039] Figure 12 A schematic diagram of through-hole alignment of a fifth chip stacking structure provided by an embodiment of the present disclosure;

[0040] Figure 13 This is a three-dimensional schematic diagram of the fifth chip stacking structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the related applications and are not intended to limit the present disclosure. It should also be noted that for ease of description, only the portions relevant to the related applications are shown in the drawings.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0043] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0045] Before introducing the embodiments of the present disclosure, three directions that may be used to describe a three-dimensional structure in the plane involved in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0046] See Figure 1A semiconductor chip (e.g., a memory chip or logic chip in a 3D stacked structure) may include a top surface on the front side and a bottom surface on the back side opposite the front side. Ignoring the flatness of the top and bottom surfaces, a direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the semiconductor chip is defined as a third direction. On the top surface of the semiconductor chip, two perpendicular directions, namely a first direction and a second direction, are defined, with the first direction being perpendicular to one edge of the semiconductor chip and the second direction being perpendicular to the other edge of the semiconductor chip.

[0047] like Figure 1 As shown, the semiconductor chip includes a substrate and a redistribution layer. The side of the substrate used to make devices (such as transistors, capacitors, etc.) forms an active surface. The side of the substrate opposite to the active surface is an inactive surface, which is also the bottom surface of the semiconductor chip. A redistribution layer is distributed between the substrate and the top surface. The redistribution layer includes multiple metal layers stacked along a third direction, such as M0 to M4. The number of metal layers is not limited.

[0048] The semiconductor chip further includes a plurality of conductive vias and a plurality of redistribution contact structures. The conductive vias penetrate the substrate along a third direction. The redistribution contact structures are located on a side of the redistribution layer away from the conductive vias. The contact structures and the conductive vias are electrically connected through the redistribution layer. For example: Figure 1 The redistributed contact structure in the embodiment is connected to the conductive vias via M3 to M0 in sequence; for example: Figure 1 The conductive vias in the chip are connected to the internal circuit via M0 ( Figure 1 The output signal processed by the internal circuit of the chip is then output to the corresponding contact structure through the metal layer M3. Figure 1 The contact structure in the chip can also be connected to the internal circuit of the chip via M3 ( Figure 1 The output signal processed by the chip internal circuit is then output to the corresponding conductive through hole via M0. Of course, in other embodiments, the contact structure and the conductive through hole can also be designed to be directly electrically connected.

[0049] In particular, the illustrations presented in this disclosure are not meant to be actual views of any particular microelectronic device or components thereof, but are merely idealized representations used to describe illustrative embodiments and, therefore, the drawings are not necessarily drawn to scale.

[0050] In one embodiment, a chip stacking structure is provided. Figure 2 , which provides a signal transmission schematic diagram of the first chip stacking structure. Figure 2As shown, the chip stack structure includes a memory chip and a logic chip. Each memory chip and logic chip includes multiple conductive vias. The conductive vias are used to transmit signals between different chips. All conductive vias can be located in any position. In particular, every four conductive vias can be functionally considered as a conductive via group, but the positions of these four conductive vias are not restricted.

[0051] like Figure 2 As shown, eight of the above-mentioned memory chips and one logic chip are stacked to form a 3D memory device. Meanwhile, the conductive vias of the eight memory chips are aligned along a third direction, and the nine conductive vias aligned along the third direction are connected to form an electrical path. Figure 2 , which shows a schematic diagram of signal transmission of a chip stacking structure Figure 1 .like Figure 2 As shown, the chip stacking structure includes memory chips 0 to 7 and a logic chip. Figure 2 Only four conductive through-holes D0 to D3 are shown for each memory chip, and these four conductive through-holes D0 to D3 belong to the same conductive through-hole group. At this time, the conductive through-holes D0 in the eight memory chips and one logic chip are all aligned to form one electrical path, and the conductive through-holes D1 in the eight memory chips and one logic chip are all aligned to form one electrical path... The remaining conductive through-holes are similar.

[0052] At the same time, each memory chip and logic chip is also provided with a plurality of driving circuits (eg Figure 2 Each conductive through hole is connected to a driving circuit; each memory chip is also provided with a plurality of data selectors (eg Figure 2 Each conductive via group corresponds to a data selector, meaning all conductive vias in a conductive via group are connected to the data port of the data selector through their respective drive circuits. This means the data selector can select which conductive via transmits the signal to output to the memory chip, or which conductive via receives the signal from the memory chip.

[0053] For the overall memory device, different areas in different memory chips will be divided into different channels (for example: CH0, CH1, CH4, CH5) for management. The signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "the conductive through hole D0 in the logic chip, the conductive through hole D0 in memory chip 0 - the conductive through hole D0 in memory chip 1 - the conductive through hole D0 in memory chip 2 - the conductive through hole D0 in memory chip 3 - the conductive through hole D0 in memory chip 4 - the conductive through hole D0 in memory chip 5 - the conductive through hole D0 in memory chip 6 - the conductive through hole D0 in memory chip 7", and the selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter the memory chip 0 and the memory chip 4 through the aforementioned electrical path; the signal output process can be understood similarly.

[0054] From the above, it can be seen that memory chip 0 only needs to obtain signals from conductive via D0, memory chip 1 only needs to obtain signals from conductive via D1... That is, each memory chip only needs to obtain signals from one conductive via in a conductive via group. It is worth noting that different memory chips need to obtain signals from different conductive vias. However, since all memory chips need to be designed with exactly the same structure during process manufacturing (so as to maximize cost and manpower savings), all conductive vias in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Further, when using Figure 2 In the chip stacking structure shown, each conductive through-hole corresponds to a driving circuit; during the operation of the chip stacking structure, it is necessary to drive all driving circuits in all storage chips in the same channel. The load is large and the parasitic capacitance is large, which seriously affects the performance of the chips, restricts transmission efficiency and increases power consumption, and also restricts the number of chips stacked in the three-dimensional device.

[0055] In another embodiment, see Figure 3 , which provides a signal transmission schematic diagram of the second chip stacking structure, in particular, Figure 3 Only some conductive through holes are marked (D0 to D3), and the others are omitted. Figure 3 For example, the conductive vias aligned along the third direction have the same identifier. Figure 3As shown, the chip stacking structure also includes 8 memory chips and 1 logic chip aligned along the third direction, but the conductive through-hole in each memory chip is rotationally connected to another conductive through-hole at a different position in another memory chip, realizing a spiral ascending connection as a whole, that is, the signal Signal_CH0 of channel CH0 is transmitted through "conductive through-hole D0 in the logic chip - conductive through-hole D1 in the memory chip 0 - conductive through-hole D2 in the memory chip 1 - conductive through-hole D3 in the memory chip 2 - conductive through-hole D0 in the memory chip 3 - conductive through-hole D1 in the memory chip 4 - conductive through-hole D2 in the memory chip 5 - conductive through-hole D3 in the memory chip 6 - conductive through-hole D0 in the memory chip 7", and the remaining signals are similar.

[0056] In this way, memory chip 0 can obtain signal Signal_CH0 through the output end of the conductive through hole D0 in the logic chip, memory chip 1 can obtain signal Signal_CH1 through the input end of the conductive through hole D0 in memory chip 0, memory chip 2 can obtain signal Signal_CH4 through the input end of the conductive through hole D0 in memory chip 1, and memory chip 3 can obtain signal Signal_CH5 through the input end of the conductive through hole D0 in memory chip 2... For each memory chip, only one conductive through hole in each conductive through hole group is required to connect to the drive circuit, and no data selector is required, which can reduce the number of devices and thus reduce parasitic capacitance. However, compared to Figure 2 The conductive through-hole direct connection configuration, Figure 3 The process of rotating the conductive through hole is more complicated. Specifically, in order to realize the rotating connection of the conductive through hole, Figure 3 A horizontal interconnection structure ( Figure 3 Only one of them is marked with a five-pointed star (in the figure), each conductive via is provided with a horizontal interconnect structure, which can be a metal interconnect line. The input signal signal_CH0 must first be transmitted upward from the conductive via D0 of the logic chip to the contact structure below the conductive via D0 of the memory chip 0 (not connected to the conductive via D0 of the memory chip 0), and then horizontally transmitted from the contact structure below the conductive via D0 of the memory chip 0 to the conductive via D1 of the memory chip 0. That is: Figure 3 The chip stacking structure shown in the figure also needs to pass through the horizontal interconnection structure in each memory chip during the signal process, and the output signal is similar, which will inevitably lead to an increase in parasitic resistance and also increase the complexity of the process.

[0057] In particular, Figure 2 and Figure 3In the chip stacking structure, all chips are active-side up, that is, different memory chips are stacked back to face, and memory chips and logic chips are also stacked back to face, that is, the bottom surface of the upper chip contacts the top surface of the lower chip.

[0058] In general, on the one hand, Figure 2 The chip stacking structure requires more conductive through-holes to transmit the corresponding signals, and the corresponding drive circuit and data selector result in large load and parasitic capacitance. Figure 3 The chip stacking structure has a large parasitic resistance due to the rotation configuration; on the other hand, Figure 2 and Figure 3 There are certain problems with stacking structures, and they cannot be directly applied to face-to-face stacking structures. Specifically, if you want to further realize the face-to-face chip stacking structure, one way is to use two sets of masks to make two different chips, one as the active-side-up chip and the other as the active-side-down chip. This method has high process complexity and uncontrollable costs. Another way is to make an additional set of conductive vias and connect both sets of conductive vias to the same drive circuit in the memory chip. However, this will lead to complex wiring inside the memory chip, which not only increases process complexity but also increases power consumption.

[0059] Therefore, the embodiments of the present disclosure provide a memory chip, a chip stacking structure, and a memory, which not only have smaller parasitic capacitance and parasitic resistance, but also have relatively low requirements for the symmetry of the through holes of the memory chip.

[0060] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0061] In one embodiment of the present disclosure, a memory chip is provided. Figure 4A , which shows a schematic structural diagram of a memory chip 10 provided by an embodiment of the present disclosure. Figure 4A As shown, the memory chip 10 includes a substrate and n conductive via groups, where n is an even number and a positive integer.

[0062] Different conductive via groups have the same structure. Figure 4A The specific structure of the conductive through hole group is shown by taking the ath conductive through hole group as an example, where a is a positive integer, and a≤n. Figure 4A As shown, the ath conductive through-hole group includes a first conductive through-hole A0, a second conductive through-hole A1, a third conductive through-hole A2 and a fourth conductive through-hole A3; the first conductive through-hole A0, the second conductive through-hole A1, the third conductive through-hole A2 and the fourth conductive through-hole A3 all penetrate the substrate along a third direction, and the third direction is perpendicular to the active surface.

[0063] Please refer to Figure 4A, each conductive via group further includes a first redistribution contact structure a0, a second redistribution contact structure a1, a third redistribution contact structure a2 and a fourth redistribution contact structure a3:

[0064] (1) The projection of the first redistribution contact structure a0 and the first conductive via A0 along the third direction at least partially overlaps, and the first redistribution contact structure a0 and the first conductive via A0 are electrically isolated, and the first redistribution contact structure a0 and the fourth conductive via A3 are electrically connected.

[0065] (2) The second redistribution contact structure a1 and the projection of the second conductive via A1 along the third direction at least partially overlap, and the two are electrically connected.

[0066] (3) The projection of the third redistribution contact structure a2 and the third conductive via A2 along the third direction at least partially overlap, and the two are electrically connected.

[0067] (4) The projection of the fourth redistribution contact structure a3 and the fourth conductive via A3 along the third direction at least partially overlap, and the fourth redistribution contact structure a3 and the fourth conductive via A3 are electrically isolated, and the first conductive via A0 and the fourth redistribution contact structure a3 are electrically connected.

[0068] In this way, cross-connection is achieved between the first conductive through-hole A1 and the fourth redistribution contact structure a3, and between the fourth conductive through-hole A3 and the first redistribution contact structure a1 through the interconnection structure in the horizontal and vertical directions, while there is no need to set up cross-interconnection between the second conductive through-hole A1 and the second redistribution contact structure a1, and between the third conductive through-hole A2 and the third redistribution contact structure a2, and only vertical interconnection needs to be achieved through the interconnection structure in the vertical direction. Under the premise of ensuring that data can be transmitted correctly after the four memory chips are stacked, the use of horizontal reverse interconnection structures can be effectively reduced, parasitic resistance and parasitic capacitance can be reduced, and the preparation requirements for the symmetry of the through-holes of the memory chips are also reduced.

[0069] It should be noted that the conductive via may be a through-silicon via (TSV), specifically a vertical interconnect structure penetrating the substrate, or, in other embodiments, may be other conductive vias with conductive functions.

[0070] Figure 4A The redistributed contact structure in FIG is only a location diagram, not a structural description. In one example, Figure 1 As shown, each redistribution contact structure may include a plurality of independent single connection structures. In another example, each redistribution contact structure is an integral structure.

[0071] Figure 4AThe distribution of the conductive through-hole groups in the entire memory chip 10 is only an example, and the specific distribution positions and numbers of the conductive through-hole groups can be determined according to requirements.

[0072] In a feasible embodiment, the ath conductive via group and the bth conductive via group are symmetrical about one of the symmetry axes of the active surface. 1<a≤n / 2, n / 2<b≤n.

[0073] See Figure 5 The active surface has a symmetry axis AA' extending along a first direction (for example, horizontally) and a symmetry axis BB' extending along a second direction (for example, vertically), the symmetry axis AA' and the symmetry axis BB' are perpendicular to each other and intersect at the center point O of the active surface, the first axis AA' is parallel to the first side of the active surface, and the second axis BB' is parallel to the second side of the active surface.

[0074] like Figure 5 As shown in (a), the ath and bth conductive via groups are symmetrical about the symmetry axis AA' of the active surface. After the memory chip is flipped downward 180° (along the symmetry axis AA') (flipping means swapping the front and back sides), the upper conductive via group A0-A3 overlaps with the (original) lower conductive via group B0-B3.

[0075] like Figure 5 As shown in (b), the ath and bth conductive via groups are symmetrical about the symmetry axis BB' of the active surface. After the memory chip (with the symmetry axis BB') is flipped 180° to the right (flipping means swapping the front and back surfaces), the left conductive via group A0-A3 overlaps with the (original) right conductive via group B0-B3.

[0076] Here, Figure 5 Only two conductive through-hole groups are used as an example to illustrate positional symmetry. In practice, the number of conductive through-hole groups in a memory chip is not limited.

[0077] For details, see Figure 5 (a) or (b) in the above examples both have the following positional characteristics:

[0078] (1) The first conductive via A0 in the ath conductive via group and the second conductive via B1 in the bth conductive via group are symmetrical about the active surface (for Figure 5 In (a), the axis of symmetry is AA'; for Figure 5 (b) in the figure, the axis of symmetry is BB');

[0079] (2) The symmetry axis of the second conductive via A1 in the ath conductive via group and the first conductive via B0 in the bth conductive via group about the active surface (for Figure 5 In (a), the axis of symmetry is AA'; for Figure 5(b) in the figure, the axis of symmetry is BB');

[0080] (3) The third conductive via A2 in the ath conductive via group and the fourth conductive via B3 in the bth conductive via group are symmetrical about the active surface (for Figure 5 In (a), the axis of symmetry is AA'; for Figure 5 (b) in the figure, the axis of symmetry is BB');

[0081] (4) The fourth conductive via A3 in the ath conductive via group and the third conductive via B2 in the bth conductive via group are symmetrical about the active surface (for Figure 5 In (a), the axis of symmetry is AA'; for Figure 5 In (b), the symmetry axis is BB').

[0082] In another possible embodiment, see Figure 6 , the ath conductive via group and the bth conductive via group are symmetrical about the center point O of the active surface; 1<a≤n / 2, n / 2<b≤n. Figure 6 , the ath conductive via group is A0~A3, and the bth conductive via group is B0~B3.

[0083] like Figure 6 As shown, after the memory chip plane is rotated 180° (the orientations of the front and back surfaces remain unchanged), the conductive via group A0-A3 on the upper left overlaps with the conductive via group B0-B3 on the lower right.

[0084] (1) The first conductive via A0 in the ath conductive via group and the third conductive via B2 in the bth conductive via group are symmetrical about the center point O of the active surface;

[0085] (2) the second conductive via A1 in the ath conductive via group and the fourth conductive via B3 in the bth conductive via group are symmetrical about the center point O of the active surface;

[0086] (3) The third conductive via A2 in the ath conductive via group and the first conductive via B0 in the bth conductive via group are symmetrical about the center point O of the active surface;

[0087] (4) The fourth conductive via A3 in the ath conductive via group and the second conductive via B1 in the bth conductive via group are symmetrical about the center point O of the active surface.

[0088] In some embodiments, as Figure 4A As shown, the memory chip 10 further includes a redistribution layer, the redistribution layer and the substrate are stacked along a third direction, and the redistribution layer is arranged on the active surface of the substrate, that is, the active surface of the substrate is close to the redistribution layer, and the inactive surface of the substrate is away from the redistribution layer.

[0089] Please refer to Figure 4A The first conductive via A0 and the fourth redistribution contact structure a3 are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer. The fourth conductive via A3 and the first redistribution contact structure a0 are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer.

[0090] The redistribution layer includes multiple metal layers M0~M3, and the first conductive through-hole A0 can be connected to the fourth redistribution contact structure a3 through the first and last two metal layers, for example, A0-M0-M4-a3; or, the first conductive through-hole A0 can be connected to the fourth redistribution contact structure a3 through multiple metal layers, for example, A0-M0-M1-M2-M4-a3; or, the first conductive through-hole A0 can be connected to the input end of the internal circuit through the metal layer, and the output end of the internal circuit is then connected to the fourth redistribution contact structure a3 through the metal layer.

[0091] In one possible implementation, Figure 1 As shown, the second conductive via A1 and the second redistribution contact structure are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer, and the third conductive via A2 and the third redistribution contact structure a2 are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer.

[0092] In another possible embodiment, Figure 7 As shown, the second conductive through-hole A1 passes through the substrate and part of the redistribution layer (for example, M0 to M3), and is electrically connected to the second redistribution contact structure a1 through the top redistribution layer (for example, M4). The third conductive through-hole A2 passes through the substrate and part of the redistribution layer (for example, M0 to M3), and is electrically connected to the third redistribution contact structure a2 through the top redistribution layer (for example, M4).

[0093] In another feasible embodiment, in the same memory chip 10, different second conductive vias A1 (or different third conductive vias A2) can be respectively configured as follows: Figure 1 The through hole structure shown and Figure 7 The through-hole structure shown.

[0094] For other examples, see Figure 4B, the redistribution layer can also be arranged below the inactive surface of the substrate (that is, the redistribution layer is arranged on the side away from the inactive surface and away from the active surface), so that the redistribution contact structure is located below the redistribution layer. In this case, the fourth redistribution contact structure a3 is connected to the first conductive via A0 through the first and last two metal layers, for example, a3-M0-M4-A0; or, the fourth redistribution contact structure a3 is connected to the first conductive via A0 through multiple metal layers, for example, a3-M0-M1-M2-M4-A0; or, the fourth redistribution contact structure a3 is connected to the input end of the internal circuit through the metal layer, and the output end of the internal circuit is then connected to the first conductive via A0 through the metal layer.

[0095] In some embodiments, see Figure 8 Memory chip 10 further includes n first drive circuits 20, each coupled to a first conductive via A0 in the n conductive via groups. First drive circuit 20 is configured to transmit a signal transmitted by the corresponding first conductive via A0 to the internal circuit of memory chip 10; alternatively, it is configured to transmit a signal generated by the internal circuit of memory chip 10 to the corresponding first conductive via A0.

[0096] Thus, for each memory chip 10 , only one conductive via in each conductive via group is connected to the first driving circuit 20 , and only the signal transmitted by this conductive via enters or is output from the memory chip 10 .

[0097] In some embodiments, each conductive via in the memory chip 10 can be prepared by any one or more of the processes of via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same memory chip 10 are electrically isolated from each other.

[0098] Among them, the through-hole process first refers to a through-hole process method that manufactures a through-hole structure before manufacturing the device structure of a device, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET or MOS tube for short). The intermediate through-hole process is a through-hole structure formed in the manufacturing process of the process flow, and is often a through-hole process manufactured after the device is formed and before the stack is manufactured. The through-hole process after is a manufacturing process that forms a through-hole from the front side of the wafer after the back end of line (BEOL) process is completed. The back through-hole process is a manufacturing process that forms a through-hole structure from the back side of the wafer after the BEOL process is completed. In other words, the through-hole process first can refer to making a through-hole first and then making a circuit, for example Figure 1 Conductive vias in the process; intermediate via process can refer to making the circuit and part of the metal layer first, then making the vias, and finally making the remaining vias; post-via process and back-via process can refer to making the circuit and metal layer first, and finally making the vias, for example Figure 7 conductive through-holes.

[0099] The embodiment of the present disclosure provides a memory chip. On the one hand, only two conductive through-holes need to be cross-connected through the horizontal and vertical interconnection structures, and the remaining two conductive through-holes only need to be vertically interconnected through the vertical interconnection structure. Under the premise of ensuring that the four memory chips can correctly transmit data after being stacked, the use of the horizontal reverse interconnection structure can be effectively reduced, the parasitic resistance and parasitic capacitance can be reduced, and the preparation requirements for the symmetry of the through-holes of the memory chip can also be reduced. On the other hand, only one conductive through-hole in each conductive through-hole group is connected to the first drive circuit. Compared with Figure 2 There is no need to set up a data selector to select conductive through-holes, which can reduce the number of devices, not only saving circuit area but also reducing chip manufacturing costs; on the other hand, the conductive through-holes have special symmetry and can be directly applied to stacked structures constructed in any manner such as face-to-face / back-to-back / face-to-back, without the need for two sets of masks or two sets of conductive through-holes; on the other hand, the conductive through-holes only need to be symmetrical along a certain symmetry axis or center point, which reduces the manufacturing difficulty and improves the chip yield.

[0100] In another embodiment of the present disclosure, see Figure 9 , which shows a schematic structural diagram of a chip stacking structure 50 provided by an embodiment of the present disclosure. Figure 9 As shown, the chip stacking structure 50 includes at least one stacking unit ( Figure 9Only one memory chip is shown), each stacking unit includes a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along a third direction, and the third direction is perpendicular to the active surface of each memory chip; the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all the aforementioned memory chips 10.

[0101] See Figure 9 Since the conductive via groups in the memory chips only need to be symmetrical about a symmetry axis or about a center point, and the placement of the memory chips is specially designed, the chip stacking structure 50 has the following characteristics:

[0102] (1) the ath conductive via group A0-A3 of the first memory chip, the bth conductive via group B0-B3 of the second memory chip, the ath conductive via group A0-A3 of the third memory chip, and the bth conductive via group B0-B3 of the fourth memory chip are aligned along a third direction;

[0103] (2) The bth conductive via group B0-B3 of the first memory chip, the ath conductive via group A0-A3 of the second memory chip, the bth conductive via group B0-B3 of the third memory chip, and the ath conductive via group A0-A3 of the fourth memory chip are aligned along the third direction.

[0104] The “alignment” in this embodiment refers to alignment within an allowable error range.

[0105] Specific embodiments are provided below for two situations: “the conductive via group in the memory chip is symmetrical about the symmetry axis of the active surface” and “the conductive via group in the memory chip is symmetrical about the center point of the active surface”.

[0106] Embodiment 1: The ath conductive via group and the bth conductive via group in each memory chip are symmetrical about one of the symmetry axes of the active surface.

[0107] In this scenario, if Figure 9 As shown, the first memory chip and the second memory chip are stacked face to face (Face to Face), the second memory chip and the third memory chip are stacked back to back (Back to Back), and the third memory chip and the fourth memory chip are stacked face to face (Face to Face). Face to face stacking means that the top surfaces of the two chips are approximately aligned along the third direction, and the center points of the two chips, the first axis AA' and the second axis BB' of the top surfaces are all aligned along the third direction; back to back stacking means that the bottom surfaces of the two chips are approximately aligned along the third direction. In other words, for two chips stacked face to face: one memory chip is flipped 180 degrees along the symmetry axis AA' or BB' plane and aligned with the other memory chip along the third direction.

[0108] Please refer to Figure 10 (a) in FIG. 1 shows a schematic cross-sectional view of an active surface of a conductive through hole group in a memory chip symmetrical along the symmetry axis BB'; see FIG. Figure 10 (b) in the figure shows a schematic diagram of the positions of the conductive through-hole groups of different memory chips along the third direction. It can be seen that the conductive through-hole groups A0 to A3 of the first memory chip, the conductive through-hole groups B0 to B3 of the second memory chip, the conductive through-hole groups A0 to A3 of the third memory chip, and the conductive through-hole groups B0 to B3 of the fourth memory chip are aligned along the third direction. Similarly, the conductive through-hole groups B0 to B3 of the first memory chip, the conductive through-hole groups A0 to A3 of the second memory chip, the conductive through-hole groups B0 to B3 of the third memory chip, and the conductive through-hole groups A0 to A3 of the fourth memory chip are aligned along the third direction (not shown in the figure).

[0109] Please refer to Figure 11 (a) in FIG. 1 shows a schematic cross-sectional view of an active surface of a conductive through-hole group in a memory chip symmetrical along the symmetry axis AA'; see FIG. Figure 11 (b) in the figure shows a schematic diagram of the positions of the conductive through-hole groups of different memory chips along the third direction. It can be seen that the conductive through-hole groups A0 to A3 of the first memory chip, the conductive through-hole groups B0 to B3 of the second memory chip, the conductive through-hole groups A0 to A3 of the third memory chip, and the conductive through-hole groups B0 to B3 of the fourth memory chip are aligned along the third direction. Similarly, the conductive through-hole groups B0 to B3 of the first memory chip, the conductive through-hole groups A0 to A3 of the second memory chip, the conductive through-hole groups B0 to B3 of the third memory chip, and the conductive through-hole groups A0 to A3 of the fourth memory chip are aligned along the third direction (not shown in the figure).

[0110] like Figure 9 As shown, the specific alignment of the conductive vias in the chip stack structure 50 is as follows:

[0111] (1) the first conductive via A0 in the ath conductive via group in each first memory chip, the second conductive via B1 in the bth conductive via group in each second memory chip, the first conductive via A0 in the ath conductive via group in each third memory chip, and the second conductive via B1 in the bth conductive via group in each fourth memory chip are aligned along the third direction;

[0112] (2) the second conductive via A1 in the ath conductive via group in each first memory chip, the first conductive via B0 in the bth conductive via group in each second memory chip, the second conductive via A1 in the ath conductive via group in each third memory chip, and the first conductive via B0 in the bth conductive via group in each fourth memory chip are aligned along a third direction;

[0113] (3) the third conductive via A2 in the ath conductive via group in each first memory chip, the fourth conductive via B3 in the bth conductive via group in each second memory chip, the third conductive via A2 in the ath conductive via group in each third memory chip, and the fourth conductive via B3 in the bth conductive via group in each fourth memory chip are aligned along a third direction;

[0114] (4) The fourth conductive through hole A3 in the ath conductive through hole group in each first storage chip, the third conductive through hole B2 in the bth conductive through hole group in each second storage chip, the fourth conductive through hole A3 in the ath conductive through hole group in each third storage chip, and the third conductive through hole B2 in the bth conductive through hole group in each fourth storage chip are aligned along the third direction.

[0115] See Figure 9 , the signal transmission channels in the chip stack structure 50 are as follows:

[0116] (1) the first conductive via A0 and the fourth redistributed contact structure a3 in the ath conductive via group in each first memory chip, the third redistributed contact structure b2 and the third conductive via B2 in the bth conductive via group in each second memory chip, the fourth conductive via A3 and the first redistributed contact structure a0 in the ath conductive via group in each third memory chip, and the second redistributed contact structure b1 and the second conductive via B1 in the bth conductive via group in each fourth memory chip are electrically connected to form a signal transmission channel;

[0117] (2) the second conductive via A1 and the second redistributed contact structure a1 in the ath conductive via group in each first memory chip, the first redistributed contact structure b0 and the fourth conductive via B3 in the bth conductive via group in each second memory chip, the third conductive via A2 and the third redistributed contact structure a2 in the ath conductive via group in each third memory chip, and the fourth redistributed contact structure b3 and the first conductive via B0 in the bth conductive via group in each fourth memory chip are electrically connected to form a signal transmission channel;

[0118] (3) the third conductive via A2 and the third redistributed contact structure a2 in the ath conductive via group in each first memory chip, the fourth redistributed contact structure b3 and the first conductive via B0 in the bth conductive via group in each second memory chip, the second conductive via A1 and the second redistributed contact structure a1 in the ath conductive via group in each third memory chip, and the first redistributed contact structure b0 and the fourth conductive via B3 in the bth conductive via group in each fourth memory chip are electrically connected to form a signal transmission channel;

[0119] (4) The fourth conductive through hole A3 and the first redistributed contact structure a0 in the ath conductive through hole group in each first storage chip, the second redistributed contact structure b1 and the second conductive through hole B1 in the bth conductive through hole group in each second storage chip, the first conductive through hole A0 and the fourth redistributed contact structure a3 in the ath conductive through hole group in each third storage chip, and the third redistributed contact structure b2 and the third conductive through hole B2 in the bth conductive through hole group in each fourth storage chip are electrically connected to form a signal transmission channel.

[0120] Thus, taking the example of sending a signal to the internal circuit of a memory chip, see Figure 9 , (1) Signal_CH0 is transmitted in sequence through A0 of the first storage chip, a3 of the second storage chip, b2 of the second storage chip, B2 of the third storage chip, A3 of the third storage chip, a0 of the fourth storage chip, b1 of the fourth storage chip, and B1. Since only the first conductive via (A0, B0) of each conductive via group is connected to the first drive circuit 20, Signal_CH0 enters the internal circuit of the first storage chip only through the first drive circuit 20 coupled to A0 of the first storage chip. (2) Signal_CH1 is transmitted in sequence through A2 of the first storage chip, a2 of the second storage chip, b3 of the second storage chip, B0 of the third storage chip, a1 of the fourth storage chip, and b0 of the fourth storage chip. Signal_CH1 enters the internal circuit of the second storage chip only through the first drive circuit 20 coupled to B0 of the second storage chip. (3) Signal_CH2 is transmitted sequentially through A3 of the first memory chip, a0, b1 of the second memory chip, B1, A0 of the third memory chip, a3, b2 of the fourth memory chip, and B2. Signal_CH2 only enters the internal circuit of the third memory chip through the first drive circuit 20 coupled to A0 of the third memory chip. (4) Signal_CH3 is transmitted sequentially through A1 of the first memory chip, a1, b0 of the second memory chip, B3, A2 of the third memory chip, a2, b3 of the fourth memory chip, and B0. Therefore, Signal_CH3 only enters the internal circuit of the fourth memory chip through the first drive circuit 20 coupled to B0 of the fourth memory chip. The internal circuit of the memory chip sending signals to the outside can be understood accordingly.

[0121] In another possibility, the first memory chip and the second memory chip are stacked back to back, the second memory chip and the third memory chip are stacked face to face, and the third memory chip and the fourth memory chip are stacked back to back, which also have similar symmetric characteristics and signal transmission channels. Please understand accordingly.

[0122] Embodiment 2: Each a-th conductive via group and each b-th conductive via group are symmetrical about the center point of the active surface.

[0123] In this scenario, adjacent memory chips are stacked face-to-back. Face-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of the other chip along a third direction. Alternatively, for two adjacent chips stacked face-to-back, one memory chip is rotated 180 degrees along the plane of the active surface center point O, then aligned with the other memory chip along the third direction, with the top surfaces facing the same direction.

[0124] Please refer to Figure 12 (a) in FIG. 1 shows a schematic cross-sectional view of an active surface of a conductive through-hole group in a memory chip symmetrical along a center point O; see FIG. Figure 12 (b) in the figure shows a schematic diagram of the positions of the conductive via groups of different memory chips along the third direction. It can be seen that the conductive via groups A0-A3 of the first memory chip, the conductive via groups B0-B3 of the second memory chip, the conductive via groups A0-A3 of the third memory chip, and the conductive via groups B0-B3 of the fourth memory chip are aligned along the third direction; the conductive via groups B0-B3 of the first memory chip, the conductive via groups A0-A3 of the second memory chip, the conductive via groups B0-B3 of the third memory chip, and the conductive via groups B0-B3 of the fourth memory chip are aligned along the third direction.

[0125] Figure 13 FIG. 5 shows a schematic diagram of a three-dimensional stacking of a chip stacking structure 50 in this scenario. Figure 13 As shown, the specific alignment of the conductive vias in the chip stack structure 50 is as follows:

[0126] (1) the first conductive via A0 in the ath conductive via group in each first memory chip, the third conductive via B2 in the bth conductive via group in each second memory chip, the first conductive via A0 in the ath conductive via group in each third memory chip, and the third conductive via B2 in the bth conductive via group in each fourth memory chip are aligned along a third direction;

[0127] (2) the second conductive via A1 in the ath conductive via group in each first memory chip, the fourth conductive via B3 in the bth conductive via group in each second memory chip, the second conductive via A1 in the ath conductive via group in each third memory chip, and the fourth conductive via B3 in the bth conductive via group in each fourth memory chip are aligned along a third direction;

[0128] (3) the third conductive via A2 in the ath conductive via group in each first memory chip, the first conductive via B0 in the bth conductive via group in each second memory chip, the third conductive via A2 in the ath conductive via group in each third memory chip, and the first conductive via B0 in the bth conductive via group in each fourth memory chip are aligned along a third direction;

[0129] (4) The fourth conductive through hole A3 in the ath conductive through hole group in each first storage chip, the second conductive through hole B1 in the bth conductive through hole group in each second storage chip, the fourth conductive through hole A3 in the ath conductive through hole group in each third storage chip, and the second conductive through hole B1 in the bth conductive through hole group in each fourth storage chip are aligned along the third direction.

[0130] See Figure 13 , the signal transmission channels in the chip stack structure 50 are as follows:

[0131] (1) the first conductive via A0 and the fourth redistributed contact structure a3 in the ath conductive via group in each first memory chip, the second conductive via B1 and the second redistributed contact structure b1 in the bth conductive via group in each second memory chip, the fourth conductive via A3 and the first redistributed contact structure a0 in the ath conductive via group in each third memory chip, and the third conductive via B2 and the third redistributed contact structure b2 in the bth conductive via group in each fourth memory chip form a signal transmission channel;

[0132] (2) the second conductive via A1 and the second redistributed contact structure a1 in the ath conductive via group in each first memory chip, the fourth conductive via B3 and the first redistributed contact structure b0 in the bth conductive via group in each second memory chip, the third conductive via A2 and the third redistributed contact structure a2 in the ath conductive via group in each third memory chip, and the first conductive via B0 and the fourth redistributed contact structure b3 in the bth conductive via group in each fourth memory chip form a signal transmission channel;

[0133] (3) the third conductive via A2 and the third redistributed contact structure a2 in the ath conductive via group in each first memory chip, the first conductive via B0 and the fourth redistributed contact structure b3 in the bth conductive via group in each second memory chip, the second conductive via A1 and the second redistributed contact structure a1 in the ath conductive via group in each third memory chip, the fourth conductive via B3 and the first redistributed contact structure b0 in the bth conductive via group in each fourth memory chip, and form a signal transmission channel;

[0134] (4) The fourth conductive through hole A3 and the first redistributed contact structure a0 in the ath conductive through hole group in each first storage chip, the third conductive through hole B2 and the third redistributed contact structure b2 in the bth conductive through hole group in each second storage chip, the first conductive through hole A0 and the fourth redistributed contact structure a3 in the ath conductive through hole group in each third storage chip, and the second conductive through hole A1 and the second redistributed contact structure a1 in the bth conductive through hole group in each fourth storage chip form a signal transmission channel.

[0135] Thus, taking the example of sending a signal to the internal circuit of a memory chip, see Figure 13 , (1) Signal_CH0 is transmitted in sequence through A0 of the first storage chip, a3, B1 of the second storage chip, b1, A3 of the third storage chip, a0, B2 of the fourth storage chip, and b2. Since only the first conductive via (A0, B0) of each conductive via group is connected to the first drive circuit 20, Signal_CH0 enters the internal circuit of the first storage chip only through the first drive circuit 20 coupled to the first storage chip A0. (2) Signal_CH3 is transmitted in sequence through A2 of the first storage chip, a2, B0 of the second storage chip, b3, A1 of the third storage chip, a1, B3 of the fourth storage chip, and b0. Signal_CH1 enters the internal circuit of the second storage chip only through the first drive circuit 20 coupled to the second storage chip B0. (3) Signal_CH2 is transmitted sequentially through A3 of the first memory chip, a0, B2 of the second memory chip, b2, A0 of the third memory chip, a3, B1 of the fourth memory chip, and b1. Signal_CH2 only enters the internal circuit of the third memory chip through the first drive circuit 20 coupled to A0 of the third memory chip. (4) Signal_CH3 is transmitted sequentially through A1 of the first memory chip, a1, B3 of the second memory chip, b0, A2 of the third memory chip, a2, B0 of the fourth memory chip, and b3. Therefore, Signal_CH3 only enters the internal circuit of the fourth memory chip through the first drive circuit 20 coupled to B0 of the fourth memory chip. The internal circuit of the memory chip sending signals to the outside can be understood accordingly.

[0136] In one possibility, for two memory chips connected face to face, the bonding surfaces of the two (the positions where the conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding (Hyperbonding, also known as a bonding column) process; for two chips connected back to back or back to face, the bonding surfaces of the two (the positions where the conductive vias are aligned along the third direction) are electrically connected through a conductive bump (UBump, also known as a micro-bump) bonding process.

[0137] In another possibility, for two memory chips connected face to face or for two chips connected back to back or for two chips connected back to face, the bonding surfaces of both (the positions where the conductive through holes are aligned along the third direction) are electrically connected through a hybrid bonding process.

[0138] In another possibility, for two memory chips connected face to face or for two chips connected back to back or for two chips connected back to face, the bonding surfaces of both (the positions where the conductive through holes are aligned along the third direction) are electrically connected through a conductive bump bonding process.

[0139] In the embodiment of the present disclosure, the chip stack structure 50 may be a high-bandwidth memory (HBM) stack product. Overall, the chip stack structure 50 has the following advantages:

[0140] (1) In each conductive via group, only two conductive vias are cross-connected through horizontal and vertical interconnect structures, while the remaining two conductive vias are vertically configured without the need for cross-interconnect structures. As shown in Table 1, the parasitic resistance is significantly reduced, and the parasitic capacitance is also reduced.

[0141] Table 1

[0142] Figure 3 The structure shown Figure 9 The structure shown Parasitic resistance 100％ 52.5％ parasitic capacitance 100％ 96.25％

[0143] (2) Similar to the flipping / planar rotation of adjacent memory chips Figure 3 The signal spiral transmission effect is achieved, there is no need to set up a data selector, the number of driving circuits is greatly reduced, and the transmission speed and transmission performance are greatly improved.

[0144] (3) The conductive through-holes of the memory chip are symmetrical about a certain symmetry axis or center point. The difficulty of symmetry is not high and the manufacturing yield is good;

[0145] (4) Memory chips with the same structure can be connected face-to-face or back-to-back without the need for two sets of masks or additional conductive vias.

[0146] In another embodiment of the present disclosure, a logic chip based on is provided, which also includes a substrate and n conductive via groups, where n is an even number and a positive integer; the substrate has an active surface and an inactive surface relative to each other; each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; the first conductive via, the second conductive via, the third conductive via, and the fourth conductive via all penetrate the substrate along a third direction, which is perpendicular to the active surface.

[0147] Each conductive via group further includes a first redistribution contact structure, a second redistribution contact structure, a third redistribution contact structure, and a fourth redistribution contact structure:

[0148] (1) The first redistribution contact structure and the projection of the first conductive through hole along the third direction at least partially overlap, and the two are electrically connected;

[0149] (2) The second redistribution contact structure and the projection of the second conductive through hole along the third direction at least partially overlap, and the two are electrically connected;

[0150] (3) The projection of the third redistributed contact structure and the third conductive through hole along the third direction at least partially overlaps, and the two are electrically connected;

[0151] (4) The fourth redistribution contact structure and the projection of the fourth conductive via along the third direction at least partially overlap, and the two are electrically connected.

[0152] It should be noted that for each conductive via in the memory chip, there is also a corresponding conductive via at the same position in the logic chip, that is, Figures 5 and 6 It can also be considered as a cross-sectional schematic diagram of the active surface of the logic chip.

[0153] In some embodiments, the logic chip also includes 4n second driving circuits 40, and the 4n second driving circuits are coupled to the 4n conductive vias in a one-to-one correspondence; the second driving circuit is used to send the signal transmitted by the corresponding coupled conductive vias to the internal circuit of the logic chip; or, to send the signal generated by the internal circuit of the logic chip to the corresponding coupled conductive vias.

[0154] That is, each conductive via in the logic chip is connected to a second driving circuit, and only the first conductive via in each conductive via group in the memory chip is connected to a first driving circuit.

[0155] Correspondingly, the chip stacking structure 50 also includes a logic chip, which is located at the bottom. The stacking unit is stacked above the logic chip, and the top surface of the logic chip is away from the stacking unit, and the bottom surface of the logic chip is close to the stacking unit, which is convenient for subsequent connection with the packaging structure.

[0156] Thus, taking sending a signal to the internal circuit of the memory chip as an example, the internal circuit of the logic chip outputs Signal_CH0 to Signal_CH3, which are sent to different conductive through-holes of the same conductive through-hole group via the corresponding second driving circuit, and subsequently transmitted to the corresponding memory chips respectively.

[0157] In yet another embodiment of the present disclosure, a memory is provided. The memory includes the chip stacking structure 50 described in the above embodiment.

[0158] The memory may be, for example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), etc., and is not specifically limited here.

[0159] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0160] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0161] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0162] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0163] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0164] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0165] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0166] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory chip, characterized in that: The memory chip includes a substrate and n conductive through-hole groups, where n is an even number and a positive integer; The substrate has an active surface and an inactive surface facing each other; each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; the first conductive via, the second conductive via, the third conductive via, and the fourth conductive via all penetrate the substrate along a third direction, and the third direction is perpendicular to the active surface; Each of the conductive via groups further includes a first redistribution contact structure, a second redistribution contact structure, a third redistribution contact structure, and a fourth redistribution contact structure; The first redistribution contact structure at least partially overlaps with a projection of the first conductive via along the third direction, and the first redistribution contact structure and the first conductive via are electrically isolated, and the first redistribution contact structure and the fourth conductive via are electrically connected; The second redistribution contact structure and the projection of the second conductive through hole along the third direction at least partially overlap, and the two are electrically connected; The third redistribution contact structure and the projection of the third conductive via along the third direction at least partially overlap, and the two are electrically connected; The fourth redistribution contact structure at least partially overlaps with a projection of the fourth conductive via along the third direction, and the fourth redistribution contact structure and the fourth conductive via are electrically isolated, and the first conductive via is electrically connected to the fourth redistribution contact structure.

2. The memory chip according to claim 1, wherein: The ath conductive via group and the bth conductive via group are symmetrical about one of the symmetry axes of the active surface, and the symmetry axis is parallel to a side edge of the active surface; 1<a≤n / 2, n / 2<b≤n.

3. The memory chip according to claim 2, wherein: The first conductive through hole in the ath conductive through hole group and the second conductive through hole in the bth conductive through hole group are symmetrical about the symmetry axis; The second conductive through hole in the ath conductive through hole group and the first conductive through hole in the bth conductive through hole group are symmetrical about the symmetry axis; The third conductive through hole in the ath conductive through hole group and the fourth conductive through hole in the bth conductive through hole group are symmetrical about the symmetry axis; The fourth conductive via in the ath conductive via group and the third conductive via in the bth conductive via group are symmetrical about the symmetry axis.

4. The memory chip according to claim 1, wherein: The ath conductive via group and the bth conductive via group are symmetrical about the center point of the active surface; 1<a≤n / 2, n / 2<b≤n.

5. The memory chip according to claim 4, wherein: The first conductive via in the ath conductive via group and the third conductive via in the bth conductive via group are symmetrical about the center point of the active surface; The second conductive via in the ath conductive via group and the fourth conductive via in the bth conductive via group are symmetrical about the center point of the active surface; The third conductive via in the ath conductive via group and the first conductive via in the bth conductive via group are symmetrical about the center point of the active surface; The fourth conductive via in the ath conductive via group and the second conductive via in the bth conductive via group are symmetrical about the center point of the active surface.

6. The memory chip according to any one of claims 1 to 5, characterized in that: The memory chip further includes a redistribution layer, and the redistribution layer is arranged on the active surface or the inactive surface; The first conductive via and the fourth redistribution contact structure are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer. The fourth conductive via and the first redistribution contact structure are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer.

7. The memory chip according to claim 6, wherein: The second conductive via and the second redistribution contact structure are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer. The third conductive via and the third redistribution contact structure are respectively located on both sides of the redistribution layer and are electrically connected through the redistribution layer.

8. The memory chip according to any one of claims 1 to 5, wherein: The memory chip further includes n first driving circuits, wherein the n first driving circuits are coupled to the first conductive vias in the n conductive via groups in a one-to-one correspondence; The first driving circuit is used to send the signal transmitted by the corresponding coupled first conductive via to the internal circuit of the memory chip; or, to send the signal generated by the internal circuit of the memory chip to the corresponding coupled first conductive via.

9. The memory chip according to any one of claims 1 to 5, wherein: The conductive vias are prepared by any one or more of the following processes: via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same memory chip are electrically isolated from each other.

10. A chip stacking structure, characterized in that: The chip stacking structure includes at least one stacking unit stacked sequentially along a third direction, each stacking unit including a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip stacked sequentially along the third direction, wherein the third direction is perpendicular to an active surface of each memory chip; the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all memory chips according to any one of claims 1 to 9; The ath conductive via group of the first memory chip, the bth conductive via group of the second memory chip, the ath conductive via group of the third memory chip, and the bth conductive via group of the fourth memory chip are aligned along a third direction; The bth conductive via group of the first memory chip, the ath conductive via group of the second memory chip, the bth conductive via group of the third memory chip, and the ath conductive via group of the fourth memory chip are aligned along a third direction; 1<a≤n / 2, n / 2<b≤n.

11. The chip stacking structure according to claim 10, wherein: Each of the ath conductive via group and the bth conductive via group are symmetrical about the symmetry axis of the active surface, and adjacent memory chips are stacked back-to-back or face-to-face; The first conductive via in the ath conductive via group in each of the first memory chips, the second conductive via in the bth conductive via group in each of the second memory chips, the first conductive via in the ath conductive via group in each of the third memory chips, and the second conductive via in the bth conductive via group in each of the fourth memory chips are aligned along a third direction; The second conductive via in the ath conductive via group in each of the first memory chips, the first conductive via in the bth conductive via group in each of the second memory chips, the second conductive via in the ath conductive via group in each of the third memory chips, and the first conductive via in the bth conductive via group in each of the fourth memory chips are aligned along a third direction; The third conductive via in the ath conductive via group in each of the first memory chips, the fourth conductive via in the bth conductive via group in each of the second memory chips, the third conductive via in the ath conductive via group in each of the third memory chips, and the fourth conductive via in the bth conductive via group in each of the fourth memory chips are aligned along a third direction; The fourth conductive through-hole in the ath conductive through-hole group in each of the first storage chips, the third conductive through-hole in the bth conductive through-hole group in each of the second storage chips, the fourth conductive through-hole in the ath conductive through-hole group in each of the third storage chips, and the third conductive through-hole in the bth conductive through-hole group in each of the fourth storage chips are aligned along a third direction.

12. The chip stacking structure according to claim 11, wherein: The first conductive via and the fourth redistributed contact structure in the ath conductive via group in each of the first memory chips, the third redistributed contact structure and the third conductive via in the bth conductive via group in each of the second memory chips, the fourth conductive via and the first redistributed contact structure in the ath conductive via group in each of the third memory chips, and the second redistributed contact structure and the second conductive via in the bth conductive via group in each of the fourth memory chips are electrically connected to form a signal transmission channel; The second conductive via and the second redistributed contact structure in the ath conductive via group in each of the first memory chips, the first redistributed contact structure and the fourth conductive via in the bth conductive via group in each of the second memory chips, the third conductive via and the third redistributed contact structure in the ath conductive via group in each of the third memory chips, and the fourth redistributed contact structure and the first conductive via in the bth conductive via group in each of the fourth memory chips are electrically connected to form a signal transmission channel; The third conductive via and the third redistributed contact structure in the ath conductive via group in each of the first memory chips, the fourth redistributed contact structure and the first conductive via in the bth conductive via group in each of the second memory chips, the second conductive via and the second redistributed contact structure in the ath conductive via group in each of the third memory chips, and the first redistributed contact structure and the fourth conductive via in the bth conductive via group in each of the fourth memory chips are electrically connected to form a signal transmission channel; The fourth conductive through hole and the first redistributed contact structure in the ath conductive through hole group in each of the first storage chips, the second redistributed contact structure and the second conductive through hole in the bth conductive through hole group in each of the second storage chips, the first conductive through hole and the fourth redistributed contact structure in the ath conductive through hole group in each of the third storage chips, and the third redistributed contact structure and the third conductive through hole in the bth conductive through hole group in each of the fourth storage chips are electrically connected to form a signal transmission channel.

13. The chip stacking structure according to claim 10, wherein: The ath conductive via group and the bth conductive via group are symmetrical about the center point of the active surface; adjacent memory chips are stacked in a face-to-back manner; The first conductive via in the ath conductive via group in each of the first memory chips, the third conductive via in the bth conductive via group in each of the second memory chips, the first conductive via in the ath conductive via group in each of the third memory chips, and the third conductive via in the bth conductive via group in each of the fourth memory chips are aligned along a third direction; The second conductive via in the ath conductive via group in each of the first memory chips, the fourth conductive via in the bth conductive via group in each of the second memory chips, the second conductive via in the ath conductive via group in each of the third memory chips, and the fourth conductive via in the bth conductive via group in each of the fourth memory chips are aligned along a third direction; The third conductive via in the ath conductive via group in each of the first memory chips, the first conductive via in the bth conductive via group in each of the second memory chips, the third conductive via in the ath conductive via group in each of the third memory chips, and the first conductive via in the bth conductive via group in each of the fourth memory chips are aligned along a third direction; The fourth conductive through-hole in the ath conductive through-hole group in each of the first storage chips, the second conductive through-hole in the bth conductive through-hole group in each of the second storage chips, the fourth conductive through-hole in the ath conductive through-hole group in each of the third storage chips, and the second conductive through-hole in the bth conductive through-hole group in each of the fourth storage chips are aligned along a third direction.

14. The chip stacking structure according to claim 13, wherein: The first conductive via in the ath conductive via group and the fourth redistribution contact structure in each of the first memory chips, the second conductive via in the bth conductive via group and the second redistribution contact structure in each of the second memory chips, the fourth conductive via in the ath conductive via group and the first redistribution contact structure in each of the third memory chips, and the third conductive via in the bth conductive via group and the third redistribution contact structure in each of the fourth memory chips form a signal transmission channel; The second conductive via and the second redistribution contact structure in the ath conductive via group in each of the first memory chips, the fourth conductive via and the first redistribution contact structure in the bth conductive via group in each of the second memory chips, the third conductive via and the third redistribution contact structure in the ath conductive via group in each of the third memory chips, and the first conductive via and the fourth redistribution contact structure in the bth conductive via group in each of the fourth memory chips form a signal transmission channel; The third conductive via and the third redistributed contact structure in the ath conductive via group in each of the first memory chips, the first conductive via and the fourth redistributed contact structure in the bth conductive via group in each of the second memory chips, the second conductive via and the second redistributed contact structure in the ath conductive via group in each of the third memory chips, and the fourth conductive via and the first redistributed contact structure in the bth conductive via group in each of the fourth memory chips form a signal transmission channel; The fourth conductive through hole and the first redistributed contact structure in the ath conductive through hole group in each of the first storage chips, the third conductive through hole and the third redistributed contact structure in the bth conductive through hole group in each of the second storage chips, the first conductive through hole and the fourth redistributed contact structure in the ath conductive through hole group in each of the third storage chips, and the second conductive through hole and the second redistributed contact structure in the bth conductive through hole group in each of the fourth storage chips form a signal transmission channel.

15. The chip stacking structure according to any one of claims 10 to 14, characterized in that: For two chips connected face to face, the positions where the conductive vias are aligned along the third direction are electrically connected by a hybrid bonding process; for two chips connected back to back or back to face, the positions where the conductive vias are aligned along the third direction are electrically connected by a conductive bump bonding process; or For two chips connected face to face, or for two chips connected back to back, or for two chips connected back to face, the positions of the conductive through holes aligned along the third direction in both chips are electrically connected by the hybrid bonding process; or For two chips connected face to face, or for two chips connected back to back, or for two chips connected back to face, the positions of the conductive through holes aligned along the third direction in both chips are electrically connected through the conductive bump bonding process.

16. A memory, characterized in that: The memory comprises the chip stacking structure according to any one of claims 10 to 15.

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