Multi-chip packaging structure, method for reducing peak current and semiconductor device

Abstract

The invention discloses a multi-chip packaging structure, a method for reducing peak current and a semiconductor device. The invention discloses a multi-chip packaging structure. The multi-chip packaging structure comprises a plurality of chips which are packaged on a substrate, and the plurality of packaging balls are embedded in the substrate, and the packaging balls are connected to a plurality of power supplies. The plurality of connection nodes are packaged on the substrate and are used for connecting the packaging balls to the chips. The power supplies include a plurality of first power supplies and a plurality of second power supplies. The packaging balls comprise a plurality of first packaging balls and a plurality of second packaging balls, the first packaging balls are connected to the first power supplies, and the second packaging balls are connected to the second power supplies. The first packaging balls are connected to a part of the chips through the connection nodes.

Description

Technical Field

[0001] The invention relates to a semiconductor package structure, a method for reducing peak current of the semiconductor package structure, and a semiconductor device. Background Art

[0002] Multi-Chip Package (MCP) is a packaging technology that combines multiple integrated circuits (ICs) into a single package. This packaging technology is typically used to integrate multiple functional components into a smaller package to save space, improve performance, or meet other specific requirements.

[0003] MCP may package multiple chips with different functions or different uses, for example: (1) Memory and processor combination: Integrate the processor and memory chip in the same package to improve data access speed and reduce latency. (2) Communication: Combine wireless communication chips and other related control or signal processors in one package to achieve more compact communication circuits or modules. (3) Sensor and controller combination: Integrate sensors (such as accelerometers, gyroscopes) and corresponding controllers in one package to provide a full-function sensing solution. (4) Chips manufactured using different processes: Multiple chips manufactured using different processes can be combined together to achieve different performance and power consumption requirements in the same package.

[0004] In general, multi-chip packaging is often used to achieve high integration, save space, improve performance, reduce power consumption, or meet other special requirements. This packaging technology is common in many applications, including mobile devices, embedded systems, communication circuits or modules.

[0005] In a multi-chip package, since multiple chips are integrated into the same package, special attention should be paid to the peak current that may occur in the multi-chip package.

[0006] In a multi-chip package, if all chips are connected to the same positive power supply (Vcc) and negative power supply (Vss), this connection method can cause some problems. For example, in this extreme connection situation, there is a concern that excessive peak current may cause system operation problems. For example, excessive peak current may cause unstable or abnormal operation of the entire system. This is because if the peak current is too high, the voltage drop within the chip will be very serious, which may cause the system to crash and enter an abnormal state.

[0007] Therefore, how to reduce the peak current to ensure stable operation of the system is an important issue that should be addressed. Summary of the Invention

[0008] According to one aspect of the present invention, a multi-chip package structure is provided, comprising: a substrate on which multiple chips are packaged; a plurality of package balls embedded in the substrate, the package balls being connected to multiple power supplies; and a plurality of connection nodes packaged on the substrate for connecting the package balls to the chips. The power supplies include a plurality of first power supplies and a plurality of second power supplies. The package balls include a plurality of first package balls and a plurality of second package balls, the first package balls being connected to the first power supplies, and the second package balls being connected to the second power supplies. The first package balls are connected to some of the chips via the connection nodes.

[0009] According to one aspect of the present invention, a method for reducing a peak current of a semiconductor package structure is provided, comprising: packaging a plurality of package balls within the semiconductor package structure, wherein the package balls are embedded in the substrate and connected to a plurality of power supplies; packaging a plurality of connection nodes on the substrate for connecting the package balls to a plurality of chips on the substrate; wherein the power supplies include a plurality of first power supplies and a plurality of second power supplies; the package balls include a plurality of first package balls and a plurality of second package balls, wherein the first package balls are connected to the first power supplies and the second package balls are connected to the second power supplies; and the first package balls are connected to some of the chips via the connection nodes.

[0010] According to one aspect of the present invention, a semiconductor device is provided, comprising: a plurality of chips; a substrate on which the chips are packaged; a plurality of package balls embedded in the substrate, the package balls connected to a plurality of power supplies; and a plurality of connection nodes packaged on the substrate for connecting the package balls to the chips. The power supplies include a plurality of first power supplies and a plurality of second power supplies. The package balls include a plurality of first package balls and a plurality of second package balls, the first package balls connected to the first power supplies, and the second package balls connected to the second power supplies. The first package balls are connected to some of the chips via the connection nodes.

[0011] In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic top view of a multi-chip package (MCP) structure according to a first embodiment of the present invention is shown.

[0013] Figure 2 A vertical schematic diagram showing a multi-chip package structure according to a first embodiment of the present invention.

[0014] Figure 3 A schematic top view of a multi-chip package (MCP) structure according to a second embodiment of the present invention is shown.

[0015] Figure 4 A method for reducing the peak current of a semiconductor package structure according to a third embodiment of the present invention is shown.

[0016] Description of reference numerals:

[0017] 100, 300: Multi-chip package (MCP) structure

[0018] 105, 305: Substrate

[0019] 110, 310: Encapsulated ball

[0020] 120, 320: connection nodes

[0021] 130, 330: Chips

[0022] 410-420: Steps DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. The following description uses the same / similar symbols to represent the same / similar elements.

[0024] First embodiment

[0025] Figure 1 A schematic top view of a multi-chip package (MCP) structure according to a first embodiment of the present invention is shown. Figure 2 A vertical schematic diagram showing a multi-chip package structure according to a first embodiment of the present invention.

[0026] like Figure 1 As shown, a multi-chip package (MCP) structure 100 according to a first embodiment of the present invention includes a substrate 105, a plurality of package balls 110, and a plurality of connection nodes 120. Furthermore, a plurality of chips 130 are packaged on the substrate 105. These chips 130 are, for example, but not limited to, NAND flash memory chips or communication chips.

[0027] The connection nodes 120 are packaged on the substrate 105 to connect the package balls 110 to the chips 130 .

[0028] These package balls 110 are embedded in the substrate 105. These package balls 110 can be connected to various power supplies (reference voltages), such as, but not limited to, Vcc, Vss, VccQ, Vpp, and VssQ. Power supply Vcc can be used to provide an operating voltage (e.g., an operating voltage during normal operation), and power supply Vss provides a ground voltage. Power supplies VccQ, Vpp, and VssQ provide the required voltages for these chips 130 during the power-up process. When these chips 130 are operating after power-up, power supplies VccQ, Vpp, and VssQ generally do not provide any voltage. For ease of understanding, power supplies Vcc and Vss may be referred to as first power supplies, while power supplies VccQ, Vpp, and VssQ may be referred to as second power supplies.

[0029] That is, if the package balls 110 connected to the power source Vcc and the power source Vss provide excessively high peak current to the chip 130 , it may cause system operation instability or abnormal operation, system crash, and other problems.

[0030] Therefore, in the first embodiment of this invention, to avoid the problem of excessive peak current, the load on the power supplies Vcc and Vss is reduced. In other words, the peak current flowing through the package balls 110 connected to the power supplies Vcc and Vss is reduced. For convenience, the package balls 110 connected to the power supplies Vcc and Vss are referred to as Vcc package balls 110 and Vss package balls 110, respectively (or, the package balls 110 connected to the power supplies Vcc and Vss are referred to as first package balls). Similarly, the package balls 110 connected to the power supplies VccQ, Vpp, and VssQ are referred to as VccQ package balls 110, Vpp package balls 110, and VssQ package balls 110, respectively (or, the package balls 110 connected to the power supplies VccQ, Vpp, and VssQ are referred to as second package balls).

[0031] Specifically, fewer chips 130 are connected to the same Vcc package ball 110 to avoid all chips 130 being connected to the same Vcc package ball 110. Similarly, fewer chips 130 are connected to the same Vss package ball 110 to avoid all chips 130 being connected to the same Vss package ball 110.

[0032] Please refer again Figure 1 .like Figure 1 As shown, only one chip 130 is connected to a single Vcc package ball 110, and only one chip 130 is connected to a single Vss package ball 110. For example, Figure 1 The top chip 130 is connected to the second Vcc package ball 110 on the left in the first column through the connection node 120, and Figure 1The topmost chip 130 in the array is connected to the leftmost Vss package ball 110 in column 1 through connection node 120 .

[0033] As for a single VccQ package ball 110 or a single Vpp package ball 110 or a single VssQ package ball 110, it can be connected to one or more chips 130. For example, Figure 1 The single Vpp package ball 110 in FIG1 is connected to all chips 130. The rest can be deduced in the same way. Because during normal system operation, the power supplies VccQ, VssQ, and Vpp are generally not required to provide large currents, there is no concern about excessive peak current.

[0034] The following example illustrates the difference between the first embodiment of this case and conventional technology. In conventional technology, assuming each chip requires 1A of current, and a single Vcc package ball is connected to three chips, the Vcc power supply (not shown) must provide 3A of current, which may exceed the peak current limit, causing system instability or even system collapse. Conversely, in the first embodiment of this case, assuming each chip requires 1A of current, and a single Vcc package ball is connected to one chip, each Vcc power supply (not shown) must provide 1A of current. In this case, the probability of exceeding the peak current limit is greatly reduced, significantly reducing the possibility of system instability or even system collapse.

[0035] Second embodiment

[0036] Figure 3 A schematic top view of a multi-chip package (MCP) structure according to a second embodiment of the present invention is shown.

[0037] like Figure 3 As shown, a multi-chip package (MCP) structure 300 according to a second embodiment of the present invention includes a substrate 305, a plurality of package balls 310, and a plurality of connection nodes 320. Furthermore, a plurality of chips 330 may be packaged on the substrate 305. These chips 330 may be, for example but not limited to, NAND flash memory chips or communication chips.

[0038] Similarly, in the second embodiment of the present case, to avoid the problem of excessive peak current, the load on the power supply Vcc and the power supply Vss is reduced, and all chips 330 are prevented from being connected to the same Vcc package ball 310, and all chips 330 are prevented from being connected to the same Vss package ball 310.

[0039] In the second embodiment of the present invention, two chips 330 are connected to a single Vcc package ball 310, and two chips 330 are connected to a single Vss package ball 310. For example, Figure 3The top chip 330 and the top second chip 330 are connected to the Vcc package ball 310 of the first column through the connection node 320, and, Figure 3 The top chip 330 and the second top chip 330 are connected to the Vss package ball 310 in the second column through the connection node 320.

[0040] As for a single VccQ package ball 310 or a single Vpp package ball 310 or a single VssQ package ball 310, it can be connected to one or more chips 330. For example, Figure 3 The single Vpp package ball 310 in the system is connected to all chips 330. The rest can be deduced in the same way. Because during normal system operation, the power supplies VccQ, VssQ, and Vpp are usually not required to provide large currents, there is no concern about excessive peak current.

[0041] Figure 4 A method for reducing the peak current of a semiconductor packaging structure according to a third embodiment of the present case is shown, comprising: (410) packaging a plurality of packaging balls in the semiconductor packaging structure, wherein the packaging balls are embedded in the substrate, and the packaging balls are connected to a plurality of power supplies; (420) packaging a plurality of connection nodes on the substrate for connecting the packaging balls to a plurality of chips on the substrate, wherein the power supplies include a plurality of first power supplies and a plurality of second power supplies, the packaging balls include a plurality of first packaging balls and a plurality of second packaging balls, the first packaging balls are connected to the first power supplies, the second packaging balls are connected to the second power supplies, and the first packaging balls are connected to some of the chips through the connection nodes.

[0042] In the above method, each of the first package balls is connected to a single chip of the chips through one of the connection nodes.

[0043] In the above method, each of the first package balls is connected to two of the chips through one of the connection nodes.

[0044] In the above method, the first power sources include an operating voltage and a ground voltage.

[0045] In the above method, each of the second package balls is connected to all of the chips via one of the connection nodes.

[0046] A fourth embodiment of this invention further discloses a semiconductor device comprising: a plurality of chips; a substrate on which the chips are packaged; a plurality of packaging balls embedded in the substrate, the packaging balls connected to a plurality of power supplies; and a plurality of connection nodes packaged on the substrate for connecting the packaging balls to the chips. The power supplies include a plurality of first power supplies and a plurality of second power supplies. The packaging balls include a plurality of first packaging balls and a plurality of second packaging balls, the first packaging balls connected to the first power supplies, and the second packaging balls connected to the second power supplies. The first packaging balls are connected to some of the chips via the connection nodes.

[0047] In the semiconductor device, each of the first package balls is connected to a single chip of the chips through one of the first connection nodes.

[0048] In the semiconductor device, each of the first package balls is connected to two of the chips through one of the first connection nodes.

[0049] In the semiconductor device, the first power sources include an operating voltage and a ground voltage.

[0050] In the semiconductor device, the second package balls are connected to all the chips through the connection nodes.

[0051] As can be seen from the above, in the above-mentioned multiple embodiments of the present case, in the packaging structure, it is possible to reduce the peak current, thereby reducing the risk of system crash due to excessive current. Since the peak current is the maximum current transiently flowing through the circuit, reducing the peak current helps maintain the stability and reliability of the system. Vcc (positive power supply) and Vss (negative power supply) are the power supplies in the circuit. By minimizing the number of chips connected to Vcc (positive power supply) and Vss (negative power supply) (through the Vcc package ball and Vss package ball), the load on Vcc (positive power supply) and Vss (negative power supply) can be reduced, reducing current fluctuations.

[0052] For example, but not limited to, by reducing the number of chips connected to a single Vcc package ball and a single Vss package ball, and by leaving some Vcc package balls and Vss package balls unconnected to chips, the goal of this design is to ensure that each Vcc package ball and each Vss package ball loads one, two, or a small number of chips instead of all chips, thereby effectively reducing peak current and thus reducing system current fluctuations.

[0053] That is, the above-mentioned multiple embodiments of the present case can reduce the risk of system crash because the load is distributed to multiple Vcc package balls and multiple Vss package balls, which helps to balance the current distribution in the system and reduces the risk of system crash due to excessive peak current.

[0054] The appropriate number of chips connected to a single Vcc ball and a single Vss ball depends on the number of Vcc and Vss balls in the package, the peak current limit, and the number of chips. Different package designs may require a different number of connections to ensure stable system operation under various operating conditions.

[0055] In summary, although the present invention has been disclosed above with reference to the embodiments, these are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A multi-chip package structure, comprising: a substrate on which a plurality of chips are packaged; A plurality of package balls are embedded in the substrate, and the package balls are connected to a plurality of power supplies; as well as, A plurality of connection nodes are packaged on the substrate to connect the package balls to the chips. in, The power supplies include a plurality of first power supplies and a plurality of second power supplies; The package balls include a plurality of first package balls and a plurality of second package balls, the first package balls are connected to the first power supplies, and the second package balls are connected to the second power supplies; as well as The first package balls are connected to some of the chips through the connection nodes.

2. The multi-chip package structure according to claim 1, wherein: Each of the first package balls is connected to a single chip of the chips through one of the connection nodes.

3. The multi-chip package structure according to claim 1, wherein: Each of the first package balls is connected to two of the chips through one of the connection nodes.

4. The multi-chip package structure according to claim 1, wherein: The first power sources include an operating voltage and a ground voltage; and Each of the second package balls is connected to all of the chips via one of the connection nodes.

5. A method for reducing a peak current of a semiconductor package structure, comprising: Encapsulating a plurality of package balls in the semiconductor package structure, wherein the package balls are embedded in a substrate, and the package balls are connected to a plurality of power supplies; Encapsulating a plurality of connection nodes on the substrate to connect the package balls to a plurality of chips on the substrate; in, The power supplies include a plurality of first power supplies and a plurality of second power supplies; The package balls include a plurality of first package balls and a plurality of second package balls, the first package balls are connected to the first power supplies, and the second package balls are connected to the second power supplies; as well as The first package balls are connected to some of the chips through the connection nodes.

6. The method according to claim 5, wherein: Each of the first package balls is connected to a single chip of the chips through one of the connection nodes.

7. The method according to claim 5, wherein: Each of the first package balls is connected to two of the chips through one of the connection nodes.

8. The method according to claim 5, wherein The first power sources include an operating voltage and a ground voltage; and Each of the second package balls is connected to all of the chips via one of the connection nodes.

9. A semiconductor device comprising: Multiple chips; a substrate on which the chips are packaged; A plurality of package balls are embedded in the substrate, and the package balls are connected to a plurality of power supplies; as well as, A plurality of connection nodes are packaged on the substrate to connect the package balls to the chips. in, The power supplies include a plurality of first power supplies and a plurality of second power supplies; The package balls include a plurality of first package balls and a plurality of second package balls, the first package balls are connected to the first power supplies, and the second package balls are connected to the second power supplies; as well as The first package balls are connected to some of the chips through the connection nodes.

10. The semiconductor device according to claim 9, wherein Each of the first package balls is connected to a single chip of the chips through one of the connection nodes, or each of the first package balls is connected to two chips of the chips through one of the connection nodes; The first power sources include an operating voltage and a ground voltage; and Each of the second package balls is connected to all of the chips via one of the connection nodes.

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