A multi-channel bidirectional current limiting protection circuit and method

Abstract

The present invention relates to the field of integrated circuit testing technology, specifically disclosing a multi-channel bidirectional current limiting protection circuit and method. The protection circuit includes: a current path comprising a first NMOS power transistor, a first resistor, a second resistor, and a second NMOS power transistor electrically connected in sequence; and a sampling control unit comprising a first NPN transistor, a second NPN transistor, and a plurality of control resistors for sampling the total voltage of the first and second resistors and adjusting the gate voltages of the first and second NMOS power transistors based on the sampled total voltage value, thereby limiting the current in the current path. The present invention uses the first NPN transistor, the second NPN transistor, and the plurality of control resistors to sample the total voltage of the first and second resistors, and adjusts the gate voltages of the first and second NMOS power transistors based on the sampled total voltage value, so that both operate in a saturation region, thereby limiting the current in the current path and effectively protecting the probes and pogo pins on the test hardware.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a multi-channel bidirectional current limiting protection circuit and method. Background Art

[0002] Semiconductor chip mass production testing often involves high-current tests, such as on-resistance measurements, load regulation measurements, and high-power surge tests. ATE (automated test equipment) applies a constant, high current to the chip under test. The direction of this current is often uncertain; it can be positive or negative, depending on the polarity of the device under test.

[0003] However, the probes and pogo pins in test hardware, such as test sockets and probe cards, that physically contact the chip under test have current ratings. While multiple probes and pogo pins can be used to evenly distribute the current across each pin, varying contact resistance or the inability of some probes and pogo pins to maintain proper contact with the chip under test can cause some probes to exceed the rated current, shortening their lifespan or even damaging them.

[0004] Based on this technical background, the present invention studies a multi-channel bidirectional current limiting protection circuit and method. Summary of the Invention

[0005] In response to the shortcomings of the existing technology, the present invention proposes a multi-channel bidirectional current limiting protection circuit and method. The protection circuit samples the total voltage of the first resistor and the second resistor through a first NPN transistor, a second NPN transistor and multiple control resistors, and adjusts the gate voltage of the first NMOS power transistor and the second NMOS power transistor based on the sampled total voltage value, so that both operate in the saturation region, thereby limiting the current in the current path, thereby effectively protecting the probes and spring pins on the test hardware.

[0006] In order to achieve the above objectives, the present invention provides a first aspect of a multi-channel bidirectional current limiting protection circuit, comprising:

[0007] A current path includes a first NMOS power tube, a first resistor, a second resistor, and a second NMOS power tube electrically connected in sequence;

[0008] A sampling control unit includes a first NPN transistor, a second NPN transistor and multiple control resistors, and is used to sample the total voltage of the first resistor and the second resistor, and adjust the gate voltage of the first NMOS power transistor and the second NMOS power transistor based on the sampled total voltage value so that both operate in the saturation region, thereby limiting the current in the current path.

[0009] A second aspect of the present invention provides a multi-channel bidirectional current limiting protection method performed in the above protection circuit, comprising:

[0010] Each protection circuit forms a current path through a first NMOS power tube, a first resistor, a second resistor, and a second NMOS power tube electrically connected in sequence;

[0011] Each protection circuit samples the total voltage of the first resistor and the second resistor through a first NPN transistor, a second NPN transistor and multiple resistors, and adjusts the gate voltage of the first NMOS power transistor and the second NMOS power transistor based on the sampled total voltage value so that both operate in the saturation region, thereby limiting the current in the current path.

[0012] The beneficial effects of the present invention include:

[0013] The multi-channel bidirectional current limiting protection circuit proposed in the present invention samples the total voltage of the first resistor and the second resistor through the first NPN transistor, the second NPN transistor and multiple control resistors, and adjusts the gate voltage of the first NMOS power transistor and the second NMOS power transistor based on the sampled total voltage value, so that both operate in the saturation region, thereby limiting the current in the current path, thereby effectively protecting the probes and spring pins on the test hardware.

[0014] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0016] Figure 1 This is a structural schematic diagram of one protection circuit in a specific implementation of the multi-channel bidirectional current limiting protection circuit proposed by the present invention.

[0017] Figure 2 This is a structural diagram of a multi-channel protection circuit in a specific embodiment of the multi-channel bidirectional current limiting protection circuit proposed by the present invention.

[0018] Figure 3 This is a structural diagram of a 10V floating voltage and a 5V floating voltage generating circuit in a specific embodiment of the multi-channel bidirectional current limiting protection circuit proposed by the present invention.

[0019] Figure 4 This is a structural diagram of the logic control circuit in a specific implementation of the multi-channel bidirectional current limiting protection circuit proposed by the present invention.

[0020] Description of reference numerals:

[0021] Q1-first NMOS power transistor, Q2-second NMOS power transistor, Q3-first NPN transistor, Q4-second NPN transistor, R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor, R5-fifth resistor, R6-sixth resistor, R7-seventh resistor, R8-eighth resistor, C1-first capacitor, C2-second capacitor, Isolated DC-DC power-isolated DC voltage regulator module, Digital Isolator-digital isolator, Analog Switch-analog switch, XOR-NAND gate, D-type Flip-Flop-DFF trigger-;

[0022] SYSTEM_POWER - system power supply, SYSTEM_GND - system ground, GATEx - gate control terminal, FLOATING_10V - 10V floating voltage, FLOATING_5V - 5V floating voltage, FLOATING_VCOM - floating reference terminal, Gate_Control - control signal, Fault_Check - error warning signal, Clear_Control - clear signal, V+ - V+ port, CTRL - CTRL port, GND - GND port, COM - COM port, NC - NC port, NO - NO port, GANGED_HC_PATH - total high current path, LIMITED_HC_PATHx - each protection circuit output path. DETAILED DESCRIPTION

[0023] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0024] In the present invention, unless otherwise specified, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of a device in normal use, and "inner" and "outer" refer to positions relative to the device's outline. Furthermore, the terms "first, second, and third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Therefore, features defined as "first, second, and third" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise explicitly and specifically defined.

[0025] The present invention provides a multi-channel bidirectional current limiting protection circuit, such as Figure 1 As shown, including:

[0026] The current path includes a first NMOS power transistor Q1, a first resistor R1, a second resistor R2 and a second NMOS power transistor Q2 electrically connected in sequence;

[0027] The sampling control unit includes a first NPN transistor Q3, a second NPN transistor Q4 and multiple control resistors, and is used to sample the total voltage of the first resistor R1 and the second resistor R2, and adjust the gate voltage of the first NMOS power transistor Q1 and the second NMOS power transistor Q2 based on the sampled total voltage value so that both operate in the saturation region, thereby limiting the current in the current path.

[0028] In the present invention, the total voltage of the first resistor R1 and the second resistor R2 is sampled through the first NPN transistor Q3, the second NPN transistor Q4 and multiple control resistors, and the gate voltage of the first NMOS power transistor Q1 and the second NMOS power transistor Q2 is adjusted based on the sampled total voltage value, so that both operate in the saturation region, thereby limiting the current in the current path, thereby effectively protecting the probes and spring pins on the test hardware.

[0029] According to the present invention, the drain of the first NMOS power transistor Q1 is electrically connected to the total high current path of the automated test equipment, and the source is electrically connected to one end of the first resistor R1;

[0030] The other end of the first resistor R1 is electrically connected to one end of the second resistor R2, and the other end of the second resistor R2 is electrically connected to the source of the second NMOS power transistor Q2;

[0031] The drain of the second NMOS power transistor Q2 is electrically connected to the test hardware that needs to be protected.

[0032] According to the present invention, each protection circuit further includes a first capacitor C1 and a second capacitor C2;

[0033] The plurality of control resistors include a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8;

[0034] The first capacitor C1 is connected across the gate and drain of the first NMOS power transistor Q1, and the second capacitor C2 is connected across the gate and drain of the second NMOS power transistor Q2;

[0035] The base of the first NPN transistor Q3 is electrically connected to the source of the second NMOS power transistor Q2, the collector is electrically connected to the gate of the first NMOS power transistor Q1 via the third resistor R3, and the emitter is electrically connected to the source of the first NMOS power transistor Q1 via the fourth resistor R4;

[0036] The base of the second NPN transistor Q4 is electrically connected to the source of the first NMOS power transistor Q1, the collector is electrically connected to the gate of the second NMOS power transistor Q2 via the seventh resistor R7, and the emitter is electrically connected to the source of the second NMOS power transistor Q2 via the sixth resistor R6.

[0037] According to the present invention, the other end of the first resistor R1 is also electrically connected to one end of the fifth resistor R5 and the eighth resistor R8 respectively;

[0038] The other end of the fifth resistor R5 is electrically connected to the gates of the first NMOS power transistor Q1 and the second NMOS power transistor Q2, and serves as the gate control terminal GATEx;

[0039] The other end of the eighth resistor R8 serves as a floating reference end FLOATING_VCOM.

[0040] According to the present invention, it also includes:

[0041] The isolated DC-DC power module is provided with a system power supply SYSTEM_POWER terminal, a system ground SYSTEM_GND terminal and positive and negative output terminals. The system power supply SYSTEM_POWER terminal and the system ground SYSTEM_GND terminal are respectively electrically connected to the system power supply SYSTEM_POWER and ground of the automated test equipment;

[0042] The LDO module includes a 10VLDO and a 5VLDO. The input terminals and ground terminals of the 10VLDO and 5VLDO are electrically connected to the positive and negative output terminals respectively. The ground terminals of the 10VLDO and 5VLDO are electrically connected to the floating reference terminal FLOATING_VCOM. The 10VLDO is provided with a 10V floating voltage FLOATING_10V output terminal, and the 5VLDO is provided with a 5V floating voltage FLOATING_5V output terminal.

[0043] According to the present invention, coupling capacitors are provided between the system power supply SYSTEM_POWER terminal and the system ground SYSTEM_GND terminal of the isolated DC-DC power regulator module, between the positive and negative output terminals, between the input terminal and the ground terminal of the 10V LDO, between the output terminal and the ground terminal of the 10V floating voltage FLOATING_10V, between the input terminal and the ground terminal of the 5V LDO, and between the output terminal and the ground terminal of the 5V floating voltage FLOATING_5V.

[0044] According to the present invention, it also includes:

[0045] The analog switch Analog Switch is provided with a V+ port, a CTRL port, a GND port, a COM port, an NC port, and a NO port. The V+ port and the NO port are electrically connected to the 10V floating voltage FLOATING_10V output terminal, the GND port and the NC port are electrically connected to the floating reference terminal FLOATING_VCOM, the COM port is electrically connected to the gate control terminal GATEx via a resistor, and the CTRL port is electrically connected to the control signal Gate_Control of the automated test equipment via a digital isolator Digital Isolator;

[0046] A NAND gate XOR, having a power supply terminal electrically connected to a 5V floating voltage FLOATING_5V output terminal, a ground terminal electrically connected to a floating reference terminal FLOATING_VCOM, and an input terminal electrically connected to the CTRL port;

[0047] DFF flip-flop - D-type Flip-Flop, the power supply terminal is electrically connected to the output terminal of the 5V floating voltage FLOATING_5V, the ground terminal is electrically connected to the floating reference terminal FLOATING_VCOM, the input terminal is electrically connected to the output terminal of the NAND gate XOR via a delay resistor, and the input terminal is also electrically connected to the floating reference terminal FLOATING_VCOM via a delay capacitor, the output terminal is electrically connected to the detection port of the automated test equipment via a digital isolator Digital Isolator, and the reset port is electrically connected to the clear control signal Gate_Control of the automated test equipment via the digital isolator Digital Isolator;

[0048] The LED has an input terminal electrically connected to the gate control terminal GATEx, an output terminal electrically connected to another input terminal of the NAND gate XOR, and an output terminal electrically connected to the floating reference terminal FLOATING_VCOM via a resistor.

[0049] The present invention also provides a multi-channel bidirectional current limiting protection method performed in the above protection circuit, comprising:

[0050] Each protection circuit forms a current path through a first NMOS power transistor Q1, a first resistor R1, a second resistor R2, and a second NMOS power transistor Q2 that are electrically connected in sequence;

[0051] Each protection circuit samples the total voltage of the first resistor R1 and the second resistor R2 through the first NPN transistor Q3, the second NPN transistor Q4 and multiple resistors, and adjusts the gate voltage of the first NMOS power transistor Q1 and the second NMOS power transistor Q2 based on the sampled total voltage value, so that both operate in the saturation region, thereby limiting the current in the current path.

[0052] According to the present invention, it also includes:

[0053] The drain of the first NMOS power transistor Q1 of each protection circuit is electrically connected to the total high current path of the automated test equipment, and the drain of the second NMOS power transistor Q2 is electrically connected to the test hardware to be protected;

[0054] The power supply from the automated test equipment is passed through the isolated DC-DC power regulator module and the LDO module to generate a floating 10V drive power supply, a floating 5V digital control power supply, and a floating reference terminal FLOATING_VCOM.

[0055] According to the present invention, it also includes:

[0056] Apply the control signal Gate_Control from the automated test equipment to the CTRL port of the analog switch Analog Switch and one input terminal of the NAND gate XOR through the digital isolator DigitalIsolator;

[0057] The gate control terminal GATEx is electrically connected to the LED input terminal, the LED output terminal is electrically connected to the other output terminal of the NAND gate XOR, and the LED output terminal is electrically connected to the floating reference terminal FLOATING_VCOM via a resistor;

[0058] The output end of the NAND gate XOR is electrically connected to the input end of the DFF trigger (D-type Flip-Flop) through a resistor-capacitor delay;

[0059] When the control signal Gate_Control is at a low level, the analog switch Analog Switch connects the gate control terminal GATEx to the floating reference terminal FLOATING_VCOM. At this time, the first NMOS power transistor Q1 and the second NMOS power transistor Q2 are completely turned off, the current path cannot conduct any current, and the LED is off, indicating to the user that the circuit is not working.

[0060] When the control signal Gate_Control is high, the analog switch Analog Switch connects the gate control terminal GATEx to the floating 10V drive power supply. At this time, the first NMOS power transistor Q1 and the second NMOS power transistor Q2 are turned on, and the LED lights up, indicating that the user circuit is working and ready to conduct current.

[0061] When the absolute value of the total voltage sampled across the first resistor R1 and the second resistor R2 is lower than the base-emitter voltage of the first NPN transistor Q3 and the second NPN transistor Q4, the first NPN transistor Q3 and the second NPN transistor Q4 are in the off state. At this time, the first NMOS power transistor Q1 and the second NMOS power transistor Q2 remain in the on state, and the conduction current is not affected.

[0062] When the absolute value of the total voltage sampled across the first resistor R1 and the second resistor R2 equals the base-emitter voltage of the first NPN transistor Q3 and the second NPN transistor Q4, one of the first NPN transistor Q3 and the second NPN transistor Q4 gradually turns on and pulls down the gate voltage of the first NMOS power transistor Q1 and the second NMOS power transistor Q2, causing the first NMOS power transistor Q1 and the second NMOS power transistor Q2 to operate in the saturation region, thereby limiting the current in the entire path. At this point, the LED does not light up, the XOR gate outputs a high level, and after a RC delay, the DFF trigger (D-type Flip-Flop) is activated to generate an error warning signal Fault_Check. This signal is then returned to the automated test equipment via digital isolation. The user reads this signal to ensure that no current limiting error occurs during high-current testing.

[0063] The present invention will be described in more detail below through specific examples. Example 1

[0064] like Figure 1 As shown, this embodiment provides a multi-channel bidirectional current limiting protection circuit, including:

[0065] The current path includes a first NMOS power transistor Q1, a first resistor R1, a second resistor R2 and a second NMOS power transistor Q2 electrically connected in sequence;

[0066] a sampling control unit, comprising a first NPN transistor Q3, a second NPN transistor Q4, and a plurality of control resistors, for sampling the total voltage of the first resistor R1 and the second resistor R2, and adjusting the gate voltages of the first NMOS power transistor Q1 and the second NMOS power transistor Q2 based on the sampled total voltage value so that both operate in a saturation region, thereby limiting the current in the current path;

[0067] The drain of the first NMOS power transistor Q1 is electrically connected to the total high current path of the automated testing equipment, and the source is electrically connected to one end of the first resistor R1;

[0068] The other end of the first resistor R1 is electrically connected to one end of the second resistor R2, and the other end of the second resistor R2 is electrically connected to the source of the second NMOS power transistor Q2;

[0069] The drain of the second NMOS power tube Q2 is electrically connected to the test hardware to be protected;

[0070] Each protection circuit further includes a first capacitor C1 and a second capacitor C2;

[0071] The plurality of control resistors include a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8;

[0072] The first capacitor C1 is connected across the gate and drain of the first NMOS power transistor Q1, and the second capacitor C2 is connected across the gate and drain of the second NMOS power transistor Q2;

[0073] The base of the first NPN transistor Q3 is electrically connected to the source of the second NMOS power transistor Q2, the collector is electrically connected to the gate of the first NMOS power transistor Q1 via the third resistor R3, and the emitter is electrically connected to the source of the first NMOS power transistor Q1 via the fourth resistor R4;

[0074] The base of the second NPN transistor Q4 is electrically connected to the source of the first NMOS power transistor Q1, the collector is electrically connected to the gate of the second NMOS power transistor Q2 via the seventh resistor R7, and the emitter is electrically connected to the source of the second NMOS power transistor Q2 via the sixth resistor R6;

[0075] The other end of the first resistor R1 is also electrically connected to one end of the fifth resistor R5 and one end of the eighth resistor R8 respectively;

[0076] The other end of the fifth resistor R5 is electrically connected to the gates of the first NMOS power transistor Q1 and the second NMOS power transistor Q2, and serves as the gate control terminal GATEx;

[0077] The other end of the eighth resistor R8 serves as a floating reference end FLOATING_VCOM;

[0078] like Figure 3 As shown, the isolated DC-DC power module is provided with a system power SYSTEM_POWER terminal, a system ground SYSTEM_GND terminal and positive and negative output terminals. The system power SYSTEM_POWER terminal and the system ground SYSTEM_GND terminal are electrically connected to the system power SYSTEM_POWER and ground of the automated test equipment respectively;

[0079] The LDO module includes a 10VLDO and a 5VLDO. The input terminals and ground terminals of the 10VLDO and 5VLDO are electrically connected to the positive and negative output terminals respectively. The ground terminals of the 10VLDO and 5VLDO are electrically connected to the floating reference terminal FLOATING_VCOM. The 10VLDO is provided with a 10V floating voltage FLOATING_10V output terminal, and the 5VLDO is provided with a 5V floating voltage FLOATING_5V output terminal.

[0080] The isolated DC-DC power module has coupling capacitors between the SYSTEM_POWER and SYSTEM_GND terminals, between the positive and negative output terminals, between the 10V LDO input and ground, between the 10V floating voltage FLOATING_10V output and ground, between the 5V LDO input and ground, and between the 5V floating voltage FLOATING_5V output and ground.

[0081] like Figure 4 As shown, the analog switch Analog Switch is provided with a V+ port, a CTRL port, a GND port, a COM port, an NC port, and a NO port. The V+ port and the NO port are electrically connected to the 10V floating voltage FLOATING_10V output terminal, the GND port and the NC port are electrically connected to the floating reference terminal FLOATING_VCOM, the COM port is electrically connected to the gate control terminal GATEx via a resistor, and the CTRL port is electrically connected to the control signal Gate_Control of the automated test equipment via a digital isolator Digital Isolator;

[0082] A NAND gate XOR, having a power supply terminal electrically connected to a 5V floating voltage FLOATING_5V output terminal, a ground terminal electrically connected to a floating reference terminal FLOATING_VCOM, and an input terminal electrically connected to the CTRL port;

[0083] DFF flip-flop - D-type Flip-Flop, the power supply terminal is electrically connected to the output terminal of the 5V floating voltage FLOATING_5V, the ground terminal is electrically connected to the floating reference terminal FLOATING_VCOM, the input terminal is electrically connected to the output terminal of the NAND gate XOR via a delay resistor, and the input terminal is also electrically connected to the floating reference terminal FLOATING_VCOM via a delay capacitor, the output terminal is electrically connected to the detection port of the automated test equipment via a digital isolator Digital Isolator, and the reset port is electrically connected to the clear control signal Gate_Control of the automated test equipment via the digital isolator Digital Isolator;

[0084] The LED has an input terminal electrically connected to the gate control terminal GATEx, an output terminal electrically connected to the other input terminal of the NAND gate XOR, and an output terminal electrically connected to the floating reference terminal FLOATING_VCOM via a resistor;

[0085] In this embodiment, Figure 2 As shown, the overall protection circuit is composed of multiple identical current limiting protection circuits, and the number of expansion paths is determined by actual hardware requirements;

[0086] The current path comes from a total large current channel GANGED_HC_PATH, and this total large current path directly comes from the ATE;

[0087] After passing through current limiting protection, each path protection circuit output path LIMITED_HC_PATHx is independently connected to the test hardware to be protected;

[0088] I(GANGED_PATH) = I(LIMITED_PATH1)+ I(LIMITED_PATH2)+ I(LIMITED_PATH3)+…。

[0089] This embodiment provides a multi-channel bidirectional current limiting protection method, including:

[0090] The power supply from the ATE system passes through the isolated DC-DC power module Isolated DC-DC power and the LDO module to generate the 10V floating voltage and 5V floating voltage required by the protection circuit;

[0091] When the control signal Gate_Control from the ATE system is at a low level L and closed, the analog switch AnalogSwitch connects the gate control terminal GATEx to the floating reference terminal FLOATING_VCOM, and the first NMOS power transistor Q1 and the second NMOS power transistor Q2 are completely turned off. At this time, the circuit cannot conduct any current, and at the same time, the LED module connected to the gate control terminal GATEx does not light up, indicating to the user that the circuit is not working at this time;

[0092] When the control signal Gate_Control is at a high level H and turned on, the analog switch Analog Switch connects the gate control terminal GATEx to the 10V floating voltage FLOATING_10V, and the first NMOS power transistor Q1 and the second NMOS power transistor Q2 are turned on; at the same time, the LED module connected to the gate control terminal GATEx lights up; indicating to the user that the circuit has started working and is ready to conduct current;

[0093] When the circuit conducts current I, the voltage drop V across the first resistor R1 and the second resistor R2 is V = I*(R1 + R2); when V is positive, it conducts a positive current, and when V is negative, the conduction is a negative current; the B-E voltage drops of the first NPN transistor Q3 and the second NPN transistor Q4 are Vbe;

[0094] When |V| < Vbe, the first NPN transistor Q3 and the second NPN transistor Q4 are in the off state; the first NMOS power transistor Q1 and the second NMOS power transistor Q2 still maintain the on state; the conduction current is not affected at all;

[0095] When V=Vbe (the current direction is positive), the second NPN transistor Q4 gradually turns on and pulls down the gate voltage of the first NMOS power transistor Q1 and the second NMOS power transistor Q2, so that the first NMOS power transistor Q1 and the second NMOS power transistor Q2 operate in the saturation region, thereby limiting the current of the entire path;

[0096] When V=-Vbe (the current direction is negative), the first NPN transistor Q3 gradually turns on and pulls down the gate voltage of the first NMOS power transistor Q1 and the second NMOS power transistor Q2, so that the first NMOS power transistor Q1 and the second NMOS power transistor Q2 operate in the saturation region, thereby limiting the current of the entire path;

[0097] Therefore, the current limit value of the circuit is determined by Vbe / (R1+R2); if the current limit value needs to be changed, the resistance values ​​of the first resistor R1 and the second resistor R2 can be changed;

[0098] When the circuit enters current-limit protection, the voltage at the gate control terminal GATEx is pulled low (depending on the gate voltage at the saturation current point of the output characteristics of the first NMOS power transistor Q1 and the second NMOS power transistor Q2). The LED module turns off, and the XOR gate outputs a high level H. After an RC delay, the DFF trigger (D-type Flip-Flop) is activated to generate an error warning signal Fault_Check, which is returned to the ATE via digital isolation. Users can read this signal to ensure that no current-limiting errors occur during high-current testing. The error signal remains until the user resets the trigger using the clear signal Clear_Control.

[0099] Because the digital isolator and analog switch operate very quickly, the speed at which the entire circuit is turned on and off depends on the gate capacitance and gate resistance of the first NMOS power transistor Q1 and the second NMOS power transistor Q2. Therefore, this circuit can also be used as a high-current analog switch that dynamically controls the entire current path and has a built-in current limiting function.

[0100] In this embodiment, the isolated floating power supply design allows it to be connected in series with any high-side or low-side high-current path. Before the current flowing through each path falls below the constant current point, it is transparent to the current path and does not affect normal test results. Once the current flowing through each path (regardless of positive or negative) reaches the constant current point, the protection circuit activates and limits the maximum current flowing through it, thereby protecting the probes and spring pins on the test hardware.

[0101] The multi-channel bidirectional current limiting protection circuit proposed in the embodiment of the present invention samples the total voltage of the first resistor R1 and the second resistor R2 through the first NPN transistor Q3, the second NPN transistor Q4 and multiple control resistors, and adjusts the gate voltage of the first NMOS power transistor Q1 and the second NMOS power transistor Q2 based on the sampled total voltage value, so that both operate in the saturation region, thereby limiting the current in the current path, thereby effectively protecting the probes and spring pins on the test hardware.

[0102] While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A multi-channel bidirectional current limiting protection circuit, characterized in that: Each protection circuit includes: A current path includes a first NMOS power tube, a first resistor, a second resistor, and a second NMOS power tube electrically connected in sequence; a sampling control unit, comprising a first NPN transistor, a second NPN transistor, and a plurality of control resistors, configured to sample the total voltage of the first resistor and the second resistor, and adjust the gate voltages of the first NMOS power transistor and the second NMOS power transistor based on the sampled total voltage value so that both operate in a saturation region, thereby limiting the current in the current path; The drain of the first NMOS power tube is electrically connected to the total high current path of the automated testing equipment, and the source is electrically connected to one end of the first resistor; The other end of the first resistor is electrically connected to one end of the second resistor, and the other end of the second resistor is electrically connected to the source of the second NMOS power transistor; The drain of the second NMOS power tube is electrically connected to the test hardware to be protected; Each protection circuit also includes a first capacitor and a second capacitor; The plurality of control resistors include a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor; The first capacitor is connected across the gate and drain of the first NMOS power transistor, and the second capacitor is connected across the gate and drain of the second NMOS power transistor; The base of the first NPN transistor is electrically connected to the source of the second NMOS power transistor, the collector is electrically connected to the gate of the first NMOS power transistor via the third resistor, and the emitter is electrically connected to the source of the first NMOS power transistor via the fourth resistor; The base of the second NPN transistor is electrically connected to the source of the first NMOS power transistor, the collector is electrically connected to the gate of the second NMOS power transistor via the seventh resistor, and the emitter is electrically connected to the source of the second NMOS power transistor via the sixth resistor; The other end of the first resistor is also electrically connected to one end of the fifth resistor and the eighth resistor respectively; The other end of the fifth resistor is electrically connected to the gates of the first NMOS power transistor and the second NMOS power transistor, and serves as a gate control end; The other end of the eighth resistor serves as a floating reference end.

2. The protection circuit according to claim 1, wherein: Also includes: An isolated DC voltage stabilizing module is provided with a system power supply terminal, a system ground terminal and positive and negative output terminals, wherein the system power supply terminal and the system ground terminal are electrically connected to the system power supply and ground of the automated test equipment respectively; The LDO module includes a 10V LDO and a 5V LDO. The input terminals and ground terminals of the 10V LDO and 5V LDO are electrically connected to the positive and negative output terminals respectively. The ground terminals of the 10V LDO and 5V LDO are electrically connected to the floating reference terminal. The 10V LDO is provided with a 10V floating voltage output terminal, and the 5V LDO is provided with a 5V floating voltage output terminal.

3. The protection circuit according to claim 2, wherein: Coupling capacitors are provided between the system power supply terminal and the system ground terminal of the isolated DC voltage regulator module, between the positive and negative output terminals, between the input terminal and the ground terminal of the 10V LDO, between the 10V floating voltage output terminal and the ground terminal, between the input terminal and the ground terminal of the 5V LDO, and between the 5V floating voltage output terminal and the ground terminal.

4. The protection circuit according to claim 2, wherein: Also includes: an analog switch, provided with a V+ port, a CTRL port, a GND port, a COM port, an NC port, and a NO port, wherein the V+ port and the NO port are electrically connected to the 10V floating voltage output terminal, the GND port and the NC port are electrically connected to the floating reference terminal, the COM port is electrically connected to the gate control terminal via a resistor, and the CTRL port is electrically connected to the control signal of the automated test equipment via a digital isolator; a NAND gate, having a power supply terminal electrically connected to the 5V floating voltage output terminal, a ground terminal electrically connected to the floating reference terminal, and an input terminal electrically connected to the CTRL port; A DFF trigger, wherein a power supply terminal is electrically connected to the 5V floating voltage output terminal, a ground terminal is electrically connected to the floating reference terminal, an input terminal is electrically connected to the output terminal of the NAND gate via a delay resistor, an input terminal is further electrically connected to the floating reference terminal via a delay capacitor, an output terminal is electrically connected to the detection port of the automated test equipment via a digital isolator, and a reset port is electrically connected to a clear control signal of the automated test equipment via a digital isolator; The LED has an input terminal electrically connected to the gate control terminal, an output terminal electrically connected to another input terminal of the NAND gate, and an output terminal electrically connected to the floating reference terminal via a resistor.

5. A multi-channel bidirectional current limiting protection method implemented in the protection circuit according to any one of claims 1 to 4, characterized in that: include: Each protection circuit forms a current path through a first NMOS power tube, a first resistor, a second resistor, and a second NMOS power tube electrically connected in sequence; Each protection circuit samples the total voltage of the first resistor and the second resistor through a first NPN transistor, a second NPN transistor and multiple resistors, and adjusts the gate voltage of the first NMOS power transistor and the second NMOS power transistor based on the sampled total voltage value so that both operate in the saturation region, thereby limiting the current in the current path.

6. The method according to claim 5, characterized in that Also includes: Electrically connect the drain of the first NMOS power transistor of each protection circuit to the total high current path of the automated test equipment, and electrically connect the drain of the second NMOS power transistor to the test hardware to be protected; The power supply from the automated test equipment is passed through an isolated DC voltage regulator module and an LDO module to generate a floating 10V drive power supply, a floating 5V digital control power supply and a floating reference terminal.

7. The method according to claim 6, characterized in that Also includes: Apply the control signal from the automated test equipment to the CTRL port of the analog switch and one input end of the NAND gate through the digital isolator; The gate control terminal is electrically connected to the LED input terminal, the LED output terminal is electrically connected to the other output terminal of the NAND gate, and the LED output terminal is electrically connected to the floating reference terminal via a resistor; The output terminal of the NAND gate is electrically connected to the input terminal of the DFF trigger via a resistance-capacitance delay; When the control signal is at a low level, the analog switch connects the gate control terminal to the floating reference terminal. At this time, the first NMOS power transistor and the second NMOS power transistor are completely turned off, the current path cannot conduct any current, and the LED is off, indicating to the user that the protection circuit is not working at this time; When the control signal is high, the analog switch connects the gate control terminal to the floating 10V drive power supply. At this time, the first NMOS power transistor and the second NMOS power transistor are turned on, and the LED lights up, indicating that the user circuit is working and ready to conduct current. When the absolute value of the total voltage sampled across the first resistor and the second resistor is lower than the base-emitter voltage of the first NPN transistor and the second NPN transistor, the first NPN transistor and the second NPN transistor are in a turned-off state. At this time, the first NMOS power transistor and the second NMOS power transistor remain in an turned-on state, and the conduction current is not affected. When the absolute value of the total voltage sampled across the first resistor and the second resistor is equal to the base-emitter voltage of the first and second NPN transistors, one of the first and second NPN transistors gradually turns on and pulls down the gate voltage of the first and second NMOS power transistors, causing the first and second NMOS power transistors to operate in a saturation region, thereby limiting the current in the entire path. At this point, the LED does not light up, the XOR gate outputs a high level, and after a resistor-capacitor delay, the DFF trigger is activated to generate an error warning signal, which is then returned to the automated test equipment via digital isolation. The user reads the signal to ensure that no current limiting error occurs during high-current testing.

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