Voltage-controlled oscillator and phase-locked loop including voltage-controlled oscillator

Abstract

The invention provides a voltage-controlled oscillator and a phase-locked loop including the same. The voltage-controlled oscillator includes: a first driving transistor including a first gate terminal connected to a first output node, the first driving transistor being connected between a second output node and a ground node; a second driving transistor connected between the first output node and the ground node, the second driving transistor including a second gate terminal connected to a second output node; a first inductor connected between the first output node and the second output node; and a second inductor and a first variable capacitance circuit connected in parallel between the first coupling node and the second coupling node. The second inductor receives the control voltage and is inductively coupled to the first inductor.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0026691 filed on February 23, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a voltage-controlled oscillator configured to generate an output clock having a frequency corresponding to a control voltage and a phase-locked loop including the voltage-controlled oscillator. Background Art

[0003] Recently, as the frequency of clocks used in electronic devices increases, there is a demand for voltage-controlled oscillators that generate high-frequency clocks with minimal noise.

[0004] A voltage-controlled oscillator (VCO) can generate an output clock based on a control voltage. For example, the VCO may include an inductance tank circuit and a capacitance tank circuit. The VCO can adjust the frequency of the output clock by adjusting the capacitance of a varactor included in the capacitance tank circuit.

[0005] However, if the voltage controlled oscillator is configured to adjust the frequency of the output clock based on the varactor, the output clock may contain significant noise due to characteristics of the varactor and the circuit configuration of the voltage controlled oscillator. Summary of the Invention

[0006] Some example embodiments of the present disclosure are provided to solve the above technical problems. For example, some example embodiments provide a voltage-controlled oscillator that generates a high-frequency output clock with reduced (and / or minimized) noise, and a phase-locked loop including the voltage-controlled oscillator.

[0007] Some example embodiments of the present disclosure provide a voltage-controlled oscillator, comprising: a first drive transistor including a first gate terminal connected to a first output node, the first drive transistor being connected between a second output node and a ground node; a second drive transistor connected between the first output node and the ground node, the second drive transistor including a second gate terminal connected to the second output node; a first inductor connected between the first output node and the second output node; a second inductor connected in parallel between a first coupling node and a second coupling node; and a first variable capacitance circuit connected in parallel between the first coupling node and the second coupling node. The second inductor receives a control voltage and is inductively coupled to the first inductor.

[0008] Some example embodiments of the present disclosure also provide a voltage-controlled oscillator that receives a control voltage and outputs a first output clock and a second output clock having a frequency corresponding to the amplitude of the control voltage. The voltage-controlled oscillator includes: a first drive transistor including a first gate terminal connected to a first output node, through which the first output clock is output, and the first drive transistor is connected between the second output node and a ground node; a second drive transistor connected between the first output node and the ground node, the second drive transistor including a second gate terminal connected to the second output node, through which the second output clock is output; an inductive oscillation circuit connected between the first output node and the second output node; and a capacitive oscillation circuit inductively coupled to the inductive oscillation circuit, the capacitive oscillation circuit operating based on an externally provided control voltage.

[0009] Some example embodiments of the present disclosure further provide a phase-locked loop (PLL), comprising: a voltage-controlled oscillator (VCO) that generates a first output clock and a second output clock based on a control voltage; a frequency divider that generates a feedback clock based on the first output clock and the second output clock; a phase frequency detector that generates a differential signal based on a difference between the feedback clock and an externally provided reference clock; and a control voltage generator that adjusts the level of the control voltage based on the differential signal. The VCO comprises: a first inductor connected between a first output node that outputs the first output clock and a second output node that outputs the second output clock; a second inductor connected between a first coupling node and a second coupling node, the first coupling node and the second coupling node being electrically isolated from the first output node and the second output node, the second inductor receiving the control voltage and inductively coupled to the first inductor; a first varactor connected between the first coupling node and a first intermediate node that receives a first bias voltage; and a second varactor connected between the second coupling node and the first intermediate node. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a phase-locked loop according to some example embodiments of the present disclosure.

[0011] Figure 2 It shows Figure 1 The graph of the quality factor of the capacitor oscillation circuit and the inductor oscillation circuit.

[0012] Figure 3 is a diagram illustrating implementation according to some example embodiments Figure 1 Circuit diagram of a voltage controlled oscillator.

[0013] Figure 4 is a diagram illustrating implementation according to some example embodiments Figure 3 Circuit diagram of the capacitor oscillation circuit.

[0014] Figure 5 is a diagram illustrating implementation according to some example embodiments Figure 2 Circuit diagram of the capacitor oscillation circuit.

[0015] Figure 6 It shows that some exemplary embodiments of the present disclosure are implemented Figure 1 Circuit diagram of a voltage controlled oscillator.

[0016] Figure 7 is a diagram illustrating a method according to some example embodiments Figure 6 Circuit diagram of the voltage controlled oscillator configuration.

[0017] Figure 8 Shown included in Figure 1 The frequency component in the output clock generated by the voltage controlled oscillator.

[0018] Figure 9 It shows that according to Figure 7 A graph showing the relationship between the bias voltage, the control voltage, and the capacitance of a variable capacitance circuit.

[0019] Figure 10 is a diagram illustrating implementation according to some example embodiments Figure 6 Circuit diagram of the voltage controlled oscillator configuration.

[0020] Figure 11 It shows Figure 10 A graph showing the relationship between the capacitance of each of the plurality of variable capacitance circuits and the capacitance of the capacitance oscillation circuit.

[0021] Figure 12 and Figure 13 is a more detailed illustration of the Figure 7 or Figure 10 Circuit diagram of a variable capacitor circuit.

[0022] Figure 14 It shows Figure 12 and Figure 13 FIG. 1 is a diagram showing the relationship between the control voltage and the capacitance of the variable capacitance circuit.

[0023] Figure 15 Showing implementation according to some example embodiments Figure 1 voltage controlled oscillator.

[0024] Figure 16 Showing implementation according to some example embodiments Figure 1 voltage controlled oscillator. DETAILED DESCRIPTION

[0025] Hereinafter, some example embodiments of the present disclosure will be described in clear and detailed manner so that a person skilled in the art can easily implement the present disclosure. Details (such as configuration and structure) are provided only to help fully understand some example embodiments of the present disclosure. Therefore, without departing from the technical spirit and scope of the present disclosure, variations of some example embodiments described herein may be performed by a person skilled in the art. In addition, for the sake of clarity and brevity, descriptions of well-known functions and structures are omitted. Components in the following figures or detailed descriptions may be connected to other components in addition to the components shown in the figures or described in the detailed description. The terms used herein are defined in consideration of the functions of the present disclosure and are not limited to specific functions. The definition of the terms may be determined based on the matters described in the detailed description.

[0026] Components described with reference to terms such as drivers or blocks used in the detailed description may be implemented in the form of software, hardware, or a combination thereof. For example, software may include machine code, firmware, embedded code, and application software. For example, hardware may include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, inertial sensors, MEMS (Micro Electro Mechanical Systems), passive devices, or a combination thereof.

[0027] In addition, for example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C") may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C (such as, for example, ABC, AB, BC, and AC).

[0028] Figure 1 is a block diagram illustrating a phase-locked loop according to some example embodiments of the present disclosure. Figure 1 The phase-locked loop PLL may include a phase frequency detector PFD, a control voltage generator CVG, a voltage-controlled oscillator VCO, and a frequency divider DIV.

[0029] A voltage-controlled oscillator (VCO) may include a capacitor oscillator circuit (CTC) and an inductor oscillator circuit (ITC). The VCO may receive a control voltage (VCTRL). The VCO generates an output clock (OCLK) having a frequency corresponding to the voltage level of the control voltage (VCTRL) by adjusting the capacitance of the capacitor oscillator circuit (CTC) and / or the inductance of the inductor oscillator circuit (ITC) based on the control voltage (VCTRL). In other words, the VCO may be implemented as an inductor-capacitor (LC-VCO). The configuration of the VCO will be described with reference to the following figures.

[0030] In some example embodiments, the frequency of the output clock OCLK may be determined as the resonant frequency of the voltage-controlled oscillator VCO. The resonant frequency for the voltage-controlled oscillator VCO may be determined based on the inductance of the inductive oscillation circuit ITC and the capacitance of the capacitive oscillation circuit CTC. In this manner, the frequency of the output clock OCLK may be changed based on the inductance of the inductive oscillation circuit ITC and / or the capacitance of the capacitive oscillation circuit CTC according to changes in the voltage level of the control voltage VCTRL.

[0031] The magnitude of the phase noise included in the output clock OCLK may be determined based on the quality factor of the voltage-controlled oscillator (VCO). For example, the higher the quality factor of the voltage-controlled oscillator (VCO), the smaller the magnitude of the phase noise included in the output clock OCLK. Conversely, the smaller the quality factor of the voltage-controlled oscillator (VCO), the larger the magnitude of the phase noise included in the output clock OCLK.

[0032] The magnitude of the phase noise included in the output clock OCLK may be calculated and / or determined based on various equations (such as the Leeson equation). However, the scope of the present disclosure is not limited to a specific method of calculating and / or determining the magnitude of the phase noise included in the output clock OCLK.

[0033] The quality factor of the voltage-controlled oscillator (VCO) can be determined based on the quality factors of the inductor oscillator circuit (ITC) and the capacitor oscillator circuit (CTC). For example, the quality factor of the voltage-controlled oscillator (VCO) can be determined by the harmonic mean of the quality factors of the inductor oscillator circuit (ITC) and the capacitor oscillator circuit (CTC). Therefore, the higher the quality factors of the inductor oscillator circuit (ITC) and the capacitor oscillator circuit (CTC), the lower the phase noise of the output clock (OCLK).

[0034] In some example embodiments, a quality factor for any circuit may be defined based on the ratio of energy stored in the circuit to energy lost during one cycle of the output clock OCLK. For example, the quality factor of the inductor oscillation circuit ITC may be defined based on the ratio of the total energy stored in the inductor oscillation circuit ITC to the energy lost during one cycle of the output clock OCLK from the inductor oscillation circuit ITC. Similarly, the quality factor of the capacitor oscillation circuit CTC may be defined based on the ratio of the total energy stored in the capacitor oscillation circuit CTC to the energy lost during one cycle of the output clock OCLK from the capacitor oscillation circuit CTC. However, the scope of the present disclosure is not limited in this regard.

[0035] The quality factor of the inductor oscillation circuit ITC and the quality factor of the capacitor oscillation circuit CTC can be changed according to the frequency of the output clock OCLK. Figure 2The quality factor of the inductance oscillation circuit ITC and the quality factor of the capacitance oscillation circuit CTC regarding the output clock OCLK are described in more detail.

[0036] The frequency divider DIV may receive the output clock OCLK. The frequency divider DIV may generate the feedback clock FCLK by dividing the output clock OCLK. For example, the frequency of the feedback clock FCLK may be lower than the frequency of the output clock OCLK.

[0037] In some example embodiments, the frequency divider DIV may adjust the frequency division ratio in response to (e.g., based on) a control signal (not shown) provided from outside the phase-locked loop PLL. For example, the frequency divider DIV may increase or decrease the frequency of the feedback clock FCLK in response to a control signal (not shown) provided from outside the phase-locked loop PLL.

[0038] The phase frequency detector PFD may receive the feedback clock FCLK and the reference clock RCLK and may generate a differential signal DS based on the difference between the feedback clock FCLK and the reference clock RCLK.

[0039] In some example embodiments, the reference clock RCLK may be provided from an oscillator external to the phase-locked loop PLL. For example, the reference clock RCLK may be provided from a crystal oscillator external to the phase-locked loop PLL. However, the scope of the present disclosure is not limited to a specific type of oscillator that generates the reference clock RCLK.

[0040] In some example embodiments, the frequency of the reference clock RCLK may be lower than the frequency of the output clock OCLK.

[0041] The control voltage generator CVG can generate the control voltage VCTRL based on the differential signal DS. In other words, the control voltage generator CVG can adjust the voltage level of the control voltage VCTRL based on the differential signal DS. For example, the voltage-controlled oscillator VCO can generate an output clock OCLK having a changed frequency in response to the adjusted control voltage VCTRL. In this way, the voltage level of the control voltage VCTRL can be adjusted until the output clock OCLK has a desired frequency.

[0042] In some example embodiments, even if the control voltage generator CVG provides the control voltage VCTRL that allows the voltage-controlled oscillator VCO to generate a desired frequency, various types of noise may be included in the output clock OCLK generated by the voltage-controlled oscillator VCO. For example, the output clock OCLK may include various types of noise (such as thermal noise and phase noise caused by circuit elements for controlling the inductance of the inductive oscillation circuit ITC or the capacitance of the capacitive oscillation circuit CTC). For example, jitter may occur in the output clock OCLK based on the amplitude of the noise included in the output clock OCLK.

[0043] Figure 2 It shows Figure 1 The quality factor curve of the capacitor oscillator circuit and the inductor oscillator circuit. Figures 1 to 2 , the quality factor QF_CTC for the capacitive oscillation circuit CTC and the quality factor QF_ITC for the inductive oscillation circuit ITC may vary according to the frequency of the output clock OCLK. Figure 2 The horizontal axis may represent frequency, and the vertical axis may represent quality factor QF. The quality factor QF_CTC for the capacitive oscillation circuit CTC is shown by a dotted line, and the quality factor QF_ITC for the inductive oscillation circuit ITC is shown by a solid line.

[0044] When the frequency of the output clock OCLK is greater than or equal to a specific value, the slope of the quality factor QF_CTC with respect to the frequency of the output clock OCLK may be negative. For example, as the frequency of the output clock OCLK increases, the quality factor QF_CTC may decrease. In other words, as the frequency of the output clock OCLK increases, the quality factor of the voltage-controlled oscillator (VCO) may decrease due to the quality factor QF_CTC, and accordingly, greater phase noise may be included in the output clock OCLK.

[0045] That is, when the voltage controlled oscillator VCO is implemented as an inductor-capacitor based voltage controlled oscillator (LC-VCO), the output clock OCLK having a high frequency may include large phase noise due to the capacitor oscillation circuit CTC.

[0046] Figure 3 is a diagram illustrating implementation according to some example embodiments Figure 1 The circuit diagram of the voltage controlled oscillator. Figures 1 to 3 The voltage controlled oscillator VCO may include a first driving transistor DT1 and a second driving transistor DT2, an inductive oscillation circuit ITC and a capacitive oscillation circuit CTC.

[0047] The first driving transistor DT1 may be connected between the second output node Nout2 and the ground node Ngnd. A gate terminal of the first driving transistor DT1 may be connected to the first output node Nout1.

[0048] The second driving transistor DT2 may be connected between the first output node Nout1 and the ground node Ngnd. A gate terminal of the second driving transistor DT2 may be connected to the second output node Nout2.

[0049] For a more concise description, the following assumes that the first and second drive transistors DT1 and DT2 are N-type metal oxide semiconductors (NMOS). However, the scope of the present disclosure is not limited to a specific type of first and second drive transistors DT1 and DT2. For example, one or more of the first and second drive transistors DT1 and DT2 may be implemented as P-type metal oxide semiconductors (PMOS).

[0050] The inductor oscillating circuit ITC may be connected between the first output node Nout1 and the second output node Nout2. Hereinafter, for a more concise description, it is assumed that the inductance of the inductor oscillating circuit ITC is fixed. However, the scope of the present disclosure is not limited thereto. For example, the inductance of the inductor oscillating circuit ITC may be implemented as variable.

[0051] The capacitor oscillator circuit CTC may be connected between the first output node Nout1 and the second output node Nout2. The capacitor oscillator circuit CTC may be connected in parallel with the inductor oscillator circuit ITC.

[0052] The capacitor oscillator circuit CTC may be connected to a control node Nctrl. The capacitor oscillator circuit CTC may receive a control voltage VCTRL via the control node Nctrl. The capacitor oscillator circuit CTC may operate based on the control voltage VCTRL. For example, the capacitance of the capacitor oscillator circuit CTC may vary based on the control voltage VCTRL.

[0053] The output clock OCLK may include at least one of a first output clock OCLK and a second output clock OCLK.

[0054] The first output node Nout1 may output a first output clock OCLK1. The second output node Nout2 may output a second output clock OCLK2. The first output clock OCLK1 and the second output clock OCLK2 may have opposite phases. The first output clock OCLK1 and the second output clock OCLK2 may have the same frequency. For example, the frequencies of the first output clock OCLK1 and the second output clock OCLK2 may be about the resonant frequency of the voltage-controlled oscillator (VCO).

[0055] Figure 4 is a diagram illustrating implementation according to some example embodiments Figure 3 The circuit diagram of the capacitor oscillation circuit. Figures 1 to 4 , the capacitor oscillation circuit CTC can be implemented as a capacitor oscillation circuit CTCa.

[0056] The capacitor oscillator circuit CTCa may include a first varactor VR1 and a second varactor VR2. The first varactor VR1 may be connected between the first output node Nout1 and the control node Nctrl. The second varactor VR2 may be connected between the second output node Nout2 and the control node Nctrl. The control node Nctrl may receive a control voltage VCTRL.

[0057] The capacitance of the capacitor oscillator circuit CTCa can be determined based on the capacitances of the first varactor VR1 and the second varactor VR2. The capacitance of the first varactor VR1 can be determined based on the voltage difference between its two terminals, and the capacitance of the second varactor VR2 can be determined based on the voltage difference between its two terminals. The voltage levels of the first output node Nout1 and the second output node Nout2 can be difficult to adjust. For example, the capacitance of the capacitor oscillator circuit CTCa can be determined based on the control voltage VCTRL.

[0058] However, the maximum variation range of the control voltage VCTRL can be limited. For example, the voltage level variation of the control voltage VCTRL can be limited. For example, the capacitance variation range of the capacitor oscillator circuit CTCa can be limited, and accordingly, the frequency variation range of the output clock OCLK (e.g., the first output clock OCLK1 and the second output clock OCLK2) can be limited. For example, when the capacitance of the capacitor oscillator circuit CTCa is controlled based solely on the control voltage VCTRL, the frequency variation range of the output clock OCLK can be limited.

[0059] Figure 5 is a diagram illustrating implementation according to some example embodiments Figure 2 The circuit diagram of the capacitor oscillation circuit. Figures 1 to 5 , the capacitor oscillation circuit CTC can be implemented as a capacitor oscillation circuit CTCb.

[0060] The capacitive oscillation circuit CTCb may include a first cut-off capacitor CC1 , a second cut-off capacitor CC2 , a first resistor R1 , a second resistor R2 , a first varactor VR1 , and a second varactor VR2 .

[0061] The first varactor VR1 may be connected between the first isolation node NS1 and the control node Nctrl. The second varactor VR2 may be connected between the second isolation node NS2 and the control node Nctrl. The control node Nctrl may receive a control voltage VCTRL.

[0062] The first cut-off capacitor CC1 may be connected between the first output node Nout1 and the first isolation node NS1. The second cut-off capacitor CC2 may be connected between the second output node Nout2 and the second isolation node NS2. That is, the first cut-off capacitor CC1 may electrically isolate the first output node Nout1 from the first isolation node NS1, and the second cut-off capacitor CC2 may electrically isolate the second output node Nout2 from the second isolation node NS2.

[0063] The first resistor R1 may be connected between the bias node NB and the first separation node NS1. The second resistor R2 may be connected between the bias node NB and the second separation node NS2. The bias node NB may receive a bias voltage VBIAS.

[0064] The capacitance of the first varactor VR1 can be determined based on the voltage difference between the first isolation node NS1 and the control node Nctrl, and the capacitance of the second varactor VR2 can be determined based on the voltage difference between the second isolation node NS2 and the control node Nctrl. The voltage levels of the first isolation node NS1 and the second isolation node NS2 can be determined based on the bias voltage VBIAS. The voltage level of the control node Nctrl can be determined based on the control voltage VCTRL. For example, the capacitance of the first varactor VR1 and the second varactor VR2 can be determined based on the bias voltage VBIAS and the control voltage VCTRL. Therefore, compared to the first varactor VR1 and the second varactor VR2 included in the capacitor oscillation circuit CTCa, the capacitance variation range of the first varactor VR1 and the second varactor VR2 included in the capacitor oscillation circuit CTCb can be relatively larger.

[0065] However, the capacitance of capacitor oscillator circuit CTCb can be determined based on the capacitances of first cutoff capacitor CC1, second cutoff capacitor CC2, first varactor VR1, and second varactor VR2. For example, due to first cutoff capacitor CC1 and second cutoff capacitor CC2, the capacitance of capacitor oscillator circuit CTCb can be relatively slightly changed even if the capacitances of first varactor VR1 and second varactor VR2 are changed. Therefore, due to first cutoff capacitor CC1 and second cutoff capacitor CC2, the frequency variation range of output clock OCLK can be limited.

[0066] Unlike the capacitor oscillation circuit CTCa, the capacitor oscillation circuit CTCb may further include a first resistor R1 and a second resistor R2. For example, thermal noise may be included in the output clock OCLK due to the first resistor R1 and the second resistor R2.

[0067] Figure 6 It shows that some exemplary embodiments of the present disclosure are implemented Figure 1 The circuit diagram of the voltage controlled oscillator. Figures 1 to 2 as well as Figure 6 The voltage controlled oscillator VCO may include a first driving transistor DT1 and a second driving transistor DT2, an inductor oscillation circuit ITC and a capacitor oscillation circuit CTC. The configuration and operation of the first driving transistor DT1 and the second driving transistor DT2 and the inductor oscillation circuit ITC are similar to those of the reference Figure 3 The configuration and operation of the first and second driving transistors DT1 and DT2 and the inductor oscillation circuit ITC are described, and thus a detailed description of the configuration and operation of the first and second driving transistors DT1 and DT2 and the inductor oscillation circuit ITC will be omitted.

[0068] The capacitor oscillator circuit CTC may be connected to a control node Nctrl. The capacitor oscillator circuit CTC may receive a control voltage VCTRL via the control node Nctrl. The capacitor oscillator circuit CTC may be operated based on the control voltage VCTRL. For example, the capacitance of the capacitor oscillator circuit CTC may vary based on the control voltage VCTRL.

[0069] The capacitive oscillating circuit CTC may be electrically isolated from the first output node Nout1 and the second output node Nout2. For example, the capacitive oscillating circuit CTC may be inductively coupled to the inductive oscillating circuit ITC. That is, instead of being directly electrically connected to the first output node Nout1 and the second output node Nout2, the capacitive oscillating circuit CTC may be indirectly connected via an inductive coupling scheme.

[0070] When the capacitor oscillation circuit CTC is indirectly connected to the first output node Nout1 and the second output node Nout2 through inductive coupling, the noise component provided from the capacitor oscillation circuit CTC to the first output node Nout1 and the second output node Nout2 can be attenuated. For example, when the capacitor oscillation circuit CTC is indirectly connected to the first output node Nout1 and the second output node Nout2 through inductive coupling, the influence of the low quality factor QF_CTC of the capacitor oscillation circuit CTC that occurs when the output clock OCLK is a high frequency can be reduced (and / or minimized). Therefore, according to some example embodiments of the present disclosure, the phase noise included in the output clock OCLK can be reduced (and / or minimized), and accordingly, the jitter of the output clock OCLK can be reduced (and / or minimized). Figure 7 A method of indirectly connecting the capacitive oscillation circuit CTC to the first output node Nout1 and the second output node Nout2 through inductive coupling is described in more detail.

[0071] In some example embodiments, the inductive coupling coefficient of the capacitive oscillation circuit CTC and the inductive oscillation circuit ITC may be 'k'. For example, the ratio of the frequency control amount of the output clock OCLK to the control voltage VCTRL may be determined based on the inductive coupling coefficient 'k'. However, the scope of the present disclosure is not limited thereto.

[0072] Figure 7 is a diagram illustrating implementation according to some example embodiments Figure 6 The circuit diagram of the voltage controlled oscillator configuration. Figures 1 to 2 and Figures 6 and 7 The voltage-controlled oscillator (VCO) may include first and second drive transistors DT1 and DT2, an inductive oscillation circuit (ITC), and a capacitive oscillation circuit (CTC). The capacitive oscillation circuit (CTC) may be implemented as a capacitive oscillation circuit (CTCc). Since the configuration and operation of the first and second drive transistors DT1 and DT2 are similar to those described above, a detailed description of the configuration and operation of the first and second drive transistors DT1 and DT2 will be omitted.

[0073] The inductive oscillation circuit ITC may include a first inductor L1. The first inductor L1 may be connected between the first output node Nout1 and the second output node Nout2.

[0074] In some example embodiments, the first inductor L1 may include a first center tap node. Figure 7 As shown in , the first center tap node can be connected to the power supply voltage VDD. For example, since power can be stably supplied to the first and second drive transistors DT1 and DT2, the voltage controlled oscillator VCO can oscillate more stably. However, the scope of the present disclosure is not limited thereto.

[0075] The capacitance oscillation circuit CTCc may include a second inductor L2 and a variable capacitance circuit VCC. The second inductor L2 may be connected between a first coupling node NCa and a second coupling node NCb. The variable capacitance circuit VCC may be connected between the first coupling node NCa and the second coupling node NCb. In other words, the second inductor L2 and the variable capacitance circuit VCC may be connected in parallel between the first coupling node NCa and the second coupling node NCb.

[0076] In some example embodiments, the first and second coupling nodes NCa and NCb may be electrically separated from the first and second output nodes Nout1 and Nout2 .

[0077] In some example embodiments, the capacitance oscillation circuit CTC may include a plurality of variable capacitance circuits VCC. For example, the second inductor L2 and the plurality of variable capacitance circuits VCC may be connected in parallel between the first coupling node NCa and the second coupling node NCb. Figure 10 Some example embodiments in which the capacitance oscillation circuit CTC includes a plurality of variable capacitance circuits VCC are described in more detail.

[0078] The second inductor L2 may include a second center tap node connected to the control node Nctrl. That is, the second inductor L2 may receive the control voltage VCTRL through the second center tap node. For example, the voltage levels of the first coupling node NCa and the second coupling node NCb may be determined based on the voltage level of the control voltage VCTRL.

[0079] The variable capacitance circuit VCC may include a first varactor VR1 and a second varactor VR2. Hereinafter, for a more concise description, it is assumed that the first varactor VR1 and the second varactor VR2 are implemented using varactor diodes. However, the scope of the present disclosure is not limited thereto.

[0080] The first varactor VR1 may be connected between the first coupling node NCa and the middle node NM. The second varactor VR2 may be connected between the second coupling node NCb and the middle node NM. The middle node NM may receive a bias voltage VBIAS.

[0081] The capacitance of the first varactor VR1 can be determined based on the voltage difference between the first coupling node NCa and the intermediate node NM, and the capacitance of the second varactor VR2 can be determined based on the voltage difference between the second coupling node NCb and the intermediate node NM. In other words, the capacitance of the first varactor VR1 and the second varactor VR2 can be determined based on both the control voltage VCTRL and the bias voltage VBIAS. For example, the capacitance of the variable capacitance circuit VCC can be adjusted based on both the control voltage VCTRL and the bias voltage VBIAS. Therefore, similar to the above reference, Figure 5 Unlike the described capacitance oscillation circuit CTCb, even without including the first and second resistors R1 and R2 and the first and second cut-off capacitors CC1 and CC2, the capacitance of the capacitance oscillation circuit CTCc can be adjusted based on both the control voltage VCTRL and the bias voltage VBIAS.

[0082] In some example embodiments, the relationship between the control voltage VCTRL and the capacitance of the variable capacitance circuit VCC may vary according to the voltage level of the bias voltage VBIAS. Figure 9 The relationship between the control voltage VCTRL and the capacitance of the variable capacitance circuit VCC according to the voltage level of the bias voltage VBIAS is described in more detail.

[0083] Similar to the previous reference Figure 6 As described, since the capacitive oscillation circuit CTC is indirectly connected to the first output node Nout1 and the second output node Nout2 through inductive coupling, the influence of the low quality factor QF_CTC occurring when the output clock OCLK is high frequency can be reduced (and / or minimized).

[0084] Therefore, according to some example embodiments of the present disclosure, since the capacitances of the first and second varactors VR1 and VR2 are adjusted based on both the control voltage VCTRL and the bias voltage VBIAS, the capacitance variation range of the capacitance oscillator circuit CTCc in response to changes in the voltage level of the control voltage VCTRL can be increased (and / or maximized). Furthermore, since the capacitance oscillator circuit CTCc does not include the first and second resistors R1 and R2, thermal noise of the output clock OCLK can be reduced (and / or minimized). Since the capacitance oscillator circuit CTCc is indirectly connected to the first and second output nodes Nout1 and Nout2 via inductive coupling, phase noise included in the output clock OCLK can be reduced (and / or minimized).

[0085] That is, according to some example embodiments of the present disclosure, noise of the output clock OCLK may be reduced (and / or minimized), and limitation of the frequency variation range of the output clock OCLK due to variation in the voltage level of the control voltage VCTRL may be overcome.

[0086] Figure 8 Shown included in Figure 1 The frequency components in the output clock generated by the voltage controlled oscillator of the Figure 5 The voltage controlled oscillator VCO described above and referenced Figure 7 The frequency component distribution of the output clock OCLK generated by each of the voltage-controlled oscillators VCO is described. Figure 8 The horizontal axis may represent frequency, and the vertical axis may represent the amount of frequency components.

[0087] As shown by the thick solid line, the output clock OCLK generated by the ideal voltage-controlled oscillator VCO may have only the target frequency FREQ_target component. That is, the output clock OCLK generated by the ideal voltage-controlled oscillator VCO may not include any frequency components other than the target frequency FREQ_target component determined based on the capacitance of the capacitive oscillator circuit CTC and the inductance of the inductive oscillator circuit ITC.

[0088] However, as indicated by the single-dot chain line, Figure 5 The output clock OCLK generated by the described voltage-controlled oscillator VCO may include various frequency components in addition to the target frequency FREQ_target component. For example, the output clock OCLK may include various phase noises, and accordingly, the frequency component distribution of the output clock OCLK may have a relatively large variance. For example, the output clock OCLK generated by the voltage-controlled oscillator VCO may include a relatively small number of frequency components corresponding to the target frequency FREQ_target, and may include a relatively large number of frequency components that do not correspond to the target frequency FREQ_target.

[0089] On the other hand, as shown by the dotted line, according to the reference Figure 7 The described voltage-controlled oscillator (VCO) can reduce (and / or minimize) noise components included in the output clock OCLK. For example, the frequency component distribution of the output clock OCLK generated by the voltage-controlled oscillator (VCO) can have a relatively small variance. For example, the output clock OCLK generated by the voltage-controlled oscillator (VCO) can include a relatively large number of frequency components corresponding to the target frequency FREQ_target and a relatively small number of frequency components that do not correspond to the target frequency FREQ_target.

[0090] Figure 9 It shows that according to Figure 7 A graph showing the relationship between the bias voltage, the control voltage, and the capacitance of a variable capacitance circuit. Figure 9 The horizontal axis may represent the voltage level of the control voltage VCTRL, and the vertical axis may represent the magnitude of the capacitance of the variable capacitance circuit VCC. Figures 1 to 2 and Figures 6 to 9 , the relationship between the voltage level of the control voltage VCTRL and the capacitance CAP_VCC with respect to the variable capacitance circuit VCC may vary according to the voltage level of the bias voltage VBIAS.

[0091] First, the relationship between the voltage level of the control voltage VCTRL and the capacitance CAP_VCC when the bias voltage VBIAS is the first voltage V1 is shown by a solid line. For example, as the control voltage VCTRL increases, the capacitance CAP_VCC may increase.

[0092] When the bias voltage VBIAS is a second voltage V2 higher than the first voltage V1, the relationship between the voltage level of the control voltage VCTRL and the capacitance CAP_VCC is shown by a dashed line. That is, when the bias voltage VBIAS is a second voltage V2 higher than the first voltage V1, the capacitance CAP_VCC can be determined based on the relatively high voltage level of the control voltage VCTRL. Similarly, when the bias voltage VBIAS is a third voltage V3 higher than the second voltage V2, the relationship between the voltage level of the control voltage VCTRL and the capacitance CAP_VCC is shown by a dashed-dotted line.

[0093] That is, as the bias voltage VBIAS increases, the capacitance CAP_VCC may be determined based on the voltage level of the relatively high control voltage VCTRL. For example, for the same capacitance CAP_VCC, the higher the bias voltage VBIAS is, the higher the control voltage VCTRL may be required. Conversely, when the same control voltage VCTRL is provided, the higher the bias voltage VBIAS is, the smaller the capacitance CAP_VCC may be. For example, as the bias voltage VBIAS increases, Figure 8The graph of the bias voltage VBIAS and the capacitance CAP_VCC shown in FIG. 1 may be moved to the right. However, the scope of the present disclosure is not limited thereto.

[0094] Figure 10 is a diagram illustrating implementation according to some example embodiments Figure 6 The circuit diagram of the voltage controlled oscillator configuration. Figures 1 to 2 and Figures 6 to 10 The voltage-controlled oscillator (VCO) may include first and second drive transistors DT1 and DT2, an inductor oscillation circuit (ITC), and a capacitor oscillation circuit (CTC). The capacitor oscillation circuit (CTC) may be implemented as a capacitor oscillation circuit (CTCd). Since the configuration and operation of the first and second drive transistors DT1 and DT2 and the inductor oscillation circuit (ITC) are similar to those described above, a detailed description of the configuration and operation of the first and second drive transistors DT1 and DT2 and the inductor oscillation circuit (ITC) will be omitted.

[0095] The capacitance oscillation circuit CTCd may include a second inductor L2 and multiple variable capacitance circuits VCC. Each of the second inductor L2 and the multiple variable capacitance circuits VCC may be connected between a first coupling node NCa and a second coupling node NCb. In other words, the second inductor L2 and the multiple variable capacitance circuits VCC may be connected in parallel between the first coupling node NCa and the second coupling node NCb. Since the configuration and operation of the second inductor L2 are similar to those described above, a detailed description will be omitted.

[0096] The capacitance oscillation circuit CTCd may include a plurality of variable capacitance circuits VCC that operate based on different bias voltages.

[0097] For a more concise description, some example embodiments in which the capacitance oscillation circuit CTCd includes three variable capacitance circuits VCC will be described below. For example, the capacitance oscillation circuit CTCd may include first to third variable capacitance circuits VCC1 to VCC3. However, the scope of the present disclosure is not limited to the number of variable capacitance circuits VCC included in the capacitance oscillation circuit CTCd. For example, the capacitance oscillation circuit CTCd may include two or more variable capacitance circuits VCC.

[0098] The first variable capacitance circuit VCC1 may include a first varactor VR11 and a second varactor VR12. The first varactor VR11 may be connected between the first coupling node NCa and the first intermediate node NM1. The second varactor VR12 may be connected between the second coupling node NCb and the first intermediate node NM1. The first intermediate node NM1 may receive a first bias voltage VBIAS1. For example, the voltage level of the first bias voltage VBIAS1 may be the first voltage V1.

[0099] The second variable capacitance circuit VCC2 may include a first varactor VR21 and a second varactor VR22. The first varactor VR21 may be connected between the first coupling node NCa and the second intermediate node NM2. The second varactor VR22 may be connected between the second coupling node NCb and the second intermediate node NM2. The second intermediate node NM2 may receive a second bias voltage VBIAS2. For example, the voltage level of the second bias voltage VBIAS2 may be the second voltage V2.

[0100] Similarly, the third variable capacitance circuit VCC3 may include a first varactor VR31 and a second varactor VR32. The first varactor VR31 may be connected between the first coupling node NCa and the third intermediate node NM3. The second varactor VR32 may be connected between the second coupling node NCb and the third intermediate node NM3. The third intermediate node NM3 may receive a third bias voltage VBIAS3. For example, the voltage level of the third bias voltage VBIAS3 may be the third voltage V3.

[0101] The first voltage V1, the second voltage V2, and the third voltage V3 may be different from each other. For example, the second voltage V2 may be greater than the first voltage V1, and the third voltage V3 may be greater than the second voltage V2. Figure 9 As described, the relationships between the capacitances of the first to third variable capacitance circuits VCC1 to VCC3 with respect to the control voltage VCTRL may be different from each other.

[0102] In some example embodiments, when the capacitance oscillation circuit CTCd includes a plurality of variable capacitance circuits VCC operating based on different bias voltages, the sum of the capacitances of the plurality of variable capacitance circuits VCC may be linear with respect to the control voltage VCTRL. That is, when the capacitance oscillation circuit CTCd includes a plurality of variable capacitance circuits VCC operating based on different bias voltages, the relationship between the capacitance of the capacitance oscillation circuit CTCd and the control voltage VCTRL may be linear. Figure 11 The relationship between the capacitance of the capacitor oscillator circuit CTCd and the control voltage VCTRL is described in more detail.

[0103] Figure 11 It shows Figure 10 A graph showing the relationship between the capacitance of each of the plurality of variable capacitance circuits and the capacitance of the capacitance oscillation circuit. Figures 1 to 2 and Figures 6 to 11 , the relationship between the voltage level of the control voltage VCTRL and the capacitance CAP_VCC of each of the plurality of variable capacitance circuits VCC may differ according to the voltage level of the bias voltage VBIAS provided to each of the plurality of variable capacitance circuits VCC.

[0104] Hereinafter, for a more concise description, the capacitance CAP_VCC1 for the first variable capacitance circuit VCC1 is shown by a solid line, the capacitance CAP_VCC2 for the second variable capacitance circuit VCC2 is shown by a dashed line, and the capacitance CAP_VCC3 for the third variable capacitance circuit VCC3 is shown by a dotted line.

[0105] The equivalent capacitance CAP_EQV between the first coupling node NCa and the second coupling node NCb can be determined based on the sum of the capacitance CAP_VCC1, the capacitance CAP_VCC2, and the capacitance CAP_VCC3. For example, as shown by the thick solid line, the equivalent capacitance CAP_EQV can increase linearly in response to an increase in the control voltage VCTRL. For example, the capacitance of the capacitive oscillation circuit CTC viewed from the first output node Nout1 and the second output node Nout2 can also increase linearly in response to the control voltage VCTRL.

[0106] That is, according to some exemplary embodiments of the present disclosure, even if the above reference Figure 5 The first and second resistors R1 and R2 and the first and second cut-off capacitors CC1 and CC2 described above can also linearly increase the capacitance of the capacitive oscillation circuit CTC in response to the control voltage VCTRL. For example, thermal noise generated by the first and second resistors R1 and R2 can be excluded from the output clock OCLK, and the frequency amplitude variation range of the output clock OCLK with respect to the control voltage VCTRL can be limited by the first and second cut-off capacitors CC1 and CC2.

[0107] Figure 12 and Figure 13 is a more detailed illustration of the Figure 7 or Figure 10 Circuit diagram of a variable capacitor circuit.

[0108] First, refer to Figures 1 to 2 and Figures 6 to 12 , Figure 7 or Figure 10 The variable capacitance circuit VCC shown in FIG. 1 may be implemented as a variable capacitance circuit VCCa.

[0109] The variable capacitance circuit VCCa may include a first varactor VR1a and a second varactor VR2a. Anode terminals of the first varactor VR1a and the second varactor VR2a may be connected to an intermediate node NM. A cathode terminal of the first varactor VR1a may be connected to a first coupling node NCa, and a cathode terminal of the second varactor VR2a may be connected to a second coupling node NCb.

[0110] On the other hand, refer to Figure 1 and Figures 6 to 13 , Figure 7 or Figure 10 The variable capacitance circuit VCC shown in FIG. 1 may be implemented as a variable capacitance circuit VCCb.

[0111] The variable capacitance circuit VCCb may include a first varactor VR1b and a second varactor VR2b. The cathode terminals of the first varactor VR1b and the second varactor VR2b may be connected to the intermediate node NM. The anode terminal of the first varactor VR1b may be connected to the first coupling node NCa, and the anode terminal of the second varactor VR2b may be connected to the second coupling node NCb.

[0112] Figure 14 It shows Figure 12 and Figure 13 A diagram showing the relationship between capacitance and control voltage of a variable capacitance circuit. Figure 14 The horizontal axis may represent the voltage level of the control voltage VCTRL, and the vertical axis may represent the size of the capacitance.

[0113] The first graph group G1 shows the above reference Figure 12 The relationship between the capacitance CAP_VCC of the variable capacitance circuit VCCa and the control voltage VCTRL is described. In the first graph group G1, the graphs shown by the solid line, the graphs shown by the dotted line, and the graphs shown by the dashed line may indicate the relationship between the capacitance CAP_VCC of the variable capacitance circuit VCCa and the control voltage VCTRL when the bias voltage VBIAS is respectively the first voltage V1 to the third voltage V3.

[0114] The second graph group G2 shows the above reference Figure 13 The relationship between the capacitance CAP_VCC of the variable capacitance circuit VCCb and the control voltage VCTRL is described. In the second graph group G2, the graphs shown by the solid line, the graphs shown by the dotted line, and the graphs shown by the dashed line may indicate the relationship between the capacitance CAP_VCC of the variable capacitance circuit VCCb and the control voltage VCTRL when the bias voltage VBIAS is respectively the first voltage V1 to the third voltage V3.

[0115] That is to say, referring to Figures 12 to 14 The relationship between the control voltage VCTRL and the capacitance of the variable capacitance circuit VCC may vary depending on the orientation of the varactor VR included in the variable capacitance circuit VCC. For example, the capacitance of the variable capacitance circuit VCCa may be smaller than the capacitance of the variable capacitance circuit VCCb. For example, when the control voltage VCTRL of the same magnitude is applied, the capacitance of the variable capacitance circuit VCCa may be smaller than the capacitance of the variable capacitance circuit VCCb.

[0116] The quality factor QF_CTC of the capacitor oscillation circuit CTC may be proportional to the inverse of the capacitance of the capacitor oscillation circuit CTC. Therefore, the quality factor QF_CTC of the capacitor oscillation circuit CTC including the variable capacitance circuit VCCa may be greater than the quality factor QF_CTC of the capacitor oscillation circuit including the variable capacitance circuit VCCb. That is, when the variable capacitance circuit VCC included in the capacitor oscillation circuit CTC is implemented as the variable capacitance circuit VCCa, the quality factor of the capacitor oscillation circuit CTC may be increased. For example, the phase noise included in the output clock OCLK may be reduced (and / or minimized). Therefore, according to Figure 12 An embodiment similar to that previously referred to Figure 8 As described, the distribution of frequency components included in the output clock OCLK may be similar to the distribution of frequency components of the output clock OCLK generated by an ideal voltage-controlled oscillator VCO.

[0117] In some example embodiments, due to the structure of the silicon oxide layer and the depletion layer included in the varactor VR, the capacitance of the varactor VR viewed from the gate terminal (e.g., the anode terminal) may differ from the capacitance of the varactor VR viewed from the source terminal (e.g., the cathode terminal). Due to this configuration of the varactor VR, the relationship between the control voltage VCTRL and the capacitance of the variable capacitance circuit VCC may vary depending on the orientation of the varactor VR included in the variable capacitance circuit VCC. However, the scope of the present disclosure is not limited to the specific reason why the relationship between the control voltage VCTRL and the capacitance of the variable capacitance circuit VCC varies depending on the orientation of the varactor VR included in the variable capacitance circuit VCC.

[0118] Figure 15 Showing implementation according to some example embodiments Figure 1 Voltage controlled oscillator. Figure 1 and Figure 15 The voltage-controlled oscillator (VCO) may include first and second drive transistors DT1 and DT2, an inductive oscillation circuit (ITC), and a capacitive oscillation circuit (CTC). The capacitive oscillation circuit (CTC) may be implemented as a capacitive oscillation circuit (CTCe). Since the configuration and operation of the first and second drive transistors DT1 and DT2 are similar to those described above, a detailed description of the configuration and operation of the first and second drive transistors DT1 and DT2 will be omitted.

[0119] The inductive oscillation circuit ITC may include a first inductor L1. The first inductor L1 may be connected between the first output node Nout1 and the second output node Nout2.

[0120] The first inductor L1 may include a first center tap node connected to the control node Nctrl. That is, the first inductor L1 may receive the control voltage VCTRL through the first center tap node.

[0121] The capacitance oscillation circuit CTCe may be connected between the first output node Nout1 and the second output node Nout2. The capacitance oscillation circuit CTCe may include a variable capacitance circuit VCC. Since the configuration and operation of the variable capacitance circuit VCC are similar to those described above, a detailed description of the configuration and operation of the variable capacitance circuit VCC will be omitted.

[0122] Figure 16 Showing implementation according to some example embodiments Figure 1 Voltage controlled oscillator. Figure 1 and Figures 15 and 16 The voltage-controlled oscillator (VCO) may include first and second drive transistors DT1 and DT2, an inductor oscillation circuit (ITC), and a capacitor oscillation circuit (CTC). The capacitor oscillation circuit (CTC) may be implemented as a capacitor oscillation circuit (CTCf). Since the configuration and operation of the first and second drive transistors DT1 and DT2 and the inductor oscillation circuit (ITC) are similar to those described above, a detailed description of the configuration and operation of the first and second drive transistors DT1 and DT2 and the inductor oscillation circuit (ITC) will be omitted.

[0123] The capacitance oscillation circuit CTCf may include a plurality of variable capacitance circuits VCC. Each of the plurality of variable capacitance circuits VCC may be connected between the first output node Nout1 and the second output node Nout2. In other words, the plurality of variable capacitance circuits VCC may be connected in parallel between the first output node Nout1 and the second output node Nout2.

[0124] The capacitance oscillation circuit CTCf may include a plurality of variable capacitance circuits VCC operating based on different bias voltages. For example, the capacitance oscillation circuit CTCd may include first to third variable capacitance circuits VCC1 to VCC3. Since the configuration and operation of the first to third variable capacitance circuits VCC1 to VCC3 are similar to those of the reference circuits Figure 10 The configurations and operations described above are omitted, and thus detailed descriptions of the configurations and operations of the first to third variable capacitance circuits VCC1 to VCC3 will be omitted.

[0125] In some example embodiments, when the capacitance oscillation circuit CTCf includes a plurality of variable capacitance circuits VCC operating based on different bias voltages, the sum of the capacitances of the plurality of variable capacitance circuits VCC may be linear with respect to the control voltage VCTRL. For example, the relationship between the capacitance of the capacitance oscillation circuit CTCf and the control voltage VCTRL may be similar to that of the reference circuit. Figure 11 Describe the relationship.

[0126] One or more of the elements disclosed above may include processing circuitry (e.g., hardware including logic circuitry; a hardware / software combination (e.g., a processor executing software); or a combination thereof) or be implemented in processing circuitry. For example, the processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

[0127] The above are specific embodiments for implementing the present disclosure. The present disclosure will include not only the above embodiments, but also embodiments that can be simply designed or easily changed. The present disclosure will also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present disclosure should not be limited to the above embodiments, but should be determined not only by the scope of the claims, but also by the scope equivalent to the scope of the claims of the present disclosure.

Claims

1. A voltage-controlled oscillator, comprising: a first drive transistor including a first gate terminal connected to the first output node, the first drive transistor being connected between the second output node and a ground node; a second drive transistor connected between the first output node and a ground node, the second drive transistor including a second gate terminal connected to the second output node; a first inductor connected between the first output node and the second output node; a second inductor connected between the first coupling node and the second coupling node; as well as A first variable capacitance circuit is connected in parallel with the second inductor between the first coupling node and the second coupling node, The second inductor is configured to receive a control voltage and be inductively coupled to the first inductor.

2. The voltage controlled oscillator according to claim 1, wherein: The first inductor is configured to receive a power supply voltage through a center tap node included in the first inductor.

3. The voltage controlled oscillator according to claim 1, wherein: The second inductor is configured to receive a control voltage through a center tap node included in the second inductor.

4. The voltage controlled oscillator according to claim 1, wherein: The first variable capacitance circuit includes: a first varactor connected between the first coupling node and the first intermediate node; and a second varactor connected between the second coupling node and the first intermediate node, and The first intermediate node is configured to receive a first bias voltage.

5. The voltage controlled oscillator according to claim 4, wherein: The first output node and the second output node are configured to respectively output a first output clock and a second output clock having the same frequency and opposite phases with respect to each other.

6. The voltage controlled oscillator according to claim 5, wherein: The frequency is based on the capacitance of the first variable capacitance circuit.

7. The voltage controlled oscillator according to claim 6, wherein: The capacitance of the first variable capacitance circuit is based on a control voltage and a first bias voltage.

8. The voltage controlled oscillator according to claim 4, wherein: The first varactor includes a first anode terminal and a first cathode terminal, The second varactor includes a second anode terminal and a second cathode terminal, The first anode terminal and the second anode terminal are connected to a first intermediate node, The first cathode terminal is connected to the first coupling node, and The second cathode terminal is connected to the second coupling node.

9. The voltage controlled oscillator according to claim 4, further comprising: The second variable capacitance circuit is connected in parallel with the second inductor and the first variable capacitance circuit, and the second variable capacitance circuit is connected between the first coupling node and the second coupling node.

10. The voltage controlled oscillator according to claim 9, wherein: The second variable capacitance circuit includes: a third varactor connected between the first coupling node and the second intermediate node; and a fourth varactor connected between the second coupling node and the second intermediate node, and The second intermediate node is configured to receive a second bias voltage different from the first bias voltage.

11. A voltage-controlled oscillator configured to receive a control voltage and output a first output clock and a second output clock having a frequency corresponding to the amplitude of the control voltage, the voltage-controlled oscillator comprising: a first driving transistor including a first gate terminal connected to a first output node through which the first output clock is output, the first driving transistor being connected between the second output node and a ground node; a second driving transistor connected between the first output node and a ground node, the second driving transistor including a second gate terminal connected to a second output node, the second output clock being outputted through the second output node; an inductive oscillation circuit connected between the first output node and the second output node; as well as The capacitive oscillation circuit is configured to be inductively coupled to the inductive oscillation circuit, and the capacitive oscillation circuit is configured to operate based on an externally provided control voltage.

12. The voltage controlled oscillator according to claim 11, wherein: The capacitive oscillation circuit is electrically separated from the first output node and the second output node.

13. The voltage controlled oscillator according to claim 11, wherein: The inductor oscillation circuit includes a first inductor connected between a first output node and a second output node, and The capacitive oscillation circuit includes a second inductor connected between the first coupling node and the second coupling node, The second inductor is inductively coupled to the first inductor.

14. The voltage controlled oscillator according to claim 13, wherein: The capacitance oscillation circuit further includes a first variable capacitance circuit connected between the first coupling node and the second coupling node, the first variable capacitance circuit being connected in parallel to the second inductor, and The first variable capacitance circuit includes: a first varactor connected between the first coupling node and the first intermediate node; and The second varactor is connected between the second coupling node and the first intermediate node.

15. The voltage controlled oscillator according to claim 14, wherein: The capacitance oscillation circuit further includes a second variable capacitance circuit connected between the first coupling node and the second coupling node, the second variable capacitance circuit being connected in parallel to the second inductor and connected in parallel to the first variable capacitance circuit, and The second variable capacitance circuit includes: a third varactor connected between the first coupling node and the second intermediate node; and The fourth varactor is connected between the second coupling node and the second intermediate node.

16. The voltage controlled oscillator of claim 15, wherein: The first intermediate node and the second intermediate node are configured to receive bias voltages having different levels with respect to each other.

17. The voltage controlled oscillator according to claim 14, wherein: The first varactor includes a first anode terminal and a first cathode terminal, The second varactor includes a second anode terminal and a second cathode terminal, The first anode terminal and the second anode terminal are connected to a first intermediate node, The first cathode terminal is connected to the first coupling node, and The second cathode terminal is connected to the second coupling node.

18. The voltage controlled oscillator according to claim 13, wherein: The first inductor is configured to receive a power supply voltage through a first center tap node included in the first inductor, and The second inductor is configured to receive a control voltage through a second center tap node included in the second inductor.

19. A phase-locked loop, comprising: a voltage-controlled oscillator configured to generate a first output clock and a second output clock based on a control voltage; a frequency divider configured to generate a feedback clock based on the first output clock and the second output clock; a phase frequency detector configured to generate a differential signal based on a difference between a feedback clock and an externally provided reference clock; as well as a control voltage generator configured to adjust a level of a control voltage based on the differential signal, Among them, the voltage controlled oscillator includes: a first inductor connected between a first output node outputting a first output clock and a second output node outputting a second output clock, a second inductor connected between the first coupling node and the second coupling node, the first coupling node and the second coupling node being electrically separated from the first output node and the second output node, and the second inductor being configured to receive the control voltage and be inductively coupled to the first inductor, a first varactor connected between the first coupling node and a first intermediate node configured to receive a first bias voltage, and The second varactor is connected between the second coupling node and the first intermediate node.

20. The phase-locked loop of claim 19, wherein: The voltage controlled oscillator also includes: a third varactor connected between the first coupling node and a second intermediate node configured to receive a second bias voltage; and The fourth varactor is connected between the second coupling node and the second intermediate node.

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