High-reliability pulse trigger circuit for radiation field measurement

Abstract

The invention discloses a high-reliability pulse trigger circuit for radiation field measurement, and solves the problems that an existing pulse trigger circuit is easy to generate false trigger operation, cannot dynamically adjust and lock time parameters on the premise of not changing hardware configuration, and is weak in reliability and poor in flexibility. The circuit specifically comprises a comparison circuit, a self-locking circuit, a narrow pulse generation circuit and a switching circuit. The in-phase input end of the comparison circuit is used for being connected with external analog signal output equipment, the inverted input end of the comparison circuit is used for being connected with an external threshold voltage power supply Vth, and the output end of the comparison circuit is connected with the B input end of the self-locking circuit; the Q1 output end of the self-locking circuit is connected with the A input end of the self-locking circuit and is used for signal closed-loop feedback; the Y output end of the self-locking circuit is connected with the input end of the narrow pulse generation circuit; the narrow pulse generation circuit is used for generating a narrow pulse trigger signal according to the trigger pulse, and the output end is connected with the input end of the switching circuit; the switching circuit is used for outputting a fast pulse trigger signal.

Description

Technical Field

[0001] The invention relates to a pulse trigger circuit, in particular to a high-reliability pulse trigger circuit for radiation field measurement. Background Art

[0002] Fast pulse trigger signals play a key role in cutting-edge scientific fields such as high-energy physics research, radiation detection technology, and explosion dynamics experiments. These experimental processes usually have transient characteristics, and the signals they generate often occur on an extremely short time scale, with signal durations of only nanoseconds to milliseconds. In addition, the experimental process is one-time and non-repeatable, so the reliability requirements for single trigger pulse signals are extremely high.

[0003] Pulse trigger circuits are used to generate fast pulse trigger signals. Their main goal is to achieve effective recognition and response to input signals through hardware design. Current mainstream technical solutions include designs based on Schmitt triggers, monostable multivibrators, and comparator + RC circuit structures. With the increasing demand for the development of precision instruments and equipment, the reliability issues of existing circuits in complex environments have become increasingly prominent. In working environments with strong interference noise, these traditional designs have exposed significant defects: when the input signal is a jitter pulse sequence, it is easy to cause false triggering operations, and good single-shot pulse characteristics cannot be guaranteed; each module has a fixed and single function and lacks scalability, and it is impossible to dynamically adjust the lock time parameters without changing the hardware configuration, resulting in a limited ability of the system to adapt to complex working conditions. To address this problem, in the September 2014 issue of the journal "Nuclear Electronics and Detection Technology", Qu Hongguang et al. used a D flip-flop combined with a counter to implement it in the paper "Research and Development of Single-Shot Fast Pulse Latch Synchronizer". This method requires an external clock source, and the stability of the signal is closely related to the clock source. At the same time, it is difficult to flexibly adjust the locking time; in the March 2021 issue of the journal "Nuclear Electronics and Detection Technology", Zhang Yanxia et al. configured the logic unit of the CPLD to implement the locking function in the "Design of a New Multi-channel Synchronous Square Wave Pulse Generator". The integrated digital circuit method is used, and the reliability is relatively weak. The locking time is also controlled by a counter, which has a complex structure and poor flexibility. Summary of the Invention

[0004] In order to solve the technical problems that the existing pulse trigger circuit is prone to false triggering operations, cannot dynamically adjust the locking time parameters without changing the hardware configuration, has weak reliability and poor flexibility, the present invention provides a high-reliability pulse trigger circuit for radiation field measurement.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A high-reliability pulse trigger circuit for radiation field measurement, which is special in that it includes a comparison circuit, a self-locking circuit, a narrow pulse generating circuit and a switching circuit;

[0007] The comparator circuit has a non-inverting input terminal for connecting to an external analog signal output device, an inverting input terminal for connecting to an external threshold voltage power supply Vth, and an output terminal connected to the B input terminal of the self-locking circuit; the comparator circuit is used to compare the analog signal with the threshold voltage and output a pulse signal;

[0008] The Q1 output terminal of the self-locking circuit is connected to the A input terminal of the self-locking circuit for signal closed-loop feedback; the Y output terminal of the self-locking circuit is connected to the input terminal of the narrow pulse generating circuit; the self-locking circuit is used to convert the pulse signal into a self-locking long pulse;

[0009] The narrow pulse generating circuit is used to generate a narrow pulse trigger signal according to the self-locking long pulse, and its output end is connected to the input end of the switching circuit;

[0010] The switch circuit is used to output a fast pulse trigger signal.

[0011] Furthermore, the comparison circuit includes an SMA connector, a current limiting resistor R1, a matching resistor R2, a voltage stabilizing diode Z1, a voltage stabilizing diode Z2, a power supply Vcc1 and a comparator CP1;

[0012] The input end of the SMA connector is used to connect to an external analog signal output device, and the output end thereof is respectively connected to one end of the current limiting resistor R1 and one end of the matching resistor R2, and the housing thereof is connected to the analog ground AGND;

[0013] The other end of the current limiting resistor R1 is connected to the non-inverting input end of the comparator CP1;

[0014] The other end of the matching resistor R2 is connected to the analog ground AGND;

[0015] The cathode of the voltage stabilizing diode Z1 is connected to the power supply Vcc1, and the anode thereof is connected to the non-inverting input terminal of the comparator CP1;

[0016] The cathode of the voltage stabilizing diode Z2 is connected to the non-inverting input terminal of the comparator CP1, and the anode thereof is connected to the analog ground AGND;

[0017] The inverting input terminal of the comparator CP1 is used to connect to an external threshold voltage power supply Vth, and the output terminal thereof is connected to the B input terminal of the self-locking circuit.

[0018] Furthermore, the self-locking circuit includes a logic OR gate OR1, a D flip-flop DFF1, a power supply Vcc2, an inverter N1, an inverter N2, a potentiometer XR1, a diode Z3 and a capacitor C1;

[0019] The B input terminal of the logic OR gate OR1 is connected to the output terminal of the comparator CP1, and the Y output terminal thereof is connected to the input terminal of the narrow pulse generating circuit and the clk1 terminal of the D flip-flop DFF1 respectively;

[0020] The D1 input terminal of the D flip-flop DFF1 is connected to the power supply Vcc2, the ~MR1 terminal thereof is connected to the output terminal of the inverter N2, the Q1 output terminal thereof is connected to the A input terminal of the logic OR gate OR1, and the ~Q1 output terminal thereof is connected to the input terminal of the inverter N1;

[0021] The output end of the inverter N1 is connected to one end of the capacitor C1 through the potentiometer XR1;

[0022] The input end of the inverter N2 is connected to one end of the capacitor C1;

[0023] The cathode of the diode Z3 is connected to the output end of the inverter N1, and the anode of the diode Z3 is connected to one end of the capacitor C1;

[0024] The other end of the capacitor C1 is connected to the digital ground DGND.

[0025] Furthermore, the narrow pulse generating circuit includes a D flip-flop DFF2, a power supply Vcc3, an inverter N3, an inverter N4, an inverter N5, a potentiometer XR2 and a capacitor C2;

[0026] The D2 input terminal of the D flip-flop DFF2 is connected to the power supply Vcc3, the clk2 terminal thereof is connected to the Y output terminal of the logic OR gate OR1, the ~MR2 terminal thereof is connected to the output terminal of the inverter N4, the Q2 output terminal thereof is connected to the input terminal of the inverter N5, and the ~Q2 output terminal thereof is connected to the input terminal of the inverter N3;

[0027] The output end of the inverter N3 is connected to one end of the capacitor C2 through the potentiometer XR2;

[0028] The input end of the inverter N4 is connected to one end of the capacitor C2;

[0029] The output end of the inverter N5 is connected to the input end of the switch circuit;

[0030] The other end of the capacitor C2 is connected to the digital ground DGND.

[0031] Furthermore, it also includes a resistor R0;

[0032] One end of the resistor R0 is connected to the analog ground AGND, and the other end is connected to the digital ground DGND.

[0033] Furthermore, the switch circuit includes a transistor BJT1, a transistor BJT2, a capacitor C3, a power supply Vcc4, a field effect transistor PMOS, a power supply Vcc5, a resistor R3, a resistor R4 and a load Load;

[0034] The transistor BJT1 is an NPN transistor, and the transistor BJT2 is a PNP transistor;

[0035] The base of the transistor BJT1 is connected to the base of the transistor BJT2 and to the output end of the inverter N5, the collector of the transistor BJT1 is connected to the power supply Vcc4, and the emitter thereof is connected to the emitter of the transistor BJT2 and to one end of the capacitor C3;

[0036] The collector of the transistor BJT2 is connected to the analog ground AGND;

[0037] The other end of the capacitor C3 is connected to the gate of the field effect transistor PMOS;

[0038] The source of the field effect transistor PMOS is connected to the power supply Vcc5, and the drain is connected to one end of the resistor R4;

[0039] The two ends of the resistor R3 are connected across the gate and source of the field effect transistor PMOS;

[0040] The other end of the resistor R4 is connected to the analog ground AGND via a load Load and is used to output a fast pulse trigger signal.

[0041] Furthermore, the D flip-flop DFF1 and the D flip-flop DFF2 are of the same model;

[0042] The inverter N1, inverter N2, inverter N3, inverter N4, and inverter N5 are of the same model;

[0043] The voltage stabilizing diode Z1 and the voltage stabilizing diode Z2 are of the same model.

[0044] Furthermore, R1=Vin / Lin1;

[0045] Wherein, Vin is the amplitude of the output signal of the external analog signal output device, and Lin1 is the maximum input current of the comparator CP1.

[0046] Furthermore, R0=0Ω, R2=50Ω, and R3=10kΩ.

[0047] Furthermore, C3=100nf.

[0048] Beneficial effects of the present invention:

[0049] 1. The present invention provides a high-reliability pulse trigger circuit for radiation field measurement, which is composed of a comparison circuit, a self-locking circuit, a narrow pulse generating circuit and a switching circuit connected in sequence. The comparison circuit receives an analog signal and determines whether it reaches a preset turn-on threshold. By converting the analog signal into a digital signal output, accurate judgment of the signal state is achieved; the self-locking circuit adopts a closed-loop feedback structure design to avoid false triggering within a preset time window, thereby improving the reliability of the pulse trigger circuit and flexibly setting the locking time to meet the needs of different scenarios; the narrow pulse generating circuit generates a narrow pulse trigger signal, and the pulse width can be flexibly set according to output requirements; the switching circuit applies the narrow pulse trigger signal to the subsequent switching circuit, and realizes the generation of a fast pulse trigger signal by triggering the rapid shutdown of the switch.

[0050] 2. The present invention provides a high-reliability pulse trigger circuit for radiation field measurement, which adopts a current-limiting resistor, a clamping voltage (the function of a voltage-stabilizing diode), and an input mode with 50-ohm impedance matching. When a high-voltage signal is input, input protection of the comparator CP1 is realized. The self-locking circuit forms a feedback loop by using a D-type flip-flop DFF1 and a logic OR gate OR1. When a valid trigger signal is first received, the response channel can be immediately blocked. This design maintains the locked state in the subsequent signal cycle until the next valid trigger instruction arrives. This mechanism can not only effectively suppress the false triggering phenomenon caused by the jitter pulse sequence, but also flexibly control the locking duration by adjusting the parameters of the RC network composed of the potentiometer XR1 and the capacitor C1. A similar structure is used in the narrow pulse generation circuit, and the parameters of the RC network composed of the potentiometer XR2 and the capacitor C2 are flexibly adjusted to control the width of the trigger pulse at the final output end. It has the characteristics of simple structure and strong portability, and can flexibly adjust the parameters while achieving reliability.

[0051] 3. The present invention provides a high-reliability pulse trigger circuit for radiation field measurement, which adopts a mixed mode of analog and digital devices. The ground of the two is divided in the design and connected through a 0-ohm resistor, which effectively ensures the isolation of analog and digital and prevents interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a structural schematic diagram of an embodiment of a high-reliability pulse trigger circuit for radiation field measurement according to the present invention;

[0053] Figure 2 This is a circuit diagram of an embodiment of a high-reliability pulse trigger circuit for radiation field measurement according to the present invention;

[0054] Figure 3 is a circuit diagram of a switching circuit in an embodiment of the present invention;

[0055] Figure 41 is a flowchart of the pulse trigger circuit in an embodiment of the present invention;

[0056] Figure 5 It is a waveform diagram of key nodes in the pulse trigger circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the accompanying drawings and embodiments. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0058] The embodiment of the present invention provides a high reliability pulse trigger circuit for radiation field measurement, combined with Figure 1 and Figure 2 As shown, the circuit includes a comparison circuit, a self-locking circuit, resistor R0, a narrow pulse generation circuit, and a switching circuit. The analog signal is generated by the comparison circuit into a digital pulse signal. The self-locking circuit outputs a certain time delay, which is fed back to the input of this stage and combined with the digital signal of the previous stage. This self-locking effect is integrated into the input signal. This result serves as a clock signal (clk) to trigger the narrow pulse generation circuit, enabling dynamic adjustment of the pulse width and the ability to quickly change the output waveform parameters according to actual needs, meeting the application requirements of different scenarios.

[0059] The non-inverting input terminal of the comparison circuit is connected to an external analog signal output device, the inverting input terminal thereof is used to connect to an external threshold voltage power supply Vth, and the output terminal thereof is connected to the B input terminal of the self-locking circuit;

[0060] Specifically, the comparison circuit includes an SMA connector, a current limiting resistor R1, a matching resistor R2, a voltage zener diode Z1, a voltage zener diode Z2, a power supply Vcc1 and a comparator CP1.

[0061] The input end of the SMA connector is used to connect to an external analog signal output device, and its output end is connected to one end of the current limiting resistor R1 and one end of the matching resistor R2 respectively, and its shell is connected to the analog ground AGND;

[0062] The other end of the current-limiting resistor R1 is connected to the non-inverting input of the comparator CP1. The current-limiting resistor R1 protects the comparator CP1 by limiting the current in the circuit to prevent damage caused by excessive current. The resistance value is determined by the amplitude Vin of the output signal of the external analog signal output device and the maximum input current Lin1 of the comparator CP1. Specifically, R1 = Vin / Lin1;

[0063] The other end of the matching resistor R2 is connected to the analog ground AGND. The matching resistor R2 is a 50Ω resistor selected according to the impedance matching requirement to effectively avoid the adverse effects of reflection on the signal and improve energy transmission efficiency.

[0064] The cathode of Zener diode Z1 is connected to the power supply Vcc1, and its anode is connected to the non-inverting input of comparator CP1; the cathode of Zener diode Z2 is connected to the non-inverting input of comparator CP1, and its anode is connected to analog ground AGND; Zener diodes Z1 and Z2 prevent damage to comparator CP1 caused by excessive input signal amplitude. According to the constructed voltage-stabilizing circuit, the input voltage is limited to the range of (Vcc1-Vz) to (Vcc1+Vz), and a device with a reverse breakdown voltage of 2Vcc1 is selected to ensure that it will not be damaged; Zener diodes Z1 and Z2 are of the same model to ensure symmetry of the input limiting range.

[0065] The negative power supply terminal of the comparator CP1 is grounded, the positive power supply terminal is connected to the power supply Vcc1, its inverting input terminal is used to connect to the external threshold voltage power supply Vth, and its output terminal is connected to the B input terminal of the self-locking circuit; when the input voltage exceeds the set threshold (i.e. Vin>Vth), the output terminal of the comparator CP1 presents a high level, otherwise it remains in a low level state. The comparator CP1 selects a device model with a fast response speed and relatively small system delay.

[0066] The Q1 output of the self-locking circuit is connected to the A input of the self-locking circuit for closed-loop signal feedback, feeding the signal back to input A to prevent false triggering within a preset time. The Y output of the self-locking circuit is connected to the input of the narrow pulse generation circuit. The self-locking circuit is composed entirely of digital logic chips and uses a separate digital ground. This self-locking circuit is responsible for generating the locking signal. By adjusting the value of potentiometer XR1, the locking time can be flexibly adjusted to meet the needs of different scenarios, usually set to milliseconds. The self-locking circuit uses a feedback loop and a logical OR gate to improve the system's triggering accuracy and reliability while also preventing additional system delays. To further enhance its anti-interference capabilities, all CMOS devices are used.

[0067] Specifically, the self-locking circuit includes a logic OR gate OR1, a D flip-flop DFF1, a power supply Vcc2, an inverter N1, an inverter N2, a potentiometer XR1, a diode Z3 and a capacitor C1.

[0068] The B input of the logic OR gate OR1 is connected to the output of the comparator CP1, and the Y output of the logic OR gate OR1 is connected to the input of the narrow pulse generating circuit and the clk1 terminal of the D flip-flop DFF1 respectively. In this embodiment, the logic OR gate OR1 adopts a two-input OR gate form. To further improve reliability, a redundant design can be performed. In this way, a "multi-input" approach is adopted. It is only necessary to replace the OR gate with a multi-input channel logic chip, which is simpler and more flexible in design.

[0069] The D1 input of the D flip-flop DFF1 is connected to the power supply Vcc2, its ~MR1 terminal is connected to the output of the inverter N2, its Q1 output terminal is connected to the A input of the logic OR gate OR1, and its ~Q1 output terminal is connected to the input of the inverter N1; the D flip-flop DFF1, as the core component of the self-locking module, has a certain data latching function, and the output terminal can follow the input terminal changes when the clear terminal is at a high level and the clock rising edge arrives. Here, the D1 input terminal is connected to the power supply Vcc2, that is, Vq1 remains at a high level state. At this time, the ~Q1 output terminal is equivalent to a secondary inversion after passing through the inverter N1, and is consistent with Vq1. The capacitor C1 is charged through the potentiometer XR1. At this time, Vch1 shows an exponential growth trend, and the charging process of the capacitor C1 follows When capacitor C1 is charged until it reaches the input level of D-type flip-flop DFF1, it is discharged immediately. Therefore, the pulse width of the self-locking signal tw1 is approximately: tw1 = 0.7 × XR1 × C1. Diode Z3 provides a fast discharge circuit for capacitor C1, which quickly reduces the voltage on capacitor C1. At the same time, for D-type flip-flop DFF1, when the reset signal arrives, the level is pulled down to form a pulse. In order for D-type flip-flop DFF1 to change quickly, it is required to have a fast response speed and a small system delay.

[0070] The output end of the inverter N1 is connected to one end of the capacitor C1 through the potentiometer XR1. The inverter N1 inverts the output signal of the output end of the D flip-flop DFF1~Q1, and the output is connected to the parallel circuit composed of the potentiometer XR1 and the diode Z3; the input end of the inverter N2 is connected to one end of the capacitor C1, so that the output signal of the output end of ~Q1 is processed and fed back to the ~MR1 end, forming a closed loop, providing a forced clear signal for the D flip-flop DFF1; the inverter N1 and the inverter N2 reverse the input signal and need to have a sufficiently fast response capability and a short signal establishment time. In this embodiment, the SN74LVC2G04 model is selected.

[0071] The cathode of the diode Z3 is connected to the output end of the inverter N1 , and the anode of the diode Z3 is connected to one end of the capacitor C1 . The diode Z3 provides a discharge circuit for the capacitor C1 .

[0072] The other end of capacitor C1 is connected to digital ground DGND.

[0073] The self-locking signal pulse width generated by the self-locking circuit is determined by the potentiometer XR1 and the capacitor C1, specifically tw1 = 0.7 × XR1 × C1. For the ns-level pulse to be generated, the self-locking signal pulse width is usually set to the ms level to ensure the single-shot reliability of the trigger.

[0074] The output of the narrow pulse generation circuit is connected to the input of the switching circuit. This circuit, also composed entirely of digital logic chips and using a separate digital ground, generates narrow pulse signals. The pulse width is consistent with the output trigger pulse and can be flexibly adjusted. The narrow pulse triggers the subsequent switching circuit, ultimately forming a high-precision fast pulse trigger signal. The specific operating principle is consistent with that of the self-locking circuit.

[0075] Specifically, the narrow pulse generating circuit includes a D flip-flop DFF2, a power supply Vcc3, an inverter N3, an inverter N4, an inverter N5, a potentiometer XR2 and a capacitor C2.

[0076] The D2 input terminal of the D flip-flop DFF2 is connected to the power supply Vcc3, and its clk2 terminal is connected to the Y output terminal of the logic OR gate OR1 to receive the output signal of the Y output terminal of the logic OR gate OR1. Its ~MR2 terminal is connected to the output terminal of the inverter N4, its Q2 output terminal is connected to the input terminal of the inverter N5, and its ~Q2 output terminal is connected to the input terminal of the inverter N3. When the ~MR2 terminal is at a high level and the rising edge of the clock arrives, its Q2 output terminal follows the change of the D2 input terminal. The output signal of the ~Q2 output terminal is processed and fed back to the ~MR2 terminal to form a closed loop.

[0077] The output of inverter N3 is connected to one end of capacitor C2 via potentiometer XR2. Inverter N3 inverts the output signal of ~Q2. The input of inverter N4 is connected to one end of capacitor C2. Potentiometer XR2 and capacitor C2 form an integrating network. Inverter N4 monitors the real-time voltage of capacitor C2. The input of inverter N4 is connected to the charging terminal of capacitor C2, and the output port is fed back to the ~MR2 terminal of D-type flip-flop DFF2, providing a forced clear signal for D-type flip-flop DFF2. The output of inverter N5 is connected to the input of the switching circuit. The other end of capacitor C2 is connected to digital ground DGND.

[0078] The pulse width tw2 of the narrow pulse generation circuit is determined by potentiometer XR2 and capacitor C2, specifically tw2 = 0.7 × XR2 × C2. This pulse width is consistent with the pulse width of the final fast pulse trigger signal. D-type flip-flops DFF1 and DFF2 should be of the same model to ensure synchronization and correct timing logic. Inverters N1 and N2 in the self-latching circuit and inverters N3, N4, and N5 in the narrow pulse generation circuit should be of the same model to ensure delay consistency and, therefore, correct timing logic.

[0079] The comparison circuit, self-locking circuit, and narrow pulse generation circuit use separate power supply and ground designs. One end of the resistor R0 is connected to the analog ground AGND, and the other end is connected to the digital ground DGND. R0 is a 0-ohm resistor. The resistor R0 connects the analog ground AGND and the digital ground DGND at a single point to separate the analog and digital modules and avoid interference between the analog and digital modules.

[0080] The output end of the switch circuit is used to output the generated fast pulse trigger signal.

[0081] Specifically, such as Figure 3 As shown, the switching circuit includes an NPN transistor BJT1, a PNP transistor BJT2, a capacitor C3, a power supply Vcc4, a field effect transistor PMOS, a power supply Vcc5, a resistor R3, a resistor R4 and a load Load; the base of the transistor BJT1 is connected to the output end of the inverter N5, its collector is connected to the power supply Vcc4, and its emitter is connected to the emitter of the transistor BJT2; the base of the transistor BJT2 is connected to the output end of the inverter N5, and its collector is connected to the analog ground AGN D; one end of capacitor C3 is connected to the emitter of transistor BJT1 and the emitter of transistor BJT2 respectively, and the other end of capacitor C3 is connected to the gate of field-effect transistor PMOS, C3 = 100nf; the source of field-effect transistor PMOS is connected to power supply Vcc5, and its drain is connected to one end of resistor R4; the two ends of resistor R3 are connected across the gate and source of field-effect transistor PMOS, R3 = 10kΩ; the other end of resistor R4 is connected to analog ground AGND through load Load and is used to output a fast pulse trigger signal.

[0082] Switching circuits are typically built around semiconductor switching elements such as field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), or bipolar junction transistors (BJTs). In this embodiment, a PMOS field-effect transistor (PMOS) is used as the switching element. Because the drive signal current generated by the narrow pulse generator is relatively low, if used directly to control the aforementioned switching element, insufficient drive capability may affect operating performance. Therefore, an additional drive circuit is required, which can be implemented using a push-pull structure of a bipolar junction transistor (BJT). The PMOS field-effect transistor (ZXMP10A13FTA model is a key component in determining the leading edge level of the fast-leading pulse. The data sheet indicates that its rising edge can reach as fast as 2ns, enabling nanosecond-level ultra-fast leading-edge pulse trigger signals. This design significantly increases the output current, thereby providing sufficient drive capability to quickly turn the switching element on and off and generate a pulse signal with a steep rising edge, ultimately improving the accuracy and response speed of the entire trigger system.

[0083] The workflow of the present invention is described below:

[0084] like Figure 4 As shown in the figure, after power-up, the system completes reset and enters standby mode. When an external analog signal, Vin, is input, its amplitude is fed into comparator CP1 for threshold determination and comparison with a reference voltage, Vth (a pre-set trigger threshold). If Vin is lower than Vth, the system remains silent: all downstream circuits enter a power-off sleep mode, with no output or feedback loop activity. When the input signal meets the valid trigger condition (i.e., Vin > Vth), comparator CP1 immediately outputs a rising-edge synchronized high-level pulse signal, which is logically ORed with the initialization self-locking signal to form a persistent enable signal. This signal is processed through two branches: one branch serves as the clock signal, clk, to trigger the self-locking pulse generation, subsequently forming a closed feedback loop; the other branch directly serves as the clock signal, clk, to drive the narrow pulse generation circuit, ensuring that the rising edge of the pulse is strictly synchronized with the valid trigger edge of the input signal, Vin, ensuring perfect time alignment between the two. The resulting narrow pulse signal is adjusted to the nanosecond level by adjusting potentiometer XR2 to meet the final trigger requirement. This narrow pulse signal then serves as the trigger signal, triggering the switching circuit to generate the final fast-leading pulse trigger signal, thus completing the process.

[0085] Figure 5 This is the waveform diagram of the key nodes in the pulse trigger circuit of this embodiment. Figure 5 Further explain the significance of the self-locking function. Among them: Vin is the input analog signal of the input end of the entire pulse trigger circuit, signal Vcp is the output signal of comparator CP1, signal Vch1 is the voltage monitoring signal of capacitor C1, signal V Q1The Q1 output signal of the D flip-flop DFF1, that is, the self-locking circuit output signal, the signal Vor is the Y output signal of the logic OR gate OR1, and the signal V Q2 is the Q2 output signal of the D flip-flop DFF2, that is, the narrow pulse trigger signal, and Vout is the output signal of the entire pulse trigger circuit, that is, the output signal of the switching circuit.

[0086] Due to the existence of key jitter or noise interference, a jitter pulse P2 may be introduced when a single trigger pulse P1 is input to the entire pulse trigger circuit. Vth is the threshold voltage of the comparator CP1. When the pulse amplitude Vin exceeds the threshold voltage Vth, a high-level pulse signal is generated. When the pulse amplitude Vin is less than the threshold voltage Vth, the pulse jumps to a low level, and the output signal of the comparator CP1 is Vcp. After the entire pulse trigger circuit is powered on, the reset terminal ~MR1 of the D flip-flop DFF1 is at a low level, so the output terminal V Q1 It is low level, so when it is logically ORed with Vcp, it responds to the first trigger. After that, the signal is used as the clock signal clk to trigger the two D flip-flops DFF1 and D flip-flop DFF2 to operate. At this time, Vch1 detects that the voltage across capacitor C1 is 0, so after passing through inverter N2, the ~MR1 end of D flip-flop DFF1 is high level, the zero state is released, and the normal working state is entered. Since the D1 output end of D flip-flop DFF1 is directly connected to the power supply Vcc2, the output signal V Q1 Will follow the change of the input terminal and will always maintain a high level state, while the output terminal of ~Q1 will maintain a low level. After being inverted by the inverter N1, it will be a high level to charge the capacitor C1. Therefore, the Vch1 signal represents the charging process of the capacitor. When Vch1 reaches 0.5Vcc2, the ~MR1 terminal is set to zero due to its opposite direction. At this time, the signal V Q1 The signal will be fed back into the A input of the logic OR gate OR1, so the falling edge of the OR gate output will be the same as the signal V Q1 The signal is aligned to cover the pulse train. It only responds to the first trigger. The output signal of the logic OR gate OR1 triggers the D flip-flop DFF2 at the same time. Therefore, the signal V Q2 With V Q1 The rising transition edge of the signal is consistent, and the working process is basically the same. Q2 The pulse width is also affected by the charging time of capacitor C2. Since the effective triggering edge is the rising edge, in order to ensure the reliability of the trigger, the potentiometer XR2 and capacitor C2 are selected to generate a narrow pulse with a pulse width of ns. This serves as a trigger signal to enable the subsequent switching circuit to output the final trigger signal Vout with a fast leading edge, effectively preventing the adverse effects caused by the pulse train sequence at the input end.

[0087] This embodiment's high-reliability pulse trigger circuit converts an analog input signal into a digital trigger signal via a comparator. This signal is then logically ORed with a self-locking signal with a feedback mechanism to generate a synchronous pulse that serves as a clock source to drive a D-type flip-flop to output a narrow pulse. This narrow pulse further controls a switching circuit to produce a final trigger signal with a steep leading edge. This embodiment employs a first-trigger lock mechanism, responding only to the first valid input signal within a preset time window, thereby eliminating multiple false triggers caused by jittery input pulse sequences. The self-locking delay and narrow pulse width can be flexibly configured by adjusting the parameters of the resistor-capacitor network. This circuit is particularly suitable for generating reliable single-shot trigger pulse signals in high-energy physics research, radiation detection technology, and detonation dynamics.

[0088] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present invention shall be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A high-reliability pulse trigger circuit for radiation field measurement, characterized in that: It includes a comparison circuit, a self-locking circuit, a narrow pulse generating circuit and a switching circuit; The comparator circuit has a non-inverting input terminal for connecting to an external analog signal output device, an inverting input terminal for connecting to an external threshold voltage power supply Vth, and an output terminal connected to the B input terminal of the self-locking circuit; the comparator circuit is used to compare the analog signal with the threshold voltage and output a pulse signal; The Q1 output terminal of the self-locking circuit is connected to the A input terminal of the self-locking circuit for signal closed-loop feedback; the Y output terminal of the self-locking circuit is connected to the input terminal of the narrow pulse generating circuit; the self-locking circuit is used to convert the pulse signal into a self-locking long pulse; The narrow pulse generating circuit is used to generate a narrow pulse trigger signal according to the self-locking long pulse, and its output end is connected to the input end of the switching circuit; The switch circuit is used to output a fast pulse trigger signal.

2. The high-reliability pulse trigger circuit for radiation field measurement according to claim 1, characterized in that: The comparison circuit includes an SMA connector, a current limiting resistor R1, a matching resistor R2, a voltage stabilizing diode Z1, a voltage stabilizing diode Z2, a power supply Vcc1 and a comparator CP1; The input end of the SMA connector is used to connect to an external analog signal output device, and the output end thereof is respectively connected to one end of the current limiting resistor R1 and one end of the matching resistor R2, and the housing thereof is connected to the analog ground AGND; The other end of the current limiting resistor R1 is connected to the non-inverting input end of the comparator CP1; The other end of the matching resistor R2 is connected to the analog ground AGND; The cathode of the voltage stabilizing diode Z1 is connected to the power supply Vcc1, and the anode thereof is connected to the non-inverting input terminal of the comparator CP1; The cathode of the voltage stabilizing diode Z2 is connected to the non-inverting input terminal of the comparator CP1, and the anode thereof is connected to the analog ground AGND; The inverting input terminal of the comparator CP1 is used to connect to an external threshold voltage power supply Vth, and the output terminal thereof is connected to the B input terminal of the self-locking circuit.

3. The high-reliability pulse trigger circuit for radiation field measurement according to claim 2, characterized in that: The self-locking circuit includes a logic OR gate OR1, a D flip-flop DFF1, a power supply Vcc2, an inverter N1, an inverter N2, a potentiometer XR1, a diode Z3 and a capacitor C1; The B input terminal of the logic OR gate OR1 is connected to the output terminal of the comparator CP1, and the Y output terminal thereof is connected to the input terminal of the narrow pulse generating circuit and the clk1 terminal of the D flip-flop DFF1 respectively; The D1 input terminal of the D flip-flop DFF1 is connected to the power supply Vcc2, the ~MR1 terminal thereof is connected to the output terminal of the inverter N2, the Q1 output terminal thereof is connected to the A input terminal of the logic OR gate OR1, and the ~Q1 output terminal thereof is connected to the input terminal of the inverter N1; The output end of the inverter N1 is connected to one end of the capacitor C1 through the potentiometer XR1; The input end of the inverter N2 is connected to one end of the capacitor C1; The cathode of the diode Z3 is connected to the output end of the inverter N1, and the anode of the diode Z3 is connected to one end of the capacitor C1; The other end of the capacitor C1 is connected to the digital ground DGND.

4. The high-reliability pulse trigger circuit for radiation field measurement according to claim 3, characterized in that: The narrow pulse generating circuit includes a D flip-flop DFF2, a power supply Vcc3, an inverter N3, an inverter N4, an inverter N5, a potentiometer XR2 and a capacitor C2; The D2 input terminal of the D flip-flop DFF2 is connected to the power supply Vcc3, the clk2 terminal thereof is connected to the Y output terminal of the logic OR gate OR1, the ~MR2 terminal thereof is connected to the output terminal of the inverter N4, the Q2 output terminal thereof is connected to the input terminal of the inverter N5, and the ~Q2 output terminal thereof is connected to the input terminal of the inverter N3; The output end of the inverter N3 is connected to one end of the capacitor C2 through the potentiometer XR2; The input end of the inverter N4 is connected to one end of the capacitor C2; The output end of the inverter N5 is connected to the input end of the switch circuit; The other end of the capacitor C2 is connected to the digital ground DGND.

5. The high-reliability pulse trigger circuit for radiation field measurement according to claim 4, characterized in that: Also includes resistor R0; One end of the resistor R0 is connected to the analog ground AGND, and the other end is connected to the digital ground DGND.

6. The high-reliability pulse trigger circuit for radiation field measurement according to claim 5, characterized in that: The switch circuit includes a transistor BJT1, a transistor BJT2, a capacitor C3, a power supply Vcc4, a field effect transistor PMOS, a power supply Vcc5, a resistor R3, a resistor R4 and a load Load; The transistor BJT1 is an NPN transistor, and the transistor BJT2 is a PNP transistor; The base of the transistor BJT1 is connected to the base of the transistor BJT2 and to the output end of the inverter N5, the collector of the transistor BJT1 is connected to the power supply Vcc4, and the emitter thereof is connected to the emitter of the transistor BJT2 and to one end of the capacitor C3; The collector of the transistor BJT2 is connected to the analog ground AGND; The other end of the capacitor C3 is connected to the gate of the field effect transistor PMOS; The source of the field effect transistor PMOS is connected to the power supply Vcc5, and the drain is connected to one end of the resistor R4; The two ends of the resistor R3 are connected across the gate and source of the field effect transistor PMOS; The other end of the resistor R4 is connected to the analog ground AGND via a load Load and is used to output a fast pulse trigger signal.

7. The high-reliability pulse trigger circuit for radiation field measurement according to claim 6, characterized in that: The D flip-flop DFF1 and the D flip-flop DFF2 are of the same model; The inverter N1, inverter N2, inverter N3, inverter N4, and inverter N5 are of the same model; The voltage stabilizing diode Z1 and the voltage stabilizing diode Z2 are of the same model.

8. The high-reliability pulse trigger circuit for radiation field measurement according to claim 7, characterized in that: R1=Vin / Lin1; Wherein, Vin is the amplitude of the output signal of the external analog signal output device, and Lin1 is the maximum input current of the comparator CP1.

9. The high-reliability pulse trigger circuit for radiation field measurement according to claim 8, characterized in that: The R0=0Ω, R2=50Ω, R3=10kΩ.

10. The high-reliability pulse trigger circuit for radiation field measurement according to claim 9, characterized in that: Said C3=100nf.

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